WO2019183912A1 - 模数转换电路、图像传感器和模数转换方法 - Google Patents

模数转换电路、图像传感器和模数转换方法 Download PDF

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Publication number
WO2019183912A1
WO2019183912A1 PCT/CN2018/081225 CN2018081225W WO2019183912A1 WO 2019183912 A1 WO2019183912 A1 WO 2019183912A1 CN 2018081225 W CN2018081225 W CN 2018081225W WO 2019183912 A1 WO2019183912 A1 WO 2019183912A1
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Prior art keywords
signal
analog
ramp
clock signal
digital conversion
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PCT/CN2018/081225
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English (en)
French (fr)
Inventor
李欣伦
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深圳市汇顶科技股份有限公司
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Priority to EP18912131.2A priority Critical patent/EP3606043B1/en
Priority to CN201880000341.5A priority patent/CN108781082B/zh
Priority to PCT/CN2018/081225 priority patent/WO2019183912A1/zh
Publication of WO2019183912A1 publication Critical patent/WO2019183912A1/zh
Priority to US16/655,099 priority patent/US10979661B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/56—Input signal compared with linear ramp
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/123—Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/141—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit in which at least one step is of the folding type; Folding stages therefore
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Definitions

  • the present invention relates to analog-to-digital conversion techniques, and more particularly to an analog-to-digital conversion circuit for analog-to-digital conversion of analog signals generated by pixels and related image sensors and analog-to-digital conversion methods.
  • CMOS image sensor typically uses a column-parallel ADC architecture to perform the signals generated by the pixels. Acquisition and conversion. Since a single slope ADC can satisfy a small-sized pixel design, a column-parallel analog-to-digital conversion structure is implemented by a single-slope analog-to-digital converter. However, as the image resolution is further increased, not only the conversion speed of the single-slope analog-to-digital converter cannot meet the requirements of high-speed imaging, but also the power consumption of the counter of the single-slope analog-to-digital converter increases.
  • One of the objects of the present invention is to disclose an analog-to-digital conversion circuit for analog-to-digital conversion of an analog signal generated by a pixel and an associated image sensor and analog-to-digital conversion method to solve the above problems.
  • An embodiment of the invention discloses an analog to digital conversion circuit.
  • the analog to digital conversion circuit is configured to convert an analog signal into a digital signal.
  • the analog to digital conversion circuit includes a first comparator, a second comparator, and a counting circuit.
  • the first comparator is configured to compare the analog signal with a ramp signal to generate a first comparison signal.
  • the second comparator is configured to compare the analog signal with the ramp signal by a predetermined offset to generate a second comparison signal.
  • the counting circuit is coupled to the first comparator and the second comparator, when the first comparison signal indicates that the signal level of the ramp signal is less than the signal level of the analog signal, Counting the number of periods of a first clock signal to generate a first portion of the digital signal, and wherein the second comparison signal indicates a signal level of the ramp signal plus the predetermined offset is greater than the analog signal At the signal level, the number of periods of a second clock signal is counted to produce a second portion of the digital signal, wherein the frequency of the first clock signal is less than the frequency of the second clock signal.
  • An embodiment of the invention discloses an image sensor.
  • the image sensor includes a pixel array, a control circuit, and an analog to digital conversion circuit.
  • the pixel array includes a plurality of pixels arranged in a plurality of rows and columns.
  • the control circuit is configured to generate a first clock signal, a second clock signal, and a ramp signal, wherein a frequency of the first clock signal is less than a frequency of the second clock signal.
  • the analog-to-digital conversion circuit is coupled to the pixel array and the control circuit for converting an analog signal generated by a column of pixels in the pixel array into a digital signal.
  • the analog to digital conversion circuit includes a first comparator, a second comparator, and a counting circuit.
  • the first comparator is configured to compare the analog signal with the ramp signal to generate a first comparison signal.
  • the second comparator is configured to compare the analog signal with the ramp signal by a predetermined offset to generate a second comparison signal.
  • the counting circuit is coupled to the first comparator and the second comparator, when the first comparison signal indicates that the signal level of the ramp signal is less than the signal level of the analog signal, Counting the number of periods of the first clock signal to generate a first portion of the digital signal, and wherein the second comparison signal indicates a signal level of the ramp signal plus the predetermined offset is greater than the simulation At the signal level of the signal, the number of periods of the second clock signal is counted to produce a second portion of the digital signal.
  • An embodiment of the invention discloses an analog to digital conversion method.
  • the analog to digital conversion method includes the steps of: comparing an analog signal with a ramp signal to generate a first comparison signal; comparing the analog signal with the ramp signal by a predetermined offset to generate a a second comparison signal; when the first comparison signal indicates that the signal level of the ramp signal is less than the signal level of the analog signal, counting the number of periods of a first clock signal to generate a digital signal a portion; and when the second comparison signal indicates a signal level of the ramp signal plus the predetermined offset is greater than a signal level of the analog signal, counting a number of periods of a second clock signal to generate a second portion of the digital signal, wherein a frequency of the first clock signal is less than a frequency of the second clock signal.
  • Figure 1 is a functional block diagram of an embodiment of an image sensor of the present invention.
  • FIG. 2 is a schematic diagram showing an embodiment of at least one analog-to-digital conversion circuit of the plurality of analog-to-digital conversion circuits shown in FIG. 1.
  • FIG. 3 is a schematic diagram of an embodiment of the analog to digital conversion circuit shown in FIG. 2.
  • FIG. 4 is a signal timing diagram of an embodiment of a signal processing operation of the analog-to-digital conversion circuit shown in FIG.
  • Figure 5 is a flow chart showing an embodiment of the analog to digital conversion method of the present invention.
  • VA 1 -VA K VA analog signal
  • FIG. 1 is a functional block diagram of an embodiment of an image sensor of the present invention.
  • the image sensor 100 may employ a column parallel analog-to-digital conversion structure to perform analog-to-digital conversion operations on the sensing signals, and may include, but is not limited to, a pixel array 102, a control circuit 110, and a plurality of moduli A conversion circuit (labeled "ADC") 120_1-120_K, where K is a positive integer greater than one.
  • ADC moduli A conversion circuit
  • the pixel array 102 may include a plurality of pixels (or pixel units) P 11 -P MK arranged in M rows and K columns, where M is a positive integer greater than 1, and each pixel P 11 -P MK may perform image sensing respectively An analog signal (such as a sense voltage or a sense current) is generated.
  • the control circuit 110 can generate a first clock signal CK1, a second clock signal CK2, and a ramp signal VR, wherein the frequency of the first clock signal CK1 is less than the CK2 frequency of the second clock signal.
  • the analog-to-digital conversion circuits 120_1-120_K are coupled to the pixel array 102 and the control circuit 110, and each of the analog-to-digital conversion circuits can respectively display the pixels P 11 -P MK according to the first clock signal CK1, the second clock signal CK2, and the ramp signal VR.
  • the generated analog signal (such as a corresponding one of the plurality of analog signals VA 1 -VA K ) is converted into a digital signal.
  • the analog-to-digital conversion circuit 120_1 can convert the analog signal VA 1 into a digital signal VD 1 according to the first clock signal CK1, the second clock signal CK2, and the ramp signal VR.
  • the digital-to-analog conversion circuits shown in FIG. 1 can directly receive the analog signals generated by the columns of pixels, this is merely a convenient description and is not intended to limit the present invention.
  • the analog signals generated by the columns of pixels may be processed by the associated signals before being transmitted to the corresponding digital to analog conversion circuitry.
  • a programmable gain amplifier PGA
  • the analog signal generated by the column of pixels can be first signaled by a programmable gain amplifier. After the amplification process, it is transmitted to the corresponding digital-to-analog conversion circuit.
  • analog to digital conversion circuit 120_1 can be based on an analog signal and the ramp signal VR VA 1 to the number of cycles of a first clock signal CK1 and the second clock signal CK2 is the number of cycles are counted to the analog Signal VA 1 is converted to digital signal VD 1 . It should be noted that since the frequency of the first clock signal CK1 is smaller than the CK2 frequency of the second clock signal, the analog-to-digital conversion circuit 120_1 can firstly use the ramp signal VR and the analog signal VA 1 for the lower frequency clock signal (ie, The number of periods of the first clock signal CK1) is counted to reduce the power consumption of signal processing.
  • the analog-to-digital conversion circuit 120_1 determines that the signal level of the ramp signal VR is about to reach the signal level of the analog signal VA 1 (for example, the difference between the signal level of the ramp signal VR and the signal level of the analog signal VA 1 is within a predetermined range
  • the analog to digital conversion circuit 120_1 can then initiate a counting operation of the higher frequency clock signal (ie, the second clock signal CK2) to ensure the accuracy of the analog to digital conversion result.
  • the analog-to-digital conversion circuit 120_1 may first perform a coarse counting operation on the lower frequency first clock signal CK1 (coarse counting) When the signal level of the ramp signal VR is about to reach the signal level of the analog signal VA 1 , the analog-to-digital conversion circuit 120_1 may start fine counting for the second clock signal CK2 having a higher frequency. In this way, the image sensor 100 can greatly reduce the power consumption of the analog to digital conversion operation while meeting the requirements of high resolution and high speed imaging.
  • FIG. 2 is a schematic diagram showing a specific embodiment of at least one analog-to-digital conversion circuit of the plurality of analog-to-digital conversion circuits 120_1-120_K shown in FIG. 1.
  • the analog to digital conversion circuit 220 can convert an analog signal VA (such as one of the plurality of analog signals VA 1 -VA K ) into a digital signal VD, and can include, but is not limited to, a first comparator 232, a first The comparator 234 and a counting circuit 240.
  • the first comparator 232 is configured to receive the analog signal VA and the ramp signal VR, and compare the analog signal VA with the ramp signal VR to generate a first comparison signal CP1.
  • the second comparator 234 compares the analog signal VA with the ramp signal VR by adding a predetermined offset Vos to generate a second comparison signal CP2. That is, the first comparison signal CP1 can indicate the magnitude relationship of the signal level between the "analog signal VA" and the "ramp signal VR", and the second comparison signal CP2 can indicate the "analog signal VA” and the "ramp signal” VR plus the predetermined offset Vos" is the magnitude relationship of the signal levels between the two. Therefore, in the process of gradually increasing the signal level of the ramp signal VR to approach the signal level of the analog signal VA, the signal level of the second comparison signal CP2 is toggled first to indicate the signal compared to the first comparison signal CP1. The change in size relationship.
  • the predetermined offset Vos may be a comparator offset inherent to the second comparator 244. That is, similar to the first comparator 242, the second comparator 244 can also receive the analog signal VA and the ramp signal VR. Since the second comparator 244 has a comparator offset, the comparison operation performed by the second comparator 244 can be considered as comparing the analog signal VA with the ramp signal VR plus a predetermined offset Vos. It is worth noting that the offset of the predetermined offset Vos can be adjusted according to the design requirements.
  • the counting circuit 240 is coupled to the first comparator 232 and the second comparator 234 for controlling the counting operation of the number of periods of the first clock signal CK1 according to the first comparison signal CP1, and at least according to the second comparison signal CP2.
  • the counting operation of controlling the number of periods of the second clock signal CK2 effectively reduces the power consumption of the analog-to-digital conversion operation.
  • the counting circuit 240 may count the number of periods of the first clock signal CK1 to generate a digital signal VD. A first part (ie the first count value CV1).
  • the counting circuit 240 can perform the coarse counting operation of the number of cycles of the first clock signal CK1.
  • the counting circuit 240 may perform the number of cycles of the second clock signal CK2. Counting to produce a second portion of the digital signal VD (ie, the second count value CV2). That is, when the difference between the signal level of the ramp signal VR and the signal level of the analog signal VA is less than the predetermined offset Vos, the counting circuit 240 can perform the fine counting operation of the number of periods of the second clock signal CK2.
  • the counting circuit 240 can stop the counting operation of the number of periods of the first clock signal CK1 and/or the second clock signal CK2 according to the first comparison signal CP1. For example, when the first comparison signal CP1 indicates that the signal level of the ramp signal VR is greater than the signal level of the analog signal VA, the counting circuit 240 may stop counting the number of periods of the first clock signal CK1 and/or the second clock signal CK2. .
  • the counting circuit 240 can include a first counter 242 and a second counter 244.
  • the first counter 242 is coupled to the first comparator 232, and can count the number of periods of the first clock signal CK1 when the first comparison signal CP1 indicates that the signal level of the ramp signal VR is less than the signal level of the analog signal VA.
  • the first portion of the digital signal VD ie, the first count value CV1.
  • the second counter 244 is coupled to the first comparator 232 and the second comparator 234, and can indicate that the signal level of the ramp signal VR is lower than the signal level of the analog signal VR at the first comparison signal CP1, and the second comparison signal CP2 indicates When the signal level of the ramp signal VR plus the predetermined offset Vos is greater than the signal level of the analog signal VA, the number of periods of the second clock signal CK2 is counted to generate the second portion of the digital signal VD (ie, Two count values CV2). Since the frequency of the first clock signal CK1 is less than the frequency of the second clock signal CK2, the first counter 242 can be regarded as a coarse counter, and the second counter 244 can be regarded as a fine counter.
  • the counting circuit 240 can initiate a counting operation of the number of cycles of the first clock signal CK1 and/or the second clock signal CK2 at an appropriate timing. In some cases, the counting circuit 240 may not count the number of periods of the first clock signal CK1 until the control circuit 110 generates the ramp signal VR. For example, before the ramp signal VR is generated, the control circuit 110 does not allow the first counter 242 to initiate a counting operation; when the ramp signal VR is generated, the counting operation of the first counter 242 is initiated.
  • the counting circuit 240 may not perform the number of periods of the second clock signal CK2. count. For example, until the difference between the signal level of the ramp signal VR and the signal level of the analog signal VA is less than the predetermined offset Vos, the counting operation of the second counter 244 is initiated.
  • the K-column pixels shown in FIG. 1 can also share a single digital-to-analog conversion circuit through a switching circuit, wherein the single digital-to-analog conversion circuit can be implemented by the digital-to-analog conversion circuit 220 shown in FIG. 2.
  • FIG. 3 is a schematic diagram of an embodiment of the analog to digital conversion circuit 220 shown in FIG. 2.
  • the analog-to-digital conversion circuit 320 can include a first comparator 332, a second comparator 334 (having a predetermined offset Vos), a first counter 342, and a second counter 344, wherein the first comparator shown in FIG. 232.
  • the second comparator 234, the first counter 242, and the second counter 244 are implemented by the first comparator 332, the second comparator 334, the first counter 342, and the second counter 344, respectively.
  • the first counter 342 can include, but is not limited to, an AND gate A11 and a plurality of flip flops.
  • the plurality of flip-flops may be implemented by a plurality of D flip-flops DF11-DF15, wherein the AND gate A11 may receive the first clock signal CK1 and the first at the two input ends, respectively.
  • the signal CP1 is compared to generate a first input clock signal CGD at the output of the AND gate A11.
  • the plurality of D flip-flops DF11-DF15 are cascaded in sequence (ie, the respective data output terminals Q of the D flip-flops DF11-DF14 are respectively coupled to the clock inputs of the D flip-flops DF12-DF15); and, the D flip-flop DF11 is coupled The output terminal of the AND gate A11 (ie, the clock input terminal of the D flip-flop DF11 is coupled to the first input clock signal CGD), wherein the data input terminal D and the inverted data output terminal Q' of each of the D flip-flops DF11-DF15 Connected to each other, and the reset terminal R of each of the D flip-flops DF11-DF15 can be coupled to a control circuit (such as the control circuit 110 shown in FIG.
  • a plurality of D flip-flops DF11-DF15 can be used to count the number of periods of the first input clock signal CGD to generate a first count value CV1 (including the output of the data output terminal Q of each flip-flop DF11-DF15) as an analog signal VA phase
  • the second counter 344 can include, but is not limited to, a first AND gate A21, a second AND gate A22, and a plurality of flip flops, wherein the plurality of flip flops are implemented by a plurality of D flip flops DF21-DF23.
  • the two input terminals of the first AND gate A21 can respectively receive the second clock signal CK2 and an inverted signal CP2b of the second comparison signal CP2 to generate an auxiliary clock signal CG1 at the output of the first AND gate A21.
  • the analog to digital conversion circuit 320 may further include an inverter (not shown) for inverting the second comparison signal CP2 to generate the inverted signal CP2b.
  • the two input terminals of the second AND gate A22 can respectively receive the auxiliary clock signal CG1 and the first comparison signal CP1 to generate a second input clock signal CG2 at the output of the second AND gate A22.
  • the plurality of D flip-flops DF21-DF23 are cascaded in sequence (ie, the respective data output terminals Q of the D flip-flops DF21-DF22 are respectively coupled to the clock inputs of the D flip-flops DF22-DF23); and the D flip-flop DF21 is coupled To the output of the second AND gate A22 (ie, the clock input of the D flip-flop DF21 is coupled to the second input clock signal CG2), wherein the data input terminal D and the inverted data output of each of the D flip-flops DF21-DF23 Q' is connected to each other.
  • a plurality of D flip-flops DF21-DF23 can be used to count the number of periods of the second input clock signal CG2 to generate a second count value CV2 (including the output of the data output terminal Q of each of the flip-flops DF21-DF23) as an analog signal VA phase Corresponding to a second portion of the digital signal (such as the digital signal VD shown in Figure 2).
  • the analog-to-digital conversion circuit 320 may further include a count value reset circuit 350, wherein the count value reset circuit 350 is coupled to the first counter 342 and the second counter 344, and the counter circuit 240 shown in FIG. At least a portion may be implemented by the first counter 342, the second counter 344, and the count value reset circuit 350. While the second counter 344 counts the number of periods of the second clock signal CK2, the count value reset circuit 350 may reset the count value of the second counter 344 when the count value of the first counter 342 increases.
  • the count value reset circuit 350 can include a first inverter I1, a second inverter I2, and an exclusive OR gate XR for generating a clear signal CLR according to the data output CN of the D flip-flop DF11.
  • a first inverter I1 for generating a clear signal CLR according to the data output CN of the D flip-flop DF11.
  • an exclusive OR gate XR for generating a clear signal CLR according to the data output CN of the D flip-flop DF11.
  • a plurality of D flip-flops DF21-DF23 can reset their respective data outputs in accordance with the clear signal CLR.
  • FIG. 4 is a signal timing diagram of an embodiment of a signal processing operation of the analog to digital conversion circuit 320 shown in FIG.
  • the frequency of the first clock signal CK1 is one eighth of the frequency of the second clock signal CK2.
  • the invention is not limited thereto.
  • the signal level of the analog signal VA is greater than the signal level of the ramp signal VR, and therefore, the first counter 342 can count the number of periods of the first input clock signal CGD.
  • the signal level of the analog signal VA is greater than the signal level of the ramp signal VR plus the predetermined offset Vos, and therefore, the counting operation of the second counter 344 does not start.
  • the signal level of the analog signal VA is still greater than the signal level of the ramp signal VR, however, the signal level of the analog signal VA is less than the signal level of the ramp signal VR plus the predetermined offset Vos. Therefore, the signal level of the second comparison signal CP2 is inverted, and the second counter 344 can start the counting operation of the number of cycles of the second input clock signal CG2 (the signal level of the second input clock signal CG2 starts to flip to trigger the D flip-flop DF21).
  • the count value reset circuit 350 can generate the clear signal CLR (ie, the pulse signal) according to the data output CN of the D flip-flop DF11.
  • the second count value CV2 of the second counter 344 is reset.
  • the second counter 344 may start to increase the second count value CV2 according to the data output of each D flip-flop.
  • the count value reset circuit 350 may reset the second counter 344 according to the data output CN of the D flip-flop DF11.
  • the second count value is CV2.
  • the signal level of the analog signal VA is less than the signal level of the ramp signal VR such that the signal level of the first comparison signal CP1 is flipped. Therefore, the first counter 342 and the second counter 344 can stop the associated counting operation, and the digital-to-analog conversion circuit 320 can output a corresponding digital output code (digital signal VD).
  • the digital-to-analog conversion mechanism disclosed in the present invention before the signal level of the ramp signal VR is about to reach the signal level of the analog signal VA (for example, the difference between the signal level of the ramp signal VR and the signal level of the analog signal VA is greater than a predetermined offset By shifting Vos), only the coarse counting operation can be performed (for example, only the first counter 342 can perform the counting operation). Since the frequency of the first clock signal CK1 is low, power consumption can be greatly reduced. Further, when the signal level of the ramp signal VR is greater than the signal level of the analog signal VA, both the coarse count operation and the fine count operation can be stopped to save power. Further, the digital-to-analog conversion mechanism disclosed by the present invention can achieve a power saving effect by requiring only a small number of comparators and without changing the design of the ramp signal generating circuit.
  • the predetermined offset Vos may be provided by a signal source external to the second comparator 334.
  • analog to digital conversion circuit 320 can include a signal source that can generate a predetermined offset Vos and transmit a predetermined offset Vos to the negative input of second comparator 334.
  • the control circuit 110 shown in FIG. 1 can generate another ramp signal different from the ramp signal VR, wherein the signal level of the other ramp signal is equal to the signal level of the ramp signal VR plus a predetermined offset Vos, and The second comparator 334 can receive the other ramp signal received at the negative input.
  • the first counter 342 and/or the second counter 344 may employ different circuit configurations.
  • the number and/or type of triggers included in the first counter 342 may be determined according to design requirements, and/or the number and/or types of triggers included in the second counter 344 may be determined according to design requirements.
  • the count value reset circuit 350 may employ a different circuit configuration to generate a pulse signal, or it may be possible to omit the count value reset circuit 350.
  • the first count value CV1 is increased for the first time after the second counter 344 starts the counting operation (for example, the time point t2 shown in FIG. 4)
  • the first counter 342 may stop the counting operation, and the second counter 344
  • the second count value CV2 can be increased according to the change of the first count value CV1 until the signal level of the ramp signal VR is greater than the signal level of the analog signal VA.
  • the analog to digital conversion mechanism disclosed in the present invention can be simply summarized into the flow chart shown in FIG. Figure 5 is a flow chart showing an embodiment of the analog to digital conversion method of the present invention. If the results obtained are substantially the same, the steps do not have to be performed in the order shown in FIG. For example, some steps can be placed in it.
  • the analog-digital conversion method shown in FIG. 5 will be described below in conjunction with the analog-digital conversion circuit 320 shown in FIG. However, it is also possible to apply the analog-to-digital conversion method shown in FIG. 5 to the analog-to-digital conversion circuit 220 shown in FIG. 2 and/or the respective analog-to-digital conversion circuits shown in FIG.
  • the analog-to-digital conversion method shown in Fig. 5 can be simply summarized as follows.
  • Step 502 Compare an analog signal with a ramp signal to generate a first comparison signal.
  • the analog signal VA is compared to the ramp signal VR to produce a first comparison signal CP1.
  • Step 504 Compare the analog signal with the ramp signal by adding a predetermined offset to generate a second comparison signal. For example, the analog signal VA is compared to the ramp signal VR plus a predetermined offset Vos to produce a second comparison signal CP2.
  • Step 506 When the first comparison signal indicates that the signal level of the ramp signal is less than the signal level of the analog signal, counting the number of periods of a first clock signal to generate a first portion of a digital signal .
  • the first comparison signal CP1 indicates that the signal level of the ramp signal VR is smaller than the signal level of the analog signal VA (such as before the time point t4 shown in FIG. 4)
  • the number of periods of the first clock signal CK1 is counted to A first portion of the digital signal VD is generated (eg, a first count value CV1).
  • Step 508 When the second comparison signal indicates that the signal level of the ramp signal plus the predetermined offset is greater than the signal level of the analog signal, counting the number of periods of a second clock signal to generate a second portion of the digital signal, wherein a frequency of the first clock signal is less than a frequency of the second clock signal.
  • the second comparison signal CP2 indicates the signal level of the ramp signal VR plus the predetermined offset Vos is greater than the signal level of the analog signal VA (such as after the time point t1 shown in FIG.
  • step 508 after counting the number of periods of the second clock signal CK2, when the first count value CV1 is increased for the first time (such as the time point t2 shown in FIG. 4), the second count value may be started to increase. CV2.
  • the analog-to-digital conversion method shown in FIG. 5 can achieve the effect of power saving by controlling the time point of the counting operation. For example, the number of periods of the first clock signal CK1 may not be counted before the ramp signal VR is generated. For another example, when the second comparison signal CP2 indicates the signal level of the ramp signal VR plus the predetermined offset Vos is smaller than the signal level of the analog signal VA (for example, before the time point t1 shown in FIG. 4), the second clock signal CK2 The number of cycles will not be counted. That is, when the signal level of the ramp signal VR plus the predetermined offset Vos is smaller than the signal level of the analog signal VA, only the number of periods of the first clock signal CK1 having a lower frequency is counted.
  • the first comparison signal CP1 indicates that the signal level of the ramp signal VR is greater than the signal level of the analog signal VA (such as the time point t4 shown in FIG. 4)
  • the first clock signal CK1 and/or the second may be stopped. The number of cycles of the clock signal CK2 is counted.
  • the analog-to-digital conversion mechanism disclosed in the present invention can reduce the quiescent current by requiring only a small number of comparators and without increasing the number of ramp signal generating circuits. With the time point of controlling the coarse counting operation and the fine counting operation, the analog-to-digital conversion mechanism disclosed by the invention can effectively reduce power consumption and achieve power saving effect.

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Abstract

本发明公开了一种模数转换电路、图像传感器和模数转换方法。所述模数转换电路用于将模拟信号转换为数字信号，并包含第一比较器、第二比较器及计数电路。所述第一比较器将所述模拟信号与斜坡信号作比较。所述第二比较器将所述模拟信号与所述斜坡信号加上预定偏移作比较。所述计数电路在所述斜坡信号的信号水平小于所述模拟信号的信号水平时，对第一时钟信号的周期个数进行计数产生所述数字信号的第一部分，并在所述斜坡信号的信号水平加上所述预定偏移大于所述模拟信号的信号水平时，对第二时钟信号的周期个数进行计数产生所述数字信号的第二部分。所述第一时钟信号的频率小于所述第二时钟信号的频率。所述模数转换电路可降低功耗，具备节电功效。

Description

模数转换电路、图像传感器和模数转换方法 技术领域
本发明涉及模数转换技术，尤其涉及一种对于像素所产生的模拟信号进行模数转换的模数转换电路及其相关的图像传感器和模数转换方法。
背景技术
为了满足高分辨率和高速成像的需求，通常互补式金属氧化物半导体图像传感器(CMOS image sensor,CIS)使用了列并行模数转换结构(column-parallel ADC architecture)来对像素所产生的信号进行采集和转换。由于单斜模数转换器(single slope ADC)可以满足小尺寸的像素设计，列并行模数转换结构几乎由单斜模数转换器来实施。然而，随着图像分辨率进一步的增加，不仅单斜模数转换器的转换速度无法满足高速成像的需求，单斜模数转换器的计数器的耗电量也随之增加。
因此，需要一种创新的模数转换结构，其可同时满足高分辨率、高速成像、小尺寸像素设计以及低耗电的需求。
发明内容
本发明的目的之一在于公开一种对于像素所产生的模拟信号进行模数转换的模数转换电路及其相关的图像传感器和模数转换方法，来解决上述问题。
本发明的一实施例公开了一种模数转换电路。所述模数转换电路用于将一模拟信号转换为一数字信号。所述模数转换电路包含一第一 比较器、一第二比较器以及一计数电路。所述第一比较器用以将所述模拟信号与一斜坡信号作比较以产生一第一比较信号。所述第二比较器用以将所述模拟信号与所述斜坡信号加上一预定偏移作比较，以产生一第二比较信号。所述计数电路耦接于所述第一比较器和所述第二比较器，用以在所述第一比较信号指示出所述斜坡信号的信号水平小于所述模拟信号的信号水平时，对一第一时钟信号的周期个数进行计数以产生所述数字信号的第一部分，以及在所述第二比较信号指示出所述斜坡信号的信号水平加上所述预定偏移大于所述模拟信号的信号水平时，对一第二时钟信号的周期个数进行计数以产生所述数字信号的第二部分，其中所述第一时钟信号的频率小于所述第二时钟信号的频率。
本发明的一实施例公开了一种图像传感器。所述图像传感器包含一像素阵列、一控制电路以及一模数转换电路。所述像素阵列包含排列成多行与多列的多个像素。所述控制电路用以产生一第一时钟信号、一第二时钟信号以及一斜坡信号，其中所述第一时钟信号的频率小于所述第二时钟信号的频率。所述模数转换电路耦接于所述像素阵列与所述控制电路，用以将所述像素阵列中一列像素所产生的一模拟信号转换为一数字信号。所述模数转换电路包含一第一比较器、一第二比较器以及一计数电路。所述第一比较器用以将所述模拟信号与所述斜坡信号作比较以产生一第一比较信号。所述第二比较器用以将所述模拟信号与所述斜坡信号加上一预定偏移作比较，以产生一第二比较信号。所述计数电路耦接于所述第一比较器和所述第二比较器，用以在所述第一比较信号指示出所述斜坡信号的信号水平小于所述模拟信号的信号水平时，对所述第一时钟信号的周期个数进行计数以产生所述数字信号的第一部分，以及在所述第二比较信号指示出所述斜坡信号的信号水平加上所述预定偏移大于所述模拟信号的信号水平时，对所述第二时钟信号的周期个数进行计数以产生所述数字信号的第二部分。
本发明的一实施例公开了一种模数转换方法。所述模数转换方法包含以下步骤：将一模拟信号与一斜坡信号作比较以产生一第一比较 信号；将所述模拟信号与所述斜坡信号加上一预定偏移作比较，以产生一第二比较信号；当所述第一比较信号指示出所述斜坡信号的信号水平小于所述模拟信号的信号水平时，对一第一时钟信号的周期个数进行计数以产生一数字信号的第一部分；以及当所述第二比较信号指示出所述斜坡信号的信号水平加上所述预定偏移大于所述模拟信号的信号水平时，对一第二时钟信号的周期个数进行计数以产生所述数字信号的第二部分，其中所述第一时钟信号的频率小于所述第二时钟信号的频率。
附图说明
图1是本发明图像传感器的一实施例的功能方框示意图。
图2绘示了图1所示的多个模数转换电路其中的至少一模数转换电路的一具体实施方式的示意图。
图3是图2所示的模数转换电路的一实施例的示意图。
图4是图3所示的模数转换电路所涉及的信号处理操作的一实施例的信号时序图。
图5是本发明模数转换方法的一实施例的流程图。
其中，附图标记说明如下：
100                             图像传感器
102                             像素阵列
110                             控制电路
120_1-120_K、220、320           模数转换电路
232、332                        第一比较器
234、334                        第二比较器
240                             计数电路
242、342                        第一计数器
244、344                         第二计数器
350                              计数值复位电路
502、504、506、508               步骤
P 11-P MK                          像素
A11                              与门
A21                              第一与门
A22                              第二与门
I1                               第一反相器
I2                               第二反相器
XR                               异或门
DF11-DF15、DF21-DF23             D触发器
D                                数据输入端
Q                                数据输出端
Q'                               反相数据输出端
R                                复位端
CK1                              第一时钟信号
CK2                              第二时钟信号
VR                               斜坡信号
VA 1-VA K、VA                      模拟信号
Vos                              预定偏移
VD                               数字信号
CP1                              第一比较信号
CP2                              第二比较信号
CV1                              第一计数值
CV2                              第二计数值
CP2b                             反相信号
CGD                              第一输入时钟信号
CG2                              第二输入时钟信号
CG1                              辅助时钟信号
CN                               数据输出
CLR                              清除信号
t1、t2、t3、t4                   时间点
具体实施方式
在说明书及之前的权利要求书当中使用了某些词汇来指称特定的组件。本领域的技术人员应可理解，制造商可能会用不同的名词来称呼同样的组件。本说明书及之前的权利要求书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的基准。在通篇说明书及之前的权利要求书当中所提及的“包含”为一开放式的用语，故应解释成“包含但不限定于”。此外，“耦接”一词在此包含任何直接和间接的电连接手段。因此，若文中描述一第一装置耦接于一第二装置，则代表所述第一装置可直接电连接于所述第二装置，或通过其它装置或连接手段间接地电连接到所述第二装置。
图1是本发明图像传感器的一实施例的功能方框示意图。于此实施例中，图像传感器100可采用列并行模数转换结构来对传感信号进行模数转换操作，并可包含(但不限于)一像素阵列102、一控制电路110以及多个模数转换电路(标记为“ADC”)120_1-120_K，其中K是大于1的正整数。像素阵列102可包含排列成M行与K列的多个像素(或像素单元)P 11-P MK，其中M是大于1的正整数，各像素P 11-P MK可分别进行图像传感以产生一模拟信号(诸如一传感电压或一传感电流)。
控制电路110可产生一第一时钟信号CK1、一第二时钟信号CK2以及一斜坡信号(ramp signal)VR，其中第一时钟信号CK1的频率小于第二时钟信号的CK2频率。模数转换电路120_1-120_K耦接于像素阵列102和控制电路110，各模数转换电路可依据第一时钟信号CK1、第二时钟信号CK2及斜坡信号VR将各列像素P 11-P MK所产生的模拟信号(诸如多个模拟信号VA 1-VA K之中相对应的模拟信号)转换为一数字信号。以一列像素P 11-P M1为例，模数转换电路120_1可依据第一时钟信号CK1、第二时钟信号CK2以及斜坡信号VR将模拟信号VA 1 转换为一数字信号VD 1。
值得注意的是，虽然图1所示的各数模转换电路可直接接收各列像素所产生的模拟信号，然而，这只是方便说明而已，并非用来限制本发明。在某些实施例中，各列像素所产生的模拟信号可先通过相关的信号处理之后，再传送到相对应的数模转换电路。举例来说，可编程增益放大器(programmable gain amplifier，PGA)可设置于一列像素和相对应的数模转换电路之间，因此，所述列像素产生的模拟信号可先通过可编程增益放大器进行信号放大处理之后，再传送到相对应的数模转换电路。
在某些实施例中，模数转换电路120_1可依据斜坡信号VR和模拟信号VA 1来对第一时钟信号CK1的周期个数以及第二时钟信号CK2的周期个数分别进行计数，以将模拟信号VA 1转换为数字信号VD 1。值得注意的是，由于第一时钟信号CK1的频率小于第二时钟信号的CK2频率，因此，模数转换电路120_1首先可依据斜坡信号VR和模拟信号VA 1来对频率较低的时钟信号(即第一时钟信号CK1)的周期个数进行计数，以减少信号处理的功耗。当模数转换电路120_1判断出斜坡信号VR的信号水平即将到达模拟信号VA 1的信号水平时(例如，斜坡信号VR的信号水平与模拟信号VA 1的信号水平两者的差距位于一预定范围内)，模数转换电路120_1接着可启动频率较高的时钟信号(即第二时钟信号CK2)的计数操作，以确保模数转换结果的准确性。也就是说，在斜坡信号VR的信号水平相对于模拟信号VA 1的信号水平仍有一段差距时，模数转换电路120_1可先针对频率较低的第一时钟信号CK1进行粗计数操作(coarse counting)；在斜坡信号VR的信号水平即将到达模拟信号VA 1的信号水平时，模数转换电路120_1可开始针对频率较高的第二时钟信号CK2进行精细计数操作(fine counting)。这样，图像传感器100可以在满足高分辨率和高速成像的需求下，大幅降低模数转换操作的功耗。
请连同图1来参阅图2。图2绘示了图1所示的多个模数转换电路120_1-120_K其中的至少一模数转换电路的一具体实施方式的示 意图。模数转换电路220可将一模拟信号VA(诸如多个模拟信号VA 1-VA K其中之一)转换为一数字信号VD，并可包含(但不限于)一第一比较器232、一第二比较器234以及一计数电路240。第一比较器232用以接收模拟信号VA和斜坡信号VR，以及将模拟信号VA与斜坡信号VR作比较以产生一第一比较信号CP1。第二比较器234则是将模拟信号VA与斜坡信号VR加上一预定偏移Vos作比较，据以产生一第二比较信号CP2。也就是说，第一比较信号CP1可指示出“模拟信号VA”与“斜坡信号VR”两者之间信号水平的大小关系，第二比较信号CP2可指示出“模拟信号VA”与“斜坡信号VR加上预定偏移Vos”两者之间信号水平的大小关系。因此，在斜坡信号VR的信号水平逐渐增加以逼近模拟信号VA的信号水平的过程中，相比于第一比较信号CP1，第二比较信号CP2的信号水平会先翻转(toggle)，指示出信号大小关系的改变。
举例来说(但本发明不限于此)，预定偏移Vos可以是第二比较器244内部固有的比较器偏移(comparator offset)。也就是说，与第一比较器242相似，第二比较器244也可接收模拟信号VA与斜坡信号VR。由于第二比较器244具有比较器偏移，因此，第二比较器244所进行的比较操作可视为对模拟信号VA与斜坡信号VR加上预定偏移Vos进行比较。值得注意的是，预定偏移Vos的偏移量可依设计需求来调整。
计数电路240耦接于第一比较器232和第二比较器234，用以依据第一比较信号CP1来控制第一时钟信号CK1的周期个数的计数操作，以及至少依据第二比较信号CP2来控制第二时钟信号CK2的周期个数的计数操作，有效地降低模数转换操作的功耗。在某些例子中，当第一比较信号CP1指示出斜坡信号VR的信号水平小于模拟信号VA的信号水平时，计数电路240可对第一时钟信号CK1的周期个数进行计数以产生数字信号VD的一第一部分(即第一计数值CV1)。也就是说，当斜坡信号VR的信号水平尚未到达模拟信号VA的信号水平时，计数电路240可进行第一时钟信号CK1的周期个数的粗计数操作。在某些例子中，当第二比较信号CP2指示出斜坡信号VR的信号水平加 上预定偏移Vos大于模拟信号VA的信号水平时，计数电路240可对第二时钟信号CK2的周期个数进行计数以产生数字信号VD的一第二部分(即第二计数值CV2)。也就是说，当斜坡信号VR的信号水平与模拟信号VA的信号水平之间的差距小于预定偏移Vos时，计数电路240可进行第二时钟信号CK2的周期个数的精细计数操作。
在某些实施例中，计数电路240可依据第一比较信号CP1来停止第一时钟信号CK1和/或第二时钟信号CK2的周期个数的计数操作。例如，当第一比较信号CP1指示出斜坡信号VR的信号水平大于模拟信号VA的信号水平时，计数电路240可停止对第一时钟信号CK1和/或第二时钟信号CK2的周期个数进行计数。
举例来说(但本发明不限于此)，计数电路240可包含一第一计数器242和一第二计数器244。第一计数器242耦接于第一比较器232，并可于第一比较信号CP1指示出斜坡信号VR的信号水平小于模拟信号VA的信号水平时，对第一时钟信号CK1的周期个数进行计数以产生数字信号VD的所述第一部分(即第一计数值CV1)。第二计数器244耦接于第一比较器232和第二比较器234，并可于第一比较信号CP1指示出斜坡信号VR的信号水平小于模拟信号VR的信号水平，且第二比较信号CP2指示出斜坡信号VR的信号水平加上预定偏移Vos大于所述模拟信号VA的信号水平时，对第二时钟信号CK2的周期个数进行计数以产生数字信号VD的所述第二部分(即第二计数值CV2)。由于第一时钟信号CK1的频率小于第二时钟信号CK2的频率，第一计数器242可视为粗计数器(coarse counter)，而第二计数器244可视为精细计数器(fine counter)。
此外，在某些实施例中，为了进一步降低功耗，计数电路240可在适当的时机才启动第一时钟信号CK1和/或第二时钟信号CK2的周期个数的计数操作。在某些情形下，在控制电路110产生斜坡信号VR之前，计数电路240可不对第一时钟信号CK1的周期个数进行计数。例如，在斜坡信号VR产生之前，控制电路110不允许第一计数器242启动计数操作；当斜坡信号VR产生时，第一计数器242的计 数操作才会启动。在某些情形下，当第二比较信号CP2指示出斜坡信号VR的信号水平加上预定偏移Vos小于模拟信号VA的信号水平时，计数电路240可不对第二时钟信号CK2的周期个数进行计数。例如，直到斜坡信号VR的信号水平增加到与模拟信号VA的信号水平之间的差距小于预定偏移Vos时，第二计数器244的计数操作才会启动。
值得注意的是，虽然以上是以列并行模数转换结构来说明本发明所公开的数模转换电路，然而，本发明并不以此为限。举例来说，图1所示的K列像素也可以通过一开关电路共享单一数模转换电路，其中所述单一数模转换电路可由图2所示的数模转换电路220来实施。
为了便于理解本发明的技术特征，以下采用一示范性电路结构来说明本发明所公开的模数转换的细节。然而，这只是方便说明而已。任何采用基于图2所示的电路结构的实施方式均是可行的。请参阅图3，其为图2所示的模数转换电路220的一实施例的示意图。模数转换电路320可包含一第一比较器332、一第二比较器334(具有预定偏移Vos)、一第一计数器342以及一第二计数器344，其中图2所示的第一比较器232、第二比较器234、第一计数器242以及第二计数器244可分别由第一比较器332、第二比较器334、第一计数器342以及第二计数器344来实施。
第一计数器342可包含(但不限于)一与门A11和多个触发器。于此实施例中，所述多个触发器可由多个D触发器(D flip-flop)DF11-DF15来实施，其中与门A11可在两个输入端分别接收第一时钟信号CK1和第一比较信号CP1，以于与门A11的输出端产生一第一输入时钟信号CGD。多个D触发器DF11-DF15依次级联(即，D触发器DF11-DF14各自的数据输出端Q分别耦接到D触发器DF12-DF15的时钟输入端)；并且，D触发器DF11耦接到与门A11的输出端(即，D触发器DF11的时钟输入端耦接到第一输入时钟信号CGD)，其中各D触发器DF11-DF15的数据输入端D与反相数据输出端Q'彼此连接，且各D触发器DF11-DF15的复位端R可耦接到一控制电路(诸如图1所示的控制电路110；未绘示)。多个D触发器DF11-DF15可用来计 数第一输入时钟信号CGD的周期个数以产生第一计数值CV1(包含各触发器DF11-DF15的数据输出端Q的输出)，作为模拟信号VA相对应的一数字信号(诸如图2所示的数字信号VD)的一第一部分。
第二计数器344可包含(但不限于)一第一与门A21、一第二与门A22和多个触发器，其中所述多个触发器由多个D触发器DF21-DF23来实施。第一与门A21的两个输入端可分别接收第二时钟信号CK2和第二比较信号CP2的一反相信号CP2b，以于第一与门A21的输出端产生一辅助时钟信号CG1。例如，模数转换电路320可进一步包含一反相器(未绘示)，用来反相第二比较信号CP2以产生反相信号CP2b。第二与门A22的两个输入端可分别接收辅助时钟信号CG1和第一比较信号CP1，以于第二与门A22的输出端产生一第二输入时钟信号CG2。多个D触发器DF21-DF23依次级联(即，D触发器DF21-DF22各自的数据输出端Q分别耦接到D触发器DF22-DF23的时钟输入端)；并且，D触发器DF21耦接到第二与门A22的输出端(即，D触发器DF21的时钟输入端耦接到第二输入时钟信号CG2)，其中各D触发器DF21-DF23的数据输入端D与反相数据输出端Q'彼此连接。多个D触发器DF21-DF23可用来计数第二输入时钟信号CG2的周期个数以产生第二计数值CV2(包含各触发器DF21-DF23的数据输出端Q的输出)，作为模拟信号VA相对应的所述数字信号(诸如图2所示的数字信号VD)的一第二部分。
于此实施例中，模数转换电路320还可包含一计数值复位电路350，其中计数值复位电路350耦接于第一计数器342和第二计数器344，而图2所示的计数电路240的至少一部分可由第一计数器342、第二计数器344和计数值复位电路350来实施。在第二计数器344对第二时钟信号CK2的周期个数进行计数的期间，计数值复位电路350可于第一计数器342的计数值增加时复位第二计数器344的计数值。举例来说，计数值复位电路350可包含一第一反相器I1、一第二反相器I2以及一异或门XR，用以依据D触发器DF11的数据输出CN来产生一清除信号CLR到各D触发器DF21-DF23的复位端R。多个D触发器DF21-DF23便可依据清除信号CLR来复位各自的数据输出。
请一并参阅图3和图4。图4是图3所示的模数转换电路320所涉及的信号处理操作的一实施例的信号时序图。为了方便说明，于此实施例中，第一时钟信号CK1的频率是第二时钟信号CK2的频率的八分之一。然而，本发明并不以此为限。在时间点t1之前，模拟信号VA的信号水平大于斜坡信号VR的信号水平，因此，第一计数器342可对第一输入时钟信号CGD的周期个数进行计数。此外，在时间点t1之前，模拟信号VA的信号水平大于斜坡信号VR的信号水平加上预定偏移Vos，因此，第二计数器344的计数操作不会启动。
在时间点t1，模拟信号VA的信号水平仍大于斜坡信号VR的信号水平，然而，模拟信号VA的信号水平小于斜坡信号VR的信号水平加上预定偏移Vos。因此，第二比较信号CP2的信号水平翻转，第二计数器344可开始进行第二输入时钟信号CG2的周期个数的计数操作(第二输入时钟信号CG2的信号水平开始翻转，以触发D触发器DF21)。
在时间点t2，第一计数器342的第一计数值CV1由N增加为N+1时，计数值复位电路350可依据D触发器DF11的数据输出CN来产生清除信号CLR(即脉冲信号)以复位第二计数器344的第二计数值CV2。于此实施例中，在第二计数器344的第二计数值CV2于时间点t2被复位之后，第二计数器344可开始根据各D触发器的资料输出增加第二计数值CV2。
相似地，在时间点t3，第一计数器342的第一计数值CV1由N+1增加为N+2时，计数值复位电路350可依据D触发器DF11的数据输出CN来复位第二计数器344的第二计数值CV2。在时间点t4，模拟信号VA的信号水平小于斜坡信号VR的信号水平，使得第一比较信号CP1的信号水平翻转。因此，第一计数器342和第二计数器344可停止相关的计数操作，数模转换电路320便可输出相对应的数字输出码(数字信号VD)。
通过本发明所公开的数模转换机制，在斜坡信号VR的信号水平即将到达模拟信号VA的信号水平之前(例如，斜坡信号VR的信号水 平与模拟信号VA的信号水平两者的差距大于预定偏移Vos)，可以只进行粗计数操作(例如，可以只有第一计数器342在进行计数操作)。由于第一时钟信号CK1的频率较低，功耗可大幅下降。此外，在斜坡信号VR的信号水平大于模拟信号VA的信号水平时，粗计数操作和精细计数操作均可停止以节省电力。进一步来说，本发明所公开的数模转换机制可以只需少量的比较器，且可无需更改斜坡信号产生电路的设计，即可达到节电的功效。
请注意，以上仅供说明的目的，并非用来作为本发明的限制。在某些设计变化例中，预定偏移Vos可以是第二比较器334外部的信号源所提供。例如，模数转换电路320可包含一信号源，所述信号源可产生预定偏移Vos，并将预定偏移Vos传送到第二比较器334的负输入端。又例如，图1所示的控制电路110可产生不同于斜坡信号VR的另一斜坡信号，其中所述另一斜坡信号的信号水平等于斜坡信号VR的信号水平加上预定偏移Vos，而第二比较器334可接收于负输入端接收所述另一斜坡信号。
在某些设计变化例中，第一计数器342和/或第二计数器344可采用不同的电路结构。举例来说，第一计数器342所包含的触发器个数和/或种类可以依照设计需求来决定，和/或第二计数器344所包含的触发器个数和/或种类可以依照设计需求来决定。在某些设计变化例中，计数值复位电路350可采用不同的电路结构来产生脉冲信号，或省略计数值复位电路350也是可行的。举例来说，当第一计数值CV1在第二计数器344启动计数操作之后第一次增加时(例如，图4所示的时间点t2)，第一计数器342可停止计数操作，第二计数器344则可根据第一计数值CV1的改变开始增加第二计数值CV2，直到斜坡信号VR的信号水平大于模拟信号VA的信号水平为止。
只要可以利用不同频率的时钟信号以及斜坡信号的预定偏移，在适当时间进行粗计数操作与精细计数操作的模数转换电路，设计上相关的变化均遵循本发明的精神而落入本发明的范畴。
本发明所公开的模数转换机制可简单归纳为图5所示的流程图。 图5是本发明模数转换方法的一实施例的流程图。假若所得到的结果实质上大致相同，则步骤不一定要按照图5所示的顺序来进行。举例来说，某些步骤可安插于其中。为了方便说明，以下搭配图3所示的模数转换电路320来说明图5所示的模数转换方法。然而，将图5所示的模数转换方法应用于图2所示的模数转换电路220和/或图1所示的各模数转换电路也是可行的。图5所示的模数转换方法可简单归纳如下。
步骤502：将一模拟信号与一斜坡信号作比较以产生一第一比较信号。例如，将模拟信号VA与斜坡信号VR作比较以产生第一比较信号CP1。
步骤504：将所述模拟信号与所述斜坡信号加上一预定偏移作比较，以产生一第二比较信号。例如，将模拟信号VA与斜坡信号VR加上预定偏移Vos作比较，以产生第二比较信号CP2。
步骤506：当所述第一比较信号指示出所述斜坡信号的信号水平小于所述模拟信号的信号水平时，对一第一时钟信号的周期个数进行计数以产生一数字信号的一第一部分。例如，当第一比较信号CP1指示出斜坡信号VR的信号水平小于模拟信号VA的信号水平时(诸如图4所示的时间点t4之前)，对第一时钟信号CK1的周期个数进行计数以产生数字信号VD的第一部分(例如，第一计数值CV1)。
步骤508：当所述第二比较信号指示出所述斜坡信号的信号水平加上所述预定偏移大于所述模拟信号的信号水平时，对一第二时钟信号的周期个数进行计数以产生所述数字信号的一第二部分，其中所述第一时钟信号的频率小于所述第二时钟信号的频率。例如，当第二比较信号CP2指示出斜坡信号VR的信号水平加上预定偏移Vos大于模拟信号VA的信号水平时(诸如图4所示的时间点t1 之后)，对第二时钟信号CK2的周期个数进行计数以产生数字信号VD的第二部分(诸如第二计数值CV2)，其中第一时钟信号CK1的频率小于第二时钟信号CK2的频率。
于步骤508中，在对第二时钟信号CK2的周期个数进行计数之后，当第一计数值CV1第一次增加时(诸如图4所示的时间点t2)，可开始增加第二计数值CV2。
图5所示的模数转换方法可通过控制计数操作的时间点，达到节电的效果。例如，在斜坡信号VR产生之前，可以不对第一时钟信号CK1的周期个数进行计数。又例如，当第二比较信号CP2指示出斜坡信号VR的信号水平加上预定偏移Vos小于模拟信号VA的信号水平时(例如，图4所示的时间点t1之前)，第二时钟信号CK2的周期个数不会被计数。也就是说，当斜坡信号VR的信号水平加上预定偏移Vos小于模拟信号VA的信号水平时，只会针对频率较低的第一时钟信号CK1的周期个数进行计数。又例如，当第一比较信号CP1指示出斜坡信号VR的信号水平大于模拟信号VA的信号水平时(诸如图4所示的时间点t4)，可停止对第一时钟信号CK1和/或第二时钟信号CK2的周期个数进行计数。
由于本领域的技术人员通过阅读图1到图4相关的段落说明之后，应可了解图5所示的方法中每一步骤的细节，因此进一步的说明在此便不再赘述。
由上可知，本发明所公开的模数转换机制可以只需少量的比较器，且可无需增加斜坡信号产生电路的数量，故可减少静态电流。搭配控制粗计数操作和精细计数操作的时间点，本发明所公开的模数转换机制可有效降低功耗，达到节电的功效。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (17)

  1. 一种模数转换电路，用于将一模拟信号转换为一数字信号，其特征在于，包含：
    一第一比较器，用以将所述模拟信号与一斜坡信号作比较以产生一第一比较信号；
    一第二比较器，用以将所述模拟信号与所述斜坡信号加上一预定偏移作比较，以产生一第二比较信号；以及
    一计数电路，耦接于所述第一比较器和所述第二比较器，用以在所述第一比较信号指示出所述斜坡信号的信号水平小于所述模拟信号的信号水平时，对一第一时钟信号的周期个数进行计数以产生所述数字信号的第一部分，以及在所述第二比较信号指示出所述斜坡信号的信号水平加上所述预定偏移大于所述模拟信号的信号水平时，对一第二时钟信号的周期个数进行计数以产生所述数字信号的第二部分，其中所述第一时钟信号的频率小于所述第二时钟信号的频率。
  2. 如权利要求1所述的模数转换电路，其特征在于，所述预定偏移是所述第二比较器固有的比较器偏移，所述第二比较器接收所述模拟信号与所述斜坡信号，以对所述模拟信号与所述斜坡信号加上所述预定偏移进行比较。
  3. 如权利要求1所述的模数转换电路，其特征在于，当所述第二比较信号指示出所述斜坡信号的信号水平加上所述预定偏移小于所述模拟信号的信号水平时，所述计数电路不会对所述第二时钟信号的周期个数进行计数。
  4. 如权利要求1所述的模数转换电路，其特征在于，当所述第一比较信号指示出所述斜坡信号的信号水平大于所述模拟信号的信号 水平时，所述计数电路停止对所述第一时钟信号的周期个数进行计数。
  5. 如权利要求1所述的模数转换电路，其特征在于，当所述第一比较信号指示出所述斜坡信号的信号水平大于所述模拟信号的信号水平时，所述计数电路停止对所述第二时钟信号的周期个数进行计数。
  6. 如权利要求1所述的模数转换电路，其特征在于，所述计数电路包含：
    一第一计数器，耦接于所述第一比较器，用以在所述第一比较信号指示出所述斜坡信号的信号水平小于所述模拟信号的信号水平时，对所述第一时钟信号的周期个数进行计数以产生所述数字信号的所述第一部分；以及
    一第二计数器，耦接于所述第一比较器和所述第二比较器，用以在所述第一比较信号指示出所述斜坡信号的信号水平小于所述模拟信号的信号水平，且所述第二比较信号指示出所述斜坡信号的信号水平加上所述预定偏移大于所述模拟信号的信号水平时，对所述第二时钟信号的周期个数进行计数以产生所述数字信号的所述第二部分。
  7. 如权利要求6所述的模数转换电路，其特征在于，所述计数电路还包含：
    一计数值复位电路，耦接于所述第一计数器和所述第二计数器，其中在所述第二计数器对所述第二时钟信号的周期个数进行计数的期间，所述计数值复位电路用以在所述第一计数器的计数值增加时复位所述第二计数器的计数值。
  8. 如权利要求6所述的模数转换电路，其特征在于，所述第一计数器包含：
    多个触发器，所述多个触发器依次级联，用来计数一第一输入时钟信号的周期个数以产生一第一计数值，所述第一计数值作为所述数字信号的所述第一部分；以及
    一与门，具有一第一输入端、一第二输入端与一输出端，所述第一输出端耦接于其中至少一个触发器，所述与门分别在所述第一输入端和所述第二输入端接收所述第一时钟信号和所述第一比较信号，以于所述输出端产生所述第一输入时钟信号。
  9. 如权利要求6所述的模数转换电路，其特征在于，所述第二计数器包含：
    多个触发器，所述多个触发器依次级联，用来计数一第二输入时钟信号的周期个数以产生一第二计数值，作为所述数字信号的所述第二部分；以及
    一第一与门，具有一第一输入端、一第二输入端与一第一输出端，所述第一与门分别在所述第一输入端和所述第二输入端接收所述第二时钟信号和所述第二比较信号的一反相信号，以在所述第一与门的第一输出端产生一辅助时钟信号；以及
    一第二与门，具有一第三输入端、一第四输入端与一第二输出端，所述第二输出端耦接于其中至少一个触发器，，所述第二与门分别在所述第三输入端和所述第四输入端接收所述辅助时钟信号和所述第一比较信号，以于所述第二与门的第二输出端产生所述第二输入时钟信号。
  10. 如权利要求1所述的模数转换电路，其特征在于，所述模数转换 电路还包括信号源，所述信号源耦接于所述第二比较器，用以向所述第二比较器提供所述预定偏移。
  11. 如权利要求1所述的模数转换电路，其特征在于，所述第二比较器用以接收另一斜坡信号并将所述模拟信号与所述另一斜坡信号进行比较，其中所述另一斜坡信号的信号水平等于所述斜坡信号的信号水平加上所述预定偏移，以实现将所述模拟信号与所述斜坡信号加上所述预定偏移进行比较。
  12. 一种图像传感器，其特征在于，包含：
    一像素阵列，包含排列成多行与多列的多个像素；
    一控制电路，用以产生一第一时钟信号、一第二时钟信号以及一斜坡信号，其中所述第一时钟信号的频率小于所述第二时钟信号的频率；以及
    至少一如权利要求1至11中任一项所述的模数转换电路，耦接于所述像素阵列与所述控制电路，用以将所述像素阵列中一列像素所产生的一模拟信号转换为一数字信号。
  13. 一种模数转换方法，其特征在于，包含：
    将一模拟信号与一斜坡信号作比较以产生一第一比较信号；
    将所述模拟信号与所述斜坡信号加上一预定偏移作比较，以产生一第二比较信号；
    当所述第一比较信号指示出所述斜坡信号的信号水平小于所述模拟信号的信号水平时，对一第一时钟信号的周期个数进行计数以产生一数字信号的第一部分；以及
    当所述第二比较信号指示出所述斜坡信号的信号水平加上所述预 定偏移大于所述模拟信号的信号水平时，对一第二时钟信号的周期个数进行计数以产生所述数字信号的第二部分，其中所述第一时钟信号的频率小于所述第二时钟信号的频率。
  14. 如权利要求13所述的模数转换方法，其特征在于，当所述第二比较信号指示出所述斜坡信号的信号水平加上所述预定偏移小于所述模拟信号的信号水平时，所述第二时钟信号的周期个数不会被计数。
  15. 如权利要求13所述的模数转换方法，其特征在于，还包含：
    当所述第一比较信号指示出所述斜坡信号的信号水平大于所述模拟信号的信号水平时，停止对所述第一时钟信号的周期个数进行计数。
  16. 如权利要求13所述的模数转换方法，其特征在于，还包含：
    当所述第一比较信号指示出所述斜坡信号的信号水平大于所述模拟信号的信号水平时，停止对所述第二时钟信号的周期个数进行计数。
  17. 如权利要求13所述的模数转换方法，其特征在于，在所述斜坡信号产生之前，所述第一时钟信号的周期个数不会被计数。
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