WO2020124469A1 - 模数转换电路、图像传感器和模数转换方法 - Google Patents

模数转换电路、图像传感器和模数转换方法 Download PDF

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Publication number
WO2020124469A1
WO2020124469A1 PCT/CN2018/122250 CN2018122250W WO2020124469A1 WO 2020124469 A1 WO2020124469 A1 WO 2020124469A1 CN 2018122250 W CN2018122250 W CN 2018122250W WO 2020124469 A1 WO2020124469 A1 WO 2020124469A1
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Prior art keywords
signal
analog
count value
counter
ramp
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PCT/CN2018/122250
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English (en)
French (fr)
Inventor
李欣伦
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2018/122250 priority Critical patent/WO2020124469A1/zh
Priority to CN201880002863.9A priority patent/CN109792498B/zh
Publication of WO2020124469A1 publication Critical patent/WO2020124469A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • the present disclosure relates to analog-to-digital conversion technology, and in particular, to an analog-to-digital conversion circuit that performs analog-to-digital conversion on analog signals generated by pixels, and related image sensors and analog-to-digital conversion methods.
  • CMOS image sensor CIS
  • CMOS image sensor CIS
  • column-parallel analog-to-digital conversion structure column-parallel ADC
  • single-slope analog-to-digital converter single ADC
  • the column parallel analog-to-digital conversion structure is almost implemented by the single-slope analog-to-digital converter.
  • the power consumption of the counter of the single-slope analog-to-digital converter increases.
  • One of the objectives of the present disclosure is to provide an analog-to-digital conversion circuit that performs analog-to-digital conversion on an analog signal generated by a pixel, and its related image sensor and analog-to-digital conversion method, to solve the above problems.
  • An embodiment of the present disclosure provides an analog-to-digital conversion circuit.
  • the analog-to-digital conversion circuit is used to convert an analog signal into a digital signal.
  • the analog-to-digital conversion circuit includes a comparison circuit, a first counter, a second counter, and a count value reset circuit.
  • the comparison circuit is used to compare the analog signal with a ramp signal to generate a first comparison signal, and to compare the analog signal with the ramp signal plus a predetermined offset to generate a second comparison signal.
  • the first counter is coupled to the comparison circuit, and is used to indicate the signal of the analog signal whenever the first comparison signal indicates a sampling period in which the signal level of the ramp signal alternately rises and falls When the level is greater than the signal level of the ramp signal, the number of cycles of the first clock signal is counted to obtain the first part of the digital signal.
  • the second counter is coupled to the comparison circuit, and is used during the sampling period whenever the first comparison signal indicates that the signal level of the analog signal is greater than the signal level of the ramp signal, When the second comparison signal indicates that the signal level of the analog signal is less than the signal level of the ramp signal plus the predetermined offset, the number of cycles of the second clock signal is counted to obtain the The second part of the digital signal, wherein the frequency of the first clock signal is less than the frequency of the second clock signal.
  • the count value reset circuit is coupled to the first counter and the second counter to store the count value of the second counter when the count is stopped as an initial count value during the sampling period, and When the count value of the first counter increases, the count value of the second counter is reset to the initial count value.
  • An embodiment of the present disclosure provides an analog-to-digital conversion method.
  • the analog-to-digital conversion method includes the steps of: comparing an analog signal with a ramp signal to generate a first comparison signal; comparing the analog signal with the ramp signal plus a predetermined offset to generate a second comparison signal; and During the sampling period in which the signal level of the ramp signal alternately rises and falls: Whenever the first comparison signal indicates that the signal level of the analog signal is greater than the signal level of the ramp signal, the first The number of cycles of the clock signal is counted to obtain a first count value; whenever the first comparison signal indicates that the signal level of the analog signal is greater than the signal level of the ramp signal, and the second comparison signal Indicating that the signal level of the analog signal is less than the signal level of the ramp signal plus the predetermined offset, counting the number of cycles of the second clock signal to obtain a second count value; When counting the number of cycles of the second clock signal, store the second count value as an initial count value; and when the first count value increases, reset the second count
  • FIG. 1 is a functional block diagram of an embodiment of an image sensor of the present disclosure.
  • FIG. 2 shows a schematic diagram of a specific implementation manner of at least one analog-to-digital conversion circuit among the multiple analog-to-digital conversion circuits shown in FIG. 1.
  • FIG. 3 is a schematic diagram of an embodiment of the analog-to-digital conversion circuit shown in FIG. 2.
  • FIG. 4 is a signal timing diagram of an embodiment of the signal processing operation involved in the analog-to-digital conversion circuit shown in FIG. 3.
  • FIG. 5 is a flowchart of an embodiment of the analog-to-digital conversion method of the present disclosure.
  • the second pulse generator is the second pulse generator
  • the second AND gate is the second AND gate
  • VA 1 -VA K VA analog signal
  • VD 1 VD digital signal
  • the first comparison signal is the first comparison signal
  • the second comparison signal is the second comparison signal
  • the reset start signal can be reset by the CLR
  • FIG. 1 is a functional block diagram of an embodiment of an image sensor of the present disclosure.
  • the image sensor 100 may use a column parallel analog-to-digital conversion structure to perform analog-to-digital conversion operations on the sensor signal, and may include (but not limited to) a pixel array 102, a control circuit 110, and multiple analog-to-digital Conversion circuit (labeled "ADC") 120_1-120_K, where K is a positive integer greater than 1.
  • ADC analog-to-digital Conversion circuit
  • the pixel array 102 may include a plurality of pixels (or pixel units) P 11 -P MK arranged in M rows and K columns, where M is a positive integer greater than 1, and each pixel P 11 -P MK may perform image sensing separately
  • An analog signal (such as a sensing voltage or a sensing current) is generated.
  • the control circuit 110 can generate a first clock signal CK_C, a second clock signal CK_F and a ramp signal VR, wherein the frequency of the first clock signal CK_C is less than the frequency of the CK_F of the second clock signal.
  • the analog-to-digital conversion circuits 120_1-120_K are coupled to the pixel array 102 and the control circuit 110. Each analog-to-digital conversion circuit can convert each column of pixels P 11 -P MK according to the first clock signal CK_C, the second clock signal CK_C and the ramp signal VR The generated analog signal (such as the corresponding analog signal among the multiple analog signals VA 1 -VA K ) is converted into a digital signal.
  • the analog-to-digital conversion circuit 120_1 can convert the analog signal VA 1 into a digital signal VD 1 according to the first clock signal CK_C, the second clock signal CK_F, and the ramp signal VR.
  • the digital-to-analog conversion circuits shown in FIG. 1 can directly receive the analog signals generated by the pixels in each column, this is only for convenience of explanation, and the present disclosure is not limited thereto.
  • the analog signals generated by the pixels in each column can be processed by the relevant signal before being transmitted to the corresponding digital-to-analog conversion circuit.
  • a programmable gain amplifier programmable gain amplifier, PGA
  • the analog signal generated by the column of pixels can be first signaled by the programmable gain amplifier After the amplification process, it is transferred to the corresponding digital-to-analog conversion circuit.
  • the analog-to-digital conversion circuit 120_1 may count the number of cycles of the first clock signal CK_C and the number of cycles of the second clock signal CK_F according to the ramp signal VR and the analog signal VA 1 , respectively, to simulate The signal VA 1 is converted into a digital signal VD 1 . It is worth noting that since the frequency of the first clock signal CK_C is lower than the frequency of the CK_F of the second clock signal, the analog-to-digital conversion circuit 120_1 can first use the ramp signal VR and the analog signal VA 1 to clock the clock signal with a lower frequency (i.e. The number of cycles of the first clock signal CK_C) is counted to reduce the power consumption of signal processing.
  • the analog-to-digital conversion circuit 120_1 determines that the signal level of the ramp signal VR is about to reach the signal level of the analog signal VA 1 (for example, the difference between the signal level of the ramp signal VR and the signal level of the analog signal VA 1 is at a Within a predetermined range)
  • the analog-to-digital conversion circuit 120_1 can then start the counting operation of the clock signal with a higher frequency (ie, the second clock signal CK_F) to ensure the accuracy of the analog-to-digital conversion result.
  • the analog-to-digital conversion circuit 120_1 may first perform a coarse counting operation on the first clock signal CK_C with a lower frequency ( coarse counting); when the signal level of the ramp signal VR is about to reach the signal level of the analog signal VA 1 , the analog-to-digital conversion circuit 120_1 may start a fine counting operation for the second clock signal CK_F with a higher frequency. In this way, the image sensor 100 can greatly reduce the power consumption of the analog-to-digital conversion operation while meeting the requirements of high resolution and high-speed imaging.
  • the analog-to-digital conversion circuit 120_1 can also use correlated multiple sampling (correlated multiple sampling) technology to reduce the noise floor.
  • the analog signal VA 1 has a reset level in a reset phase in which the pixel output of the pixel P 11 is reset.
  • the analog-to-digital conversion circuit 120_1 may determine the number of cycles and the number of cycles of the first clock signal CK_C according to the ramp signal VR and the analog signal VA 1 The number of cycles of the two clock signals CK_F is counted separately to generate a digital signal VD 1 corresponding to the analog signal VA 1 having a reset level.
  • pixel P 11 is the pixel output may be communicated to analog to digital conversion circuit 120_1.
  • the analog-to-digital conversion circuit 120_1 may alternate the number of cycles of the first clock signal CK_C and the number of cycles of the second clock signal CK_F according to the ramp signal VR and the analog signal VA 1 during the period when the signal level of the ramp signal VR alternately rises and falls Count separately to convert the analog signal VA 1 having a data level into the corresponding digital signal VD 1 .
  • the image sensor 100 not only has the advantage of low power consumption, but also further reduces the noise floor of the analog-to-digital converter.
  • FIG. 2 shows a schematic diagram of a specific implementation manner of at least one analog-to-digital conversion circuit among the multiple analog-to-digital conversion circuits 120_1-120_K shown in FIG. 1.
  • the analog-to-digital conversion circuit 220 can convert an analog signal VA (such as one of a plurality of analog signals VA 1 -VA K ) into a digital signal VD, and can include (but not limited to) a comparison circuit 230 and a first counter 242 and a second counter 244.
  • the comparison circuit 230 is used to compare the analog signal VA with the ramp signal VR to generate a first comparison signal CP1, and to compare the analog signal VA with the digital signal VD plus a predetermined offset Vos to generate a second comparison signal CP2 .
  • the first comparison signal CP1 can indicate the magnitude relationship between the "analog signal VA” and the "slope signal VR”
  • the second comparison signal CP2 can indicate the "analog signal VA” and the "slope”
  • the signal level of the ramp signal VR may alternately rise and fall.
  • the signal level of the second comparison signal CP2 is compared to the first comparison signal CP1 It will toggle first, indicating a change in the signal size relationship.
  • the signal level of the second comparison signal CP2 will be inverted before the first comparison signal CP1 , Indicating the change of the signal size relationship.
  • the comparison circuit 230 may include (but not limited to) a first comparator 232 and a second comparator 234.
  • the first comparator 232 is used to receive the analog signal VA and the ramp signal VR, and compare the analog signal VA with the ramp signal VR to generate a first comparison signal CP1.
  • the second comparator 234 compares the analog signal VA with the ramp signal VR plus a predetermined offset Vos to generate a second comparison signal CP2.
  • the predetermined offset Vos may be (but not limited to) a comparator offset inherent within the second comparator 234. That is, similar to the first comparator 232, the second comparator 234 can also receive the analog signal VA and the ramp signal VR.
  • the comparison operation performed by the second comparator 234 can be regarded as a comparison between the analog signal VA and the ramp signal VR plus a predetermined offset Vos.
  • the offset of the predetermined offset Vos can be adjusted according to design requirements.
  • the first comparator 232 and the second comparator 234 may be combined into a single comparison circuit with two output terminals.
  • the second comparator 234 may be incorporated into the first comparator 232.
  • the design changes related to the comparison circuit 230 are included in the protection scope of the present disclosure.
  • the first counter 242 is coupled to the comparison circuit 230 for controlling the counting operation of the number of cycles of the first clock signal CK_C according to the first comparison signal CP1. For example, during the sampling period in which the signal level of the ramp signal VR alternately rises and falls, whenever the first comparison signal CP1 indicates that the signal level of the analog signal VA is greater than the signal level of the ramp signal VR, the first counter 242 may The number of cycles of the first clock signal CK_C is counted to obtain the first part of the digital signal VD (ie, the first count value CV_C).
  • the second counter 244 is coupled to the comparison circuit 230 for controlling the counting operation of the number of cycles of the second clock signal CK_F according to the first comparison signal CP1 and the second comparison signal CP2. For example, during the sampling period in which the signal level of the ramp signal VR alternately rises and falls, whenever the first comparison signal CP1 indicates that the signal level of the analog signal VA is greater than the signal level of the ramp signal VR, the second comparison signal When CP2 indicates that the signal level of the analog signal VA is less than the signal level of the ramp signal VR plus a predetermined offset Vos, the second counter 244 may count the number of cycles of the second clock signal CK_F to obtain the first signal of the digital signal VD Two parts (ie the second count value CV_F).
  • the first counter 242 can be regarded as a coarse counter, and the second counter 244 can be regarded as a fine counter. That is, during the sampling period in which the signal level of the ramp signal VR alternately rises and falls, when the signal level of the ramp signal VR has not reached the signal level of the analog signal VA, the first counter 242 may perform the first clock signal The coarse counting operation of the number of cycles of CK_C; when the difference between the signal level of the ramp signal VR and the signal level of the analog signal VA is less than the predetermined offset Vos, the second counter 244 can perform the cycle of the second clock signal CK_F Fine count operation of the number. By selectively performing at least one of the coarse count operation and the fine count operation, the analog-to-digital conversion circuit 220 can effectively reduce the power consumption of the analog-to-digital conversion operation.
  • the first counter 242 and/or the second counter 244 may stop the counting operation according to the first comparison signal CP1. For example, during the sampling period in which the signal level of the ramp signal VR alternately rises and falls, whenever the first comparison signal CP1 indicates that the signal level of the analog signal VA is less than or equal to the signal level of the ramp signal VR, the first counter 242 can stop/pause counting the number of cycles of the first clock signal CK_C; until the signal level of the analog signal VA is greater than the signal level of the ramp signal VR again during this sampling period, the first counter 242 can continue to count The number of cycles of a clock signal CK_C is counted.
  • the second counter 244 may stop/pause counting the number of cycles of the second clock signal CK_F ; During this sampling period, when the signal level of the analog signal VA is again greater than the signal level of the ramp signal VR, the second counter 244 may continue to count the number of cycles of the second clock signal CK_F
  • the second counter 244 can provide a numerical scale between two adjacent values of the first count value CV_C (ie, the second count Value CV_F). Therefore, during the counting operation of both the first counter 242 and the second counter 244 (for example, the difference between the signal level of the analog signal VA and the signal level of the ramp signal VR is less than the predetermined offset Vos), whenever the first When a count value CV_C increases (carry), the second count value CV_F can be reset to an initial count value and restart counting. That is, the second count value CV_F may be reset one or more times during one sampling period of the correlated multi-sampling operation (that is, the period during which the signal level of the ramp signal VR rises and falls alternately).
  • the analog-to-digital conversion circuit 220 may further include a count value reset circuit 250.
  • the count value reset circuit 250 is coupled to the second counter 244 to store the second count value CV_F of the second counter 244 when the counting stops during the sampling period in which the signal level of the ramp signal VR alternately rises and falls The initial count value CV_I.
  • the count value reset circuit 250 may reset the second count value CV_F to the stored initial count value CV_I.
  • the count value reset circuit 250 may reset the second count value CV_F to the initial count value CV_I while the second counter 244 counts the number of cycles of the second clock signal CK_F.
  • the second count value CV_F when the second counter 244 stops counting for the first time can be stored in the count value reset circuit 250;
  • the second count value CV_F can be reset to the result obtained by the previous counting operation, so that the second counter 244 can use the second value obtained when the operation was last stopped.
  • the count value CV_F starts to count again.
  • the K-column pixels shown in FIG. 1 can also share a single digital-analog conversion circuit through a switch circuit, where the single digital-analog conversion circuit can be implemented by the digital-analog conversion circuit 220 shown in FIG. 2.
  • FIG. 3 is a schematic diagram of an embodiment of the analog-to-digital conversion circuit 220 shown in FIG. 2.
  • the analog-to-digital conversion circuit 320 may include a first comparator 332, a second comparator 334 (with a predetermined offset Vos), a first counter 342, a second counter 344, and a count value reset circuit 350, of which FIG.
  • the illustrated first comparator 232, second comparator 234, first counter 242, second counter 244, and count value reset circuit 250 can be composed of a first comparator 332, a second comparator 334, a first counter 342, The second counter 344 and the count value reset circuit 350 are implemented.
  • the first comparator 332 is used to compare the analog signal VA with the ramp signal VR
  • the second comparator 334 is used to compare the analog signal VA with the ramp signal VR plus a predetermined offset Vos.
  • the predetermined offset Vos may be the comparator offset inherent in the second comparator 334.
  • Both the first comparator 332 and the second comparator 334 can receive the analog signal VA and the ramp signal VR, so that the first comparator 332 can compare the analog signal VA and the ramp signal VR, and the second comparator 334 can compare the analog signal VA is compared with the ramp signal VR plus a predetermined offset Vos.
  • the first comparator 332 can receive the analog signal VA and the ramp signal VR
  • the second comparator 334 can receive the advanced copy VR' of the ramp signal VR, where the advanced copy VR' of the ramp signal VR can be shown in FIG.
  • the control circuit 110 shown in 1 is provided. There is a predetermined phase offset between the leading copy VR' of the ramp signal VR and the ramp signal VR so that the signal level of the leading copy VR' of the ramp signal VR is equal to the signal level of the ramp signal VR plus a predetermined offset Vos.
  • the first comparator 332 can compare the analog signal VA with the ramp signal VR
  • the second comparator 334 can compare the analog signal VA with the advanced copy VR′ of the ramp signal VR to compare the analog signal VA with the ramp
  • the signal VR is added with a predetermined offset Vos for comparison.
  • the first counter 342 may include (but is not limited to) an AND gate A11 and Y flip-flops (Y is a positive integer greater than 1).
  • the Y flip-flops can be implemented by 8 D flip-flops DF11-DF18, and the AND gate A11 can receive the first clock signal CK_C and the first The comparison signal CP1 is used to generate a first input clock signal CGD at the output of the AND gate A11.
  • Multiple D flip-flops DF11-DF15 are cascaded in sequence (ie, the respective data output terminals Q of the D flip-flops DF11-DF17 are respectively coupled to the clock input terminals of the D flip-flops DF12-DF18); and, the D flip-flop DF11 is coupled To the output terminal of the AND gate A11 (that is, the clock input terminal of the D flip-flop DF11 is coupled to the first input clock signal CGD), wherein the data input terminal D and the inverted data output terminal Q′ of each D flip-flop DF11-DF18 They are connected to each other, and the reset terminals R of the D flip-flops DF11-DF18 can be coupled to a control circuit (such as the control circuit 110 shown in FIG.
  • Multiple D flip-flops DF11-DF18 can be used to count the number of cycles of the first input clock signal CGD to generate a first count value CV_C (including the output of the data output terminal Q of each flip-flop DF11-DF18) as an analog signal VA phase Corresponding to the first part of a digital signal (such as the digital signal VD shown in FIG. 2).
  • the second counter 344 may include (but is not limited to) a first AND gate A21, a second AND gate A22 and P flip-flops (P is a positive integer greater than 1), wherein the P flip-flops may be 5 D Trigger DF21-DF25 to implement.
  • the two input terminals of the first AND gate A21 can respectively receive the second clock signal CK_F and an inverted signal CP2b of the second comparison signal CP2 to generate an auxiliary clock signal CG1 at the output terminal of the first AND gate A21.
  • the analog-to-digital conversion circuit 320 may further include an inverter (not shown) for inverting the second comparison signal CP2 to generate an inverted signal CP2b.
  • the two input terminals of the second AND gate A22 can respectively receive the auxiliary clock signal CG1 and the first comparison signal CP1, so as to generate a second input clock signal CG2 at the output terminal of the second AND gate A22.
  • Multiple D flip-flops DF21-DF25 are cascaded in sequence (ie, the respective data output terminals Q of the D flip-flops DF21-DF24 are respectively coupled to the clock input terminals of the D flip-flops DF22-DF25); and, the D flip-flop DF21 is coupled To the output terminal of the second AND gate A22 (ie, the clock input terminal of the D flip-flop DF21 is coupled to the second input clock signal CG2), wherein the data input terminal D and the inverted data output terminal of each D flip-flop DF21-DF25 Q'are connected to each other.
  • a plurality of D flip-flops DF21-DF25 can be used to count the number of cycles of the second input clock signal CG2 to generate a multi-bit data output (i.e., a 3-bit data output) as the second count value CV_F.
  • the second count value CV_F is the second part of the digital signal (such as the digital signal VD shown in FIG. 2) corresponding to the analog signal VA.
  • the count value reset circuit 350 is coupled to the first counter 342 and the second counter 344, and may include a processing circuit 360 and a detection circuit 370.
  • the processing circuit 360 is coupled to the second counter 344 for storing the second count value CV_F of the second counter 344 when counting is stopped as the initial count value CV_I, and according to a reset start signal CLR to store the second count value CV_F is reset to the initial count value CV_I.
  • the processing circuit 360 may include, but is not limited to, a plurality of storage units MC1-MC5 and a plurality of control units LG1-LG5.
  • the plurality of storage units MC1-MC5 are respectively coupled to the plurality of D flip-flops DF21-DF25 of the second counter 344, wherein each storage unit is used to store the bit value generated by the corresponding D flip-flop when the second counter 344 stops counting , As part of the initial count value CV_I.
  • each storage unit may store the bit value generated by the corresponding D flip-flop according to a storage start signal EN, where the storage start signal EN may be (but not limited to) the one shown in FIG. 1
  • the control circuit 110 provides.
  • each storage unit may be implemented by a latch or other type of storage unit.
  • a plurality of control units LG1-LG5 are respectively coupled to a plurality of D flip-flops DF21-DF25 and respectively coupled to a plurality of storage units MC1-MC5, wherein each control unit can change the corresponding D flip-flop according to the reset start signal CLR
  • the data output is set to the bit value stored by the corresponding storage unit.
  • each control unit may be coupled to the setting terminal S and the reset terminal R of the corresponding D flip-flop.
  • the control unit can decide whether to drive the setting terminal S or the reset terminal R of the corresponding D flip-flop according to the bit value stored by the corresponding storage unit.
  • each control unit may be implemented by a logic circuit or other type of control unit.
  • the control unit LG1 (coupled The D flip-flop DF21 used to output the least significant bit can be controlled by a single signal, and the other control units (that is, multiple control units LG2-LG5) can be controlled by another signal. In this way, it can be ensured that the control unit LG1 sets the bit value of the least significant bit of the second count value CV_F within a predetermined time (for example, half of the period of the second clock signal CK_F).
  • the reset enable signal CLR may include a first clear signal CR1 (such as a pulse signal) and a second clear signal CR2 (such as a pulse signal).
  • the control unit LG1 can set the data output of the D flip-flop DF21 used to output the least significant bit according to the first clear signal CR1; the multiple control units LG2-LG5 set other triggers according to the second clear signal CR2 Device (ie multiple D flip-flops DF22-DF25) data output.
  • the detection circuit 370 is coupled to the first counter 342 and the processing circuit 360 for detecting the change of the first count value CV_C and generating the reset enable signal CLR when the first count value CV_C increases.
  • the first counter 342 may increase/carry the first count value CV_C when the first clock signal CK_C is at a predetermined signal edge (eg, rising edge), therefore,
  • the detection circuit 370 may detect the change of the first count value CV_C by detecting whether the first clock signal CK_C is on the predetermined signal edge (for example, a rising edge or a falling edge).
  • the detection circuit 370 can determine that the first count value CV_C increases (or is about to increase), and generates the reset start signal CLR. It is worth noting that in some embodiments, the first counter 342 can also be designed to increase/carry the first count value CV_C when the first clock signal CK_C is on the falling edge, therefore, the detection circuit 370 can be designed to pass the detection Whether the first clock signal CK_C is on the falling edge to detect the change of the first count value CV_C.
  • the detection circuit 370 may include (but is not limited to) a frequency divider 372 and a signal generator 374.
  • the frequency divider 372 may divide the first clock signal CK_C by two to generate a frequency-divided signal CK_Cx.
  • the frequency divider 372 can be implemented by a D flip-flop DF_T, wherein the clock input of the D flip-flop DF_T is coupled to the first clock signal CK_C, the data input D of the D flip-flop DF_T and the inverted data
  • the output terminals Q′ are connected to each other, and the reset terminal R of the D flip-flop DF_T may be coupled to a control circuit (such as the control circuit 110 shown in FIG. 1; not shown). In this way, the frequency of the signal output from the data output terminal Q (that is, the frequency-divided signal CK_Cx) will be half the frequency of the first clock signal CK_C.
  • the signal generator 374 is coupled to the frequency divider 372, and is used to generate a reset start signal CLR when the signal level of the frequency division signal CK_Cx is inverted.
  • the signal generator 374 may be implemented by one or more pulse generators. Each pulse generator can generate a clear signal (ie, a pulse signal) when the signal level of the frequency-divided signal CK_Cx is inverted, as at least part of the reset start signal CLR, where each clear signal can indicate whether the first clock signal CK_C is At the predetermined signal edge.
  • the signal generator 374 may include (but not limited to) a first pulse generator 375 and a second pulse generator 376.
  • the first pulse generator 375 can generate a first clear signal CR1 as the first part of the reset enable signal CLR when the signal level of the frequency division signal CK_Cx is inverted.
  • the second pulse generator 376 can generate a second clear signal CR2 as the first part of the reset enable signal CLR when the signal level of the frequency division signal CK_Cx is inverted.
  • the processing circuit 360 may reset the least significant bit of the second count value CV_F according to the first clear signal CR1, and reset other bits of the second count value CV_F according to the second clear signal CR2.
  • the first pulse generator 375 and the second pulse generator 376 may adopt the same circuit structure, however, the present disclosure is not limited thereto.
  • the first pulse generator 375 includes (but is not limited to) a plurality of inverters I11 and I12, and an XOR gate XR1.
  • the second pulse generator 376 includes (but is not limited to) a plurality of inverters I21 and I22, and an XOR gate XR1.
  • both the first pulse generator 375 and the second pulse generator 376 can generate a pulse signal (ie, the first clear signal CR1/the second clear signal CR2), indicating the first clock
  • the signal CK_C is at the predetermined signal edge.
  • the frequency divider 372 may adopt the structure of other frequency dividing circuits.
  • the signal generator 374 may adopt other circuit structures to detect whether the signal level of the frequency-divided signal CK_Cx is inverted.
  • the detection circuit 370 may adopt other circuit structures to detect whether the first clock signal CK_C is on the predetermined signal edge.
  • the input of at least one of the first pulse generator 375 and the second pulse generator 376 may be connected to the D flip-flop DF11 of the first counter 342 to detect whether the first clock signal CK_C is in the predetermined Signal edge.
  • the detection circuit 370 may also detect the change of the first count value CV_C in other ways. These design-related changes are included in the protection scope of the present disclosure.
  • FIG. 4 is a signal timing diagram of an embodiment of the signal processing operation involved in the analog-to-digital conversion circuit 320 shown in FIG. 3.
  • the analog-to-digital conversion circuit 320 can operate in a correlated multi-sampling mode for analog-to-digital conversion, and the frequency of the first clock signal CK_C is one-third of the frequency of the second clock signal CK_F.
  • the invention is not limited to this.
  • FIG. 4 only shows the signal timing of the signal readout phase P_read in the correlated multi-sampling mode.
  • the signal timing of the reset phase P_rst when the analog-to-digital conversion circuit 320 operates in the relevant multi-sampling mode after reading the relevant description of FIG. 4.
  • the leading copy VR' of the ramp signal VR is input to the second comparator 334. Since the signal level of the analog signal VA is greater than the signal level of the advanced copy VR' of the ramp signal VR (i.e., the signal level of the ramp signal VR plus a predetermined offset Vos), the counting operation of the second counter 344 will not start.
  • the ramp signal VR is input to the first comparator 332. Since the signal level of the analog signal VA is greater than the signal level of the ramp signal VR, the signal level of the inverted signal CP1b (inverted signal of the first comparison signal CP1) is inverted, so that the first comparator 332 starts to respond to the first clock signal
  • the number of cycles of CK_C is counted. For example, the first count value CV_C starts from the value N, and corresponding to each rising edge of the first clock signal CK_C increases by 1.
  • the second counter 344 can start the counting operation of the number of cycles of the second input clock signal CG2 (second input The signal level of the clock signal CG2 starts to invert to trigger the D flip-flop DF21).
  • the detection circuit 370 can generate a reset start signal CLR (first pulse signal CR1/second pulse signal CR2), and the processing circuit 360 can reset according to The enable signal CLR resets the second count value CV_F to 0.
  • the second counter 344 can restart counting the number of cycles of the second clock signal CK_F.
  • the second count value CV_F may increase by 1 corresponding to each rising edge of the second clock signal CK_F until the time point t5 (the first count value CV_C increases from N+3 to N+4), and the processing circuit 360 may again reset according to The enable signal CLR resets the second count value CV_F from 31 to 0.
  • the signal level of the ramp signal VR plus the predetermined offset Vos (that is, the signal level of the leading copy VR' of the ramp signal VR) reaches the signal level of the analog signal VA, and the time of the ramp signal VR
  • the shortest time difference TD between the time when the signal level reaches the signal level of the analog signal VA may be greater than one cycle of the first clock signal CK_C, so that the second counter 344 may be reset at least once before stopping counting.
  • the signal level of the analog signal VA is smaller than the signal level of the ramp signal VR, so that the signal level of the inverted signal CP1b (the inverted signal of the first comparison signal CP1) is inverted. Therefore, the first counter 342 and the second counter 344 may stop related counting operations.
  • the processing circuit 360 may store the bit values generated by the multiple D flip-flops DF21-DF25 according to the storage start signal EN.
  • the storage start signal EN can be input to the processing circuit 360 at a time point t7 (when the ramp signal VR has a peak level), so that the processing circuit 360 stores the respective data outputs of the plurality of D flip-flops DF21-DF25 as The initial count value CV_I.
  • the signal level of the analog signal VA starts to be less than the signal level of the leading copy VR' of the ramp signal VR.
  • the counting operation of the second counter 344 will not start.
  • the signal level of the analog signal VA starts to be greater than the signal level of the ramp signal VR, and the first counter 342 can perform the counting operation again.
  • the first count value CV_C may increase from N+4 to N+5 corresponding to the rising edge of the first clock signal CK_C.
  • the signal level of the analog signal VA starts to be less than the signal level of the leading copy VR' of the ramp signal VR. Therefore, the signal level of the inverted signal CP2b is inverted, and the second counter 344 can again perform the counting operation of the number of cycles of the second input clock signal CG2.
  • the detection circuit 370 detects that the first clock signal CK_C is at a rising edge, and accordingly generates a reset start signal CLR (first pulse signal CR1/second pulse signal CR2).
  • the processing circuit 360 may reset the second count value CV_F to the initial count value CV_I according to the reset start signal CLR.
  • the second counter 344 starts to count the number of cycles of the second clock signal CK_F based on the count value obtained when the count was last stopped.
  • the signal level of the analog signal VA is smaller than the signal level of the ramp signal VR, so that the signal level of the inverted signal CP1b is inverted.
  • the first counter 342 and the second counter 344 can stop related counting operations.
  • the processing circuit 360 can store the bits generated by the multiple D flip-flops DF21-DF25 according to the storage start signal EN value.
  • the storage start signal EN can be input to the processing circuit 360 at a time point t14 (when the ramp signal VR has a peak level) to update the initial count value CV_I to the current data output of multiple D flip-flops DF21-DF25 .
  • the digital-to-analog conversion mechanism of the present disclosure can only require a small number of comparators, and can achieve the power saving effect without changing the design of the ramp signal generating circuit, and is applied to the related multi-sampling operation mode.
  • the predetermined offset Vos may be provided by a signal source external to the second comparator 334.
  • the analog-to-digital conversion circuit 320 may include a signal source that generates a predetermined offset Vos and transmits the predetermined offset Vos to the negative input terminal of the second comparator 334.
  • the control circuit 110 shown in FIG. 1 may generate another ramp signal different from the ramp signal VR, where the signal level of the other ramp signal is equal to the signal level of the ramp signal VR plus a predetermined offset Vos, The second comparator 334 can receive the other ramp signal at the negative input.
  • the first counter 342 and/or the second counter 344 may adopt different circuit structures.
  • the number and/or types of triggers included in the first counter 342 can be determined according to design requirements, and/or the number and/or types of triggers included in the second counter 344 can be determined according to design requirements.
  • the count value reset circuit 350 may use different circuit structures to store/set the count value of the second counter 344.
  • the reset start signal CLR generated by the detection circuit 370 may be a single pulse signal, and each control unit in the processing circuit 360 may set the data output of the corresponding D flip-flop according to the single pulse signal.
  • the multiple digital-to-analog conversion circuits in the multiple analog-to-digital conversion circuits 120_1-120_K shown in FIG. 1 are composed of the analog-to-digital conversion circuit 320 shown in FIG. 3 (or the analog-to-digital conversion circuit 220 shown in FIG. 2)
  • the plurality of digital-to-analog conversion circuits may share a part of the circuits in the count value reset circuit 350 shown in FIG. 3 (or the analog-to-digital conversion circuit 250 shown in FIG. 2), for example (but Not limited to) the frequency divider 372 shown in FIG. 3.
  • the analog-to-digital conversion circuit that performs the coarse count operation and the fine count operation at an appropriate time, and records the count value at the time when the fine count operation is stopped, as the next fine count
  • the initial count value of the operation and related changes in design fall within the scope of the present disclosure in accordance with the spirit of the present disclosure.
  • FIG. 5 is a flowchart of an embodiment of the analog-to-digital conversion method of the present invention. If the results obtained are substantially the same, the steps need not be performed in the order shown in FIG. For example, certain steps may be inserted therein.
  • the analog-to-digital conversion method shown in FIG. 5 is described below with the analog-to-digital conversion circuit 320 shown in FIG. 3 and the signal timing chart shown in FIG. 4. However, it is feasible to apply the analog-to-digital conversion method shown in FIG. 5 to each analog-to-digital conversion circuit shown in FIG. 1 and/or the analog-to-digital conversion circuit 220 shown in FIG. 2.
  • the analog-to-digital conversion method shown in Fig. 6 can be simply summarized as follows.
  • Step 502 Compare an analog signal with a ramp signal to generate a first comparison signal.
  • the first comparator 332 compares the analog signal VA with the ramp signal VR to generate the first comparison signal CP1.
  • Step 504 Compare the analog signal with the ramp signal plus a predetermined offset to generate a second comparison signal.
  • the second comparator 334 compares the analog signal VA with the ramp signal VR plus a predetermined offset Vos to generate a second comparison signal CP2.
  • Step 506 During a sampling period in which the signal level of the ramp signal alternately rises and falls, whenever the first comparison signal indicates that the signal level of the analog signal is greater than the signal level of the ramp signal , Counting the number of cycles of a first clock signal to obtain a first count value. For example, in the signal readout phase P_read, whenever the first comparison signal CP1 (or inverted signal CP1b) indicates that the signal level of the analog signal VA is greater than the signal level of the ramp signal VR, the first counter 342 may The number of cycles of the clock signal CK_C is counted to obtain the first count value CV_C.
  • Step 508 During the sampling period, whenever the first comparison signal indicates that the signal level of the analog signal is greater than the signal level of the ramp signal, and the second comparison signal indicates the simulation When the signal level of the signal is less than the signal level of the ramp signal plus the predetermined offset, the number of cycles of the second clock signal is counted to obtain a second count value.
  • the first count value and the second count value are used as the first part and the second part of the digital signal, respectively.
  • the second counter 344 can The number of cycles of the second clock signal CK_F is counted to obtain the second count value CV_F.
  • Step 510 During the sampling period, when counting the number of cycles of the second clock signal is stopped, store the second count value as an initial count value. For example, in the signal readout phase P_read, when the second counter 344 stops counting the number of cycles of the second clock signal CK_F, the count value reset circuit 350 (or the processing circuit 360) may set the second count value at this time CV_F is stored as the initial count value CV_I (such as time t7).
  • Step 512 During the sampling period, when the first count value increases, reset the second count value to the initial count value. For example, in the signal readout phase P_read, when the count value reset circuit 350 (or the detection circuit 370) detects that the first count value CV_C increases, the count value reset circuit 350 (or the processing circuit 360) may change the second count value CV_F Reset to the initial count value CV_I (such as time t12).
  • the second count value may be reset to the initial count value when the first count value increases by detecting the change of the first count value. For example, it may be detected whether the first clock signal is on a rising edge. When it is detected that the first clock signal is at the rising edge, it is determined that the first count value will increase, and the second count value is reset to the initial count value.

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Abstract

一种模数转换电路(220)、图像传感器和模数转换方法。所述模数转换电路(220)包括比较电路(230)、第一计数器(242)、第二计数器(244)和计数值复位电路(250)；所述比较电路(230)比较模拟信号与斜坡信号产生第一比较信号，并比较所述模拟信号与所述斜坡信号加上预定偏移产生第二比较信号；在所述斜坡信号的信号电平交替上升和下降的期间，所述第一计数器(242)根据所述第一比较信号计数第一时钟信号的周期个数获得数字信号的一部分；所述第二计数器(244)根据所述第一、第二比较信号计数第二时钟信号的周期个数获得所述数字信号的一部分；所述计数值复位电路(250)储存所述第二计数器的计数值，据以在所述第一计数器(242)的计数值增加时设定所述第二计数器(244)的计数值。所述模数转换电路(220)具备节电的功效。

Description

模数转换电路、图像传感器和模数转换方法 技术领域
本公开涉及模数转换技术，尤其涉及一种对于像素所产生的模拟信号进行模数转换的模数转换电路及其相关的图像传感器和模数转换方法。
背景技术
为了满足高分辨率和高速成像的需求，通常互补式金属氧化物半导体图像传感器(CMOS image sensor,CIS)使用了列并行模数转换结构(column-parallel ADC architecture)来对像素所产生的信号进行采集和转换。由于单斜模数转换器(single slope ADC)可以满足小尺寸的像素设计，列并行模数转换结构几乎由单斜模数转换器来实施。然而，随着图像分辨率进一步的增加，不仅单斜模数转换器的转换速度无法满足高速成像的需求，单斜模数转换器的计数器的耗电量也随之增加。
因此，需要一种创新的模数转换结构，其可同时满足高分辨率、高速成像、小尺寸像素设计以及低耗电的需求。
发明内容
本公开的目的之一在于提供一种对于像素所产生的模拟信号进行模数转换的模数转换电路及其相关的图像传感器和模数转换方法，来解决上述问题。
本公开的一实施例提供了一种模数转换电路。所述模数转换电 路用于将模拟信号转换为数字信号。所述模数转换电路包括比较电路、第一计数器、第二计数器及计数值复位电路。所述比较电路用以将所述模拟信号与斜坡信号作比较以产生第一比较信号，以及将所述模拟信号与所述斜坡信号加上预定偏移作比较以产生第二比较信号。所述第一计数器耦接于所述比较电路，用以在所述斜坡信号的信号电平交替地上升和下降的采样期间内，每当所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平时，对第一时钟信号的周期个数进行计数以获得所述数字信号的第一部分。所述第二计数器耦接于所述比较电路，用以在所述采样期间内，每当所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平，而所述第二比较信号指示出所述模拟信号的信号电平小于所述斜坡信号的信号电平加上所述预定偏移时，对第二时钟信号的周期个数进行计数以获得所述数字信号的第二部分，其中所述第一时钟信号的频率小于所述第二时钟信号的频率。所述计数值复位电路耦接于所述第一计数器和所述第二计数器，用以在所述采样期间内，将所述第二计数器在停止计数时的计数值储存为初始计数值，以及在所述第一计数器的计数值增加时将所述第二计数器的计数值复位到所述初始计数值。
本公开的一实施例提供了一种模数转换方法。所述模数转换方法包括以下步骤：将模拟信号与斜坡信号作比较以产生第一比较信号；将所述模拟信号与所述斜坡信号加上预定偏移作比较以产生第二比较信号；以及在所述斜坡信号的信号电平交替地上升和下降的采样期间内：每当所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平时，对第一时钟信号的周期个数进行计数以获得第一计数值；每当所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平，而所述第二比较信号指示出所述模拟信号的信号电平小于所述斜坡信号的信号电平加上所述预定偏移时，对第二时钟信号的周期个数进行计数以获得第二计数值；在停止对所述第二时钟信号的周期个数进行计数时，将所述第二计数值储存为初始计数值；以及在所述第一计数值增加时， 将所述第二计数值复位到所述初始计数值。所述第一计数值和所述第二计数值分别作为数字信号的第一部分和第二部分。
附图说明
图1是本公开图像传感器的一实施例的功能方框示意图。
图2示出了图1所示的多个模数转换电路其中的至少一模数转换电路的一具体实施方式的示意图。
图3是图2所示的模数转换电路的一实施例的示意图。
图4是图3所示的模数转换电路所涉及的信号处理操作的一实施例的信号时序图。
图5是本公开模数转换方法的一实施例的流程图。
其中，附图标记说明如下：
100                              图像传感器
102                              像素阵列
110                              控制电路
120_1-120_K、220、320            模数转换电路
232、332                         第一比较器
234、334                         第二比较器
242、342                         第一计数器
244、344                         第二计数器
250、350                         计数值复位电路
360                              处理电路
370                              检测电路
372                              分频器
374                              信号产生器
375                              第一脉冲产生器
376                                第二脉冲产生器
502-512                            步骤
P 11-P MK                             像素
A11                                与门
A21                                第一与门
A22                                第二与门
I11、I12、I21、I22                 反相器
XR1、XR1                           异或门
DF11-DF18、DF21-DF25、DF_T         D触发器
D                                  数据输入端
Q                                  数据输出端
Q'                                 反相数据输出端
S                                  设定端
R                                  复位端
MC1-MC5                            储存单元
LG1-LG5                            控制单元
CK_C                               第一时钟信号
CK_F                               第二时钟信号
CK_Cx                              分频信号
VR                                 斜坡信号
VR’                               斜坡信号的超前副本
VA 1-VA K、VA                        模拟信号
Vos                                预定偏移
VD 1、VD                            数字信号
CP1                                第一比较信号
CP2                                第二比较信号
CV_C                               第一计数值
CV_F                               第二计数值
CV_I                               初始计数值
CP2b、CP2b                         反相信号
CGD                              第一输入时钟信号
CG2                              第二输入时钟信号
CG1                              辅助时钟信号
CLR                              复位始能信号
CR1、CR2                         清除信号
EN                               储存始能信号
t1-t13                           时间点
P_rst                            复位阶段
P_read                           信号读出阶段
具体实施方式
在说明书及之前的权利要求书当中使用了某些词汇来指称特定的组件。本领域的技术人员应可理解，制造商可能会用不同的名词来称呼同样的组件。本说明书及之前的权利要求书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的基准。在通篇说明书及之前的权利要求书当中所提及的“包含”为一开放式的用语，故应解释成“包含但不限定于”。此外，“耦接”一词在此包含任何直接和间接的电连接手段。因此，若文中描述一第一装置耦接于一第二装置，则代表所述第一装置可直接电连接于所述第二装置，或通过其它装置或连接手段间接地电连接到所述第二装置。
图1是本公开图像传感器的一实施例的功能方框示意图。于此实施例中，图像传感器100可采用列并行模数转换结构来对传感信号进行模数转换操作，并可包含(但不限于)一像素阵列102、一控制电路110以及多个模数转换电路(标记为“ADC”)120_1-120_K，其中K是大于1的正整数。像素阵列102可包含排列成M行与K列的多个像素(或像素单元)P 11-P MK，其中M是大于1的正整数，各像素P 11-P MK可分别进行图像传感以产生一模拟信号(诸如一传感电压或一传感电流)。
控制电路110可产生一第一时钟信号CK_C、一第二时钟信号CK_F以及一斜坡信号(ramp signal)VR，其中第一时钟信号CK_C的频率小于第二时钟信号的CK_F频率。模数转换电路120_1-120_K耦接于像素阵列102和控制电路110，各模数转换电路可依据第一时钟信号CK_C、第二时钟信号CK_C及斜坡信号VR将各列像素P 11-P MK所产生的模拟信号(诸如多个模拟信号VA 1-VA K之中相对应的模拟信号)转换为一数字信号。以一列像素P 11-P M1为例，模数转换电路120_1可依据第一时钟信号CK_C、第二时钟信号CK_F以及斜坡信号VR将模拟信号VA 1转换为一数字信号VD 1。
值得注意的是，虽然图1所示的各数模转换电路可直接接收各列像素所产生的模拟信号，然而，这只是方便说明而已，本公开并不以此为限。在某些实施例中，各列像素所产生的模拟信号可先通过相关的信号处理之后，再传送到相对应的数模转换电路。举例来说，可编程增益放大器(programmable gain amplifier，PGA)可设置于一列像素和相对应的数模转换电路之间，因此，所述列像素产生的模拟信号可先通过可编程增益放大器进行信号放大处理之后，再传送到相对应的数模转换电路。
在某些实施例中，模数转换电路120_1可依据斜坡信号VR和模拟信号VA 1来对第一时钟信号CK_C的周期个数以及第二时钟信号CK_F的周期个数分别进行计数，以将模拟信号VA 1转换为数字信号VD 1。值得注意的是，由于第一时钟信号CK_C的频率小于第二时钟信号的CK_F频率，因此，模数转换电路120_1首先可依据斜坡信号VR和模拟信号VA 1来对频率较低的时钟信号(即第一时钟信号CK_C)的周期个数进行计数，以减少信号处理的功耗。当模数转换电路120_1判断出斜坡信号VR的信号电平即将到达模拟信号VA 1的信号电平时(例如，斜坡信号VR的信号电平与模拟信号VA 1的信号电平两者的差距位于一预定范围内)，模数转换电路120_1接着可启动频率较高的时钟信号(即第二时钟信号CK_F)的计数操作，以确保模数转换结果的准确性。也就是说，在斜坡信号VR的信号电平相对于模拟信号VA 1的信号电平仍有一段差距时，模数转换电路120_1可 先针对频率较低的第一时钟信号CK_C进行粗计数操作(coarse counting)；在斜坡信号VR的信号电平即将到达模拟信号VA 1的信号电平时，模数转换电路120_1可开始针对频率较高的第二时钟信号CK_F进行精细计数操作(fine counting)。这样，图像传感器100可以在满足高分辨率和高速成像的需求下，大幅降低模数转换操作的功耗。
在某些实施例中，模数转换电路120_1还可采用相关多采样(correlated multiple sampling)技术，降低噪声基底(noise floor)。以像素P 11为例，在像素P 11的像素输出被复位的复位阶段(reset phase)，模拟信号VA 1具有复位电平。在斜坡信号VR的信号电平交替上升(ramp up)和下降(ramp down)的期间，模数转换电路120_1可根据斜坡信号VR和模拟信号VA 1对第一时钟信号CK_C的周期个数以及第二时钟信号CK_F的周期个数分别进行计数，以产生具有复位电平的模拟信号VA 1相对应的数字信号VD 1。接下来，在信号读出阶段(signal readout phase)，像素P 11的像素输出(即具有数据电平的模拟信号VA 1)可传送到模数转换电路120_1。模数转换电路120_1可在斜坡信号VR的信号电平交替上升和下降的期间，根据斜坡信号VR和模拟信号VA 1对第一时钟信号CK_C的周期个数以及第二时钟信号CK_F的周期个数分别进行计数，以将具有数据电平的模拟信号VA 1转换为相对应的数字信号VD 1。也就是说，图像传感器100不仅具有低耗电的优点，还可进一步降模数转换器的噪声基底。
请连同图1来参阅图2。图2示出了图1所示的多个模数转换电路120_1-120_K其中的至少一模数转换电路的一具体实施方式的示意图。模数转换电路220可将一模拟信号VA(诸如多个模拟信号VA 1-VA K其中之一)转换为一数字信号VD，并可包含(但不限于)一比较电路230、一第一计数器242及一第二计数器244。比较电路230用以将模拟信号VA与斜坡信号VR作比较以产生一第一比较信号CP1，以及将模拟信号VA与数字信号VD加上一预定偏移Vos作比较以产生一第二比较信号CP2。也就是说，第一比较信号CP1可 指示出“模拟信号VA”与“斜坡信号VR”两者之间信号电平的大小关系，第二比较信号CP2可指示出“模拟信号VA”与“斜坡信号VR加上预定偏移Vos”两者之间信号电平的大小关系。举例来说，在模数转换电路220利用相关多采样技术以转换模拟信号VA的情形下，斜坡信号VR的信号电平可交替上升和下降。在斜坡信号VR的信号电平逐渐增加以逼近模拟信号VA的信号电平的过程中，当预定偏移Vos大于零时，相比于第一比较信号CP1，第二比较信号CP2的信号电平会先翻转(toggle)，指示出信号大小关系的改变。在斜坡信号VR的信号电平逐渐减少以逼近模拟信号VA的信号电平的过程中，当预定偏移Vos小于零时，第二比较信号CP2的信号电平会比第一比较信号CP1先翻转，指示出信号大小关系的改变。
举例来说(但本公开不限于此)，比较电路230可包括(但不限于)一第一比较器232和一第二比较器234。第一比较器232用以接收模拟信号VA和斜坡信号VR，并将模拟信号VA与斜坡信号VR作比较以产生第一比较信号CP1。第二比较器234则是将模拟信号VA与斜坡信号VR加上预定偏移Vos作比较，据以产生第二比较信号CP2。预定偏移Vos可以是(但不限于)第二比较器234内部固有的比较器偏移(comparator offset)。也就是说，与第一比较器232相似，第二比较器234也可接收模拟信号VA与斜坡信号VR。由于第二比较器234具有比较器偏移，因此，第二比较器234所进行的比较操作可视为对模拟信号VA与斜坡信号VR加上预定偏移Vos进行比较。预定偏移Vos的偏移量可依设计需求来调整。
值得注意的是，在某些实施例中，第一比较器232和第二比较器234可合并成具有两个输出端的单一比较电路。在某些实施例中，第二比较器234可并入第一比较器232中。也就是说，比较电路230相关的设计变化，均包含在本公开的保护范围内。
第一计数器242耦接于比较电路230，用以依据第一比较信号CP1来控制第一时钟信号CK_C的周期个数的计数操作。例如，在斜坡信号VR的信号电平交替地上升和下降的采样期间内，每当第一比 较信号CP1指示出模拟信号VA的信号电平大于斜坡信号VR的信号电平时，第一计数器242可对第一时钟信号CK_C的周期个数进行计数以获得数字信号VD的第一部分(即第一计数值CV_C)。
第二计数器244耦接于比较电路230，用以依据第一比较信号CP1与第二比较信号CP2来控制第二时钟信号CK_F的周期个数的计数操作。例如，在斜坡信号VR的信号电平交替地上升和下降的采样期间内，每当第一比较信号CP1指示出模拟信号VA的信号电平大于斜坡信号VR的信号电平，而第二比较信号CP2指示出模拟信号VA的信号电平小于斜坡信号VR的信号电平加上预定偏移Vos时，第二计数器244可对第二时钟信号CK_F的周期个数进行计数以获得数字信号VD的第二部分(即第二计数值CV_F)。
由于第一时钟信号CK_C的频率小于第二时钟信号CK_F的频率，第一计数器242可视为粗计数器(coarse counter)，而第二计数器244可视为精细计数器(fine counter)。也就是说，在斜坡信号VR的信号电平交替地上升和下降的采样期间内，当斜坡信号VR的信号电平尚未到达模拟信号VA的信号电平时，第一计数器242可进行第一时钟信号CK_C的周期个数的粗计数操作；当斜坡信号VR的信号电平与模拟信号VA的信号电平之间的差距小于预定偏移Vos时，第二计数器244可进行第二时钟信号CK_F的周期个数的精细计数操作。通过选择性地进行粗计数操作与精细计数操作两者的至少一个，模数转换电路220可有效地降低模数转换操作的功耗。
在某些实施例中，第一计数器242和/或第二计数器244可依据第一比较信号CP1来停止计数操作。例如，在斜坡信号VR的信号电平交替地上升和下降的采样期间内，每当第一比较信号CP1指示出模拟信号VA的信号电平小于或等于斜坡信号VR的信号电平时，第一计数器242可停止/暂停对第一时钟信号CK_C的周期个数进行计数；直到在此采样期间内，模拟信号VA的信号电平再次大于斜坡信号VR的信号电平时，第一计数器242可继续对第一时钟信号CK_C的周期个数进行计数。相似地，每当第二比较信号CP2指示出模拟 信号VA的信号电平小于或等于斜坡信号VR的信号电平时，第二计数器244可停止/暂停对第二时钟信号CK_F的周期个数进行计数；直到在此采样期间内，模拟信号VA的信号电平再次大于斜坡信号VR的信号电平时，第二计数器244可继续对第二时钟信号CK_F的周期个数进行计数
值得注意的是，由于第一计数器242和第二计数器244可分别作为粗计数器和精细计数器，第二计数器244可提供第一计数值CV_C相邻两个数值之间的数值刻度(即第二计数值CV_F)。因此，在第一计数器242和第二计数器244均进行计数操作的期间(例如，模拟信号VA的信号电平与斜坡信号VR的信号电平之间的差距小于预定偏移Vos)，每当第一计数值CV_C增加(进位)时，第二计数值CV_F可复位至一初始计数值，并重新开始计数。也就是说，在相关多采样操作的一个采样期间内(即，斜坡信号VR的信号电平交替地上升和下降的期间)，第二计数值CV_F可能会被复位一次或多次。
为使在停止操作后再次进行计数的第二计数器244，能够以停止操作时所获得的第二计数值CV_F开始重新计数，模数转换电路220还可包括一计数值复位电路250。计数值复位电路250耦接于第二计数器244，用以在斜坡信号VR的信号电平交替地上升和下降的采样期间内，将第二计数器244在停止计数时的第二计数值CV_F储存为初始计数值CV_I。当第一计数值CV_C增加时，计数值复位电路250可将第二计数值CV_F复位到所储存的初始计数值CV_I。举例来说，计数值复位电路250可在第二计数器244对第二时钟信号CK_F的周期个数进行计数的期间，将第二计数值CV_F复位到初始计数值CV_I。这样，在相关多采样操作的一个采样期间内，在第二计数器244第一次停止计数时的第二计数值CV_F便可储存到计数值复位电路250；在第二计数器244再次进行计数操作的时间区间内，每当第一计数值CV_C增加时，第二计数值CV_F可被复位到前一次进行计数操作所得到的结果，使第二计数器244能够以最近一次停止操作时所获得的第二计数值CV_F开始重新计数。
值得注意的是，虽然以上是以列并行模数转换结构来说明本发明所公开的数模转换电路，然而，本发明并不以此为限。举例来说，图1所示的K列像素也可以通过一开关电路共享单一数模转换电路，其中所述单一数模转换电路可由图2所示的数模转换电路220来实施。
为了便于理解本发明的技术特征，以下采用一示范性电路结构来说明本发明所公开的模数转换的细节。然而，这只是方便说明而已。任何采用基于图2所示的电路结构的实施方式均是可行的。请参阅图3，其为图2所示的模数转换电路220的一实施例的示意图。模数转换电路320可包含一第一比较器332、一第二比较器334(具有预定偏移Vos)、一第一计数器342、一第二计数器344以及一计数值复位电路350，其中图2所示的第一比较器232、第二比较器234、第一计数器242、第二计数器244以及计数值复位电路250可分别由第一比较器332、第二比较器334、第一计数器342、第二计数器344以及计数值复位电路350来实施。
第一比较器332用以将模拟信号VA与斜坡信号VR作比较，而第二比较器334用以将模拟信号VA与斜坡信号VR加上预定偏移Vos作比较。举例来说，预定偏移Vos可以是第二比较器334固有的比较器偏移。第一比较器332和第二比较器334均可接收模拟信号VA与斜坡信号VR，使第一比较器332可对模拟信号VA与斜坡信号VR进行比较，第二比较器334则是对模拟信号VA与斜坡信号VR加上预定偏移Vos进行比较。又例如，第一比较器332可接收模拟信号VA与斜坡信号VR，第二比较器334则是接收斜坡信号VR的超前副本(advanced replica)VR’，其中斜坡信号VR的超前副本VR’可由图1所示的控制电路110提供。斜坡信号VR的超前副本VR’与斜坡信号VR之间具有预定相位偏移，使斜坡信号VR的超前副本VR’的信号电平等于斜坡信号VR的信号电平加上预定偏移Vos。因此，第一比较器332可对模拟信号VA与斜坡信号VR进行比较，第二比较器334则是通过对模拟信号VA与斜坡信号VR的超前副本VR’进行比较，以将模拟信号VA与斜坡信号VR加上预定偏移Vos 作比较。
第一计数器342可包含(但不限于)一与门A11和Y个触发器(Y是大于1的正整数)。于此实施例中，所述Y个触发器可由8个D触发器(D flip-flop)DF11-DF18来实施，其中与门A11可在两个输入端分别接收第一时钟信号CK_C和第一比较信号CP1，以于与门A11的输出端产生一第一输入时钟信号CGD。多个D触发器DF11-DF15依次级联(即，D触发器DF11-DF17各自的数据输出端Q分别耦接到D触发器DF12-DF18的时钟输入端)；并且，D触发器DF11耦接到与门A11的输出端(即，D触发器DF11的时钟输入端耦接到第一输入时钟信号CGD)，其中各D触发器DF11-DF18的数据输入端D与反相数据输出端Q'彼此连接，且各D触发器DF11-DF18的复位端R可耦接到一控制电路(诸如图1所示的控制电路110；未绘示)。多个D触发器DF11-DF18可用来计数第一输入时钟信号CGD的周期个数以产生第一计数值CV_C(包含各触发器DF11-DF18的数据输出端Q的输出)，作为模拟信号VA相对应的一数字信号(诸如图2所示的数字信号VD)的第一部分。
第二计数器344可包含(但不限于)一第一与门A21、一第二与门A22和P个触发器(P是大于1的正整数)，其中所述P个触发器可由5个D触发器DF21-DF25来实施。第一与门A21的两个输入端可分别接收第二时钟信号CK_F和第二比较信号CP2的一反相信号CP2b，以于第一与门A21的输出端产生一辅助时钟信号CG1。例如，模数转换电路320可进一步包含一反相器(未绘示)，用来反相第二比较信号CP2以产生反相信号CP2b。第二与门A22的两个输入端可分别接收辅助时钟信号CG1和第一比较信号CP1，以于第二与门A22的输出端产生一第二输入时钟信号CG2。多个D触发器DF21-DF25依次级联(即，D触发器DF21-DF24各自的数据输出端Q分别耦接到D触发器DF22-DF25的时钟输入端)；并且，D触发器DF21耦接到第二与门A22的输出端(即，D触发器DF21的时钟输入端耦接到第二输入时钟信号CG2)，其中各D触发器DF21-DF25的数据输入端D与反相数据输出端Q'彼此连接。多个D触发器DF21-DF25可用来 计数第二输入时钟信号CG2的周期个数以产生多个比特的数据输出(即3个比特的数据输出)，作为第二计数值CV_F。第二计数值CV_F是模拟信号VA相对应的所述数字信号(诸如图2所示的数字信号VD)的第二部分。
计数值复位电路350耦接于第一计数器342和第二计数器344，并可包含一处理电路360和一检测电路370。处理电路360耦接于第二计数器344，用以将所述第二计数器344在停止计数时的第二计数值CV_F储存为初始计数值CV_I，并且根据一复位始能信号CLR将第二计数值CV_F复位到初始计数值CV_I。在此实施例中，处理电路360可包括(但不限于)多个储存单元MC1-MC5以及多个控制单元LG1-LG5。多个储存单元MC1-MC5分别耦接于第二计数器344的多个D触发器DF21-DF25，其中各储存单元分别用以储存第二计数器344在停止计数时相应的D触发器产生的比特值，作为初始计数值CV_I的一部分。例如，当第二计数器344停止计数时，各储存单元可根据一储存始能信号EN储存相应的D触发器产生的比特值，其中储存始能信号EN可由(但不限于)图1所示的控制电路110提供。此外，在某些实施例中，各储存单元可由锁存器或其他类型的储存单元来实施。
多个控制单元LG1-LG5分别耦接于多个D触发器DF21-DF25以及分别耦接于多个储存单元MC1-MC5，其中各控制单元可根据复位始能信号CLR将相应的D触发器的数据输出设定为相应的储存单元储存的比特值。在此实施例中，各控制单元可耦接到相应的D触发器的设定端S与复位端R。当复位始能信号CLR输入到一控制单元时，所述控制单元可根据相应的储存单元所储存的比特值，来决定要驱动相应的D触发器的设定端S还是复位端R。以控制单元LG1为例，当复位始能信号CLR输入到控制单元LG1时，若储存单元MC1所储存的比特值是“1”(即，最近一次第二计数器344停止操作时D触发器DF21的数据输出是“1”)，控制单元LG1可驱动D触发器DF21的设定端S，以将D触发器DF21的数据输出设定为“1”；若储存单元MC1所储存的比特值是“0”(即，最近一次第二计数器 344停止操作时D触发器DF21的数据输出是“1”)，控制单元LG1可驱动D触发器DF21的复位端R，以将D触发器DF21的数据输出设定为“0”。在某些实施例中，各控制单元可由逻辑电路或其他类型的控制单元来实施。
值得注意的是，由于在第二计数器344进行计数的期间，第二计数值CV_F的最低有效位的比特值(即D触发器DF21的数据输出)变动最为频繁，因此，控制单元LG1(耦接于用来输出所述最低有效位的D触发器DF21)可单独由一个信号控制，而其他的控制单元(即多个控制单元LG2-LG5)则可由另一个信号控制。这样，可确保控制单元LG1在预定时间(例如，第二时钟信号CK_F的周期的二分之一)内设定第二计数值CV_F的最低有效位的比特值。举例来说(但本公开不限于此)，复位始能信号CLR可包括第一清除信号CR1(例如一脉冲信号)和第二清除信号CR2(例如一脉冲信号)。控制单元LG1可根据第一清除信号CR1设定用来输出所述最低有效位的D触发器DF21的数据输出；而多个控制单元LG2-LG5则是根据第二清除信号CR2设定其他的触发器(即多个D触发器DF22-DF25)的数据输出。
检测电路370耦接于第一计数器342和处理电路360，用以检测第一计数值CV_C的变化，以及在第一计数值CV_C增加时产生复位始能信号CLR。在此实施例中(但本公开不限于此)，第一计数器342可在第一时钟信号CK_C处在一预定信号沿(例如，上升沿)时，增加/进位第一计数值CV_C，因此，检测电路370可通过检测第一时钟信号CK_C是否处在所述预定信号沿(例如，上升沿或下降沿)，检测第一计数值CV_C的变化。当检测出第一时钟信号CK_C处在所述预定信号沿时，检测电路370可判断第一计数值CV_C增加(或即将增加)，并产生复位始能信号CLR。值得注意的是，在某些实施例中，第一计数器342也可设计成在第一时钟信号CK_C处在下降沿时增加/进位第一计数值CV_C，因此，检测电路370可设计为通过检测第一时钟信号CK_C是否处在下降沿，以检测第一计数值CV_C的变化。
检测电路370可包括(但不限于)一分频器372以及一信号产生器374。分频器372可将第一时钟信号CK_C进行二分频以产生一分频信号CK_Cx。在此实施例中，分频器372可由一D触发器DF_T来实施，其中D触发器DF_T的时钟输入端耦接到第一时钟信号CK_C，D触发器DF_T的数据输入端D与反相数据输出端Q'彼此连接，而D触发器DF_T的复位端R可耦接到一控制电路(诸如图1所示的控制电路110；未绘示)。这样，从数据输出端Q输出的信号(即分频信号CK_Cx)的频率会是第一时钟信号CK_C的频率的二分之一。
信号产生器374耦接于分频器372，用以在分频信号CK_Cx的信号电平翻转时产生复位始能信号CLR。在此实施例中，信号产生器374可由一个或多个脉冲产生器来实施。各脉冲产生器可在分频信号CK_Cx的信号电平翻转时产生一清除信号(即脉冲信号)，作为复位始能信号CLR的至少一部分，其中各清除信号可指示出第一时钟信号CK_C是否处在所述预定信号沿。例如，在采用单一信号来设定第二计数值CV_F的最低有效位的比特值的情形下，信号产生器374可包括(但不限于)一第一脉冲产生器375以及一第二脉冲产生器376。第一脉冲产生器375可在分频信号CK_Cx的信号电平翻转时产生一第一清除信号CR1，作为复位始能信号CLR的第一部份。第二脉冲产生器376可在分频信号CK_Cx的信号电平翻转时产生一第二清除信号CR2，作为复位始能信号CLR的第一部份。处理电路360可根据第一清除信号CR1复位所述第二计数值CV_F的最低有效位，以及根据第二清除信号CR2复位所述第二计数值CV_F其他的比特位。
为了方便说明，在此实施例中，第一脉冲产生器375和第二脉冲产生器376可采用相同的电路结构，然而，本公开并不以此为限。第一脉冲产生器375包括(但不限于)多个反相器I11和I12，以及一异或门XR1。第二脉冲产生器376包括(但不限于)多个反相器I21和I22，以及一异或门XR1。当分频信号CK_Cx的信号电平翻转时，第一脉冲产生器375与第二脉冲产生器376均可产生脉冲信号(即，第一清除信号CR1/第二清除信号CR2)，表示第一时钟信号 CK_C处在所述预定信号沿。
以上所述的检测电路370的结构只是方便说明，并非作为本公开的限制。在某些实施例中，分频器372可采用其他分频电路的结构。在某些实施例中，信号产生器374可采用其他电路结构来检测分频信号CK_Cx的信号电平是否翻转。在某些实施例中，检测电路370可采用其他电路结构来检测第一时钟信号CK_C是否处在所述预定信号沿。例如，第一脉冲产生器375与第二脉冲产生器376其中的至少一个脉冲产生器的输入可以连接到第一计数器342的D触发器DF11，以检测第一时钟信号CK_C是否处在所述预定信号沿。此外，在某些实施例中，检测电路370也可以采用其他方式来检测第一计数值CV_C的变动。这些设计上相关的变化均包含在本公开的保护范围内。
请一并参阅图3和图4。图4是图3所示的模数转换电路320所涉及的信号处理操作的一实施例的信号时序图。为了方便说明，于此实施例中，模数转换电路320可操作在相关多采样模式以进行模数转换，以及第一时钟信号CK_C的频率是第二时钟信号CK_F的频率的32分之一。然而，本发明并不以此为限。此外，为简洁起见，图4仅示出相关多采样模式中信号读出阶段P_read的信号时序。本领域的技术人员在阅读图4的相关说明之后，应可了解模数转换电路320操作在相关多采样模式时复位阶段P_rst的信号时序。
在时间点t1，斜坡信号VR的超前副本VR’输入到第二比较器334。由于模拟信号VA的信号电平大于斜坡信号VR的超前副本VR’的信号电平(即斜坡信号VR的信号电平加上预定偏移Vos)，第二计数器344的计数操作不会启动。
在时间点t2，斜坡信号VR输入到第一比较器332。由于模拟信号VA的信号电平大于斜坡信号VR的信号电平，反相信号CP1b(第一比较信号CP1的反相信号)的信号电平翻转，使第一比较器332开始对第一时钟信号CK_C的周期个数进行计数。例如，第一计数值CV_C的从数值N开始，对应第一时钟信号CK_C的各个上升沿增加1。
在时间点t3，模拟信号VA的信号电平仍大于斜坡信号VR的信号电平，然而，模拟信号VA的信号电平小于斜坡信号VR的超前副本VR’的信号电平。因此，反相信号CP2b的信号电平翻转(即，第二比较信号CP2的信号电平翻转)，第二计数器344可开始进行第二输入时钟信号CG2的周期个数的计数操作(第二输入时钟信号CG2的信号电平开始翻转，以触发D触发器DF21)。
在时间点t4，第一计数值CV_C由N+2增加为N+3，检测电路370可产生复位始能信号CLR(第一脉冲信号CR1/第二脉冲信号CR2)，处理电路360可根据复位始能信号CLR将第二计数值CV_F复位至0。第二计数器344可重新开始对第二时钟信号CK_F的周期个数进行计数。例如，第二计数值CV_F可对应第二时钟信号CK_F的各个上升沿增加1，一直到时间点t5(第一计数值CV_C由N+3增加为N+4)，处理电路360可再次根据复位始能信号CLR将第二计数值CV_F从31复位至0。
在此实施例中，斜坡信号VR的信号电平加上预定偏移Vos(即斜坡信号VR的超前副本VR’的信号电平)到达模拟信号VA的信号电平的时间，与斜坡信号VR的信号电平到达模拟信号VA的信号电平的时间两者之间的最短时间差TD，可大于第一时钟信号CK_C的一个周期，使第二计数器344在停止计数之前至少可被复位一次。
在时间点t6，模拟信号VA的信号电平小于斜坡信号VR的信号电平，使反相信号CP1b(第一比较信号CP1的反相信号)的信号电平翻转。因此，第一计数器342和第二计数器344可停止相关的计数操作。在第二计数器344停止计数时，处理电路360可根据储存始能信号EN储存多个D触发器DF21-DF25产生的比特值。在此实施例中，储存始能信号EN可在时间点t7(斜坡信号VR具有峰值电平时)输入到处理电路360，使处理电路360将多个D触发器DF21-DF25各自的数据输出储存为初始计数值CV_I。
在时间点t8，模拟信号VA的信号电平开始小于斜坡信号VR的超前副本VR’的信号电平。然而，由于模拟信号VA的信号电平仍 小于斜坡信号VR的信号电平，因此，第二计数器344的计数操作不会启动。
在时间点t9，模拟信号VA的信号电平开始大于斜坡信号VR的信号电平，第一计数器342可再次进行计数操作。例如，在时间点t10，第一计数值CV_C可对应第一时钟信号CK_C的上升沿从N+4增加为N+5。
在时间点t11，模拟信号VA的信号电平开始小于斜坡信号VR的超前副本VR’的信号电平。因此，反相信号CP2b的信号电平翻转，第二计数器344可再次进行第二输入时钟信号CG2的周期个数的计数操作。
在时间点t12，检测电路370检测出第一时钟信号CK_C处于上升沿，并据以产生复位始能信号CLR(第一脉冲信号CR1/第二脉冲信号CR2)。处理电路360可根据复位始能信号CLR将第二计数值CV_F复位至初始计数值CV_I。也就是说，第二计数器344会以最近一次停止计数时所获得的计数值，开始对第二时钟信号CK_F的周期个数进行计数。
在时间点t13，模拟信号VA的信号电平小于斜坡信号VR的信号电平，使反相信号CP1b的信号电平翻转。第一计数器342和第二计数器344可停止相关的计数操作，相似地，在第二计数器344停止计数时，处理电路360可根据储存始能信号EN储存多个D触发器DF21-DF25产生的比特值。在此实施例中，储存始能信号EN可在时间点t14(斜坡信号VR具有峰值电平时)输入到处理电路360，使初始计数值CV_I更新为多个D触发器DF21-DF25目前的数据输出。
通过本公开的数模转换机制，在斜坡信号VR的信号电平交替上升和下降的期间，不仅可选择性地进行粗计数操作与精细计数操作其中的至少一个，还可记录精细计数操作停止时的计数值，作为下一次精细计数操作的初始计数值，以将模拟信号VA转换为相对应的数字信号VD。因此，本公开的数模转换机制可以只需少量的比较器，且可无需更改斜坡信号产生电路的设计，即可达到节电的功效，并 应用于相关多采样的操作模式中。
请注意，以上仅供说明的目的，并非用来作为本公开的限制。在某些实施例中，预定偏移Vos可以是第二比较器334外部的信号源所提供。例如，模数转换电路320可包含一信号源，所述信号源可产生预定偏移Vos，并将预定偏移Vos传送到第二比较器334的负输入端。又例如，图1所示的控制电路110可产生不同于斜坡信号VR的另一斜坡信号，其中所述另一斜坡信号的信号电平等于斜坡信号VR的信号电平加上预定偏移Vos，而第二比较器334可接收于负输入端接收所述另一斜坡信号。
在某些实施例中，第一计数器342和/或第二计数器344可采用不同的电路结构。例如，第一计数器342所包含的触发器个数和/或种类可以依照设计需求来决定，和/或第二计数器344所包含的触发器个数和/或种类可以依照设计需求来决定。在某些实施例中，计数值复位电路350可采用不同的电路结构来储存/设定第二计数器344的计数值。例如，检测电路370所产生的复位始能信号CLR可以是单一脉冲信号，处理电路360中各控制单元可根据此单一脉冲信号设定相应的D触发器的数据输出。
此外，在图1所示的多个模数转换电路120_1-120_K中的多个数模转换电路是由图3所示的模数转换电路320(或图2所示的模数转换电路220)来实施的某些实施例中，所述多个数模转换电路可共用图3所示的计数值复位电路350(或图2所示的模数转换电路250)中的一部分电路，例如(但不限于)图3所示的分频器372。
只要可以利用不同频率的时钟信号以及斜坡信号的预定偏移，在适当时间进行粗计数操作与精细计数操作的模数转换电路，并且在记录精细计数操作停止时的计数值，作为下一次精细计数操作的初始计数值，设计上相关的变化均遵循本公开的精神而落入本公开的范畴。
本公开的模数转换机制可简单归纳为图5所示的流程图。图5是本发明模数转换方法的一实施例的流程图。假若所得到的结果实 质上大致相同，则步骤不一定要按照图5所示的顺序来进行。举例来说，某些步骤可安插于其中。为了方便说明，以下搭配图3所示的模数转换电路320和图4所示的信号时序图来说明图5所示的模数转换方法。然而，将图5所示的模数转换方法应用于图1所示的各模数转换电路和/或图2所示的模数转换电路220均是可行的。图6所示的模数转换方法可简单归纳如下。
步骤502：将一模拟信号与一斜坡信号作比较以产生一第一比较信号。例如，第一比较器332将模拟信号VA与斜坡信号VR作比较以产生第一比较信号CP1。
步骤504：将所述模拟信号与所述斜坡信号加上一预定偏移作比较以产生一第二比较信号。例如，第二比较器334将模拟信号VA与斜坡信号VR加上预定偏移Vos作比较以产生第二比较信号CP2。
步骤506：在所述斜坡信号的信号电平交替地上升和下降的一采样期间内，每当所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平时，对一第一时钟信号的周期个数进行计数以获得一第一计数值。例如，在信号读出阶段P_read中，每当第一比较信号CP1(或反相信号CP1b)指示出模拟信号VA的信号电平大于斜坡信号VR的信号电平时，第一计数器342可对第一时钟信号CK_C的周期个数进行计数以获得第一计数值CV_C。
步骤508：在所述采样期间内，每当所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平，而所述第二比较信号指示出所述模拟信号的信号电平小于所述斜坡信号的信号电平加上所述预定偏移时，对第二时钟信号的周期个数进行计数以获得第二计数值。所述第一计数值和所述第二计数值分别作为数字信号的第一部分和第二部分。例如，在信号 读出阶段P_read中，每当第一比较信号CP1(或反相信号CP1b)指示出模拟信号VA的信号电平大于斜坡信号VR的信号电平，而第二比较信号CP2(或反相信号CP2b)指示出模拟信号VA的信号电平小于斜坡信号VR的信号电平加上预定偏移Vos(斜坡信号VR的超前副本VR’的信号电平)时，第二计数器344可对第二时钟信号CK_F的周期个数进行计数以获得第二计数值CV_F。
步骤510：在所述采样期间内，在停止对所述第二时钟信号的周期个数进行计数时，将所述第二计数值储存为初始计数值。例如，在信号读出阶段P_read中，在第二计数器344停止对第二时钟信号CK_F的周期个数进行计数时，计数值复位电路350(或处理电路360)可将此时的第二计数值CV_F储存为初始计数值CV_I(如时间点t7)。
步骤512：在所述采样期间内，在所述第一计数值增加时，将所述第二计数值复位到所述初始计数值。例如，在信号读出阶段P_read中，在计数值复位电路350(或检测电路370)检测出第一计数值CV_C增加时，计数值复位电路350(或处理电路360)可将第二计数值CV_F复位到初始计数值CV_I(如时间点t12)。
于步骤512中，可通过检测所述第一计数值的变化，以在所述第一计数值增加时将所述第二计数值复位到所述初始计数值。例如，可检测所述第一时钟信号是否处在上升沿。当检测出所述第一时钟信号处在所述上升沿时，判断所述第一计数值会增加，并将所述第二计数值复位到所述初始计数值。
由于本领域的技术人员通过阅读图1到图4相关的段落说明之后，应可了解图5所示的模数转换方法中每一步骤的细节，因此进一步的说明在此便不再赘述。
以上所述仅为本公开的实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种模数转换电路，用于将模拟信号转换为数字信号，其特征在于，包括：
    比较电路，用以将所述模拟信号与斜坡信号作比较以产生第一比较信号，以及将所述模拟信号与所述斜坡信号加上预定偏移作比较以产生第二比较信号；
    第一计数器，耦接于所述比较电路，用以在所述斜坡信号的信号电平交替地上升和下降的采样期间内，每当所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平时，对第一时钟信号的周期个数进行计数以获得所述数字信号的第一部分；
    第二计数器，耦接于所述比较电路，用以在所述采样期间内，每当所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平，而所述第二比较信号指示出所述模拟信号的信号电平小于所述斜坡信号的信号电平加上所述预定偏移时，对第二时钟信号的周期个数进行计数以获得所述数字信号的第二部分，其中所述第一时钟信号的频率小于所述第二时钟信号的频率；以及
    计数值复位电路，耦接于所述第一计数器和所述第二计数器，用以在所述采样期间内，将所述第二计数器在停止计数时的计数值储存为初始计数值，以及在所述第一计数器的计数值增加时将所述第二计数器的计数值复位到所述初始计数值。
  2. 如权利要求1所述的模数转换电路，其特征在于，所述计数值复位电路是在所述第二计数器对所述第二时钟信号的周期个数进行计数的期间，将所述第二计数器的计数值复位到所述初始计数值。
  3. 如权利要求2所述的模数转换电路，其特征在于，所述计数值复位电路包括：
    处理电路，耦接于所述第二计数器，用以储存所述初始计数值，以及根据复位始能信号将所述第二计数器的计数值复位到所述初始计数值；以及
    检测电路，耦接于所述第一计数器和所述处理电路，用以检测所述第一计数器的计数值的变化，以及在所述第一计数器的计数值增加时产生所述复位始能信号。
  4. 如权利要求3所述的模数转换电路，其特征在于，所述第二计数器包括依次级联的P个触发器，P是大于1的正整数；所述P个触发器用来计数所述第二时钟信号的周期个数以产生P个比特的数据输出，作为所述第二计数器的计数值；所述处理电路包括：
    P个储存单元，分别耦接于所述P个触发器，各储存单元分别用以储存所述第二计数器在停止计数时相应的触发器产生的比特值，作为所述初始计数值的一部分；以及
    P个控制单元，分别耦接于所述P个触发器以及分别耦接于所述P个储存单元，其中各控制单元根据所述复位始能信号将相应的触发器的数据输出设定为相应的储存单元储存的比特值。
  5. 如权利要求4所述的模数转换电路，其特征在于，所述复位始能信号包括第一清除信号和第二清除信号；用来输出所述第二计数器的计数值的最低有效位的触发器所耦接的控制单元，根据所述第一脉冲信号设定用来输出所述最低有效位的所述触发器的数据输出；所述P个控制单元中其他的控制单元，根据所述第二脉冲信号设定所述P个触发器中其他的触发器的数据输出。
  6. 如权利要求3所述的模数转换电路，其特征在于，所述检测电路通过检测所述第一时钟信号是否处在预定信号沿，检测所述第一计数器的计数值的变化；当检测出所述第一时钟信号处在所述预定信号沿时，所述检测电路判断所述第一计数器的计数值会增加，并产生所述复位始能信号。
  7. 如权利要求6所述的模数转换电路，其特征在于，所述预定信号沿是所述第一时钟信号的上升沿。
  8. 如权利要求6所述的模数转换电路，其特征在于，所述检测电路包括：
    分频器，用以将所述第一时钟信号进行二分频以产生分频信号；以及
    信号产生器，耦接于所述分频器，用以在所述分频信号的信号电平翻转时产生所述复位始能信号。
  9. 如权利要求8所述的模数转换电路，其特征在于，所述信号产生器包括：
    第一脉冲产生器，用以在所述分频信号的信号电平翻转时产生第一清除信号，作为所述复位始能信号的第一部份；以及
    第二脉冲产生器，用以在所述分频信号的信号电平翻转时产生第二清除信号，作为所述复位始能信号的第二部份；
    其中所述处理电路根据所述第一清除信号复位所述第二计数器的计数值的最低有效位，以及根据所述第二清除信号复位所述第二计数器的计数值其他的比特位。
  10. 如权利要求1所述的模数转换电路，其特征在于，所述比较电路包括：
    第一比较器，用以接收所述模拟信号与所述第一斜坡信号，以将所述模拟信号与所述斜坡信号作比较；以及
    第二比较器，其中所述预定偏移是所述第二比较器固有的比较器偏移，所述第二比较器用以接收所述模拟信号与所述第一斜坡信号，以将所述模拟信号与所述斜坡信号加上所述预定偏移作比较。
  11. 如权利要求1所述的模数转换电路，其特征在于，所述比较电路包括：
    第一比较器，用以接收所述模拟信号与所述斜坡信号，以将所述模拟信号与所述斜坡信号作比较；以及
    第二比较器，用以接收所述斜坡信号的超前副本，其中所述斜坡信号的超前副本的信号电平等于所述斜坡信号的信号电平加上所述预定偏移；所述第二比较器通过对所述模拟信号与所述斜坡信号的超前副本进行比较，以将所述模拟信号与所述斜坡信号加上所述预定偏移作比较。
  12. 如权利要求1所述的模数转换电路，其特征在于，所述斜坡信号的信号电平加上所述预定偏移到达所述模拟信号的信号电平的时间，与所述斜坡信号的信号电平到达所述模拟信号的信号电平的时间两者之间的最短时间差，大于所述第一时钟信号的一个周期。
  13. 一种图像传感器，其特征在于，包括：
    像素阵列，包含排列成多行与多列的多个像素；
    控制电路，用以产生第一时钟信号、第二时钟信号以及斜坡信号，其中所述第一时钟信号的频率小于所述第二时钟信号的频率；以及
    至少一如权利要求1至12中任一项所述的模数转换电路，耦接于所述像素阵列与所述控制电路，用以将所述像素阵列中一列像素所产生的模拟信号转换为数字信号。
  14. 一种模数转换方法，其特征在于，包括：
    将模拟信号与斜坡信号作比较以产生第一比较信号；
    将所述模拟信号与所述斜坡信号加上预定偏移作比较以产生第二比较信号；以及
    在所述斜坡信号的信号电平交替地上升和下降的采样期间内：
    每当所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平时，对第一时钟信号的周期个数进行计数以获得第一计数值；
    每当所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平，而所述第二比较信号指示出所述模拟信号的信号电平小于所述斜坡信号的信号电平加上所述预定偏移时，对第二时钟信号的周期个数进行计数以获得第二计数值；
    在停止对所述第二时钟信号的周期个数进行计数时，将所述第二计数值储存为初始计数值；以及
    在所述第一计数值增加时，将所述第二计数值复位到所述初始计数值；
    其中所述第一计数值和所述第二计数值分别作为数字信号 的第一部分和第二部分。
  15. 如权利要求14所述的模数转换方法，其特征在于，将所述第二计数值复位到所述初始计数值的步骤是在对所述第二时钟信号的周期个数进行计数的期间所进行。
  16. 如权利要求15所述的模数转换方法，其特征在于，将所述第二计数值复位到所述初始计数值的步骤包括：
    在所述第一计数值增加时产生复位始能信号；以及
    根据所述复位始能信号将所述第二计数值复位到所述初始计数值。
  17. 如权利要求16所述的模数转换方法，其特征在于，在所述第一计数值增加时产生复位始能信号的步骤包括：
    检测所述第一时钟信号是否处在上升沿；以及
    当检测出所述第一时钟信号处在所述上升沿时，判断所述第一计数值会增加，并产生所述复位始能信号。
  18. 如权利要求17所述的模数转换方法，其特征在于，检测所述第一时钟信号是否处在所述上升沿的步骤包括：
    将所述第一时钟信号进行二分频以产生分频信号；以及
    在所述分频信号的信号电平翻转时，判断所述第一时钟信号处在所述上升沿。
  19. 如权利要求16所述的模数转换方法，其特征在于，所述复位始 能信号包括第一清除信号和第二清除信号；将所述第二计数值复位到所述初始计数值的步骤包括：
    根据所述第一清除信号复位所述第二计数值的最低有效位；以及
    根据所述第二脉冲信号复位所述第二计数值其他的比特位。
  20. 如权利要求14所述的模数转换方法，其特征在于，将所述模拟信号与所述斜坡信号加上所述预定偏移作比较的步骤包括：
    接收所述斜坡信号的超前副本，其中所述斜坡信号的超前副本的信号电平等于所述斜坡信号的信号电平加上所述预定偏移；以及
    将所述模拟信号与所述斜坡信号的超前副本进行比较，以将所述模拟信号与所述斜坡信号加上所述预定偏移作比较。
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