WO2022001643A1 - 模数转换方法、模数转换器及图像传感器 - Google Patents

模数转换方法、模数转换器及图像传感器 Download PDF

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Publication number
WO2022001643A1
WO2022001643A1 PCT/CN2021/099914 CN2021099914W WO2022001643A1 WO 2022001643 A1 WO2022001643 A1 WO 2022001643A1 CN 2021099914 W CN2021099914 W CN 2021099914W WO 2022001643 A1 WO2022001643 A1 WO 2022001643A1
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counting
counter
signal
analog
conversion
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PCT/CN2021/099914
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English (en)
French (fr)
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李志升
郭佳
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深圳市南北微电子技术有限公司
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Publication of WO2022001643A1 publication Critical patent/WO2022001643A1/zh
Priority to US18/080,144 priority Critical patent/US11870455B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/03—Digital function generators working, at least partly, by table look-up
    • G06F1/0321—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/56—Input signal compared with linear ramp

Definitions

  • the invention relates to the technical field of analog-to-digital conversion, in particular to an analog-to-digital conversion method, an analog-to-digital converter and an image sensor.
  • a basic image sensor consists of an array of pixels, an analog-to-digital converter (ADC), which converts analog signals from the array of pixels into digital signals.
  • ADC analog-to-digital converter
  • the conversion rate of the analog-to-digital converter directly affects the work efficiency of the image sensor, so it is necessary to increase the conversion rate of the analog-to-digital converter to improve the work efficiency of the image sensor.
  • the present invention aims to solve at least one of the technical problems existing in the prior art.
  • the present invention proposes an analog-to-digital conversion method.
  • a comparison signal is generated by comparing a ramp signal and an analog signal.
  • the segment counts the rising edge of the clock signal and the falling edge of the clock signal respectively to improve the counting accuracy of the digital-to-analog converter and shorten the conversion time.
  • the present invention also proposes an analog-to-digital converter for performing the above-mentioned analog-to-digital conversion method.
  • the present invention also provides an image sensor including the above analog-to-digital converter.
  • the analog-to-digital conversion method includes: in a first conversion period, resetting the ramp signal to a first reference level signal and using the first reference level signal as a starting level to generate a first a ramp signal; obtaining a first analog signal and comparing the first ramp signal and the first analog signal to generate a first comparison signal; obtaining a count clock signal and according to the first comparison signal, the count clock The signal generates a first count clock signal and a second count clock signal; the first counter counts in a first count direction according to the first count clock signal; the first comparison signal generates a signal inversion, and the first counter Stop counting, and the second counter starts counting in the second counting direction according to the second counting clock signal to complete the counting of the first conversion cycle; in the second conversion cycle, the counting directions of the first counter and the second counter are reversed , and keep the counting result of the first counter and the second counter as the starting value; reset the ramp signal to the second reference level signal and use the second reference level signal as the starting level to
  • the analog-to-digital conversion method has at least the following beneficial effects: in each conversion cycle, the first counting clock signal and the second counting clock signal are generated according to the first comparison signal, the second comparison signal, and the counting clock signal .
  • the first counter performs time-division counting along the preset direction according to the first counting clock signal and the second counter according to the second counting clock signal.
  • the first counter and the second counter perform counting switching, and output the conversion result according to the first counting result and the second counting result, which can realize the conversion step size of half a clock cycle , thereby shortening the conversion period and improving the conversion efficiency.
  • the first counter and the second counter switch the counting direction at the interval of two conversion cycles to realize double sampling of the first analog signal and the second analog signal to eliminate systematic errors.
  • the first counting direction and the second counting direction are opposite counting directions; or the first counting direction and the second counting direction are the same counting direction.
  • the first counting direction and the second counting direction are opposite counting directions; the first counting result and the second counting result are added by an adder to output a conversion result .
  • the first counting direction and the second counting direction are the same counting direction; the first counting result and the second counting result are subtracted by an adder to output a conversion result .
  • the first ramp signal and the second ramp signal are ramp signals from a low level to a high level; or the first ramp signal and the second ramp signal are from a high level to a high level. low level ramp signal.
  • the first reference level and the second reference level are the same level; or the first reference level and the second reference level are different levels.
  • the first counter is valid for counting the rising edges of the clock signal
  • the second counter is valid for counting the falling edges of the clock signal
  • the first counter is valid for counting the falling edges of the clock signal
  • the second counter is effective to count the rising edge of the clock signal
  • the analog-to-digital converter is used to execute the analog-to-digital conversion method of the above-mentioned embodiments.
  • the analog-to-digital converter according to the embodiment of the present invention has at least the following beneficial effects: in each conversion period of the analog-to-digital converter, the first counter according to the first count clock signal, the second counter according to the second count clock signal along the Preset direction for time division counting. Wherein, when the first comparison signal and the second comparison signal are inverted, the first counter and the second counter perform counting switching, and by outputting the conversion result according to the first counting result and the second counting result, the conversion of half a clock cycle can be realized. step size, thereby shortening the conversion period of the analog-to-digital converter and improving the conversion efficiency.
  • the first counter and the second counter switch the counting direction at the interval of two conversion cycles to realize double sampling of the first analog signal and the second analog signal to eliminate systematic errors.
  • An image sensor includes the above-mentioned analog-to-digital converter.
  • the image sensor according to the embodiment of the present invention has at least the following beneficial effects: in the image sensor, by setting the analog-to-digital converter in the above-mentioned embodiment, in each conversion cycle of the analog-to-digital converter, the first counter The counting clock signal and the second counter perform time-division counting along the preset direction according to the second counting clock signal. Wherein, when the first comparison signal and the second comparison signal are inverted, the first counter and the second counter perform counting switching, and by outputting the conversion result according to the first counting result and the second counting result, a half clock cycle can be realized.
  • the conversion step length is shortened, thereby shortening the conversion period of the analog-to-digital converter and improving the conversion efficiency of the analog-to-digital converter.
  • the first counter and the second counter switch the counting direction at the interval of two conversion cycles to realize double sampling of the first analog signal and the second analog signal to eliminate systematic errors.
  • FIG. 1 is a flowchart of an analog-to-digital conversion method according to an embodiment of the present invention
  • FIG. 2 is a schematic time sequence diagram of an analog-to-digital converter according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a signal flow of an analog-to-digital converter according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of counting conversion of an analog-to-digital converter according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a circuit structure of a comparator of an analog-to-digital converter according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of a clock control logic of an analog-to-digital converter according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a bit asynchronous counter of an analog-to-digital converter according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a circuit structure of a first counter unit bit of an analog-to-digital converter according to an embodiment of the present invention
  • FIG. 9 is a schematic diagram of a circuit structure of a second counter unit bit of an analog-to-digital converter according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a counter direction control sequence diagram of an analog-to-digital converter according to an embodiment of the present invention
  • FIG. 11 is a schematic diagram of a circuit structure of an adder of an analog-to-digital converter according to an embodiment of the present invention.
  • the azimuth description such as the azimuth or position relationship indicated by up, down, front, rear, left, right, etc.
  • the azimuth description is based on the azimuth or position relationship shown in the drawings, only In order to facilitate the description of the present invention and simplify the description, it is not indicated or implied that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present invention.
  • the meaning of several is one or more, the meaning of multiple is two or more, greater than, less than, exceeding, etc. are understood as not including this number, above, below, within, etc. are understood as including this number. If it is described that the first and the second are only for the purpose of distinguishing technical features, it cannot be understood as indicating or implying relative importance, or indicating the number of the indicated technical features or the order of the indicated technical features. relation.
  • the embodiments of the present invention provide an analog-to-digital conversion method and an analog-to-digital converter applied to an image sensor, which can improve the analog-to-digital conversion rate without increasing the instantaneous power consumption generated by the digital-to-analog conversion process.
  • analog-to-digital conversion methods and analog-to-digital converters in the following various embodiments can be applied to different imaging processing devices, and the description of the comparator, counter, and adder is only applicable
  • the exemplary description of the embodiment can be replaced by other electronic devices that can realize the same function according to the specific application environment.
  • an analog-to-digital conversion method includes: step S1, resetting the ramp signal to a first reference level signal and using the first reference level signal as a starting level to generate a first ramp signal; step S2 , obtain the first analog signal and compare the first ramp signal and the first analog signal to generate the first comparison signal; Step S3, generate the first count clock signal and the second count clock signal according to the first comparison signal and the count clock signal ; Step S4, the first counter counts according to the first counting clock signal according to the first counting direction; Step S5, the first comparison signal generates a signal overturn, the first counter stops counting, and the second counter starts counting according to the second counting clock signal according to the first count clock signal.
  • Step S6 Two counting directions are counted to complete the counting of the first conversion cycle; Step S6, the counting directions of the first counter and the second counter are reversed, and the counting results of the first counter and the second counter are kept as the initial value; Step S7, the The ramp signal is reset to the second reference level signal and the second reference level signal is used as the starting level to generate the second ramp signal; step S8, acquire the second analog signal and perform the second ramp signal and the second analog signal Compare to generate the second comparison signal; Step S9, generate the first count clock signal and the second count clock signal according to the second comparison signal and the count clock signal; Step S10, the first counter counts according to the first count clock signal; Step S11 , The second comparison signal generates a signal inversion, the first counter stops counting, and the second counter starts to count according to the second counting clock signal to complete the second conversion cycle count; Step S12, obtain the first count result of the first counter, the second counter The second count result of , output the conversion result according to the first count result and the second count result.
  • the first counter counts
  • the first counter and the second counter perform counting switching, and output the conversion result according to the first counting result and the second counting result, which can realize the conversion step size of half a clock cycle , thereby shortening the conversion period and improving the conversion efficiency.
  • the first counter and the second counter respectively perform effective counting on the rising edge and the falling edge of the clock signal
  • the counting step size of the first counter and the second counter is one counter clock cycle.
  • the first comparison signal is inverted
  • the first counter stops counting
  • the second counter starts counting.
  • the conversion result is output according to the first counting result and the second counting result, and a conversion step size of half a clock cycle can be realized, so as to shorten the conversion time of the actual counting of the digital-to-analog converter.
  • the conversion result is output by counting the first conversion period and the second conversion period, and processing the first counting result and the second counting result. Among them, the conversion result is the sum of the quantization result and the fixed deviation.
  • the clock logic controller generates the first count clock signal and the second count clock signal based on the first comparison signal and the count clock signal.
  • the first counter performs time-division counting according to the first counting clock signal and the second counter respectively along the preset direction according to the second counting clock signal. Different time periods of the same conversion cycle are time-divisionally counted by the first counter and the second counter to improve the counting precision and shorten the conversion time. In the same conversion cycle, the clock valid edges of the first counter and the second counter are different.
  • the clock logic controller receives the first comparison signal and performs logical operation processing to generate the first count clock signal and the second count clock signal and drive the first counter and the second counter to count. .
  • the first counter counts according to the first counting direction, and when the first comparison signal generated by the comparator turns over, the first counter stops counting; the second counter counts according to the second counting clock signal according to the second counting direction.
  • the first counter counts and performs single-edge counting along the first counting direction, and the second counter does not count; after the first comparison signal is inverted, the first counter Stop counting, and the second counter performs single-edge counting along the second counting direction.
  • the first ramp signal is reset, and the first counter and the second counter stop counting.
  • the first counter and the second counter may be configured to perform time-division and single-edge counting in opposite counting directions.
  • one of the first counter and the second counter counts, and the other counter stops counting.
  • the first counter and the second counter stop counting, and the counting directions of the first counter and the second counter are reversed. Wherein, the clock valid edges of the first counter and the second counter are different.
  • the first counter and the second counter may be configured to perform time-division and single-edge counting in the same counting direction.
  • one of the first counter and the second counter counts, and the other counter stops counting.
  • the first counter and the second counter stop counting, and the counting directions of the first counter and the second counter are reversed. Wherein, the clock valid edges of the first counter and the second counter are different.
  • the first count result and the second count result are subtracted by the adder to output the conversion result.
  • the first counter counts along the first counting direction
  • the second counter counts along the second counting direction.
  • the first count direction counts down and the second count direction counts up. That is, the first counter counts down and the falling edge is valid, and the second counter counts up and the rising edge is valid.
  • the counting in the first counting direction and the counting in the second counting direction may be other counting directions.
  • the first count direction counts up and the second count direction counts down.
  • the second ramp signal is generated with the second reference level signal as the reference signal, and the second ramp signal is compared with the second analog signal to generate the second comparison signal
  • the clock logic controller generates a first count clock signal and a second count clock signal according to the second comparison signal and the count clock signal; the first counter performs time-division counting according to the first count clock signal and the second counter according to the second count clock signal.
  • the counting directions of the first counter and the second counter are both switched to opposite counting directions. That is, the first counter and the second counter both reversely switch the counting direction before the next conversion cycle starts.
  • the first counter counts down and the falling edge is valid, the second counter counts up and the rising edge is valid; in the second conversion cycle, the first counter counts up and the falling edge is valid, and the second counter counts down Counting and valid on rising edge.
  • the first counter counts in the reverse direction of the first counting direction according to the first counting clock signal, and further includes: when the second comparison signal generated by the comparator turns over, the first counter stops counting; the second counter counts according to the second The count clock signal counts in the reverse direction of the second count direction.
  • the first count result and the second count result obtained by the first counter and the second counter are respectively outputted to the adder and added to output the count result.
  • the clock logic controller is used to determine whether the first comparison signal and the second comparison signal are inverted to switch the counting states of the first counter and the second counter. For example, when a signal inversion occurs in the first comparison signal, the first counter stops counting, and the second counter starts counting; when a signal inversion occurs in the second comparison signal, the first counter stops counting, and the second counter starts counting.
  • the first counter and the second counter both stop counting.
  • the counting results of the first counter and the second counter are added by the adder to obtain the conversion result of the analog-to-digital converter, and the conversion result is the sum of the quantization result and the fixed deviation.
  • the analog-to-digital converter made based on the above-mentioned analog-to-digital conversion method can correctly convert the difference between the first analog signal and the second analog signal, and use the first counter and the second counter to switch counts between two conversion cycles. direction to achieve double sampling of the first analog signal and the second analog signal to eliminate systematic errors. And the count step is half a clock cycle. Assuming that an analog-to-digital conversion resolution of L bits needs to be obtained, the working time is 2 L-1 clock cycles.
  • the conversion result of the signal inversion of the first comparison signal and the second comparison signal occurring when the clock signal is at a high level or a low level will be described below.
  • the first counter is a counter valid at the falling edge of the clock
  • the second counter is a counter valid at the rising edge of the clock.
  • Q represents the initial value of the first counter
  • P represents the initial value of the second counter
  • the dotted line represents the inversion position of the comparison signal in different count periods.
  • the first counting situation the first comparison signal and the second comparison signal respectively have signal inversions, and the clock signals corresponding to the inversion positions of the first comparison signal and the second comparison signal are both low level.
  • the first count result of the first counter starts to count down from the initial value Q, when the first comparison signal turns over, the first counter stops counting, and the count value is Q-2; the second counter Counting up from the initial value P until the end of the first conversion period, the second counter stops counting, and the count value is P+3.
  • the first counter and the second counter stop counting at the interval of the first conversion period and the second conversion period.
  • the first counter starts to count up from the end value Q-2 of the first conversion cycle.
  • the second comparison signal turns over, the first counter stops counting, and the count value is Q+2;
  • the second counter Counting down from the end value P+3 of the first conversion period until the end of the second conversion period, the second counter stops counting, and the count value is P+1.
  • the final conversion result (the sum of the count value of the first counter and the count value of the second counter) is P+Q+3;
  • the second counting condition the first comparison signal and the second comparison signal respectively have signal inversion, and the clock signal corresponding to the inversion position of the first comparison signal is low, and the clock signal corresponding to the inversion position of the second comparison signal is high level.
  • the first counter starts to count down from the initial value Q, when the first comparison signal turns over, the first counter stops counting, and the count value is Q-2; the second counter starts from the initial value P Start to count up until the end of the first conversion cycle, the second counter stops counting, and the count value is P+3.
  • the first counter and the second counter stop counting at the interval of the first conversion period and the second conversion period.
  • the first counter starts to count up from the end value Q-2 of the first conversion cycle.
  • the second comparison signal turns over, the first counter stops counting, and the count value is Q+1;
  • the second counter Counting down from the end value P+3 of the first conversion period until the end of the second conversion period, the second counter stops counting, and the count value is P+1.
  • the final conversion result (the sum of the count value of the first counter and the count value of the second counter) is P+Q+2;
  • the third counting state the first comparison signal and the second comparison signal are respectively inverted, and the clock signal corresponding to the inversion position of the first comparison signal is high, and the clock signal corresponding to the inversion position of the second comparison signal is low level.
  • the first counter starts counting down from the initial value Q, when the first comparison signal turns over, the first counter stops counting, and the count value is Q-1; the second counter starts from the initial value P Start to count up until the end of the first conversion cycle, the second counter stops counting, and the count value is P+3.
  • the first counter and the second counter stop counting at the interval of the first conversion period and the second conversion period.
  • the first counter starts to count up from the end value Q-1 of the first conversion cycle.
  • the second comparison signal turns over, the first counter stops counting, and the count value is Q+3;
  • the second counter Counting down from the end value P+3 of the first conversion period until the end of the second conversion period, the second counter stops counting, and the count value is P+1.
  • the final conversion result (the sum of the count value of the first counter and the count value of the second counter) is P+Q+4;
  • the fourth counting condition the first comparison signal and the second comparison signal are respectively inverted, and the clock signal corresponding to the inversion position of the first comparison signal is high, and the clock signal corresponding to the inversion position of the first comparison signal is high level.
  • the first counter starts counting down from the initial value Q, when the first comparison signal turns over, the first counter stops counting, and the count value is Q-1; the second counter starts from the initial value P Start to count up until the end of the first conversion cycle, the second counter stops counting, and the count value is P+3.
  • the first counter and the second counter stop counting at the interval of the first conversion period and the second conversion period.
  • the first counter starts to count up from the end value Q-1 of the first conversion cycle.
  • the second comparison signal turns over, the first counter stops counting, and the count value is Q+2; the second counter Counting down from the end value P+3 of the first conversion period until the end of the second conversion period, the second counter stops counting, and the count value is P+1.
  • the final conversion result (the sum of the count value of the first counter and the count value of the second counter) is P+Q+3.
  • the analog-to-digital conversion method can realize a conversion step size of half a clock cycle, thereby improving the efficiency of the analog-to-digital conversion.
  • the first ramp signal and the second ramp signal are ramp signals from a low level to a high level; or the first ramp signal and the second ramp signal are ramp signals from a high level to a low level .
  • the analog-to-digital converter is suitable for different digital-to-analog conversion scenarios.
  • FIG. 5 is a schematic structural diagram of a comparator of an analog-to-digital converter according to an embodiment of the present invention.
  • Vramp is the ramp signal
  • Vin is the analog input signal
  • VBIASN is the bias voltage of the current mirror tube M5 and the current mirror tube M6, and Vout is the output signal of the comparator.
  • the bias voltage of the current mirror tube M5 and the current mirror tube M6 By controlling the bias voltage of the current mirror tube M5 and the current mirror tube M6 to control the current of the current mirror tube M5 and the current mirror tube M6; by comparing the ramp signal Vramp and the analog input signal Vin to generate a comparison signal and use it as a comparator Output signal Vout.
  • the output signal Vout drives the first counter and the second counter through the clock control logic.
  • the output signal Vout drives the first counter to stop counting and the second counter to start counting.
  • the counting clock and the output signal of the comparator generate the first counting clock signal and the second counting clock signal through the clock control logic to drive the first counter and the second counter respectively, so that the first counter and the second counter are realized. Tick count.
  • the counter includes several bits, which can be implemented as an asynchronous counter, that is, several bits are sequentially connected with signals.
  • the initial counter clock is only used as the count clock of the lowest bit, and the input count clock of the remaining bits is the count output of the previous bit.
  • BIT is the output signal of the current bit of the counter
  • BIT_PRE is the output signal of the previous bit of the counter
  • CNT_INVERT and CNT_KEEP are the control signals required to control the counting direction of the counter.
  • Each bit of the first counter and the second counter outputs the output signal BIT of the current bit of the counter according to the control signal CNT_INVERT, the control signal CNT_KEEP, and the input signal BIT_PRE.
  • the output signal BIT of the previous bit of the counter is output to the BIT_PRE of the current bit of the counter, the current bit of the counter is counted and the output signal BIT of the current bit of the counter is output to the next bit of the counter.
  • the control signal CNT_INVERT and the control signal CNT_KEEP of different bits may be the same control signal.
  • control signal CNT_INVERT is level inverted to reverse the counting direction of the first counter and the second counter.
  • the control signal CNT_KEEP needs to be inverted in CNT_INVERT. Goes high before transition and goes back low before the start of the second transition cycle.
  • the adder adds the output results of the first counter and the second counter to obtain the final analog-to-digital conversion result. As shown in FIG. 11 , the adder starts from the lowest bit and adds the first counter and the second counter bit by bit, and each adder clock cycle completes the addition of one bit until the highest bit.
  • an analog-to-digital converter is also provided, and the analog-to-digital converter is used to perform the analog-to-digital conversion method of the above-mentioned embodiments.
  • the first counter performs time-division counting along a preset direction according to the first counting clock signal and the second counter according to the second counting clock signal.
  • the first counter and the second counter perform counting switching, that is, at the same moment when the first counter stops counting, the second counter starts counting, and the valid edges of the clocks of the two are different.
  • an image sensor is also provided, including the analog-to-digital converter of the above-mentioned embodiments.
  • the first counter and the second counter perform counting switching, and according to the first counting result, the second counting As a result, the conversion result is output, and a conversion step length of half a clock cycle can be realized, so as to shorten the conversion period of the analog-to-digital converter and improve the conversion efficiency of the analog-to-digital converter.

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Abstract

本发明公开了一种模数转换方法、模数转换器及图像传感器，其中，模数转换方法，包括第一转换周期和第二转换周期：第一转换周期和第二转换周期中，第一计数器根据第一计数时钟信号、第二计数器根据第二计数时钟信号进行分时计数；第二转换周期中，第一计数器、第二计数器的计数方向发生反转，并保持第一转换周期的计数结果作为第二转换周期的起始值；根据第一计数结果、第二计数结果输出转换结果。本发明通过第一计数器、第二计数器在两个转换周期的间隔切换计数方向以实现对第一模拟信号和第二模拟信号的双采样以消除系统误差。通过第一计数器、第二计数器在一个转换周期内进行分时计数以提高计数精度及缩短转换时间。

Description

模数转换方法、模数转换器及图像传感器 技术领域
本发明涉及模数转换技术领域，尤其是涉及一种模数转换方法、模数转换器及图像传感器。
背景技术
目前，图像传感器通过半导体的光电二极管对入射光进行响应以将光信号转换为电信号，从而生成图像。基础的图像传感器由像素阵列、模数转换器(ADC)构成，模数转换器将来自像素阵列的模拟信号转换成数字信号。
模数转换器的转换速率直接影响图像传感器的工作效率，因而需提高模数转换器的转换速率以提高图像传感器的工作效率。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一。为此，本发明提出一种模数转换方法，在不同转换周期中，通过对斜坡信号和模拟信号进行比较以生成比较信号，第一计数器和第二计数器对比较信号发生信号翻转前后的不同时间段分别进行时钟信号上升沿、时钟信号下降沿计数以提高数模转换器的计数精度及缩短转换时间。
本发明还提出一种用于执行上述模数转换方法的模数转换器。
本发明还提出一种包括上述模数转换器的图像传感器。
根据本发明的第一方面实施例的模数转换方法，包括：第一转换周期中，将斜坡信号复位至第一参考电平信号并将第一参考电平信号作为起始电平以生成第一斜坡信号；获取第一模拟信号并对所述第一斜坡信号、所述第一模拟信号进行比较以生成第一比较信号；获取计数时钟信号并根据所述第一比较信号、所述计数时钟信号生成第一计数时钟信号和第二计数时钟信号；所述第一计数器根据所述第一计数时钟信号按第一计数方向进行计数；所述第一比较信号发生信号翻转，所述第一计数器停止计数、第二计数器开始根据第二计数时钟信号按第二计数方向计数以完成第一转换周期计数；第二转换周期中，所述第一计数器、所述 第二计数器的计数方向发生反转，并保持第一计数器和第二计数器的计数结果作为起始值；将所述斜坡信号复位至第二参考电平信号并将所述第二参考电平信号作为起始电平以生成第二斜坡信号；获取第二模拟信号并对所述第二斜坡信号、所述第二模拟信号进行比较以生成第二比较信号；根据所述第二比较信号、计数时钟信号生成第一计数时钟信号和第二计数时钟信号；所述第一计数器根据所述第一计数时钟信号进行计数；所述第二比较信号发生信号翻转，所述第一计数器停止计数、第二计数器开始根据第二计数时钟信号计数以完成第二转换周期计数；获取所述第一计数器的第一计数结果、所述第二计数器的第二计数结果，根据所述第一计数结果、所述第二计数结果输出转换结果；其中，第二转换周期中，所述第一计数器沿第一计数方向的相反方向进行计数；所述第二计数器沿第二计数方向的相反方向进行计数。通过获取所述第一计数器的第一计数结果、所述第二计数器的第二计数结果，并根据所述第一计数结果、所述第二计数结果输出转换结果。
根据本发明实施例的模数转换方法，至少具有如下有益效果：在每个转换周期中，根据第一比较信号和第二比较信号、计数时钟信号生成第一计数时钟信号和第二计数时钟信号。第一计数器根据第一计数时钟信号、第二计数器根据第二计数时钟信号沿着预设方向进行分时计数。当第一比较信号和第二比较信号发生信号翻转时，第一计数器、第二计数器进行计数切换，根据第一计数结果、第二计数结果输出转换结果，可以实现半个时钟周期的转换步长，从而缩短转换周期、提高转换效率。通过第一计数器、第二计数器在两个转换周期的间隔切换计数方向以实现对第一模拟信号和第二模拟信号的双采样以消除系统误差。
根据本发明的一些实施例，还包括：所述第一计数方向和第二计数方向为相反的计数方向；或所述第一计数方向和第二计数方向为相同的计数方向。
根据本发明的一些实施例，当所述第一计数方向和第二计数方向为相反计数方向；通过加法器将所述第一计数结果、所述第二计数结果进行相加处理以输出转换结果。
根据本发明的一些实施例，当所述第一计数方向和第二计数方向为相同计数方向；通过加法器将所述第一计数结果、所述第二计数结果进行相减处理以输出转换结果。
根据本发明的一些实施例，所述第一斜坡信号和第二斜坡信号为从低电平到高电平的斜坡信号；或所述第一斜坡信号和第二斜坡信号为从高电平到低电平的斜坡信号。
根据本发明的一些实施例，所述第一参考电平、所述第二参考电平为相同电平；或所述第一参考电平、所述第二参考电平为不同电平。
根据本发明的一些实施例，所述第一计数器对时钟信号的上升沿计数有效，所述第二计数器对时钟信号的下降沿计数有效；或所述第一计数器对时钟信号的下降沿计数有效，所述第二计数器对时钟信号的上升沿计数有效。
根据本发明的第二方面实施例的模数转换器，模数转换器用于执行上述实施例的模数转换方法。
根据本发明实施例的模数转换器，至少具有如下有益效果：在模数转换器的每个转换周期中，第一计数器根据第一计数时钟信号、第二计数器根据第二计数时钟信号沿着预设方向进行分时计数。其中，第一比较信号和第二比较信号发生信号翻转时，第一计数器、第二计数器进行计数切换，通过根据第一计数结果、第二计数结果输出转换结果，可以实现半个时钟周期的转换步长，从而缩短模数转换器的转换周期、提高转换效率。通过第一计数器、第二计数器在两个转换周期的间隔切换计数方向以实现对第一模拟信号和第二模拟信号的双采样以消除系统误差。
根据本发明的第三方面实施例的图像传感器，包括上述模数转换器。
根据本发明实施例的图像传感器，至少具有如下有益效果：在图像传感器中，通过设置上述实施例中的模数转换器，在模数转换器的每个转换周期中，第一计数器根据第一计数时钟信号、第二计数器根据第二计数时钟信号沿着预设方向进行分时计数。其中，在第一比较信号和第二比较信号发生信号翻转时，第一计数器、第二计数器进行计数切换，通过根据第一计数结果、第二计数结果输出转换结果，可以实现半个时钟周期的转换步长，从而缩短模数转换器的转换周期、提高模数转换器的转换效率。通过第一计数器、第二计数器在两个转换周期的间隔切换计数方向以实现对第一模拟信号和第二模拟信号的双采样以消除系统误差。
本发明的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。
附图说明
本发明的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解，其中：
图1为本发明实施例一种模数转换方法的流程图；
图2为本发明实施例一种模数转换器的时序示意图；
图3为本发明实施例一种模数转换器的信号流向示意图；
图4为本发明实施例一种模数转换器的计数转换示意图；
图5为本发明实施例一种模数转换器的比较器的电路结构示意图；
图6为本发明实施例一种模数转换器的时钟控制逻辑示意图；
图7为本发明实施例一种模数转换器的比特异步计数器示意图；
图8为本发明实施例一种模数转换器的第一计数器单比特位的电路结构示意图；
图9为本发明实施例一种模数转换器的第二计数器单比特位的电路结构示意图；
图10为本发明实施例一种模数转换器的计数器方向控制时序示意图；
图11为本发明实施例一种模数转换器的加法器的电路结构示意图。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
在本发明的描述中，需要理解的是，涉及到方位描述，例如上、下、前、后、左、右等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明的描述中，若干的含义是一个或者多个，多个的含义是两个以上，大于、小于、超过等理解为不包括本数，以上、以下、以内等理解为包括本数。如果有描述到第一、第二只是用于区分技术特征为目的，而不能理解为指示或暗 示相对重要性或者隐含指明所指示的技术特征的数量或者隐含指明所指示的技术特征的先后关系。
本发明的描述中，除非另有明确的限定，设置、安装、连接等词语应做广义理解，所属技术领域技术人员可以结合技术方案的具体内容合理确定上述词语在本发明中的具体含义。
在半导体器件成像中，模数转换器的转换速率将直接影响图像传感器的工作效率，因此，如何提高模数转换器的转换速率以提高图像传感器的工作效率成为一个待解决的技术问题。
基于此，本发明实施例提供了应用于图像传感器的模数转换方法、模数转换器，能够不增加数模转换过程所产生的瞬时功耗的情况下提高模数转换速率。
需要说明的是，根据具体需要，下列多种实施例中的模数转换方法、模数转换器可被运用至不同的成像处理装置中，且对比较器、计数器、加法器的描述仅为可实施方式的示范性说明，根据具体应用环境可使用其他可实现相同功能的电子器件进行替换。
请参照图1，一种模数转换方法，包括：步骤S1、将斜坡信号复位至第一参考电平信号并将第一参考电平信号作为起始电平以生成第一斜坡信号；步骤S2、获取第一模拟信号并对第一斜坡信号、第一模拟信号进行比较以生成第一比较信号；步骤S3、根据第一比较信号、计数时钟信号生成第一计数时钟信号和第二计数时钟信号；步骤S4、第一计数器根据第一计数时钟信号按第一计数方向进行计数；步骤S5、第一比较信号发生信号翻转，第一计数器停止计数、第二计数器开始根据第二计数时钟信号按第二计数方向计数以完成第一转换周期计数；步骤S6、第一计数器、第二计数器的计数方向发生反转，并保持第一计数器和第二计数器的计数结果作为起始值；步骤S7、将斜坡信号复位至第二参考电平信号并将第二参考电平信号作为起始电平以生成第二斜坡信号；步骤S8、获取第二模拟信号并对第二斜坡信号、第二模拟信号进行比较以生成第二比较信号；步骤S9、根据第二比较信号、计数时钟信号生成第一计数时钟信号和第二计数时钟信号；步骤S10、第一计数器根据第一计数时钟信号进行计数；步骤S11、第二比较信号发生信号翻转，第一计数器停止计数、第二计数器开始根据第二计数时钟信号计数以完成第二转换周期计数；步骤S12、获取第一计数器的第一计 数结果、第二计数器的第二计数结果，根据第一计数结果、第二计数结果输出转换结果。其中，第一计数器沿第一计数方向的相反方向进行计数；第二计数器沿第二计数方向的相反方向进行计数。
当第一比较信号和第二比较信号发生信号翻转时，第一计数器、第二计数器进行计数切换，根据第一计数结果、第二计数结果输出转换结果，可以实现半个时钟周期的转换步长，从而缩短转换周期、提高转换效率。
例如，第一计数器、第二计数器分别对时钟信号的上升沿、下降沿进行有效计数，第一计数器、第二计数器的计数步长为一个计数器时钟周期。当第一比较信号发生信号翻转，第一计数器停止计数，且在同一时刻，第二计数器开始计数。根据第一计数结果、第二计数结果输出转换结果，可以实现半个时钟周期的转换步长，以缩短数模转换器的实际计数的转换时间。
通过对第一转换周期、第二转换周期进行计数，并对第一计数结果、第二计数结果进行处理以输出转换结果。其中，转换结果为量化结果与固定偏差之和。
在一些实施例中，时钟逻辑控制器根据第一比较信号、计数时钟信号生成第一计数时钟信号和第二计数时钟信号。第一计数器根据第一计数时钟信号、第二计数器根据第二计数时钟信号分别沿着预设方向进行分时计数。通过第一计数器、第二计数器对同一转换周期的不同时间段进行分时计数以提高计数精度及缩短转换时间。同一转换周期内，第一计数器、第二计数器的时钟有效边沿不同。
请一并参照图2、图3，通过时钟逻辑控制器接收第一比较信号并进行逻辑运算处理以生成第一计数时钟信号和第二计数时钟信号并驱动进行第一计数器、第二计数器进行计数。
第一计数器按第一计数方向进行计数，当比较器生成的第一比较信号发生信号翻转，则第一计数器停止计数；第二计数器根据第二计数时钟信号按第二计数方向进行计数。在第一转换周期中，第一比较信号发生信号翻转前，第一计数器进行计数沿着第一计数方向进行单边沿计数，第二计数器不计数；第一比较信号发生信号翻转后，第一计数器停止计数，第二计数器沿着第二计数方向进行单边沿计数。当第一转换周期完成，第一斜坡信号发生复位，第一计数器、第二计数器停止计数。
在一些实施例中，第一计数器、第二计数器可设置为按相反的计数方向进行 分时单边沿计数。
在同一转换周期中，第一计数器、第二计数器中的一个计数器进行计数，另一个计数器停止计数。每完成一个转换周期，第一计数器、第二计数器均停止计数，且第一计数器、第二计数器的计数方向均发生反转。其中，第一计数器、第二计数器的时钟有效边沿不同。当所有转换周期结束，通过加法器将第一计数结果、第二计数结果进行相加处理以输出转换结果。
在一些实施例中，第一计数器、第二计数器可设置为按相同的计数方向进行分时单边沿计数。
在同一转换周期中，第一计数器、第二计数器中的一个计数器进行计数，另一个计数器停止计数。每完成一个转换周期，第一计数器、第二计数器停止计数，第一计数器、第二计数器的计数方向均发生反转。其中，第一计数器、第二计数器的时钟有效边沿不同。通过加法器将第一计数结果、第二计数结果进行相减处理以输出转换结果。
本实施例中，第一计数器沿着第一计数方向计数，第二计数器沿着第二计数方向计数。第一计数方向计数为向下，第二计数方向计数为向上。即第一计数器向下计数且下降沿有效，第二计数器向上计数且上升沿有效。
在其他实施例中，根据具体设置要求，第一计数方向计数、第二计数方向计数可为其他计数方向。例如，第一计数方向计数为向上，第二计数方向计数为向下。
请再参图1、图2，在第二转换周期中，以第二参考电平信号为基准信号生成第二斜坡信号，第二斜坡信号与第二模拟信号进行比较以生成第二比较信号，时钟逻辑控制器根据第二比较信号、计数时钟信号生成第一计数时钟信号和第二计数时钟信号；第一计数器根据第一计数时钟信号、第二计数器根据第二计数时钟信号进行分时计数。当第一计数器、第二计数器由第一转换周期切换至第二转换周期时，第一计数器、第二计数器的计数方向均切换为相反的计数方向。即第一计数器、第二计数器在下一个转换周期开始之前均对计数方向进行反向切换。
在第一转换周期中，第一计数器向下计数且下降沿有效，第二计数器向上计数且上升沿有效；在第二转换周期中，第一计数器向上计数且下降沿有效，第二计数器向下计数且上升沿有效。
其中，第一计数器根据第一计数时钟信号按第一计数方向的反向进行计数，还包括：当比较器生成的第二比较信号发生信号翻转，第一计数器停止计数；第二计数器根据第二计数时钟信号按第二计数方向的反向进行计数。通过分别将第一计数器、第二计数器所获得第一计数结果、第二计数结果输出至加法器并进行相加处理以输出计数结果。
具体地，通过时钟逻辑控制器判断第一比较信号、第二比较信号是否发生信号翻转以切换第一计数器、第二计数器的计数状态。例如，当第一比较信号发生信号翻转，第一计数器停止计数，第二计数器开始计数；当第二比较信号发生信号翻转，第一计数器停止计数，第二计数器开始计数。
当第二转换周期完成，斜坡信号发生复位，则第一计数器、第二计数器均停止计数。通过加法器对第一计数器、第二计数器的计数结果进行相加处理以获得模数转换器的转换结果，转换结果为量化结果与固定偏差之和。
基于上述的模数转换方法所制作的模数转换器能够对第一模拟信号、第二模拟信号的差值进行正确的转换，通过第一计数器、第二计数器在两个转换周期的间隔切换计数方向以实现对第一模拟信号和第二模拟信号的双采样以消除系统误差。且计数步长为半个时钟周期。假设需获得L比特位的模数转换分辨率，则工作时长为2 L-1个时钟周期。
参照图4，以下对数模转换器中，第一比较信号和第二比较信号发生信号翻转发生在时钟信号为高电平或低电平时的转换结果进行说明。
其中，第一计数器为时钟下降沿有效的计数器，第二计数器为时钟上升沿有效的计数器。Q代表第一计数器的起始值，P代表第二计数器的起始值，虚线代表不同计数周期的比较信号翻转位置。
第一种计数状况：第一比较信号和第二比较信号分别发生信号翻转，且第一比较信号和第二比较信号的翻转位置对应的时钟信号均为低电平。
在第一转换周期中，第一计数器的第一计数结果从起始值Q开始向下计数，当第一比较信号发生信号翻转，第一计数器停止计数，计数值为Q-2；第二计数器从起始值P开始向上计数，直至第一转换周期结束，第二计数器停止计数，计数值为P+3。
第一计数器和第二计数器在第一转换周期和第二转换周期的间隔停止计数。
在第二转换周期中，第一计数器从第一转换周期的结束值Q-2开始向上计数，当第二比较信号发生信号翻转，第一计数器停止计数，计数值为Q+2；第二计数器从第一转换周期的结束值P+3开始向下计数，直至第二转换周期结束，第二计数器停止计数，计数值为P+1。最终转换结果(第一计数器的计数值与第二计数器的计数值之和)为P+Q+3；
第二种计数状况：第一比较信号和第二比较信号分别发生信号翻转，且第一比较信号的翻转位置对应的时钟信号为低电平，第二比较信号的翻转位置对应的时钟信号为高电平。
在第一转换周期中，第一计数器从起始值Q开始向下计数，当第一比较信号发生信号翻转，第一计数器停止计数，计数值为Q-2；第二计数器从起始值P开始向上计数，直至第一转换周期结束，第二计数器停止计数，计数值为P+3。
第一计数器和第二计数器在第一转换周期和第二转换周期的间隔停止计数。
在第二转换周期中，第一计数器从第一转换周期的结束值Q-2开始向上计数，当第二比较信号发生信号翻转，第一计数器停止计数，计数值为Q+1；第二计数器从第一转换周期的结束值P+3开始向下计数，直至第二转换周期结束，第二计数器停止计数，计数值为P+1。最终转换结果(第一计数器的计数值与第二计数器的计数值之和)为P+Q+2；
第三种计数状况：第一比较信号和第二比较信号分别发生信号翻转，且第一比较信号的翻转位置对应的时钟信号为高电平，第二比较信号的翻转位置对应的时钟信号为低电平。
在第一转换周期中，第一计数器从起始值Q开始向下计数，当第一比较信号发生信号翻转，第一计数器停止计数，计数值为Q-1；第二计数器从起始值P开始向上计数，直至第一转换周期结束，第二计数器停止计数，计数值为P+3。
第一计数器和第二计数器在第一转换周期和第二转换周期的间隔停止计数。
在第二转换周期中，第一计数器从第一转换周期的结束值Q-1开始向上计数，当第二比较信号发生信号翻转，第一计数器停止计数，计数值为Q+3；第二计数器从第一转换周期的结束值P+3开始向下计数，直至第二转换周期结束，第二计数器停止计数，计数值为P+1。最终转换结果(第一计数器的计数值与第二计数器的计数值之和)为P+Q+4；
第四种计数状况：第一比较信号和第二比较信号分别发生信号翻转，且第一比较信号的翻转位置对应的时钟信号为高电平，第一比较信号的翻转位置对应的时钟信号为高电平。
在第一转换周期中，第一计数器从起始值Q开始向下计数，当第一比较信号发生信号翻转，第一计数器停止计数，计数值为Q-1；第二计数器从起始值P开始向上计数，直至第一转换周期结束，第二计数器停止计数，计数值为P+3。
第一计数器和第二计数器在第一转换周期和第二转换周期的间隔停止计数。
在第二转换周期中，第一计数器从第一转换周期的结束值Q-1开始向上计数，当第二比较信号发生信号翻转，第一计数器停止计数，计数值为Q+2；第二计数器从第一转换周期的结束值P+3开始向下计数，直至第二转换周期结束，第二计数器停止计数，计数值为P+1。最终转换结果(第一计数器的计数值与第二计数器的计数值之和)为P+Q+3。
参照图4，由上述描述可知，在不同的计数状况中，当第一比较信号的翻转时刻差异跨越时钟边沿也就是半个钟周期时，最终转换结果差1；当第二比较信号的翻转时刻差异跨越时钟边沿也就是半个钟周期时，最终转换结果差1。因此，本模数转换方法可以实现半个时钟周期的转换步长，从而提高了模数转换的效率。
在一些实施例中，第一斜坡信号和第二斜坡信号为从低电平到高电平的斜坡信号；或第一斜坡信号和第二斜坡信号为从高电平到低电平的斜坡信号。通过设置不同的斜坡信号类型，以使模数转换器适用于不同的数模转换场景。
参照图5，图5为本发明实施例一种模数转换器的比较器结构示意图。其中，Vramp为斜坡信号、Vin为模拟输入信号、VBIASN为电流镜管M5和电流镜管M6的偏置电压、Vout为比较器的输出信号。
通过控制电流镜管M5、电流镜管M6的偏置电压以控制电流镜管M5、电流镜管M6的电流；通过对斜坡信号Vramp、模拟输入信号Vin进行比较以生成比较信号并作为比较器的输出信号Vout。输出信号Vout通过时钟控制逻辑器驱动第一计数器和第二计数器。当对斜坡信号Vramp、模拟输入信号Vin进行比较所生成的比较信号发生信号翻转时，输出信号Vout驱动第一计数器停止计数、第二计数器开始计数。
参照图6，计数时钟和比较器输出信号通过时钟控制逻辑器生成第一计数时钟信号和第二计数时钟信号分别对第一计数器、第二计数器进行驱动，以使第一计数器、第二计数器实现分时计数。
参照图7，计数器包括若干比特位，其实现方式可为异步计数器，即若干比特位依次信号连接。初始计数器时钟仅作为最低比特位的计数时钟，其余比特位的输入计数时钟为前一比特位的计数输出。
参照图8、图9，BIT为计数器当前比特位的输出信号、BIT_PRE为计数器前一级比特位的输出信号、CNT_INVERT和CNT_KEEP为控制计数器计数方向所需的控制信号。第一计数器和第二计数器的各比特位根据控制信号CNT_INVERT、控制信号CNT_KEEP、输入信号BIT_PRE以输出计数器当前比特位的输出信号BIT。
计数器前一级比特位的输出信号BIT输出至计数器当前比特位的BIT_PRE，计数器当前比特位进行计数处理并输出计数器当前比特位的输出信号BIT至计数器下一比特位。其中，不同比特位的控制信号CNT_INVERT、控制信号CNT_KEEP可为相同的控制信号。
如图10所示，在第一转换周期和第二转换周期的间隔，控制信号CNT_INVERT发生电平反转，以反转第一计数器和第二计数器的计数方向，同时控制信号CNT_KEEP需在CNT_INVERT反转前变为高电平，并在第二转换周期开始前变回低电平。
请参照图11，当经历完第一转换周期、第二转换周期，加法器将第一计数器、第二计数器的输出结果进行加法计算以得到最终的模数转换结果。如图11所示，加法器由最低比特位开始计算以第一计数器、第二计数器按比特位依次相加，且每个加法器时钟周期完成一个比特位的相加，直到最高比特位。
在一些实施例中还提供一种模数转换器，模数转换器用于执行上述实施例的模数转换方法。
在模数转换器中，第一计数器根据第一计数时钟信号、第二计数器根据第二计数时钟信号沿着预设方向进行分时计数。其中，第一比较信号发生信号翻转时，第一计数器、第二计数器进行计数切换，即在第一计数器停止计数的同一时刻，第二计数器开始计数，且两者的时钟有效边沿不同。通过根据第一计数结果、第 二计数结果输出转换结果，可以实现半个时钟周期的转换步长，以缩短模数转换器的转换周期、提高转换效率。
在一些实施例中还提供一种图像传感器，包括上述实施例的模数转换器。
在图像传感器中，通过设置上述实施例中的模数转换器，其中，在第一比较信号发生信号翻转时，第一计数器、第二计数器进行计数切换，通过根据第一计数结果、第二计数结果输出转换结果，可以实现半个时钟周期的转换步长，以缩短模数转换器的转换周期、提高模数转换器的转换效率。
上面结合附图对本发明实施例作了详细说明，但是本发明不限于上述实施例，在所属技术领域普通技术人员所具备的知识范围内，还可以在不脱离本发明宗旨的前提下作出各种变化。
以上所描述的装置实施例仅仅是示意性的，其中作为分离部件说明的单元可以是或者也可以不是物理上分开的，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示意性实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
尽管已经示出和描述了本发明的实施例，本领域的普通技术人员可以理解：在不脱离本发明的原理和宗旨的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由权利要求及其等同物限定。

Claims (9)

  1. 一种模数转换方法，其特征在于，包括第一转换周期和第二转换周期：
    第一转换周期中，将斜坡信号复位至第一参考电平信号并将所述第一参考电平信号作为起始电平以生成第一斜坡信号；
    获取第一模拟信号并对所述第一斜坡信号、所述第一模拟信号进行比较以生成第一比较信号；
    获取计数时钟信号并根据所述第一比较信号、所述计数时钟信号生成第一计数时钟信号和第二计数时钟信号；
    第一计数器根据所述第一计数时钟信号按第一计数方向进行计数；
    所述第一比较信号发生信号翻转，所述第一计数器停止计数；第二计数器开始根据所述第二计数时钟信号按第二计数方向计数以完成第一转换周期的计数；
    第二转换周期中，所述第一计数器、所述第二计数器的计数方向发生反转，并保持所述第一计数器和所述第二计数器的计数结果作为起始值；
    将所述斜坡信号复位至第二参考电平信号并将所述第二参考电平信号作为起始电平以生成第二斜坡信号；
    获取第二模拟信号并对所述第二斜坡信号、所述第二模拟信号进行比较以生成第二比较信号；
    根据所述第二比较信号、所述计数时钟信号生成第一计数时钟信号和第二计数时钟信号；
    所述第一计数器根据所述第一计数时钟信号进行计数；
    所述第二比较信号发生信号翻转，所述第一计数器停止计数、第二计数器开始根据所述第二计数时钟信号计数以完成第二转换周期计数；
    获取所述第一计数器的第一计数结果、所述第二计数器的第二计数结果，根据所述第一计数结果、所述第二计数结果输出转换结果；
    其中，在第二转换周期中，所述第一计数器沿第一计数方向的相反方向进行计数；所述第二计数器沿第二计数方向的相反方向进行计数。
  2. 根据权利要求1所述的模数转换方法，其特征在于，还包括：所述第一计数方向和第二计数方向为相反的计数方向；
    或
    所述第一计数方向和第二计数方向为相同的计数方向。
  3. 根据权利要求2所述的模数转换方法，其特征在于，还包括：当所述第一计数方向和第二计数方向为相反计数方向；
    通过加法器将所述第一计数结果、所述第二计数结果进行相加处理以输出转换结果。
  4. 根据权利要求2所述的模数转换方法，其特征在于，还包括：当所述第一计数方向和第二计数方向为相同计数方向；
    通过加法器将所述第一计数结果、所述第二计数结果进行相减处理以输出转换结果。
  5. 根据权利要求1所述的模数转换方法，其特征在于，还包括：所述第一斜坡信号和所述第二斜坡信号为从低电平到高电平的斜坡信号；
    或
    所述第一斜坡信号和所述第二斜坡信号为从高电平到低电平的斜坡信号。
  6. 根据权利要求1所述的模数转换方法，其特征在于，还包括：所述第一参考电平、所述第二参考电平为相同电平；
    或
    所述第一参考电平、所述第二参考电平为不同电平。
  7. 根据权利要求1所述的模数转换方法，其特征在于，还包括：所述第一计数器对时钟信号的上升沿计数有效，所述第二计数器对时钟信号的下降沿计数有效；
    或
    所述第一计数器对时钟信号的下降沿计数有效，所述第二计数器对时钟信号的上升沿计数有效。
  8. 一种模数转换器，其特征在于，所述模数转换器用于执行权利要求1至7任一项所述的模数转换方法。
  9. 一种图像传感器，其特征在于，包括权利要求8所述的模数转换器。
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