WO2019179432A1 - 防闩锁电路及集成电路 - Google Patents

防闩锁电路及集成电路 Download PDF

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Publication number
WO2019179432A1
WO2019179432A1 PCT/CN2019/078701 CN2019078701W WO2019179432A1 WO 2019179432 A1 WO2019179432 A1 WO 2019179432A1 CN 2019078701 W CN2019078701 W CN 2019078701W WO 2019179432 A1 WO2019179432 A1 WO 2019179432A1
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WIPO (PCT)
Prior art keywords
transistor
control
switch
voltage
supply voltage
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PCT/CN2019/078701
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English (en)
French (fr)
Inventor
陈天豪
吴俊杰
Original Assignee
北京集创北方科技股份有限公司
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Application filed by 北京集创北方科技股份有限公司 filed Critical 北京集创北方科技股份有限公司
Priority to US16/628,017 priority Critical patent/US20200220532A1/en
Priority to KR1020197038599A priority patent/KR102230214B1/ko
Publication of WO2019179432A1 publication Critical patent/WO2019179432A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/20—Modifications for resetting core switching units to a predetermined state
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0826—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in bipolar transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors

Definitions

  • the present invention relates to the field of integrated circuit technologies, and in particular, to an anti-latch circuit and an integrated circuit.
  • a parasitic transistor also known as a parasitic thyristor, or SCR for short
  • the latch-up effect means that the parasitic bipolar transistor is triggered to conduct, forming a low-impedance and high-current path between the power supply VDD and the ground GND. The phenomenon that the circuit does not work properly or even burns.
  • parasitic bipolar transistors exist in various parts of the integrated circuit, including inputs, outputs, internal inverters, and the like.
  • the parasitic bipolar transistor is composed of a PNP transistor and a lateral NPN transistor.
  • Q1 is a Bipolar Junction Transistor (BJT)
  • the control terminal is an N-type well region
  • the second end is a P-type substrate
  • the first end is a P-channel
  • Q2 is a side-type transistor BJT
  • the control terminal is a P-type
  • the substrate has an N-type well region at the second end and an N-channel at the first end.
  • the above two components constitute a thyristor SCR circuit.
  • the two BJTs When no external interference is caused to trigger, the two BJTs are in an off state, and the second terminal current is a reverse leakage current of the second terminal-control terminal, and the current gain is very small. No latch-up effect is produced.
  • the current of the second terminal of one of the BJTs When the current of the second terminal of one of the BJTs is suddenly increased to a certain value by external interference, it is fed back to another BJT, so that the two BJTs are turned on by the trigger, and a low-impedance and large current path is formed between the power supply VDD and the ground GND.
  • a latch-up effect is produced. For example, when the voltage V P at the second end of Q1 rises and the voltage V N at the second end of Q2 falls, a latch-up effect occurs.
  • an object of the present invention to provide an anti-latch circuit and an integrated circuit having latch-up resistance.
  • an anti-latch circuit comprising: a first transistor having a control end, a first end and a second end, the control end receiving the first control voltage, and the first end receiving the first supply voltage a second transistor, opposite to the first transistor type, having a control terminal, a first terminal, and a second terminal, the control terminal receiving the second control voltage, and being coupled to the second terminal of the first transistor, the first terminal and the first transistor
  • the control terminal is connected, the second terminal receives the second supply voltage, and the control circuit sets a path formed by the first transistor and the second transistor between the first supply voltage and the second supply voltage for when the first control voltage and / or the second control voltage is disconnected when the preset range is exceeded.
  • control circuit is disposed between the first supply voltage and the first transistor, and includes a first comparison module and a first switch module, wherein the first comparison module is configured to exceed a pre-control voltage
  • the first range is configured to output a first switching signal for turning off the first switching module; the first switching module is configured to disconnect the first supply voltage from the first transistor when receiving the first switching signal.
  • the first comparison module is a first comparator
  • the first switch module is a first switch tube
  • a first input end of the first comparator receives a first control voltage
  • a second input end receives a first a reference voltage
  • the output end is connected to the control end of the first switch tube
  • the first end of the first switch tube receives a first supply voltage
  • the second end is connected to the first end of the first transistor.
  • control circuit is disposed between the second supply voltage and the second transistor, and includes a second comparison module and a second switch module, wherein the second comparison module is configured to exceed the pre-control voltage
  • the second range is configured to output a second switch signal for turning off the second switch module; the second switch module is configured to disconnect the second supply voltage from the second transistor when receiving the second switch signal.
  • the second comparison module is a second comparator
  • the second switch module is a second switch
  • the first input of the second comparator receives a second control voltage
  • the second input receives a second a second reference voltage
  • the output end is connected to the control end of the second switch tube
  • the first end of the second switch tube receives the second supply voltage
  • the second end is connected to the first end of the second transistor.
  • the control circuit is disposed between the first supply voltage and the first transistor and between the second supply voltage and the second transistor, and includes a first comparison module, a first switch module, and a second Comparing the module and the second switch module, the first comparison module is configured to output a first switch signal for turning off the first switch module when the first control voltage exceeds the preset first range; Disconnecting the first supply voltage from the first transistor when receiving the first switching signal; and the second comparison module is configured to output the second switching module when the second control voltage exceeds the preset second range Turning off the second switching signal; the second switching module is configured to disconnect the second supply voltage from the second transistor when receiving the second switching signal.
  • the first comparison module is a first comparator
  • the first switch module is a first switch tube
  • the second comparison module is a second comparator
  • the second switch module is a second switch tube
  • the first input end of the first comparator receives a first control voltage
  • the second input end receives a first reference voltage
  • the output end is connected to a control end of the first switch tube;
  • the output end is connected to the control end of the second switch tube;
  • the first end of the second switch tube receives a second supply voltage, and the second end is connected to the first end of the second transistor.
  • the first switching transistor is a PMOS transistor
  • the second switching transistor is an NMOS transistor
  • the first transistor is a PNP type transistor
  • the second transistor is an NPN type transistor.
  • the first supply voltage is greater than the second supply voltage.
  • an integrated circuit including the latch-proof circuit described above.
  • the anti-latch circuit and the integrated circuit provided by the invention provide a control circuit on a path formed by the first transistor and the second transistor between the first supply voltage and the second supply voltage, when the first control voltage of the first transistor is / or the second control voltage of the second transistor is disconnected when the preset control range is exceeded, thereby preventing the occurrence of a latch-up effect in the case of power-on.
  • FIG. 1 is a schematic structural view of a parasitic thyristor in the prior art
  • FIG. 2 is an equivalent circuit diagram of the parasitic thyristor shown in FIG. 1;
  • FIG. 3 is a circuit diagram showing an anti-latch circuit according to a first embodiment of the present invention.
  • FIG. 4 is a circuit diagram of an anti-latch circuit provided by a second embodiment of the present invention.
  • Fig. 5 is a circuit diagram showing an anti-latch circuit provided by a third embodiment of the present invention.
  • Fig. 3 is a circuit diagram showing an anti-latch circuit according to a first embodiment of the present invention.
  • the latch-up circuit includes a first transistor Q1 and a second transistor Q2 and a control circuit 10.
  • the first transistor Q1 has a control end, a first end and a second end, the control end receives the first control voltage V N , and the first end receives the first supply voltage V H .
  • the second transistor Q2 opposite to the first transistor type, has a control end, a first end and a second end, and the control end receives the second control voltage V P and is connected to the second end of the first transistor Q1, the first end is The control terminal of the first transistor Q1 is connected, and the second terminal receives the second supply voltage V L .
  • the first transistor and the second transistor are opposite-type bipolar transistors, and the control terminal is a base, the first end is an emitter, and the second end is a collector.
  • the first transistor Q1 is a PNP-type bipolar transistor and the second transistor Q2 is an NPN-type bipolar transistor.
  • the control circuit 10 sets a path between the first supply voltage V H and the second supply voltage V L formed by the first transistor Q1 and the second transistor Q2 for the first control voltage V N and/or the second control voltage The path is broken when V P exceeds the preset range.
  • the control circuit 10 is disposed between the first supply voltage V H and the first transistor Q1, and includes a first comparison module 101 and a first switch module 102.
  • the first comparison module 101 is configured to output a first switch signal for turning off the first switch module 102 when the first control voltage V N exceeds a preset first range; the first switch module 102 is used to The first supply voltage V H is disconnected from the first transistor Q1 upon receiving the first switching signal.
  • the first comparison module 101 is a first comparator U1
  • the first switch module 102 is a first switch tube M1.
  • the first input terminal of the first comparator U1 receives the first control voltage V N
  • the second input terminal receives the first reference voltage V RH
  • the output end is connected to the control end of the first switch tube M1;
  • the first end of the first switch M1 receives the first supply voltage V H , and the second end is connected to the first end of the first transistor Q1.
  • the first switching signal outputted by the first comparator U1 controls the first switching transistor M1 to be turned off.
  • the first reference voltage V RH may be equal to the first supply voltage V H .
  • the first switch M1 is a PMOS transistor, and the control end of the first switch M1 is a gate, the first end is a source, and the second end is a drain.
  • the first switching signal is at a high level.
  • the first switch M1 is an NMOS transistor, and the control end of the first switch M1 is a gate, the first end is a drain, and the second end is a source.
  • the first switching signal is low.
  • the first control voltage V N or the second control voltage V P may be changed. If the first control voltage V N is caused to drop first, when the voltage difference between the first terminal and the control terminal of the first transistor Q1 is greater than the turn-on voltage of the first transistor Q1, the first transistor Q1 is turned on, and the first supply voltage will be Is provided to the control terminal of the second transistor Q2, causing the control terminal voltage V P of the second transistor Q2 to rise, when the voltage difference between the control terminal of the second transistor Q2 and the first terminal is greater than the turn-on voltage of the second transistor Q2, The second transistor Q2 is turned on, creating a latch path.
  • a voltage disorder for example, a voltage disorder caused by static electricity or a circuit operation error
  • the second control voltage V P is caused to rise first, when the voltage difference between the control terminal of the second transistor Q2 and the first terminal is greater than the turn-on voltage of the second transistor Q2, the second transistor Q2 is turned on, and the second power supply voltage is provided.
  • the control terminal of the first transistor Q1 causes the first control voltage V N to drop.
  • the first transistor Q1 is turned on. Generate a latch path.
  • the first control voltage V N is directly or indirectly decreased, and V N is compared with the first reference voltage V RH .
  • V N is compared with the first reference voltage V RH .
  • the first comparator U1 outputs the first The switching signal controls the first switch M1 to be turned off, so that the current path is closed, and no latch-up effect is generated.
  • the anti-latch circuit provided by the present invention provides a control circuit on a path formed by the first transistor and the second transistor between the first supply voltage and the second supply voltage, when the control voltage of the first transistor exceeds a preset first The first supply voltage is disconnected from the first transistor during the range, thereby preventing the occurrence of a latch-up effect in the case of power-on.
  • FIG. 4 is a circuit diagram showing an anti-latch circuit provided by a second embodiment of the present invention.
  • the control circuit 20 is provided between the second supply voltage V L and the second transistor Q2, a second comparison module 201 includes a second switch module 202.
  • the second comparison module 201 is configured to output a second switch signal for turning off the second switch module 202 when the second control voltage V P exceeds the preset second range; the second switch module 202 is used to upon receiving the second switching signal and a second supply voltage V L of the second transistor Q2 is turned off.
  • the second comparison module 201 is a second comparator U2, and the second switch module 202 is a second switch tube M2.
  • the first input end of the second comparator U2 receives the second control voltage V P
  • the second input terminal receives the second reference voltage V RL
  • the output end is connected to the control end of the second switch tube M2;
  • the first terminal receiving a second supply voltage V L of the second switching transistor M2, and a second end connected to a first terminal of the second transistor Q2.
  • the second switching signal output by the second comparator U2 controls the second switching transistor M2 to be turned off.
  • the second reference voltage V RL may be equal to the second supply voltage V L .
  • the second switch M2 is a PMOS transistor, and the control end of the second switch M2 is a gate, the first end is a drain, and the second end is a source.
  • the second switching signal is at a high level.
  • the second switch M2 is an NMOS transistor, and the control end of the second switch M2 is a gate, the first end is a source, and the second end is a drain.
  • the second switching signal is low.
  • the second control voltage V P is directly or indirectly caused to rise, and V P is compared with the second reference voltage V RL .
  • the second comparator U2 outputs the second switching signal.
  • the second switch M2 is controlled to be turned off, so that the current path is closed, and no latch-up effect is generated.
  • the anti-latch circuit provided by the present invention provides a control circuit on a path formed by the first transistor and the second transistor between the first supply voltage and the second supply voltage, when the control voltage of the second transistor exceeds a preset second
  • the second common voltage is disconnected from the second transistor during the range, thereby preventing the occurrence of a latch-up effect in the case of power-on.
  • Fig. 5 is a circuit diagram showing an anti-latch circuit provided by a third embodiment of the present invention.
  • the control circuit includes a first control circuit 10 and a second control circuit 20, wherein the first control circuit 10 is disposed at the first supply voltage VH and the first transistor Between Q1, a first comparison module 101 and a first switch module 102 are included.
  • the second control circuit 20 is disposed between the second supply voltage VL and the second transistor Q2, and includes a second comparison module 201 and a second switching module 202.
  • the first comparison module 101 is configured to output a first switch signal for turning off the first switch module 102 when the first control voltage V N exceeds a preset first range; the first switch module 102 is used to The first supply voltage V H is disconnected from the first transistor Q1 upon receiving the first switching signal.
  • the first comparison module 101 is a first comparator U1
  • the first switch module 102 is a first switch tube M1.
  • the first input terminal of the first comparator U1 receives the first control voltage V N
  • the second input terminal receives the first reference voltage V RH
  • the output end is connected to the control end of the first switch tube M1;
  • the first end of the first switch M1 receives the first supply voltage V H , and the second end is connected to the first end of the first transistor Q1.
  • the first switching signal outputted by the first comparator U1 controls the first switching transistor M1 to be turned off.
  • the first reference voltage V RH may be equal to the first supply voltage V H .
  • the first switch M1 is a PMOS transistor, and the control end of the first switch M1 is a gate, the first end is a source, and the second end is a drain.
  • the first switching signal is at a high level.
  • the first switch M1 is an NMOS transistor, and the control end of the first switch M1 is a gate, the first end is a drain, and the second end is a source.
  • the first switching signal is low.
  • the second comparison module 201 is configured to output a second switch signal for turning off the second switch module 202 when the second control voltage VP exceeds the preset second range; the second switch module 202 is configured to receive The second supply voltage V L is disconnected from the second transistor Q2 when the second switching signal is applied.
  • the second comparison module 201 is a second comparator U2, and the second switch module 202 is a second switch tube M2.
  • the first input end of the second comparator U2 receives the second control voltage V P
  • the second input terminal receives the second reference voltage V RL
  • the output end is connected to the control end of the second switch tube M2;
  • the first terminal receiving a second supply voltage V L of the second switching transistor M2, a first end connected to the second terminal of the second transistor Q2.
  • the second switching signal output by the second comparator U2 controls the second switching transistor M2 to be turned off.
  • the second reference voltage V RL may be equal to the second supply voltage V L .
  • the second switch M2 is a PMOS transistor, and the control end of the second switch M2 is a gate, the first end is a drain, and the second end is a source.
  • the second switching signal is at a high level.
  • the second switch M2 is an NMOS transistor, and the control end of the second switch M2 is a gate, the first end is a source, and the second end is a drain.
  • the second switching signal is low.
  • the first control voltage V N decreases and the second control voltage V P rises, and V N is compared with the first reference voltage V RH and V P and the second reference voltage V RL are directly or indirectly caused.
  • V N ⁇ V RH
  • the first comparator U1 outputs a first switching signal
  • the first switching transistor M1 is controlled to be turned off
  • VP>V RL the second comparator U2 outputs a second switching signal.
  • the second switch M2 is controlled to be turned off, so that the current path is closed, and no latch-up effect is generated.
  • the anti-latch circuit provided by the present invention provides a control circuit on a path formed by the first transistor and the second transistor between the first supply voltage and the second supply voltage, when the control voltage of the first transistor exceeds a preset first
  • the first supply voltage is disconnected from the first transistor and the second common voltage is disconnected from the second transistor when the control voltage of the second transistor exceeds the preset second range, thereby preventing latch-up effect in power-on condition happened.
  • the present invention also provides an integrated circuit comprising the latch-proof circuit of any of the above embodiments.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

公开了一种防闩锁电路，包括：第一晶体管，其控制端接收第一控制电压，第一端接收第一供电电压；第二晶体管，与第一晶体管类型相反，其控制端接收第二控制电压，并且与第一晶体管的第二端相连，第一端与第一晶体管的控制端相连，第二端接收第二供电电压；控制电路，设置第一供电电压与第二供电电压之间由第一晶体管和第二晶体管形成的通路上，用于当第一控制电压和/或第二控制电压超出预设范围时将通路断开。本发明提供的防闩锁电路，在第一供电电压与第二供电电压之间由第一晶体管和第二晶体管形成的通路上设置控制电路，当第一控制电压和/或第二控制电压超出预设范围时将通路断开，从而防止上电情况下闩锁效应的发生。

Description

防闩锁电路及集成电路
本申请要求了2018年3月20日提交的、申请号为201810227939.X、发明名称为“防闩锁电路及集成电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及集成电路技术领域，特别涉及一种防闩锁电路及集成电路。
背景技术
随着IC制造工艺的发展，芯片的尺寸越来越小，芯片封装密度和集成度越来越高，产生闩锁效应(Latch up)的可能性就会越来越大，模块之间互相干扰的可能性也会越来越大。一般的集成电路中均存在寄生晶体管(又称寄生可控硅，简称SCR)，闩锁效应是指寄生双极性晶体管被触发导通，在电源VDD与地GND之间形成低阻抗大电流通路，导致电路无法正常工作，甚至烧毁的现象。这种寄生双极性晶体管存在集成电路的各个部分，包括输入端、输出端、内部反相器等。
图1和图2分别示出了现有技术中寄生可控硅的结构示意图和等效电路图。如图1和图2所示，寄生双极性晶体管由一个PNP晶体管和一横向NPN晶体管组成。Q1为垂直式晶体管(Bipolar Junction Transistor,BJT)，控制端为N型阱区，第二端为P型衬底，第一端为P沟道；Q2为侧面式晶体管BJT，控制端为P型衬底，第二端为N型阱区，第一端为N沟道。以上两元件构成可控硅SCR电路，当无外界干扰未引起触发时，两个BJT处于截止状态，第二端电流是第二端-控制端的反向漏电流构成，电流增益非常小，此时不会产生闩锁效应。当其中一个BJT的第二端电流受到外部干扰突然增加到一定值时，会反馈至另一个BJT，从而使两个BJT因触发而导通，电源VDD至地GND间形成低阻抗大电流通路，产生闩锁效应。例如，当Q1的第二端处电压V P上升，Q2的第二端处电压V N下降时，产生闩锁效应。
发明内容
鉴于上述问题，本发明的目的在于提供一种防闩锁电路及集成电路，具有抗闩锁能力。
根据本发明的第一方面，提供一种防闩锁电路，包括：第一晶体管，具有控制端、第一端和第二端，控制端接收第一控制电压，第一端接收第一供电电压；第二晶体管，与第一晶体管类型相反，具有控制端、第一端和第二端，控制端接收第二控制电压，并且与第一晶体管的第二端相 连，第一端与第一晶体管的控制端相连，第二端接收第二供电电压；控制电路，设置第一供电电压与第二供电电压之间由第一晶体管和第二晶体管形成的通路上，用于当第一控制电压和/或第二控制电压超出预设范围时将所述通路断开。
优选地，所述控制电路设置在所述第一供电电压和所述第一晶体管之间，包括第一比较模块和第一开关模块，所述第一比较模块用于在第一控制电压超出预设的第一范围时输出用于使第一开关模块关断的第一开关信号；第一开关模块用于在接收到第一开关信号时将第一供电电压与第一晶体管断开。
优选地，所述第一比较模块为第一比较器，所述第一开关模块为第一开关管；所述第一比较器的第一输入端接收第一控制电压，第二输入端接收第一参考电压，输出端与所述第一开关管的控制端连接；所述第一开关管的第一端接收第一供电电压，第二端与所述第一晶体管的第一端连接。
优选地，所述控制电路设置在所述第二供电电压和所述第二晶体管之间，包括第二比较模块和第二开关模块，所述第二比较模块用于在第二控制电压超出预设的第二范围时输出用于使第二开关模块关断的第二开关信号；第二开关模块用于在接收到第二开关信号时将第二供电电压与第二晶体管断开。
优选地，所述第二比较模块为第二比较器，所述第二开关模块为第二开关管；所述第二比较器的第一输入端接收第二控制电压，第二输入端接收第二参考电压，输出端与所述第二开关管的控制端连接；所述第二开关管的第一端接收第二供电电压，第二端与所述第二晶体管的第一端连接。
优选地，所述控制电路设置在所述第一供电电压和所述第一晶体管之间以及第二供电电压和所述第二晶体管之间，包括第一比较模块、第一开关模块、第二比较模块和第二开关模块，所述第一比较模块用于在第一控制电压超出预设的第一范围时输出用于使第一开关模块关断的第一开关信号；第一开关模块用于在接收到第一开关信号时将第一供电电压与第一晶体管断开；所述第二比较模块用于在第二控制电压超出预设的第二范围时输出用于使第二开关模块关断的第二开关信号；第二开关模块用于在接收到第二开关信号时将第二供电电压与第二晶体管断开。
优选地，所述第一比较模块为第一比较器，所述第一开关模块为第一开关管；所述第二比较模块为第二比较器，所述第二开关模块为第二开关管；所述第一比较器的第一输入端接收第一控制电压，第二输入端接收第一参考电压，输出端与所述第一开关管的控制端连接；所述第一开关管的第一端接收第一供电电压，第二端与所述第一晶体管的第一端连接；所述第二比较器的第一输入端接收第二控制电压，第二输入端接收第二参考电压，输出端与所述第二开关管的控制端连 接；所述第二开关管的第一端接收第二供电电压，第二端与所述第二晶体管的第一端连接。
优选地，所述第一开关管为PMOS晶体管，所述第二开关管为NMOS晶体管。
优选地，所述第一晶体管为PNP型晶体管，所述第二晶体管为NPN型晶体管。
优选地，所述第一供电电压大于第二供电电压。
根据本发明的另一方面，提供一种集成电路，包括上述所述的防闩锁电路。
本发明提供的防闩锁电路及集成电路，在第一供电电压与第二供电电压之间由第一晶体管和第二晶体管形成的通路上设置控制电路，当第一晶体管的第一控制电压和/或第二晶体管的第二控制电压超出预设范围时将通路断开，从而防止上电情况下闩锁效应的发生。
附图说明
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1示出了现有技术中寄生可控硅的结构示意图；
图2示出了图1所示的寄生可控硅的等效电路图；
图3示出了本发明第一实施例提供的防闩锁电路的电路图；
图4示出了本发明第二实施例提供的防闩锁电路的电路图；
图5示出了本发明第三实施例提供的防闩锁电路的电路图。
具体实施方式
以下将参照附图更详细地描述本发明的各种实施例。在各个附图中，相同的元件采用相同或类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。
图3示出了本发明第一实施例提供的防闩锁电路的电路图。如图1所示，所述防闩锁电路包括第一晶体管Q1和第二晶体管Q2以及控制电路10。
第一晶体管Q1具有控制端、第一端和第二端，控制端接收第一控制电压V N，第一端接收第一供电电压V H。
第二晶体管Q2，与第一晶体管类型相反，具有控制端、第一端和第二端，控制端接收第二控制电压V P，并且与第一晶体管Q1的第二端相连，第一端与第一晶体管Q1的控制端相连，第二端接收第二供电电压V L。在本实施例中，第一晶体管和第二晶体管为类型相反的双极性晶体管， 控制端为基极，第一端为发射极，第二端为集电极。
在一个优选地实施例中，第一晶体管Q1为PNP型双极性晶体管，第二晶体管Q2为NPN型双极性晶体管。
控制电路10设置第一供电电压V H与第二供电电压V L之间由第一晶体管Q1和第二晶体管Q2形成的通路上，用于当第一控制电压V N和/或第二控制电压V P超出预设范围时将所述通路断开。
所述控制电路10设置在所述第一供电电压V H和所述第一晶体管Q1之间，包括第一比较模块101和第一开关模块102。
其中，所述第一比较模块101用于在第一控制电压V N超出预设的第一范围时输出用于使第一开关模块102关断的第一开关信号；第一开关模块102用于在接收到第一开关信号时将第一供电电压V H与第一晶体管Q1断开。
在本实施例中，所述第一比较模块101为第一比较器U1，所述第一开关模块102为第一开关管M1。所述第一比较器U1的第一输入端接收第一控制电压V N，第二输入端接收第一参考电压V RH，输出端与所述第一开关管M1的控制端连接；
所述第一开关管M1的第一端接收第一供电电压V H，第二端与所述第一晶体管Q1的第一端连接。
当V N＜V RH时，第一比较器U1输出的第一开关信号控制第一开关管M1关断。其中，第一参考电压V RH可以等于第一供电电压V H。
在一个优选地实施例中，第一开关管M1为PMOS晶体管，第一开关管M1的控制端为栅极，第一端为源极，第二端为漏极。第一开关信号为高电平。
在一个优选地实施例中，第一开关管M1为NMOS晶体管，第一开关管M1的控制端为栅极，第一端为漏极，第二端为源极。第一开关信号为低电平。
当出现电压错乱(例如静电引起的或者电路操作错误引起的电压错乱)时，可能会引起第一控制电压V N或第二控制电压V P发生变化。若先引起第一控制电压V N下降，当第一晶体管Q1的第一端与控制端电的压差大于第一晶体管Q1的开启电压时，第一晶体管Q1会导通，第一供电电压将会提供给第二晶体管Q2的控制端，导致第二晶体管Q2的控制端电压V P上升，当第二晶体管Q2的控制端与第一端的压差大于第二晶体管Q2的开启电压时，第二晶体管Q2会导通，产生闩锁路径。若先引起第二控制电压V P上升，当第二晶体管Q2的控制端与第一端的压差大于第二晶体管Q2的开启电压时，第二晶体管Q2会导通，第二供电电压会提供给第一晶体管Q1的控制端，导致第一控制电压V N下降，当第一晶体管Q1的第一端与控制端的压差大于第一晶体管Q1的开 启电压时，第一晶体管Q1会导通，产生闩锁路径。
因此，电压错乱的情况下会直接或间接地引起第一控制电压V N下降，将V N与第一参考电压V RH进行比较，当V N＜V RH时，第一比较器U1输出第一开关信号，控制第一开关管M1关断，使得电流路径关闭，不会产生闩锁效应。
本发明提供的防闩锁电路，在第一供电电压与第二供电电压之间由第一晶体管和第二晶体管形成的通路上设置控制电路，当第一晶体管的控制电压超出预设的第一范围时将第一供电电压与第一晶体管断开，从而防止上电情况下闩锁效应的发生。
图4示出了本发明第二实施例提供的防闩锁电路的电路图。与第一实施例相比，区别在于，所述控制电路20设置在所述第二供电电压V L和所述第二晶体管Q2之间，包括第二比较模块201和第二开关模块202。
其中，所述第二比较模块201用于在第二控制电压V P超出预设的第二范围时输出用于使第二开关模块202关断的第二开关信号；第二开关模块202用于在接收到第二开关信号时将第二供电电压V L与第二晶体管Q2断开。
在本实施例中，所述第二比较模块201为第二比较器U2，所述第二开关模块202为第二开关管M2。所述第二比较器U2的第一输入端接收第二控制电压V P，第二输入端接收第二参考电压V RL，输出端与所述第二开关管M2的控制端连接；
所述第二开关管M2的第一端接收第二供电电压V L，第二端与所述第二晶体管Q2的第一端连接。
当V P＞V RL时，第二比较器U2输出的第二开关信号控制第二开关管M2关断。其中，第二参考电压V RL可以等于第二供电电压V L。
在一个优选地实施例中，第二开关管M2为PMOS晶体管，第二开关管M2的控制端为栅极，第一端为漏极，第二端为源极。第二开关信号为高电平。
在一个优选地实施例中，第二开关管M2为NMOS晶体管，第二开关管M2的控制端为栅极，第一端为源极，第二端为漏极。第二开关信号为低电平。
电压错乱的情况下会直接或间接地引起第二控制电压V P上升，将V P与第二参考电压V RL进行比较，当VP＞V RL时，第二比较器U2输出第二开关信号，控制第二开关管M2关断，使得电流路径关闭，不会产生闩锁效应。
本发明提供的防闩锁电路，在第一供电电压与第二供电电压之间由第一晶体管和第二晶体管形成的通路上设置控制电路，当第二晶体管的控制电压超出预设的第二范围时将第二公共电压与 第二晶体管断开，从而防止上电情况下闩锁效应的发生。
图5示出了本发明第三实施例提供的防闩锁电路的电路图。与第一实施例相比，区别在于，所述控制电路包括第一控制电路10和第二控制电路20，其中，第一控制电路10设置在所述第一供电电压VH和所述第一晶体管Q1之间，包括第一比较模块101和第一开关模块102。第二控制电路20设置在所述第二供电电压VL和所述第二晶体管Q2之间，包括第二比较模块201和第二开关模块202。
其中，所述第一比较模块101用于在第一控制电压V N超出预设的第一范围时输出用于使第一开关模块102关断的第一开关信号；第一开关模块102用于在接收到第一开关信号时将第一供电电压V H与第一晶体管Q1断开。
在本实施例中，所述第一比较模块101为第一比较器U1，所述第一开关模块102为第一开关管M1。所述第一比较器U1的第一输入端接收第一控制电压V N，第二输入端接收第一参考电压V RH，输出端与所述第一开关管M1的控制端连接；
所述第一开关管M1的第一端接收第一供电电压V H，第二端与所述第一晶体管Q1的第一端连接。
当V N＜V RH时，第一比较器U1输出的第一开关信号控制第一开关管M1关断。其中，第一参考电压V RH可以等于第一供电电压V H。
在一个优选地实施例中，第一开关管M1为PMOS晶体管，第一开关管M1的控制端为栅极，第一端为源极，第二端为漏极。第一开关信号为高电平。
在一个优选地实施例中，第一开关管M1为NMOS晶体管，第一开关管M1的控制端为栅极，第一端为漏极，第二端为源极。第一开关信号为低电平。
所述第二比较模块201用于在第二控制电压VP超出预设的第二范围时输出用于使第二开关模块202关断的第二开关信号；第二开关模块202用于在接收到第二开关信号时将第二供电电压V L与第二晶体管Q2断开。
在本实施例中，所述第二比较模块201为第二比较器U2，所述第二开关模块202为第二开关管M2。所述第二比较器U2的第一输入端接收第二控制电压V P，第二输入端接收第二参考电压V RL，输出端与所述第二开关管M2的控制端连接；
所述第二开关管M2的第一端接收第二供电电压V L，第二端与所述第二晶体管Q2的第一端连接。
当V P＞V RL时，第二比较器U2输出的第二开关信号控制第二开关管M2关断。其中，第二 参考电压V RL可以等于第二供电电压V L。
在一个优选地实施例中，第二开关管M2为PMOS晶体管，第二开关管M2的控制端为栅极，第一端为漏极，第二端为源极。第二开关信号为高电平。
在一个优选地实施例中，第二开关管M2为NMOS晶体管，第二开关管M2的控制端为栅极，第一端为源极，第二端为漏极。第二开关信号为低电平。
电压错乱的情况下会直接或间接地引起第一控制电压V N下降以及第二控制电压V P上升，将V N与第一参考电压V RH进行比较以及将V P与第二参考电压V RL进行比较，当V N＜V RH时，第一比较器U1输出第一开关信号，控制第一开关管M1关断，以及当VP＞V RL时，第二比较器U2输出第二开关信号，控制第二开关管M2关断，使得电流路径关闭，不会产生闩锁效应。
本发明提供的防闩锁电路，在第一供电电压与第二供电电压之间由第一晶体管和第二晶体管形成的通路上设置控制电路，当第一晶体管的控制电压超出预设的第一范围时将第一供电电压与第一晶体管断开以及当第二晶体管的控制电压超出预设的第二范围时将第二公共电压与第二晶体管断开，从而防止上电情况下闩锁效应的发生。
本发明还提供一种集成电路，包括上述任一实施例所述的防闩锁电路。
依照本发明的实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。

Claims (11)

  1. 一种防闩锁电路，其特征在于，包括：
    第一晶体管，具有控制端、第一端和第二端，控制端接收第一控制电压，第一端接收第一供电电压；
    第二晶体管，与第一晶体管类型相反，具有控制端、第一端和第二端，控制端接收第二控制电压，并且与第一晶体管的第二端相连，第一端与第一晶体管的控制端相连，第二端接收第二供电电压；
    控制电路，设置第一供电电压与第二供电电压之间由第一晶体管和第二晶体管形成的通路上，用于当第一控制电压和/或第二控制电压超出预设范围时将所述通路断开。
  2. 根据权利要求1所述的防闩锁电路，其特征在于，所述控制电路设置在所述第一供电电压和所述第一晶体管之间，包括第一比较模块和第一开关模块，
    所述第一比较模块用于在第一控制电压超出预设的第一范围时输出用于使第一开关模块关断的第一开关信号；
    第一开关模块用于在接收到第一开关信号时将第一供电电压与第一晶体管断开。
  3. 根据权利要求2所述的防闩锁电路，其特征在于，所述第一比较模块为第一比较器，所述第一开关模块为第一开关管；
    所述第一比较器的第一输入端接收第一控制电压，第二输入端接收第一参考电压，输出端与所述第一开关管的控制端连接；
    所述第一开关管的第一端接收第一供电电压，第二端与所述第一晶体管的第一端连接。
  4. 根据权利要求1所述的防闩锁电路，其特征在于，所述控制电路设置在所述第二供电电压和所述第二晶体管之间，包括第二比较模块和第二开关模块，
    所述第二比较模块用于在第二控制电压超出预设的第二范围时输出用于使第二开关模块关断的第二开关信号；
    第二开关模块用于在接收到第二开关信号时将第二供电电压与第二晶体管断开。
  5. 根据权利要求4所述的防闩锁电路，其特征在于，所述第二比较模块为第二比较器，所述第二开关模块为第二开关管；
    所述第二比较器的第一输入端接收第二控制电压，第二输入端接收第二参考电压，输出端与所述第二开关管的控制端连接；
    所述第二开关管的第一端接收第二供电电压，第二端与所述第二晶体管的第一端连接。
  6. 根据权利要求1的防闩锁电路，其特征在于，所述控制电路设置在所述第一供电电压和所述第一晶体管之间以及第二供电电压和所述第二晶体管之间，包括第一比较模块、第一开关模块、第二比较模块和第二开关模块，
    所述第一比较模块用于在第一控制电压超出预设的第一范围时输出用于使第一开关模块关断的第一开关信号；
    第一开关模块用于在接收到第一开关信号时将第一供电电压与第一晶体管断开；
    所述第二比较模块用于在第二控制电压超出预设的第二范围时输出用于使第二开关模块关断的第二开关信号；
    第二开关模块用于在接收到第二开关信号时将第二供电电压与第二晶体管断开。
  7. 根据权利要求6所述的防闩锁电路，其特征在于，所述第一比较模块为第一比较器，所述第一开关模块为第一开关管；所述第二比较模块为第二比较器，所述第二开关模块为第二开关管；
    所述第一比较器的第一输入端接收第一控制电压，第二输入端接收第一参考电压，输出端与所述第一开关管的控制端连接；
    所述第一开关管的第一端接收第一供电电压，第二端与所述第一晶体管的第一端连接；
    所述第二比较器的第一输入端接收第二控制电压，第二输入端接收第二参考电压，输出端与所述第二开关管的控制端连接；
    所述第二开关管的第一端接收第二供电电压，第二端与所述第二晶体管的第一端连接。
  8. 根据权利要求7所述的防闩锁电路，其特征在于，所述第一开关管为PMOS晶体管，所述第二开关管为NMOS晶体管。
  9. 根据权利要求1所述的防闩锁电路，其特征在于，所述第一晶体管为PNP型晶体管，所述第二晶体管为NPN型晶体管。
  10. 根据权利要求9所述的防闩锁电路，其特征在于，所述第一供电电压大于第二供电电压。
  11. 一种集成电路，包括如权利要求1-10中任一项所述的防闩锁电路。
PCT/CN2019/078701 2018-03-20 2019-03-19 防闩锁电路及集成电路 WO2019179432A1 (zh)

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