WO2019179404A1 - 通信方法、通信装置和系统 - Google Patents

通信方法、通信装置和系统 Download PDF

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Publication number
WO2019179404A1
WO2019179404A1 PCT/CN2019/078583 CN2019078583W WO2019179404A1 WO 2019179404 A1 WO2019179404 A1 WO 2019179404A1 CN 2019078583 W CN2019078583 W CN 2019078583W WO 2019179404 A1 WO2019179404 A1 WO 2019179404A1
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Prior art keywords
bit sequence
coded bit
check matrix
information
sequence
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PCT/CN2019/078583
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English (en)
French (fr)
Inventor
张朝龙
黄凌晨
徐晨
李榕
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华为技术有限公司
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Publication of WO2019179404A1 publication Critical patent/WO2019179404A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

Definitions

  • the present application relates to the field of communications and, more particularly, to a communication method, communication apparatus and system.
  • a Low Density Parity Check (LDPC) code is a linear block code with a sparse check matrix.
  • the LDPC code not only has good performance close to the Shannon limit, but also has low decoding complexity and flexible structure. It is a research hotspot in the field of channel coding in recent years.
  • Quasi-Cyclic LDPC (QC-LDPC) codes are currently used as a class of structured LDPC codes. Because of their simple description, easy construction, and storage space savings, in some communication systems. For example, in the new radio access technology (NR) of the fifth generation (5th generation, 5G) communication system, it is well applied.
  • NR new radio access technology
  • the performance of the block error rate (BLER) at 10-2 and its vicinity is considered, and the signal-to-noise ratio (SNR) decreases significantly with the decrease of BLER.
  • BLER block error rate
  • SNR signal-to-noise ratio
  • the value of BLER is in some range, for example, at 10-4 or lower and even lower, the trend of SNR decreasing with the decrease of BLER is obviously smaller, that is, there is a relatively obvious error leveling layer (error) Floor).
  • error leveling layer results in a lower decoding performance of the QC-LDPC code in the actual application process.
  • the application provides a communication method, communication device and system to improve decoding performance.
  • a communication method comprising:
  • the information sequence is cascading LDPC coded by the encoding device, and the decoding device performs cascading LDPC decoding on the second coded bit sequence, thereby avoiding obvious error flatness of the BLER in the range of 10 0 to 10 -6
  • the layer ie, facilitates a lower BLER over a higher signal to noise ratio range, thereby achieving better decoding performance over a larger signal to noise ratio range.
  • the performing LDPC encoding based on the second parity check matrix and the first coded bit sequence includes:
  • the interleaved or scrambled first coded bit sequence is LDPC encoded based on the second check matrix.
  • burst interference, regular interference, and the like that may be encountered during signal transmission can be randomly dispersed in the coded bits, so that data can be recovered by error correction technology, thereby improving The anti-interference ability of signal transmission improves the demodulation performance.
  • the method further comprises:
  • indication information where the indication information is used to indicate a length of the first coded bit sequence.
  • the indication information may directly indicate the length of the first coded bit sequence, and may also indicate the code rate of the first LDPC code, so that the decoding device determines the length of the first coded bit sequence based on the code rate and the length of the information sequence.
  • the application does not limit this.
  • the method further comprises:
  • the length of the first coded bit sequence is determined based on the length of the sequence of information and a predefined code rate.
  • the encoding device and the decoding device can determine the length of the first encoding bit sequence according to the length of the information sequence and the encoding bit rate without signaling indication, thereby saving signaling overhead.
  • a communication method including:
  • the information sequence is cascading LDPC coded by the encoding device, and the decoding device performs cascading LDPC decoding on the second coded bit sequence, thereby avoiding obvious error flatness of the BLER in the range of 10 0 to 10 -6
  • the layer ie, facilitates a lower BLER over a higher signal to noise ratio range, thereby achieving better decoding performance over a larger signal to noise ratio range.
  • the third coded bit sequence is a first coded bit sequence, or the third coded bit sequence is a first coded bit that is interleaved or scrambled Sequence, and
  • the performing LDPC decoding based on the first parity check matrix and the third coded bit sequence includes:
  • the third coded bit sequence is the first coded bit sequence, performing LDPC decoding on the soft value information or the hard value information of the third coded bit sequence based on the first check matrix; or
  • the third coded bit sequence is the first coded bit sequence that is interleaved or scrambled
  • the soft value information or the hard value information of the third coded bit sequence that is deinterleaved or descrambled based on the first check matrix Perform LDPC decoding.
  • whether the third coded bit sequence is the first coded bit sequence or the interleaved or scrambled first coded bit sequence is related to whether the coding device has interleaved or scrambled the first coded bit sequence. If the first coded bit sequence is interleaved and/or scrambled, burst interference, regular interference, and the like that may be encountered during signal transmission may be randomly dispersed in the coded bits, so that data can be recovered by error correction technology, thereby improving The anti-interference ability of signal transmission improves the demodulation performance.
  • the method further includes:
  • the indication information is used to indicate a length of the first coded bit sequence.
  • the indication information may directly indicate the length of the first coded bit sequence, and may also indicate the code rate of the first LDPC code, so that the decoding device determines the length of the first coded bit sequence based on the code rate and the length of the information sequence.
  • the application does not limit this.
  • the method further includes:
  • the length of the first coded bit sequence is determined based on the length of the sequence of information and a predefined code rate.
  • the encoding device and the decoding device can determine the length of the first encoding bit sequence according to the length of the information sequence and the encoding bit rate without signaling indication, thereby saving signaling overhead.
  • the length K of the information sequence and the length L 1 of the first coded bit sequence are:
  • the performance loss caused by multiple LDPC encoding can be reduced, and overall, it is beneficial to improve system performance, so that the transmission system can meet the requirements of different service types. .
  • the length K of the information sequence and the length L 1 of the first coded bit sequence are:
  • the performance loss caused by multiple LDPC encoding can be reduced, and overall, it is beneficial to improve system performance, so that the transmission system can meet the requirements of different service types. .
  • adjusting the code rate of the first LDPC coding under the length of different information sequences by the correction value is advantageous for obtaining better decoding performance.
  • ⁇ is -Z ⁇ ⁇ ⁇ Z
  • ⁇ is an integer
  • the base map of the first check matrix and the base map of the second check matrix may be predefined, or may be determined by an encoding device or a decoding device.
  • the method further includes:
  • a base map of the second check matrix is determined.
  • the base map of the first check matrix may be predefined in the protocol.
  • the encoding device and the decoding device may only determine the base map of the second check matrix; or, the second check matrix may be predefined in the protocol.
  • Base diagram in this case, the encoding device and the decoding device may only determine the base map of the first check matrix; or, the base of the first check matrix and the base of the second check matrix are not predefined in the protocol.
  • the encoding device and the decoding device can determine a base map of the first check matrix and a base map of the second check matrix.
  • the base map of the first check matrix is the base map 1BG1 in the new air interface NR protocol
  • the base map of the second check matrix is Base diagram 2BG2 in the NR protocol
  • the base map of the first check matrix is the BG2, and the base map of the second check matrix is the BG1; or
  • the base map of the first check matrix is the BG1, and the base map of the second check matrix is the BG1; or
  • the base map of the first check matrix is the BG2, and the base map of the second check matrix is the BG2;
  • the BG1 is used to determine a check matrix with a dimension of 46Z ⁇ 68Z
  • the BG2 is used to determine a check matrix with a dimension of 42Z ⁇ 52Z
  • Z is an expansion factor
  • an encoding device having the functionality to implement an encoding device in the method design of the first aspect above. These functions can be implemented in hardware or in software by executing the corresponding software.
  • the hardware or software includes one or more units corresponding to the functions described above.
  • a decoding apparatus having the functionality of a decoding apparatus in implementing the method design of the first aspect described above. These functions can be implemented in hardware or in software by executing the corresponding software.
  • the hardware or software includes one or more units corresponding to the functions described above.
  • an encoding device including a transceiver, a processor, and a memory.
  • the processor is configured to control a transceiver transceiver signal for storing a computer program, the processor for calling and running the computer program from the memory, such that the encoding device performs any of the above first aspect or the first aspect The method in the implementation.
  • a decoding apparatus including a transceiver, a processor, and a memory.
  • the processor is configured to control a transceiver transceiver signal for storing a computer program, the processor for calling and running the computer program from the memory, such that the decoding device performs any of the second aspect or the second aspect described above The method in the implementation.
  • a communication device having a function for implementing the behavior of an encoding device in the above method aspect, comprising means for performing the steps or functions described in the above method aspects.
  • the steps or functions may be implemented by software, or by hardware, or by a combination of hardware and software.
  • the above apparatus includes one or more processors and communication units.
  • the one or more processors are configured to support the communication device to perform the corresponding functions of the encoding device in the above method.
  • the information sequence and the first coded bit sequence are LDPC encoded.
  • the communication unit is configured to support the communication device to communicate with other devices to implement a receiving and/or transmitting function. For example, send an indication.
  • the apparatus may further comprise one or more memories for coupling with the processor, which store program instructions and/or data necessary for the network device.
  • the one or more memories may be integrated with the processor or may be separate from the processor. This application is not limited.
  • the communication device may be a base station, gNB or TRP or the like.
  • the communication unit can be a transceiver or an input/output interface.
  • the transceiver may be a transceiver circuit.
  • the input/output interface may be an input/output circuit.
  • the communication device may also be a smart terminal or a wearable device or the like.
  • the communication unit can be a transceiver or an input/output interface.
  • the transceiver may be a transceiver circuit.
  • the input/output interface may be an input/output circuit.
  • the communication device can also be a communication chip.
  • the communication unit may be an input/output circuit or interface of a communication chip.
  • the communication device includes a transceiver, a processor, and a memory.
  • the processor is for controlling transceiver transceiver signals for storing a computer program for executing a computer program in a memory, such that the communication device performs the coding in any of the possible implementations of the first aspect or the first aspect The method by which the device is completed.
  • the communication device has a function of implementing the behavior of the decoding device in the method aspect described above, and includes means for performing the steps or functions described in the above method aspects.
  • the steps or functions may be implemented by software, or by hardware, or by a combination of hardware and software.
  • the above apparatus includes one or more processors and communication units.
  • the one or more processors are configured to support the communication device to perform the corresponding functions of the decoding device of the above method. For example, LDPC decoding is performed on the first coded bit sequence and the second coded bit sequence.
  • the communication unit is configured to support the communication device to communicate with other devices to implement receiving and/or transmitting functions. For example, receiving indication information.
  • the apparatus may further comprise one or more memories for coupling with the processor, which store program instructions and/or data necessary for the network device.
  • the one or more memories may be integrated with the processor or may be separate from the processor. This application is not limited.
  • the communication device may be a base station, gNB or TRP or the like.
  • the communication unit can be a transceiver or an input/output interface.
  • the transceiver may be a transceiver circuit.
  • the input/output interface may be an input/output circuit.
  • the communication device may also be a smart terminal or a wearable device or the like.
  • the communication unit can be a transceiver or an input/output interface.
  • the transceiver may be a transceiver circuit.
  • the input/output interface may be an input/output circuit.
  • the communication device can also be a communication chip.
  • the communication unit may be an input/output circuit or interface of a communication chip.
  • the communication device includes a transceiver, a processor, and a memory.
  • the processor is configured to control a transceiver transceiver signal for storing a computer program for executing a computer program in a memory, such that the communication device performs a second aspect or a second aspect The method of completing the code device.
  • a computer program product comprising: computer program code, when the computer program code is run on a computer, causing the computer to perform the method of the above aspects.
  • a computer readable medium storing program code for causing a computer to perform the method of the above aspects when the computer program code is run on a computer.
  • a chip system comprising a processor for supporting an encoding device to implement the functions involved in the above aspects, for example, generating, receiving, transmitting, or processing data involved in the above method And / or information.
  • the chip system further comprises a memory for storing necessary program instructions and data of the terminal device.
  • the chip system can be composed of chips, and can also include chips and other discrete devices.
  • a chip system comprising a processor for supporting a decoding device to implement the functions involved in the above aspects, for example, generating, receiving, transmitting, or processing the methods involved in the above method Data and / or information.
  • the chip system further comprises a memory for storing necessary program instructions and data of the terminal device.
  • the chip system can be composed of chips, and can also include chips and other discrete devices.
  • FIG. 1 is a schematic diagram of a communication system applicable to a communication method provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of signal processing provided by an embodiment of the present application.
  • FIG. 3 is a comparison diagram of decoding performance of an LDPC code and a Polar code in the prior art
  • FIG. 4 is a schematic flowchart of a communication method provided by an embodiment of the present application.
  • FIG. 5 is a performance comparison diagram of LDPC encoding and decoding using the LDPC codec and the communication method provided by the embodiment of the present application;
  • FIG. 6 is a schematic block diagram of a communication apparatus according to an embodiment of the present application.
  • FIG. 7 is another schematic block diagram of a communication apparatus according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a network device according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a terminal device according to an embodiment of the present application.
  • the technical solution of the embodiment of the present application can be applied to various communication systems, such as, but not limited to, a Narrow Band-Internet of Things (NB-IoT), and a Global System of Mobile communication (GSM) system.
  • Code Division Multiple Access (CDMA) system Wideband Code Division Multiple Access (WCDMA) system, General Packet Radio Service (GPRS), Long Term Evolution (Long Term Evolution) , LTE) system, LTE Frequency Division Duplex (FDD) system, LTE Time Division Duplex (TDD), Universal Mobile Telecommunication System (UMTS), Global Interconnected Microwave Access ( Worldwide Interoperability for Microwave Access, WiMAX) communication system, future 5th Generation (5G) system or new radio access technology (NR).
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • LTE Long Term Evolution Frequency Division Duplex
  • TDD Time Division Duplex
  • UMTS Universal Mobile Telecommunication System
  • FIG. 1 shows a schematic diagram of a communication system suitable for the communication method of the embodiment of the present application.
  • the communication system 100 can include at least one network device (e.g., network device 102) and at least one (e.g., terminal device 104) that can communicate with the terminal device 104.
  • the communication system 100 may further include more network devices and/or more terminal devices, which is not limited in this application.
  • the network device may be any device with a wireless transceiver function, including but not limited to: an evolved Node B (eNB), a Radio Network Controller (RNC), and a Node B ( Node B, NB), Base Station Controller (BSC), Base Transceiver Station (BTS), Home Base Station (for example, Home evolved NodeB, or Home Node B, HNB), Baseband Unit (BaseBand Unit) , BBU), Access Point (AP) in wireless Fidelity (WIFI) system, wireless relay node, wireless backhaul node, transmission point (transmission and reception point, TRP or transmission point, TP And so on, it can also be 5G, such as NR, gNB in the system, or transmission point (TRP or TP), one or a group of base stations (including multiple antenna panels) in the 5G system, or, It may be a network node constituting a gNB or a transmission point, such as a baseband unit (BBU), or a distributed unit (DU) or the like.
  • the gNB may include a centralized unit (CU) and a DU.
  • the gNB may also include a radio unit (RU).
  • the CU implements some functions of the gNB, and the DU implements some functions of the gNB.
  • the CU implements radio resource control (RRC), the function of the packet data convergence protocol (PDCP) layer, and the DU implements the wireless chain.
  • RRC radio resource control
  • PDCP packet data convergence protocol
  • the DU implements the wireless chain.
  • the functions of the radio link control (RLC), the media access control (MAC), and the physical (PHY) layer Since the information of the RRC layer eventually becomes information of the PHY layer or is transformed by the information of the PHY layer, high-level signaling, such as RRC layer signaling or PHCP layer signaling, can also be used in this architecture.
  • the network device can be a CU node, or a DU node, or a device including a CU node and a DU node.
  • the CU may be divided into network devices in the access network RAN, and the CU may be divided into network devices in the core network CN, which is not limited herein.
  • a terminal device may also be called a user equipment (UE), an access terminal, a subscriber unit, a subscriber station, a mobile station, a mobile station, a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, and a user.
  • Agent or user device may be a mobile phone, a tablet, a computer with a wireless transceiver function, a virtual reality (VR) terminal device, and an augmented reality (AR) terminal.
  • VR virtual reality
  • AR augmented reality
  • the embodiment of the present application does not limit the application scenario.
  • network device 102 can communicate with a plurality of terminal devices (e.g., including terminal device 104 shown in the figures).
  • the terminal device 104 can also communicate with a plurality of network devices (e.g., including the network device 102 shown in the figures).
  • the scenario in which the network device 102 shown in FIG. 1 communicates with the terminal device 104 is only one possible scenario to which the communication method provided by the present application is applicable.
  • the communication method provided by the present application is also applicable to more scenarios. For example, a Coordination Multiple Point (CoMP) transmission scenario, a device to device (D2D) communication scenario, and the like are exemplified in FIG. 1 for ease of understanding and are not shown.
  • CoMP Coordination Multiple Point
  • D2D device to device
  • processing of the signal shown in FIG. 2 may be performed by the network device, or may be performed by the terminal device, which is not limited in this application.
  • the communication device #1 may transmit information data from the upper layer according to the size of the transport block supported by the system (for example, The information data of the media access control (MAC) layer is divided into a plurality of transport blocks (TBs), and for each transport block a 0 , a 1 , a 2 , a 3 , ..
  • MAC media access control
  • Each of the code blocks may include a number of bits in the transport block, and may also include CRC check bits of the bits, such as CRC check bits of 24 bits in length.
  • the code block may further include padding bits such that the code block length satisfies the block length requirement. For example, in the case of LPDC coding, the code block length satisfies an integral multiple of the spreading factor Z.
  • the communication device #1 can perform channel coding on each code block, for example, using LDPC coding to obtain a corresponding coded block.
  • a code block is sometimes referred to as an information sequence.
  • Each of the coded code blocks may include a plurality of pre-encoded information bits and a code-generated check bit in the code block, which may be collectively referred to as coded bits in the present application, and the sequence formed by the plurality of coded bits may be referred to as a coded bit sequence. .
  • the communication device #1 can store the above-described coded bit sequence in the circular buffer of the communication device #1 for rate matching.
  • the communication device #1 may select a piece of coded bits from the cyclic buffer, perform interleaving processing, perform modulation processing, map to modulation symbols, and transmit a signal including the modulation symbols.
  • the length of the coded bit sequence may refer to a bit sequence length of the transport block after code block partitioning and LDPC encoding. More specifically, the transport block is code-divided, LDPC-encoded, and then stored in the circular buffer, and then the bit data of the specified length is continuously read from the designated position of the buffer, and the padding bit is automatically skipped.
  • the soft value of the received coded bits can be stored in the corresponding position in the soft information buffer. If a retransmission occurs, the communication device #2 combines the soft values of the coded bits retransmitted each time in the soft information buffer, where the combination means that if the received coded bits are in the same position, they will be twice. The received soft values of the coded bits are combined.
  • the communication device #2 can directly decode all soft values in the soft information buffer, for example, LDPC decoding, to obtain a corresponding information sequence, for example, using LDPC decoding to obtain a corresponding information sequence.
  • the sequence of information obtained by channel decoding can be sent to the upper layer (eg, the MAC layer).
  • the process by which the communication device #2 processes the received modulation symbols to obtain a sequence of information can be regarded as the inverse of the process in which the communication device #1 processes the information data to be transmitted to obtain a coded bit sequence.
  • the communication device #1 and the communication device #2 can communicate using wireless technology.
  • the communication device #1 transmits a signal
  • the communication device #1 is a transmitting device.
  • the transmitting device can be referred to as an encoding device
  • the communication device #2 receives a signal
  • the communication device #2 is a receiving device.
  • the receiving end device may be referred to as a decoding (or decoding) device.
  • the communication device #1 may be the network device 102 shown in FIG. 1 or a chip configured in the network device 102.
  • the communication device #2 may be the terminal device 104 shown in FIG. 1 or configured in the terminal device 104.
  • the chip, or the communication device #1 may be the terminal device 104 shown in FIG. 1 or a chip configured in the terminal device 104, and the communication device #2 may be the network device 102 shown in FIG. 1 or configured on the network device 102. In the chip.
  • Low-density parity check (LDPC) code A class of linear block codes with sparse check matrices, that is, the density of non-zero elements in the check matrix is relatively low, that is, the zero elements in the check matrix are required to be much more Non-zero elements.
  • An [N, K] linear block code can be understood as a coded sequence of length K, which is encoded to obtain coded bits of code length N.
  • Coding code rate used to indicate the ratio of information code words to total code words in the channel coding process. For example, if the length of the information sequence is K and the length of the coded bit sequence is N, the code rate is K/N.
  • the ratio of the sequence length before each LDPC encoding to the length of the sequence obtained after encoding can be recorded as the encoding code rate.
  • the encoding code rate is the ratio of the length of the information sequence before the first LDPC encoding to the length of the first encoding bit sequence obtained after the encoding.
  • the code rate of the first LDPC coding may be referred to as a first coding bit rate; for the second LDPC coding, the coding code rate may be the length of the first coding bit sequence before the second LDPC coding The ratio of the length of the second coded bit sequence obtained after the coding is used in the embodiment of the present application.
  • the code rate of the second LDPC code may be referred to as a second code rate.
  • the code rate may be the ratio of the length of the information sequence before the first LDPC coding to the length of the second coded bit sequence obtained after the second LDPC coding.
  • Quasi-cyclic low-density parity check (QC-LDPC) code a subclass of LDPC.
  • the parity check matrix of QC-LDPC is obtained by extending a base matrix.
  • the base matrix can be referred to as H b and the check matrix as H.
  • the base map can be expressed as m ⁇ n matrix, including zero elements and non-zero elements, where zero elements can be represented by 0, -1 or null, etc., non-zero elements can be represented by 1, can be used to indicate The position of a non-zero element in one or more LDPC basis matrices, that is, the row and column positions of non-zero elements in the matrix. It can also be simplified in some implementations as a table indicating the row and column locations of non-zero elements. Usually, the first two columns of the base map are called built-in punch columns.
  • Base matrix A check matrix H that can be used to construct a QC-LDPC code.
  • the size of the basis matrix H b may be m ⁇ n, which is the same as the base map, and the size of the corresponding check matrix H is (m ⁇ Z) ⁇ (n ⁇ Z), where Z is called the expansion factor of the check matrix. (lifting size), m, n, Z are positive integers. Examples of extension factor values and set partitioning can be found in Table 1:
  • the expression of the base matrix in the QC-LDPC may be as follows, wherein the element of the position corresponding to the non-zero element in the base map has a value greater than or equal to 0, and the element of the position corresponding to the zero element may have a value of -1 or Null:
  • Check matrix The expression of the check matrix in QC-LDPC can be as follows:
  • Each element I(p i,j ) (0 ⁇ i ⁇ m-1 , 0 ⁇ j ⁇ n-1) in the check matrix H may be a zero matrix or a cyclic shift matrix.
  • the cyclic shift matrix (for example, I(p i,j )) may be obtained by cyclically shifting the unit matrix of the dimension Z ⁇ Z by p i,j bits. Therefore, p i,j is also referred to as the shift factor of the cyclic shift matrix.
  • the value of p i,j can be -1 ⁇ p i, j ⁇ Z.
  • each non-zero element p i,j (0 ⁇ i ⁇ m-1 , 0 ⁇ j ⁇ n-1) in the base matrix can be used to indicate the corresponding unit matrix required in the constructed check matrix The number of bits to be rotated.
  • p 0,0 can be used to indicate that the unit matrix I(p 0,0 ) of the upper left corner of the check matrix having a dimension of Z ⁇ Z needs to be cyclically shifted by p 0,0 . If I(p 0,0 ) is treated as a whole, the position of I(p 0,0 ) in the check matrix is the same as the position of p 0,0 in the base matrix, ie, row 0, column 0. .
  • the zero elements in the base or base matrix are replaced by a Z ⁇ Z zero matrix.
  • the first two columns in the base map of the check matrix H are built-in punctured bit columns, and the spreading factor is Z.
  • the number of corresponding built-in puncturing bits is 2Z, that is, c 0 , c 1 , c 2 , c 3 , ..., c 2Z-1 .
  • each element in the base matrix can be determined with reference to the prior art, for example, according to Table 5.3.2-2 LDPC base map 1 (H BG ) and its matrix (V i,j ) defined in the NR protocol TS 38.212. (See Table 3 below) and Table 5.3.2-3 LDPC Base Diagram 2 (H BG ) and its matrix (V i,j ) (see Table 2 below), due to different extension factor Z values
  • H BG LDPC Base Diagram 2
  • V i,j LDPC Base Diagram 2
  • a base map can often correspond to multiple base matrices or check matrices, and the values of non-zero elements in these matrices can be determined based on the set index of the spreading factor Z.
  • check matrix H is a full rank matrix
  • each information bit position after expansion is used to place information bits. If K is not divisible by k b , resulting in Z ⁇ k b >K, there will be (Z ⁇ k b -K) redundant information bit positions in the parity check matrix H of the extended LDPC, which may be called padding bits.
  • the padding bits can be represented by 0 or null.
  • QPSK Quadrature Phase Shift Keyin
  • AWGN additive white Gaussian
  • FIG. 3 is a comparison diagram of symbol-to-noise ratio and BLER relationship between LDPC code and Polar code.
  • BLER decreases with the increase of symbol SNR, and the curve does not float significantly; when LDPC coding is used, BLER is in the range of 10 0 to about 10 -3 ( Specifically, it may correspond to the range of A to B in the figure) the tendency of the BLER to decrease as the symbol signal to noise ratio increases (for example, can be characterized by the slope k 1 ), and the BLER is in the range of about 10 -3 to 10 -6 (specifically A significant fluctuation in the tendency of the BLER to decrease as the symbol-to-noise ratio increases (eg, can be characterized by the slope k 2 ), which corresponds to the range of B to C in the figure), is approximately 10 -3 in the BLER.
  • the BLER decreases with the increase of the signal-to-noise ratio, causing a significant floating, resulting in decoding.
  • a decrease in performance can be considered as an error floor in the BLER range of about 10 -3 to 10 -6 .
  • the error leveling can be understood as: a sudden decrease in the error performance curve from the low/medium signal to noise ratio waterfall area to the high signal to noise ratio area.
  • whether a fault leveling layer occurs may be determined according to a slope change in a different BLER range in a signal-to-noise ratio-BLER decoding performance curve. For example, when the difference or ratio of the slopes in two consecutive BLER ranges is greater than the preset threshold, an error leveling is considered; otherwise, no error leveling is considered.
  • the preset threshold may be predefined, and the value may be determined based on the strictness of the decision of the error leveling.
  • the present application provides a communication method to avoid the occurrence of an error leveling layer and improve LDPC decoding performance.
  • pre-definition may be implemented by pre-storing corresponding codes, tables, or other manners that can be used to indicate related information in a device (for example, including a terminal device and a network device).
  • a device for example, including a terminal device and a network device.
  • pre-definition can be defined in the protocol.
  • the “storage” involved in the embodiment of the present application may be stored in one or more memories.
  • the one or more memories may be separate arrangements or integrated in an encoder or decoder, processor, or communication device.
  • the one or more memories may also be partially provided separately, and some of them may be integrated in a decoder, a processor, or a communication device.
  • the type of the memory may be any form of storage medium, which is not limited herein.
  • the “protocol” may refer to a standard protocol in the communication field, and may include, for example, the LTE protocol, the NR protocol, and related protocols used in a communication system in the future, which is not limited in this application.
  • first, second, etc. are merely for facilitating the differentiation of different objects, and should not be construed as limiting the application. For example, distinguish between different check matrices, different coded bit sequences, and the like.
  • “and/or” describes the association relationship of the associated objects, indicating that there may be three relationships, for example, A and/or B, which may indicate that A exists separately, A and B exist simultaneously, and B exists separately. These three situations.
  • the character "/” generally indicates that the contextual object is an "or” relationship.
  • At least one means one or more; “at least one of A and B", similar to "A and/or B", describing the association of associated objects, indicating that there may be three relationships, for example, A and B. At least one of them may indicate that A exists separately, and A and B exist simultaneously, and B cases exist separately.
  • the communication method provided by the present application is applicable to a wireless communication system, such as the wireless communication system 100 shown in FIG.
  • the encoding device may correspond to (for example, may be configured or itself) the network device 102 in FIG. 1, and the decoding device may correspond to (for example, may be configured or itself) the terminal device 104 in FIG. 1;
  • the encoding device may correspond to (for example, may be configured or itself) to the terminal device 104 in FIG. 1
  • the decoding device may correspond to (eg, may be configured or itself) to the network device 102 in FIG.
  • the wireless communication system shown in FIG. 1 does not limit the scenario to which the communication method provided by the present application is applicable.
  • an encoding device can communicate with one or more decoding devices having a wireless communication connection based on the same method, and one decoding device can also be based on the same method, with one or more encodings having a wireless communication connection.
  • the device communicates. This application does not limit this.
  • FIG. 4 is a schematic flowchart of a communication method 200 provided by an embodiment of the present application, which is shown from the perspective of device interaction. As shown, the method 200 shown in FIG. 4 can include steps 210 through 260. The method 200 is described in detail below in conjunction with FIG.
  • step 210 the encoding device performs LDPC encoding on the information sequence based on the first check matrix to obtain a first encoded bit sequence.
  • the check matrix on which the first LDPC encoding is based is referred to as a first check matrix.
  • the coded bit sequence obtained by performing the first LDPC encoding on the information sequence based on the first check matrix may be referred to as a first coded bit sequence.
  • the process of performing LDPC encoding on the information sequence by the encoding device based on the first check matrix in step 210 can be recorded as the first LDPC encoding, and the corresponding code rate can be recorded as the first encoding rate.
  • the length L 1 of the first coded bit sequence and the length K of the information sequence satisfy: K/L 1 ⁇ 0.9.
  • the first code rate is greater than or equal to 0.9.
  • the encoding device may control the length L 1 of the first encoded bit sequence after the first encoding according to the requirement of the encoding code rate. For example, when the code rate is low and the first code rate is not satisfied, the length of the first coded bit sequence may be reduced by puncturing to achieve an effect of increasing the code rate.
  • the first code rate is
  • the LDPC code rate may be adjustable, that is, to be adjustable with the length of the information sequence. For example, when the length of the information sequence is long, the coding rate can be correspondingly increased; when the length of the information sequence is short, the coding rate can be correspondingly reduced.
  • the code rate when ⁇ and K are determined, the code rate can be adjusted by the correction value ⁇ to achieve the expected value.
  • the value of ⁇ is -Z ⁇ ⁇ ⁇ Z, and ⁇ is an integer.
  • the first code rate is predefined.
  • the first code rate is a protocol definition.
  • the encoding device and the decoding device may pre-store the first encoded bit rate.
  • the code rate can be designed to be a fixed value, for example, 0.9; it can also be designed to be tunable, for example, different code rates can be defined for different lengths of information sequences, for example, when the length of the information sequence is 100. At 300 o'clock, the corresponding code rate is 0.93; when the length of the information sequence is 300 to 500, the corresponding code rate is 0.95. It should be understood that the values of the coded rate and the correspondence between the length of the information sequence and the coded rate are merely exemplary and should not be construed as limiting the application.
  • the first code rate is determined by the source device and can be signaled to the sink device.
  • the method 200 further includes:
  • Step 220 The encoding device sends indication information, where the indication information is used to indicate the first encoding code rate.
  • the length of the first coded bit sequence can be determined based on the length of the information sequence and the first code rate.
  • the first code rate can be determined based on the length of the information sequence and the length of the first coded bit sequence.
  • the indication information may directly indicate the first encoding bit rate, or the indication information may also indicate the length of the first encoding bit sequence.
  • the indication information may be carried in high layer signaling.
  • the high layer signaling may include, for example, a radio resource control (RRC) message or a media access control (MAC) control element (CE).
  • RRC radio resource control
  • MAC media access control
  • the indication information may be carried in physical layer signaling.
  • physical layer signaling may include, for example, downlink control information.
  • the downlink control information may be DCI (downlink control information) in the NR protocol, or may be other signaling that can be used to carry downlink control information transmitted in the physical downlink control channel.
  • the physical downlink control channel mentioned herein may be a PDCCH (physical downlink control channel), an enhanced physical downlink control channel (EPDCCH), or a PDCCH in the NR. And other downstream channels with the above functions as the network evolves.
  • PDCCH physical downlink control channel
  • EPDCCH enhanced physical downlink control channel
  • the indication information may be carried by a modulation and coding scheme (MCS) field in the downlink control information.
  • MCS modulation and coding scheme
  • the process of performing LDPC encoding on the information sequence by the encoding device based on the first check matrix may be implemented by the following steps:
  • the encoding device determines the first check matrix according to the base map of the first check matrix
  • the encoding device performs LDPC encoding on the information sequence to be encoded based on the first check matrix to obtain a first encoded bit sequence.
  • the base map of the first check matrix is the base map 1BG1 in the new air interface NR protocol TS38.212.
  • the base map of the first check matrix is the base map 2BG2 in the NR protocol TS38.212.
  • each element in the base matrix is defined by different index values, that is, a plurality of different forms of the base matrix are indicated by different index values, and the check matrix can be constructed according to the base matrix and the spreading factor.
  • BG1 and BG2 see Tables 2 and 3 below.
  • the base map type of the first check matrix may be predefined.
  • the base map type of the first check matrix is predefined in the protocol.
  • the base map of the first check matrix is predefined as BG2, or the base map of the first check matrix is defined as BG1.
  • the base map of the first check matrix may be determined by referring to the NR protocol base map selection manner. That is, optionally, the method 200 further includes determining a base map of the first check matrix.
  • BG2 is used as the base map of the check matrix; otherwise, BG1 is used as the base map of the check matrix.
  • the code rate when determining the first check matrix for the first LDPC coding, may be the first code rate; and correspondingly, determining the second check matrix for the second LDPC code
  • the code rate may be a second code rate.
  • the base map of the first check matrix may be determined according to at least one of a size of an information payload in the transport block corresponding to the information sequence or a first code rate.
  • the spreading factor of the first check matrix can be determined based on the length of the information sequence, and then based on the base map and the first check The spreading factor of the matrix determines the first check matrix.
  • the above-listed BG1 and BG2 are merely illustrative and should not be construed as limiting the present application.
  • the present application does not exclude modification of an existing base map (for example, BG1 or BG2) in a future protocol.
  • the possibility of defining other forms of base maps in future agreements is not excluded.
  • the following takes BG1 and BG2 as examples, respectively, and details the specific process of determining the spreading factor of the first check matrix according to the length of the information sequence, and constructing the first check matrix based on the base map and the spreading factor of the first check matrix.
  • Step i determining the number of information columns k b according to the length of the information sequence.
  • k b can be determined by executing the following code:
  • Step ii Determine an expansion factor Z 1 of the first check matrix according to the number of information columns k b .
  • the lifting size Z 1 is determined , and the value of Z 1 is taken from the set of spreading factors listed in the foregoing Table 1, and Z 1 is satisfied.
  • Step iii Determine a first check matrix according to a base map of the first check matrix and a spreading factor Z 1 .
  • Table 2 shows the BG2 defined in the NR protocol TS38.212. The position of the non-zero elements in the base map is indicated by the row and column index in Table 2, and the other positions not shown are the positions where the zero elements are located.
  • Table 2 can be used to determine eight possible basis matrices, corresponding to the case where the index value (i LS ) is 1 to 8.
  • the dimension of each base matrix is 42 ⁇ 52, that is, each base matrix can be a matrix of 42 rows and 52 columns.
  • the number of columns (i.e., information columns) used for carrying information may be 10, or may be an integer less than 10, for example, 9, 8, or 6. When the number of information columns is less than 10, the partial columns in the 10 columns used as the information column may be intercepted, and are not used to carry information bits.
  • the first check matrix dimension is 42Z 1 ⁇ 52Z 1 .
  • the first check matrix can be determined.
  • Table 3 shows the BG1 defined in the NR protocol TS38.212.
  • the position of the non-zero element in the base map is indicated by the row and column index in Table 3.
  • the other positions not shown are the positions where the zero element is located.
  • Table 3 can be used to determine eight possible basis matrices, corresponding to the case where the index value (i LS ) is 1 to 8.
  • the dimension of each base matrix is 46 ⁇ 68, that is, each base matrix can be a matrix of 46 rows and 68 columns.
  • the number of columns for carrying information bits may be 22.
  • the specific process of determining the first check matrix according to BG1 and the spreading factor Z 1 is similar to the specific process of determining the first check matrix according to BG2 and the spreading factor in step iii above. For brevity, details are not described herein again. . It can be understood that when the base map of the first check matrix is BG1, the dimension of the first check matrix may be 46Z 1 ⁇ 68Z 1 .
  • the encoding device may perform LDPC encoding on the information sequence based on the first check matrix to obtain a first encoded bit sequence.
  • the first check matrix is a sparse matrix composed of 0 and 1.
  • the check matrix may be a sparse matrix composed of 0 and 1.
  • Each row in the check matrix can construct a check equation, and the value of each column can be used to indicate whether a bit in the information sequence appears in the check equation. For example, "1" represents occurrence and "0" represents no occurrence.
  • v 1 to v 4 represent the first to fourth bits in the information bits
  • v 5 represents the first bit in the parity bits.
  • the first bit in the check bit is obtained by the check equation, that is, the first bit in the output coded bit sequence.
  • the method for determining a coded bit sequence based on a check matrix is exemplified herein for convenience of understanding and description.
  • the specific process of determining a coded bit sequence based on the check matrix may refer to the prior art, and the present application determines the check matrix based on the check matrix.
  • the specific method of encoding the bit sequence is not limited.
  • the encoding device may perform LDPC encoding on the information sequence of length K.
  • a sequence of information of length K can be placed by k b ⁇ Z bits, and when K > k b ⁇ Z, the remaining (Kk b ⁇ Z) bits can be placed with padding bits.
  • the encoding device may perform code block segmentation on the transport block from the upper layer according to the size of the transport block supported by the system.
  • the size of the transport block supported by the system can be understood as the length of the information sequence, and the size of the length can be predefined, for example, a protocol definition.
  • step 230 the encoding device performs LDPC encoding based on the second parity check matrix and the first coded bit sequence to obtain a second coded bit sequence.
  • the check matrix on which the second LDPC encoding is based is referred to as a second check matrix.
  • the coded bit sequence obtained by performing the second LDPC encoding on the information sequence and the first coded bit sequence based on the second check matrix may be referred to as a second coded bit sequence.
  • the process of performing LDPC encoding by the encoding device based on the second parity check matrix and the first coded bit sequence in step 210 can be recorded as the second LDPC code, and the code rate corresponding thereto can be recorded as the second code rate.
  • the encoding device may perform LDPC encoding on the first coded bit sequence based on the second check matrix.
  • the encoding device may process the first coded bit sequence, for example, perform interleaving, or scrambling, or interleave and scramble, and then perform processing on the processed first coded bit sequence.
  • LDPC encoding may be to change or exchange the positions of the bits in the first coded bit sequence.
  • the scrambling process may be a scrambling operation using a specific scrambling code sequence or a random sequence on the first coded bit sequence.
  • step 230 can include:
  • Encoding the device to perform LDPC encoding on the first coded bit sequence based on the second check matrix to obtain a second coded bit sequence
  • the encoding device performs LDPC encoding on the interleaved or scrambled first coded bit sequence based on the second check matrix to obtain a second coded bit sequence.
  • burst interference, regular interference, and the like that may be encountered during signal transmission can be randomly dispersed in the coded bits, so that data can be recovered by error correction technology, thereby improving signal transmission.
  • step 230 can be implemented by the following steps:
  • the encoding device determines a second check matrix based on the base map of the second check matrix
  • the encoding device performs LDPC encoding based on the second parity check matrix and the first coded bit sequence to obtain a second coded bit sequence.
  • the base map of the second check matrix may be predefined, for example, a base map type of the second check matrix is predefined in the protocol.
  • the base map of the second check matrix may also be based on the length or information of the coded bit sequence to be subjected to the second LDPC coding (for example, the first coded bit sequence or the first coded bit sequence that is interleaved or scrambled) At least one of the code rates of the transport blocks corresponding to the sequence is determined. That is, optionally, the method 200 further includes determining a base map of the second check matrix.
  • the length of the first coded bit sequence after the interleaving or scrambling process may be based on the first coded bit output after the first LDPC coding.
  • the length of the sequence and the pre-defined interleaving algorithm or scrambling sequence are determined.
  • the specific method for determining the length of the first coded bit sequence after interleaving or scrambling is not limited.
  • the second encoding rate may be predefined or may be based on a predefined encoding rate (ie, the ratio of the length of the information sequence to the length of the encoded bit sequence output after LDPC encoding) and the first encoding.
  • the code rate is calculated, which is not limited in this application.
  • the spreading factor Z 2 of the second check matrix can also be re-determined according to the length L 1 of the encoded bit sequence to be subjected to the second LDPC encoding.
  • the value of Z 2 can be, for example, taken from the set of spreading factors listed in Table 1 above, and Z 2 is the minimum value satisfying k b ⁇ Z 2 ⁇ L 1 .
  • the coded bit sequence to be subjected to the second LDPC coding may be the first coded bit sequence itself, or may be an interleaved or scrambled first coded bit sequence, and the length of the first coded bit sequence is The length of the interleaved or scrambled first coded bit sequence may be the same or different, which is not limited in this application.
  • the base map of the second check matrix is BG1 in the new air interface NR protocol TS38.212.
  • the base map of the second check matrix is BG2 in the NR protocol TS38.212.
  • the expansion factor of the second check matrix is determined according to the length of the sequence to be encoded, and the specific structure of the check matrix is constructed based on the spreading factors of the base map and the second check matrix.
  • a process, in step 230, determining a spreading factor of the second check matrix according to a length of the first coded bit sequence or a length of the processed first coded bit sequence, and constructing an extension factor based on the base map and the second check matrix The specific process of the second check matrix is similar to the specific process in the above step 210. For the sake of brevity, a detailed description of the specific process is omitted here.
  • base map of the first check matrix and the base map of the second check matrix may be the same or different, which is not limited in this application.
  • the input may be a sequence of information to be encoded, and the output may be a first coded bit sequence.
  • the input may be the first coded bit sequence, or may be interleaved.
  • the output may be a second coded bit sequence, that is, the output of step 210 may be used as an input to step 230, or the output of step 210 may be processed as an input to step 230. .
  • steps 210 and 230 may be performed by two independent encoders that LDPC encode the input sequence by executing program code.
  • the information sequence to be encoded may be used as an input, and the first coded bit sequence may be used as an output.
  • the encoder #2 the first coded bit sequence or the processed The first coded bit sequence is used as an input and the second coded bit sequence is taken as an output. It can be understood that after the encoder #1 outputs the first coded bit sequence, it can be used to perform LDPC encoding on the newly input information sequence to be encoded; before the encoder #1 outputs the first coded bit sequence, the code is encoded.
  • the device #2 can also be used for LDPC encoding the other coded bit sequences that have been input before, which is not limited in this application.
  • step 210 and step 230 may also be performed by two coding units of an encoder that can perform LDPC encoding of the input sequence by executing program code.
  • the information sequence to be coded may be used as an input, and the first coded bit sequence may be used as an output.
  • the first coded bit sequence or the processed may be used. The first coded bit sequence is used as an input and the second coded bit sequence is taken as an output.
  • the coding unit #1 after the coding unit #1 outputs the first coded bit sequence, it can be used to perform LDPC coding on the newly input information sequence to be encoded; before the coding unit #1 outputs the first coded bit sequence, the coding The unit #2 can also be used for LDPC encoding other previously encoded bit sequences, which is not limited in this application.
  • step 210 and step 230 may also be performed by the same coding unit of an encoder. Taking the information sequence to be encoded as an input, after obtaining the first coded bit sequence, the obtained first coded bit sequence or the processed first coded bit sequence is re-inputted until the second coded bit sequence is obtained and output.
  • a method for performing LDPC encoding on a sequence of information multiple times may be referred to as cascading LDPC encoding.
  • the information sequence is LDPC coded twice, the number of cascades is said to be 2.
  • the embodiment of the present application is only for ease of understanding and description.
  • the process of LDPC encoding the information sequence by the encoding device is described in detail by taking the process of two LDPC encoding as an example, but this application should not constitute any limitation.
  • the number of times of LDPC coding is not limited.
  • the second coded bit sequence may be used as an input of the next LDPC code to output a third coded bit sequence, which may be sent to the decoding device.
  • the coded bit sequence can also be used as an input of another LDPC code, which is not limited in this application.
  • the specific process of performing LDPC encoding on the coded bit sequence is similar to the specific process described in step 210 above. For brevity, no further details are provided herein.
  • the encoding device performs LDPC encoding twice.
  • the method 200 further includes: Step 240, the encoding device sends the second encoded bit sequence.
  • step 240 the decoding device receives the second sequence of coded bits.
  • the encoding device may further transmit the second coded bit sequence (the second coded bit sequence transmitted by the encoding device is referred to as the original second coded bit sequence for convenience of distinction and description), and the second coded bit sequence may be further Processing such as rate matching, interleaving, modulation, etc., is performed to transmit the second coded bit sequence to the decoding device through the antenna in the form of a symbol.
  • the signal received by the decoding device may be a symbol obtained by interpolating, modulating, etc.
  • the decoding device may first perform demodulation, deinterleaving, and rate matching on the symbol to obtain Soft value information or hard value information of the second coded bit sequence (for convenience of distinction and description, the second coded bit sequence recovered by the decoding device is referred to as a recovered second coded bit sequence), and then the second coded bit is The soft value information or hard value information of the sequence is decoded.
  • soft value information or hard value information is obtained depending on the method used.
  • bit sequence A if bit sequence A is subjected to encoding, rate matching, interleaving, and modulation, etc., a signal that can be transmitted is obtained, and demodulation of the signal can obtain demodulated soft value information or demodulation hard of bit sequence A.
  • the value information is used to decode the demodulated soft value information or the demodulated hard value information of the bit sequence A to obtain the decoded soft value information or the decoded hard value information of the bit sequence A.
  • a hard decision is used, and the hard value information of the corresponding bit sequence is obtained, and each bit of the bit sequence is judged to be a value of 0 or 1; for example, in demodulation Or soft decision is used in decoding, the soft value information of the corresponding bit sequence can be obtained, and the soft value can include the measure of information reliability, and can also include hard value information, so that the information is judged according to the information when decoding. Bits.
  • the examples are merely examples and are not limited thereto.
  • the specific process of the coding device to process the coded bit sequence after the channel coding and the specific process of the decoding device to process the received signal to obtain the coded bit sequence to be decoded may refer to the prior art, and for the sake of brevity, the description is omitted here. A detailed description of the specific process.
  • the decoding device solves the received symbol.
  • the restored second coded bit sequence corresponding to the soft value information or the hard value information obtained after the modulation, deinterleaving, and de-rate matching may not be identical to the original second coded bit sequence, but this should not constitute the present application. Any restrictions.
  • the original second coded bit sequence and the recovered second coded bit sequence are referred to as a second coded bit sequence.
  • the decoding device may perform LDPC decoding on the received encoded bit sequence in a corresponding manner.
  • the manner in which the decoding apparatus performs LDPC decoding may be referred to as cascaded LDPC decoding.
  • step 250 the decoding device performs LDPC decoding on the soft value information or the hard value information of the second coded bit sequence based on the second check matrix to obtain soft value information or hard value information of the third coded bit sequence.
  • the process of performing LDPC decoding on the coded bits by the decoding device may be regarded as a reverse process of the process of performing LDPC encoding on the information sequence by the encoding end. That is, for the decoding device, the soft value information or the hard value information of the second coded bit sequence may be used as the input of the first LDPC decoding, and the output may be the soft value information or the hard value information of the third coded bit sequence.
  • the soft value information or the hard value information of the third coded bit sequence may be used as an input of the second LDPC decoding, and the output may be an information sequence, that is, information sent by the coding device that the decoding device wishes to recover by decoding. sequence.
  • the soft bit information obtained by the first LDPC decoding or the coded bit sequence corresponding to the hard value information is recorded as the third coded bit sequence.
  • the process of performing LDPC decoding on the soft value information or the hard value information of the second coded bit sequence by the decoding device in step 250 based on the second check matrix may be recorded as the first LDPC decoding.
  • the soft code information obtained by the first LDPC decoding in step 250 or the third coded bit sequence corresponding to the hard value information may correspond to the coded bit sequence to be subjected to the second LDPC coding in step 230.
  • the third coded bit sequence may be understood as a first coded bit sequence obtained by LDPC decoding;
  • the check matrix performs LDPC encoding on the interleaved or scrambled first coded bit sequence, and the third coded bit sequence can be understood as an interleaved or scrambled first coded bit sequence obtained by LDPC decoding.
  • the decoded first coded bit sequence and the decoded interleaved or scrambled first coded bit sequence are collectively referred to as a third coded bit sequence.
  • step 250 specifically includes:
  • Decoding device determines a second check matrix according to a base map of the second check matrix
  • the decoding device performs LDPC decoding on the second coded bit sequence based on the second check matrix to obtain soft value information or hard value information of the third coded bit sequence.
  • the specific method of determining the second check matrix based on the base map of the second check matrix may be the same as the specific method of determining the second check matrix based on the second base matrix in step 230.
  • the decoding device may determine a spreading factor of the second check matrix according to a length of the third coded bit sequence, and determine the second check matrix based on a base factor and a spreading factor of the second matrix.
  • the length of the third coded bit sequence may be, for example, determined by the decoding device according to the first code rate (for example, may be predefined or The encoding device indicates) and the length of the predefined information sequence is determined, or may be indicated by the encoding device by signaling; if the third encoded bit sequence is the LDPC decoded interleaved or scrambled first encoded bit Sequence, the length of the third coded bit sequence may be determined by the decoding device according to the first code rate, the predefined interleaving algorithm, the predefined scrambling sequence, and the length of the predefined information sequence, or may be The encoding device is indicated by signaling.
  • the specific method for determining the length of the third coded bit sequence is not limited in the present application.
  • the decoding device may perform the first LDPC decoding on the soft value information or the hard value information of the second coded bit sequence by using an existing decoding algorithm to obtain soft value information or hard value information of the first coded bit sequence.
  • the LDPC coding algorithm may include, for example, a Belief Propagation algorithm, a layered offset min-sum (LOMS) algorithm, a layered normalized min- Sum, LNMS) algorithm, etc. These algorithms are based on the evolution of the Message Passing Algorithm, which is an iterative calculation between the check node and the bit node.
  • step 260 the decoding device performs LDPC decoding based on the soft value information or the hard value information of the first parity check matrix and the third coded bit sequence to obtain a sequence of information.
  • the process of performing LDPC decoding by the decoding apparatus in step 260 based on the soft value information or the hard value information of the first parity check matrix and the third coded bit sequence may be recorded as the second LDPC decoding.
  • the third coded bit sequence may be the first coded bit sequence, or may be the first coded bit sequence that is interleaved or scrambled.
  • the decoding device may be based on the first A parity check matrix performs LDPC decoding on soft value information or hard value information of the third coded bit sequence; in another possible implementation manner, the decoding device may perform deinterleaving or descrambling based on the first check matrix pair
  • the soft value information or the hard value information of the third coded bit sequence is LDPC decoded.
  • step 260 can include:
  • Decoding by the decoding device, LDPC decoding the soft value information or the hard value information of the third coded bit sequence to obtain an information sequence;
  • the decoding device performs LDPC decoding on the soft value information or the hard value information of the third coded bit sequence after deinterleaving or descrambling based on the first check matrix to obtain an information sequence.
  • the object of the second LDPC decoding by the decoding device may depend on whether the encoding device interleaves or scrambles the first coded bit sequence before the second LDPC encoding.
  • the encoding device interleaves or scrambling the first coded bit sequence
  • burst interference, regular interference, and the like that may be encountered during signal transmission can be randomly dispersed in the coded bits, so that data can be recovered by error correction technology, thereby improving signal transmission.
  • Anti-interference ability improve demodulation performance.
  • step 260 specifically includes:
  • Decoding device determines a first check matrix based on a base map of the first check matrix
  • the decoding device performs LDPC decoding based on the soft value information or the hard value information of the first parity check matrix and the third coded bit sequence to obtain soft value information or hard value information of the information sequence;
  • the decoding device determines the soft value information or the hard value information of the information sequence to obtain a sequence of information.
  • the specific method for determining the first check matrix based on the base map of the first check matrix may be the same as the specific method for determining the first check matrix based on the base map of the first check matrix in step 210.
  • the decoding device may determine the spreading factor of the first check matrix according to the length of the information sequence, and determine the first check matrix based on the base map and the spreading factor of the first check matrix.
  • the decoding apparatus may perform a second LDPC decoding on the soft value information or the hard value information of the third coded bit sequence by using a decoding algorithm to obtain soft value information or hard value information of the information sequence, and The soft value information or the hard value information of the information sequence may be further determined to obtain the information sequence.
  • the specific process of performing LDPC decoding by using a decoding algorithm may refer to the prior art, and a detailed description of the specific process is omitted here for brevity.
  • steps 250 and 260 may be performed by two independent decoders that LDPC decode the input sequence by executing program code.
  • the soft value information or the hard value information of the second coded bit sequence to be decoded may be input, and the soft value information or the hard value information of the third coded bit sequence may be Output
  • the soft value information or hard value information of the third coded bit sequence or the soft value information or hard value information of the third coded bit sequence subjected to interleaving or scrambling processing may be input. Take the sequence of information as an output.
  • the decoder #1 after the decoder #1 outputs the soft value information or the hard value information of the first coded bit sequence, it can be used for the soft value information or the hard value information of the newly input coded bit sequence to be decoded.
  • the decoder #2 before the decoder #1 outputs the soft value information or the hard value information of the first decoding bit sequence, the decoder #2 can also be used for soft value information of other coded bit sequences previously input or Hard value information is used for LDPC decoding, which is not limited in this application.
  • steps 250 and 260 may also be performed by two decoding units of a decoder that can perform LDPC on the input sequence by executing program code.
  • Decoding Specifically, for the decoding unit #1, the soft value information or the hard value information of the second coded bit sequence to be decoded may be input, and the soft value information or the hard value information of the third coded bit sequence may be output.
  • the soft value information or the hard value information of the third coded bit sequence or the soft value information or the hard value information of the third coded bit sequence subjected to the interleaving or scrambling process may be input. The sequence of information is output.
  • the decoding unit #1 after the decoding unit #1 outputs the soft value information or the hard value information of the first coded bit sequence, it can be used for the soft value information or the hard value information of the newly input coded bit sequence to be decoded.
  • the decoding unit #2 may also be used for soft value information of other coded bit sequences previously input or Hard value information is used for LDPC decoding, which is not limited in this application.
  • steps 250 and 260 may also be performed by the same decoding unit of a decoder.
  • the soft value information or the hard value information of the second coded bit sequence to be decoded is input, and after the soft value information or the hard value information of the third coded bit sequence is obtained, the soft value information of the obtained third coded bit sequence is obtained.
  • the soft value information or the hard value information or the hard value information of the processed third coded bit sequence is re-inputted until the information sequence is obtained and output.
  • the information sequence that the encoding device wants to transmit and that has not undergone LDPC encoding (for the sake of distinction and description, the information sequence that has not undergone LDPC encoding is referred to as the original information sequence) and the decoding device LDPC
  • the decoded information sequence (the sequence of information obtained by decoding the LDPC decoding device is referred to as a recovered information sequence for convenience of distinction and description) may not be identical, and the method provided by the present application aims to improve the recovered information sequence. Similarity to the original sequence of information.
  • the similarity of two binary sequences can be characterized by the Hamming distance of the two binary sequences.
  • the Hamming distance may refer to the total number of different locations of the two binary sequences. For example, for binary codes “110” and “111”, Hamming distance is 1; for binary codes “000” and “111”, Hamming distance is 3; for binary codes "101" and "101", Hamming distance It is 0. Therefore, the smaller the Hamming distance, the higher the similarity.
  • the number of times that the decoding device performs LDPC decoding is the same as the number of times that the encoding device performs LDPC encoding.
  • the performance loss due to the cascaded LDPC coding can be reduced as much as possible.
  • the first code rate is controlled to be around 0.9.
  • FIG. 5 is a performance comparison diagram of LDPC encoding and decoding using the LDPC codec and the communication method provided by the embodiment of the present application.
  • FIG. 5 if LDPC encoding and decoding are performed only once, an error leveling layer occurs in a range where the BLER is less than 10 -3 ; if the communication method provided by the present application is used to perform two cascaded LDPC encoding and decoding, When the BLER is less than 10 -3 , the curve of BLER and symbol signal-to-noise ratio does not significantly float. The trend of BLER decreasing with the increase of signal-to-noise ratio has not changed significantly, that is, the BLER is less than 10 -3 .
  • the error leveling layer is therefore beneficial for improving decoding performance.
  • the length of the information sequence is 420
  • the length of the first coded bit sequence is 108
  • the length of the second coded bit sequence is 94.
  • the first check matrix and the second check matrix are respectively based on BG2 determines, and the first check matrix is determined based on BG2, and the second check matrix is determined based on BG1.
  • the information sequence is cascading LDPC coded by the encoding device, and the decoding device performs cascading LDPC decoding on the second coded bit sequence, thereby avoiding obvious error flatness of the BLER in the range of 10 0 to 10 -6
  • the layer ie, facilitates a lower BLER over a higher signal to noise ratio range, thereby achieving better decoding performance over a larger signal to noise ratio range.
  • the performance loss caused by multiple LDPC coding can be reduced, and overall, it is beneficial to improve system performance, so that the transmission system can meet different service types. Demand.
  • FIG. 6 is a schematic block diagram of a communication apparatus provided by an embodiment of the present application. As shown in FIG. 6, the communication device 300 can include an encoding unit 310.
  • the communication device 300 can be an encoding device, or a chip disposed in the encoding device.
  • the encoding device can be a transmitting device in wireless transmission.
  • the coding device may be a network device in the downlink transmission, a terminal device in the uplink transmission, or a terminal device in the D2D transmission, which is not limited in this application.
  • the encoding unit 310 is configured to perform low-density parity check LDPC encoding on the information sequence to be encoded according to the first check matrix, to obtain a first encoded bit sequence;
  • the encoding unit 310 is further configured to perform LDPC encoding based on the second parity check matrix and the first coded bit sequence to obtain a second coded bit sequence.
  • the coding unit 310 is specifically configured to:
  • the interleaved or scrambled first coded bit sequence is LDPC encoded based on the second check matrix.
  • the length K of the information sequence and the length L 1 of the first coded bit sequence are:
  • the length K of the information sequence and the length L 1 of the first coded bit sequence are:
  • the communication device 300 further includes a communication unit 320, configured to send indication information, where the indication information is used to indicate a length of the first coded bit sequence.
  • the communication device 300 further includes a determining unit 330, configured to determine a length of the first coded bit sequence according to the length of the information sequence and a predefined code rate.
  • a determining unit 330 configured to determine a length of the first coded bit sequence according to the length of the information sequence and a predefined code rate.
  • the communication device 300 further includes a determining unit 330, configured to determine a base map of the first check matrix; and/or a base map of the second check matrix.
  • a determining unit 330 configured to determine a base map of the first check matrix; and/or a base map of the second check matrix.
  • the base map of the first check matrix is the base map 1BG1 in the new air interface NR protocol
  • the base map of the second check matrix is the base map 2BG2 in the NR protocol
  • the base map of the first check matrix is BG2, and the base map of the second check matrix is BG1; or
  • the base map of the first check matrix is BG1, and the base map of the second check matrix is BG1; or
  • the base map of the first check matrix is BG2, and the base map of the second check matrix is BG2;
  • BG1 is used to determine the check matrix with the dimension of 46Z ⁇ 68Z
  • BG2 is used to determine the check matrix with the dimension of 42Z ⁇ 52Z
  • Z is the expansion factor.
  • the communication device 300 can correspond to an encoding device in the communication method 200 in accordance with an embodiment of the present invention, which can include a unit for performing the method performed by the encoding device of the communication method 200 of FIG.
  • the units in the communication device 300 and the other operations and/or functions described above are respectively used to implement the corresponding processes of the communication method 200 in FIG. 2, and specifically, the encoding unit 310 is configured to perform steps 210 and 230 in the method 200.
  • the communication unit 320 is configured to perform the steps 220 and 240 in the method 200. The specific process in which each unit performs the foregoing steps is described in detail in the method 200. For brevity, no further details are provided herein.
  • FIG. 7 is another schematic block diagram of a communication apparatus according to an embodiment of the present application.
  • the communication device 400 can include a decoding unit 410.
  • the communication device 300 can be a decoding device or a chip disposed in the decoding device.
  • the decoding device can be a receiving device in wireless transmission.
  • the decoding device may be a terminal device in a downlink transmission, a network device in an uplink transmission, or a terminal device in a D2D transmission, which is not limited in this application.
  • the decoding unit 410 may be configured to perform low-density parity check LDPC decoding on the soft-value information or the hard-value information of the second coded bit sequence to be coded by the second check matrix to obtain a third coded bit sequence.
  • Soft value information or hard value information Soft value information
  • the decoding unit 410 is further configured to perform LDPC decoding based on the first check matrix and the soft value information or the hard value information of the third coded bit sequence to obtain an information sequence.
  • the third coded bit sequence is a first coded bit sequence, or the third coded bit sequence is a first coded bit sequence that is interleaved or scrambled.
  • the decoding unit 410 is specifically configured to perform LDPC decoding on the soft value information or the hard value information of the first coded bit sequence based on the first check matrix;
  • the decoding unit 410 is specifically configured to: perform soft value information on the first coded bit sequence that is deinterleaved or descrambled based on the first check matrix. Or hard value information for LDPC decoding.
  • the length K of the information sequence and the length L 1 of the first coded bit sequence are:
  • the length K of the information sequence and the length L 1 of the first coded bit sequence are:
  • the communication device 400 further includes a communication unit 420, configured to receive indication information, where the indication information is used to indicate a length of the first coded bit sequence.
  • the communication device 400 further includes a determining unit 430, configured to determine a length of the first coded bit sequence according to the length of the information sequence and a predefined code rate.
  • a determining unit 430 configured to determine a length of the first coded bit sequence according to the length of the information sequence and a predefined code rate.
  • the communication device 400 further includes a determining unit 430, configured to determine a base map of the first check matrix; and/or a base map of the second check matrix.
  • a determining unit 430 configured to determine a base map of the first check matrix; and/or a base map of the second check matrix.
  • the base map of the first check matrix is the base map 1BG1 in the new air interface NR protocol
  • the base map of the second check matrix is the base map 2BG2 in the NR protocol
  • the base map of the first check matrix is BG2, and the base map of the second check matrix is BG1; or
  • the base map of the first check matrix is BG1, and the base map of the second check matrix is BG1; or
  • the base map of the first check matrix is BG2, and the base map of the second check matrix is BG2;
  • BG1 is used to determine the check matrix with the dimension of 46Z ⁇ 68Z
  • BG2 is used to determine the check matrix with the dimension of 42Z ⁇ 52Z
  • Z is the expansion factor.
  • the communication device 400 can correspond to a coding device in the communication method 200 in accordance with an embodiment of the present invention, which can include a unit for performing the method performed by the coding device of the communication method 200 of FIG.
  • each unit in the communication device 400 and the other operations and/or functions described above are respectively used to implement the corresponding flow of the communication method 200 in FIG. 2, and specifically, the decoding unit 410 is configured to perform steps 250 and steps in the method 200. 260.
  • the communication unit 420 is configured to perform the steps 220 and 240 in the method 200. The specific process of performing the foregoing steps in each unit has been described in detail in the method 200. For brevity, no further details are provided herein.
  • FIG. 8 is a schematic structural diagram of a network device 500 according to an embodiment of the present application.
  • the network device 500 includes a processor 500 and a transceiver 520.
  • the network device 500 further includes a memory 530.
  • the processor 510, the transceiver 520, and the memory 530 communicate with each other through an internal connection path for transferring control and/or data signals.
  • the memory 530 is used to store a computer program, and the processor 510 is configured to be called from the memory 530.
  • the computer program is run to control the transceiver 520 to send and receive signals.
  • the processor 510 and the memory 530 may be combined to form a processing device, and the processor 510 is configured to execute the program code stored in the memory 530 to implement the above functions.
  • the memory 530 may also be integrated in the processor 510 or independent of the processor 510 when implemented.
  • the network device 500 may further include an antenna 540, configured to send downlink data or downlink control signaling output by the transceiver 520 by using a wireless signal.
  • the network device 500 may correspond to the encoding device in the communication method 200 according to the embodiment of the present application, and may also correspond to the decoding device in the communication method 200 of the embodiment of the present application.
  • the network device 500 may include a module for performing the method performed by the encoding device of the communication method 200 of FIG.
  • each module in the network device 500 and the other operations and/or functions described above are respectively implemented to implement the corresponding flow of the communication method 200 in FIG.
  • the memory 530 is configured to store program code, such that when the program code is executed, the processor 510 executes step 210 and step 230 in the method 200, and controls the transceiver 520 to perform step 220 in the method 200 through the antenna 540.
  • step 240 The specific process in which each module performs the above-mentioned corresponding steps has been described in detail in the method 200. For brevity, no further details are provided herein.
  • the encoding unit 310 and the determining unit 330 in FIG. 6 may correspond to (for example, may be configured or be itself) the processor 510 in FIG. 8, and the communication unit 320 in FIG. 6 may be Corresponding to (eg, may be configured or itself) is the transceiver 520 of FIG.
  • the network device 500 may include a module for performing the method performed by the decoding device of the communication method 200 of FIG.
  • each module in the network device 500 and the other operations and/or functions described above are respectively implemented to implement the corresponding flow of the communication method 200 in FIG.
  • the memory 530 is configured to store program code, such that when the program code is executed, the processor 510 executes steps 250 and 260 of the method 200, and controls the transceiver 520 to perform step 220 of the method 200 through the antenna 540.
  • step 240 The specific process in which each module performs the above-mentioned corresponding steps has been described in detail in the method 200. For brevity, no further details are provided herein.
  • the coding unit 410 and the determining unit 430 in FIG. 7 may correspond to (eg, may be configured or be itself) the processor 510 of FIG. 4, the communication unit 420 of FIG.
  • the transceiver 520 of FIG. 8 may be corresponding (eg, may be configured or itself).
  • FIG. 9 is a schematic structural diagram of a terminal device 600 according to an embodiment of the present application.
  • the terminal device 600 includes a processor 601 and a transceiver 602.
  • the terminal device 600 further includes a memory 603.
  • the processor 601, the transceiver 602 and the memory 603 communicate with each other through an internal connection path for transmitting control and/or data signals
  • the memory 603 is for storing a computer program
  • the processor 601 is used for the memory 603.
  • the computer program is called and executed to control the transceiver 602 to send and receive signals.
  • the processor 601 and the memory 603 may be combined to form a processing device 604 for executing the program code stored in the memory 603 to implement the above functions.
  • the memory 603 may also be integrated in the processor 601 or independent of the processor 601.
  • the terminal device 600 may further include an antenna 610, configured to send uplink data or uplink control signaling output by the transceiver 602 by using a wireless signal.
  • the terminal device 600 may correspond to the decoding device in the communication method 200 according to an embodiment of the present application, which may also correspond to the encoding device in the communication method 200 of the embodiment of the present application.
  • the communication device 600 may include a module for performing the method performed by the decoding device of the communication method 200 of FIG. 2, and the terminal
  • the various modules in device 600 and the other operations and/or functions described above are respectively implemented to implement the corresponding flow of communication method 200 of FIG.
  • the memory 603 is configured to store program code such that when executing the program code, the processor 601 executes steps 250 and 260 of the method 200 and controls the transceiver 602 to perform steps 220 and 240 of the method 200.
  • the specific process in which each module performs the above-mentioned corresponding steps has been described in detail in the method 200. For brevity, no further details are provided herein.
  • the above processor 601 can be used to perform the actions implemented by the decoding device described in the foregoing method embodiments, and the transceiver 602 can be used to execute the decoding device described in the foregoing method embodiment to receive the signal transmitted or transmitted by the encoding device. Actions. For details, please refer to the description in the previous method embodiments, and details are not described herein again.
  • the coding unit 410 and the determining unit 430 in FIG. 7 may correspond to (eg, may be configured or itself) the processor 601 in FIG. 9, the communication unit 420 in FIG.
  • the transceiver 602 of Figure 9 may be corresponding (e.g., may be configured or itself).
  • the terminal device 600 may include a module for performing the method performed by the encoding device of the communication method 200 of FIG. 2, and the terminal device 600
  • the memory 603 is configured to store the program code, so that when the program code is executed, the processor 601 executes step 210 and step 230 in the method 200, and controls the transceiver 602 to perform step 220 in the method 200 through the antenna 610.
  • step 240 The specific process in which each module performs the above-mentioned corresponding steps has been described in detail in the method 200. For brevity, no further details are provided herein.
  • the above processor 601 can be used to perform the actions implemented by the encoding device described in the foregoing method embodiments, and the transceiver 602 can be used to perform the action of the encoding device described in the foregoing method embodiment to transmit or transmit a signal to the decoding device. .
  • the transceiver 602 can be used to perform the action of the encoding device described in the foregoing method embodiment to transmit or transmit a signal to the decoding device.
  • the encoding unit 310 and the determining unit 330 in FIG. 6 may correspond to (for example, may be configured or be itself) the processor 601 in FIG. 9, and the communication unit 320 in FIG. 6 may be Corresponding to (e.g., may be configured or itself) the transceiver 602 of Figure 9.
  • processor 601 and the memory 603 may be integrated into one processing device, and the processor 601 is configured to execute the program code stored in the memory 603 to implement the above functions.
  • the memory 603 can also be integrated in the processor 601.
  • the terminal device 600 described above may also include a power source 605 for providing power to various devices or circuits in the terminal.
  • the terminal device 600 may further include one or more of an input unit 614, a display unit 616, an audio circuit 618, a camera 620, a sensor 622, and the like, the audio circuit.
  • an input unit 614 a display unit 616
  • an audio circuit 618 a camera 620
  • a sensor 622 a sensor
  • the audio circuit a speaker 6182, a microphone 6184, and the like can also be included.
  • the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSPs), and dedicated integration.
  • DSPs digital signal processors
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be a read-only memory (ROM), a programmable read only memory (ROMM), an erasable programmable read only memory (erasable PROM, EPROM), or an electrical Erase programmable EPROM (EEPROM) or flash memory.
  • the volatile memory can be a random access memory (RAM) that acts as an external cache.
  • RAM random access memory
  • RAM random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • synchronous dynamic randomness synchronous dynamic randomness.
  • Synchronous DRAM SDRAM
  • DDR SDRAM double data rate synchronous DRAM
  • ESDRAM enhanced synchronous dynamic random access memory
  • SLDRAM synchronous connection dynamic random access memory Take memory
  • DR RAM direct memory bus random access memory
  • the application further provides a computer program product, comprising: computer program code, when the computer program code is run on a computer, causing the computer to execute the embodiment shown in FIG. 2 The method in .
  • the application further provides a computer readable medium storing program code, when the program code is run on a computer, causing the computer to execute the embodiment shown in FIG. 2 The method in .
  • the present application further provides a system, including the foregoing one or more encoding devices and one or more decoding devices.
  • the above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination.
  • the above-described embodiments may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded or executed on a computer, the processes or functions described in accordance with embodiments of the present application are generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be wired from a website site, computer, server or data center (for example, infrared, wireless, microwave, etc.) The method is transmitted to another website site, computer, server or data center.
  • the computer readable storage medium can be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that contains one or more sets of available media.
  • the usable medium can be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium.
  • the semiconductor medium can be a solid state hard drive.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product.
  • the technical solution of the present application which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including
  • the instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program codes. .

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Abstract

本申请提供了一种通信方法、通信装置和系统，能够提高译码性能。该方法包括：基于第一校验矩阵对信息序列进行低密度奇偶校验LDPC编码，得到第一编码比特序列；基于第二校验矩阵和第一编码比特序列进行LDPC编码，得到第二编码比特序列。

Description

通信方法、通信装置和系统
本申请要求于2018年3月19日提交中国专利局、申请号为201810226284.4、申请名称为“通信方法、通信装置和系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，并且更具体地，涉及一种通信方法、通信装置和系统。
背景技术
低密度奇偶校验(Low Density Parity Check，LDPC)码是一种具有稀疏校验矩阵的线性分组码。LDPC码不仅具有逼近香农极限的良好性能，而且译码复杂度低，结构灵活，是近年来信道编码领域的研究热点。其中，目前，准循环低密度奇偶校验(Quasi-Cyclic LDPC，QC-LDPC)码作为一类结构化LDPC码，因其描述简单、易于构造、节省存储空间等优点，在某些通信系统中，例如，第五代(5th generation，5G)通信系统的新空口接入技术(new radio access technology，NR)中，得以良好应用。
然而，在当前技术中，重点考虑了块误码率(block error rate，BLER)在10 -2及其附近的性能，信噪比(signal noise ratio，SNR)随BLER的降低显著下降。而当BLER的值居于某些范围时，例如，在10 -4及其附近甚至更低时，SNR随BLER的降低而下降的趋势明显变小，也就是出现了比较明显的错误平层(error floor)。错误平层的出现导致QC-LDPC码在实际应用过程中译码性能较低。
发明内容
本申请提供一种通信方法、通信装置和系统，以提高译码性能。
第一方面，提供了一种通信方法，包括：
基于第一校验矩阵对待编码的信息序列进行低密度奇偶校验LDPC编码，得到第一编码比特序列；
基于第二校验矩阵和所述第一编码比特序列进行LDPC编码，得到第二编码比特序列。
基于上述技术方案，通过编码设备对信息序列进行级联LDPC编码，译码设备对第二编码比特序列进行级联LDPC译码，可避免BLER在10 0至10 -6范围内出现明显的错误平层，即，有利于在较高的信噪比范围保证较低的BLER，从而可以在更大的信噪比范围内获得较好的译码性能。
结合第一方面，在第一方面的某些实现方式中，所述基于第二校验矩阵和所述第一编码比特序列进行LDPC编码，包括：
基于所述第二校验矩阵对所述第一编码比特序列进行LDPC编码；或者
基于所述第二校验矩阵对经过交织或加扰的第一编码比特序列进行LDPC编码。
通过对第一编码比特序列进行交织和/或加扰，可以将信号传输过程中可能遭遇的突发干扰、规律性干扰等随机地分散在编码比特，便于通过纠错技术恢复数据，从而可以提高信号传输的抗干扰能力，提高解调性能。
结合第一方面，在第一方面的某些实现方式中，所述方法还包括：
发送指示信息，所述指示信息用于指示所述第一编码比特序列的长度。
该指示信息可直接指示第一编码比特序列的长度，也可指示第一次LDPC编码的码率，以便于译码设备基于该码率和信息序列的长度确定第一编码比特序列的长度，本申请对此不做限定。
结合第一方面，在第一方面的某些实现方式中，所述方法还包括：
根据所述信息序列的长度和预先定义的编码码率确定所述第一编码比特序列的长度。
通过预先定义编码码率，编码设备和译码设备可根据信息序列的长度和编码码率确定第一编码比特序列的长度，而无需信令指示，从而节省信令开销。
第二方面，提供了一种通信方法，包括：
基于第二校验矩阵对待译码的第二编码比特序列的软值信息或硬值信息进行低密度奇偶校验LDPC译码，得到第三编码比特序列的软值信息或硬值信息；
基于第一校验矩阵和所述第三编码比特序列的软值信息或硬值信息进行LDPC译码，得到信息序列。
基于上述技术方案，通过编码设备对信息序列进行级联LDPC编码，译码设备对第二编码比特序列进行级联LDPC译码，可避免BLER在10 0至10 -6范围内出现明显的错误平层，即，有利于在较高的信噪比范围保证较低的BLER，从而可以在更大的信噪比范围内获得较好的译码性能。
结合第二方面，在第二方面的某些实现方式中，所述第三编码比特序列为第一编码比特序列，或者，所述第三编码比特序列为经过交织或加扰的第一编码比特序列，以及
所述基于第一校验矩阵和所述第三编码比特序列进行LDPC译码，包括：
若所述第三编码比特序列为所述第一编码比特序列，基于所述第一校验矩阵对所述第三编码比特序列的软值信息或硬值信息进行LDPC译码；或者
若所述第三编码比特序列为经过交织或加扰的第一编码比特序列，基于所述第一校验矩阵对经过解交织或解扰的第三编码比特序列的软值信息或硬值信息进行LDPC译码。
应理解，第三编码比特序列为第一编码比特序列还是交织或加扰后的第一编码比特序列，与编码设备是否对第一编码比特序列是否进行了交织或加扰有关。若对第一编码比特序列进行交织和/或加扰，可以将信号传输过程中可能遭遇的突发干扰、规律性干扰等随机地分散在编码比特，便于通过纠错技术恢复数据，从而可以提高信号传输的抗干扰能力，提高解调性能。
结合第二方面，在第二方面的某些实现方式中，所述方法还包括：
接收指示信息，所述指示信息用于指示所述第一编码比特序列的长度。
该指示信息可直接指示第一编码比特序列的长度，也可指示第一次LDPC编码的码率，以便于译码设备基于该码率和信息序列的长度确定第一编码比特序列的长度，本申请对此不做限定。
结合第二方面，在第二方面的某些实现方式中，所述方法还包括：
根据所述信息序列的长度和预先定义的编码码率确定所述第一编码比特序列的长度。
通过预先定义编码码率，编码设备和译码设备可根据信息序列的长度和编码码率确定第一编码比特序列的长度，而无需信令指示，从而节省信令开销。
结合第一方面或第二方面，在某些可能的实现方式中，所述信息序列的长度K与所述第一编码比特序列的长度L 1满足：
K/L 1≥0.9。
通过将第一次LDPC编码码率控制在较高值，可以减小多次LDPC编码带来的性能损失，从整体上看，有利于提高系统性能，使得该传输系统能够满足不同业务类型的需求。
结合第一方面或第二方面，在某些可能的实现方式中，所述信息序列的长度K与所述第一编码比特序列的长度L 1满足：
L 1＝αK+β，
其中，α≥0.9，β为修正值。
通过将第一次LDPC编码码率控制在较高值，可以减小多次LDPC编码带来的性能损失，从整体上看，有利于提高系统性能，使得该传输系统能够满足不同业务类型的需求。并且，通过修正值来调节不同信息序列的长度下的第一次LDPC编码的码率，有利于获得更好的译码性能。
可选地，β的取值为-Z≤β≤Z，且β为整数。
结合第一方面或第二方面，在某些可能的实现方式中，第一校验矩阵的基图和第二校验矩阵的基图可预先定义，也可以由编码设备或译码设备确定。
可选地，所述方法还包括：
确定所述第一校验矩阵的基图；和/或
确定所述第二校验矩阵的基图。
例如，协议中可预先定义第一校验矩阵的基图，此情况下，编码设备和译码设备可仅确定第二校验矩阵的基图；或者，协议中可预先定义第二校验矩阵的基图，此情况下，编码设备和译码设备可仅确定第一校验矩阵的基图；或者，协议中并未预先定义第一校验矩阵的基图和第二校验矩阵的基图，此情况下，编码设备和译码设备可确定第一校验矩阵的基图和第二校验矩阵的基图。
结合第一方面或第二方面，在某些可能的实现方式中，所述第一校验矩阵的基图为新空口NR协议中的基图1BG1，所述第二校验矩阵的基图为NR协议中的基图2BG2；或者
所述第一校验矩阵的基图为所述BG2，所述第二校验矩阵的基图为所述BG1；或者
所述第一校验矩阵的基图为所述BG1，所述第二校验矩阵的基图为所述BG1；或者
所述第一校验矩阵的基图为所述BG2，所述第二校验矩阵的基图为所述BG2；
其中，所述BG1用于确定维度为46Z×68Z的校验矩阵，所述BG2用于确定维度为42Z×52Z的校验矩阵，Z为扩展因子。
第三方面，提供了一种编码设备，所述编码设备具有实现上述第一方面的方法设计中的编码设备的功能。这些功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的单元。
第四方面，提供了一种译码设备，所述译码设备具有实现上述第一方面的方法设计中的译码设备的功能。这些功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的单元。
第五方面，提供了一种编码设备，包括收发器、处理器和存储器。该处理器用于控制收发器收发信号，该存储器用于存储计算机程序，该处理器用于从存储器中调用并运行该计算机程序，使得该编码设备执行上述第一方面或第一方面任意一种可能的实现方式中的方法。
第六方面，提供了一种译码设备，包括收发器、处理器和存储器。该处理器用于控制收发器收发信号，该存储器用于存储计算机程序，该处理器用于从存储器中调用并运行该计算机程序，使得该译码设备执行上述第二方面或第二方面任意一种可能的实现方式中的方法。
第七方面，提供了一种通信装置，所述通信装置具有实现上述方法方面中编码设备行为的功能，其包括用于执行上述方法方面所描述的步骤或功能相对应的部件(means)。所述步骤或功能可以通过软件实现，或硬件实现，或者通过硬件和软件结合来实现。
在一种可能的设计中，上述装置包括一个或多个处理器和通信单元。所述一个或多个处理器被配置为支持所述通信装置执行上述方法中编码设备相应的功能。例如，对信息序列和第一编码比特序列进行LDPC编码。所述通信单元用于支持所述通信装置与其他设备通信，实现接收和/或发送功能。例如，发送指示信息。
可选地，所述装置还可以包括一个或多个存储器，所述存储器用于与处理器耦合，其保存网络设备必要的程序指令和/或数据。所述一个或多个存储器可以和处理器集成在一起，也可以与处理器分离设置。本申请并不限定。
所述通信装置可以为基站，gNB或TRP等。所述通信单元可以是收发器，或，输入/输出接口。可选地，所述收发器可以为收发电路。可选地，所述输入/输出接口可以为输入/输出电路。
所述通信装置也可以为智能终端或者可穿戴设备等。所述通信单元可以是收发器，或，输入/输出接口。可选地，所述收发器可以为收发电路。可选地，所述输入/输出接口可以为输入/输出电路。
所述通信装置还可以为通信芯片。所述通信单元可以为通信芯片的输入/输出电路或者接口。
在另一种可能的设计中，所述通信装置包括收发器、处理器和存储器。该处理器用于控制收发器收发信号，该存储器用于存储计算机程序，该处理器用于运行存储器中的计算机程序，使得该通信装置执行第一方面或第一方面中任一种可能实现方式中编码设备完成的方法。
第八方面，所述通信装置具有实现上述方法方面中译码设备行为的功能，其包括用于执行上述方法方面所描述的步骤或功能相对应的部件(means)。所述步骤或功能可以通过软件实现，或硬件实现，或者通过硬件和软件结合来实现。
在一种可能的设计中，上述装置包括一个或多个处理器和通信单元。所述一个或多个处理器被配置为支持所述通信装置执行上述方法中译码设备相应的功能。例如，对第一编码比特序列和第二编码比特序列进行LDPC译码。所述通信单元用于支持所述通信装置与 其他设备通信，实现接收和/或发送功能。例如，接收指示信息。
可选地，所述装置还可以包括一个或多个存储器，所述存储器用于与处理器耦合，其保存网络设备必要的程序指令和/或数据。所述一个或多个存储器可以和处理器集成在一起，也可以与处理器分离设置。本申请并不限定。
所述通信装置可以为基站，gNB或TRP等。所述通信单元可以是收发器，或，输入/输出接口。可选地，所述收发器可以为收发电路。可选地，所述输入/输出接口可以为输入/输出电路。
所述通信装置也可以为智能终端或者可穿戴设备等。所述通信单元可以是收发器，或，输入/输出接口。可选地，所述收发器可以为收发电路。可选地，所述输入/输出接口可以为输入/输出电路。
所述通信装置还可以为通信芯片。所述通信单元可以为通信芯片的输入/输出电路或者接口。
在另一种可能的设计中，所述通信装置包括收发器、处理器和存储器。该处理器用于控制收发器收发信号，该存储器用于存储计算机程序，该处理器用于运行存储器中的计算机程序，使得该通信装置执行第二方面或第二方面中任一种可能实现方式中译码设备完成的方法。
第九方面，提供了一种计算机程序产品，所述计算机程序产品包括：计算机程序代码，当所述计算机程序代码在计算机上运行时，使得计算机执行上述各方面中的方法。
第十方面，提供了一种计算机可读介质，所述计算机可读介质存储有程序代码，当所述计算机程序代码在计算机上运行时，使得计算机执行上述各方面中的方法。
第十一方面，提供了一种芯片系统，该芯片系统包括处理器，用于支持编码设备实现上述方面中所涉及的功能，例如，生成，接收，发送，或处理上述方法中所涉及的数据和/或信息。在一种可能的设计中，所述芯片系统还包括存储器，所述存储器，用于保存终端设备必要的程序指令和数据。该芯片系统可以由芯片构成，也可以包括芯片和其他分立器件。
第十二方面，提供了一种芯片系统，该芯片系统包括处理器，用于支持译码设备实现上述方面中所涉及的功能，例如，生成，接收，发送，或处理上述方法中所涉及的数据和/或信息。在一种可能的设计中，所述芯片系统还包括存储器，所述存储器，用于保存终端设备必要的程序指令和数据。该芯片系统可以由芯片构成，也可以包括芯片和其他分立器件。
附图说明
图1是适用于本申请实施例提供的通信方法的通信系统的示意图；
图2是本申请实施例提供的信号处理的示意图；
图3是当前技术中采用LDPC码和极化(Polar)码的译码性能对比图；
图4是本申请实施例提供的通信方法的示意性流程图；
图5是当前技术中采用LDPC编解码与采用本申请实施例提供的通信方法进行LDPC编码和译码的性能对比图；
图6是本申请实施例提供的通信装置的示意性框图；
图7是本申请实施例提供的通信装置的另一示意性框图；
图8是本申请实施例提供的网络设备的结构示意图；
图9是本申请实施例提供的终端设备的结构示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
本申请实施例的技术方案可以应用于各种通信系统，例如但不限于，窄带物联网系统(Narrow Band-Internet of Things，NB-IoT)、全球移动通信(Global System of Mobile communication，GSM)系统、码分多址(Code Division Multiple Access，CDMA)系统、宽带码分多址(Wideband Code Division Multiple Access，WCDMA)系统、通用分组无线业务(General Packet Radio Service，GPRS)、长期演进(Long Term Evolution，LTE)系统、LTE频分双工(Frequency Division Duplex，FDD)系统、LTE时分双工(Time Division Duplex，TDD)、通用移动通信系统(Universal Mobile Telecommunication System，UMTS)、全球互联微波接入(Worldwide Interoperability for Microwave Access，WiMAX)通信系统、未来的第五代(5th Generation，5G)系统或新一代无线接入技术(new radio access technology，NR)等。
为便于理解本申请实施例，首先以图1中示出的通信系统为例详细说明适用于本申请实施例的通信系统。图1示出了适用于本申请实施例的通信方法的通信系统的示意图。如图1所示，该通信系统100可包括至少一个网络设备(例如，网络设备102)和至少一个(例如，终端设备104)，网络设备102可与终端设备104通信。可选地，该通信系统100还可包括更多的网络设备和/或更多的终端设备，本申请对此不做限定。
其中，网络设备可以是任意一种具有无线收发功能的设备，该设备包括但不限于：演进型节点B(evolved Node B，eNB)、无线网络控制器(Radio Network Controller，RNC)、节点B(Node B，NB)、基站控制器(Base Station Controller，BSC)、基站收发台(Base Transceiver Station，BTS)、家庭基站(例如，Home evolved NodeB，或Home Node B，HNB)、基带单元(BaseBand Unit，BBU)，无线保真(Wireless Fidelity，WIFI)系统中的接入点(Access Point，AP)、无线中继节点、无线回传节点、传输点(transmission and reception point，TRP或者transmission point，TP)等，还可以为5G，如，NR，系统中的gNB，或，传输点(TRP或TP)，5G系统中的基站的一个或一组(包括多个天线面板)天线面板，或者，还可以为构成gNB或传输点的网络节点，如基带单元(BBU)，或，分布式单元(distributed unit，DU)等。
在一些部署中，gNB可以包括集中式单元(centralized unit，CU)和DU。gNB还可以包括射频单元(radio unit，RU)。CU实现gNB的部分功能，DU实现gNB的部分功能，比如，CU实现无线资源控制(radio resource control，RRC)，分组数据汇聚层协议(packet data convergence protocol，PDCP)层的功能，DU实现无线链路控制(radio link control，RLC)、媒体接入控制(media access control，MAC)和物理(physical，PHY)层的功能。由于RRC层的信息最终会变成PHY层的信息，或者，由PHY层的信息转变而来，因而，在这种架构下，高层信令，如RRC层信令或PHCP层信令，也可以认为是由DU发送的，或者，由DU+RU发送的。可以理解的是，网络设备可以为CU节点、或 DU节点、或包括CU节点和DU节点的设备。此外，CU可以划分为接入网RAN中的网络设备，也可以将CU划分为核心网CN中的网络设备，在此不做限制。
终端设备也可以称为用户设备(user equipment，UE)、接入终端、用户单元、用户站、移动站、移动台、远方站、远程终端、移动设备、用户终端、终端、无线通信设备、用户代理或用户装置。本申请的实施例中的终端设备可以是手机(mobile phone)、平板电脑(Pad)、带无线收发功能的电脑、虚拟现实(Virtual Reality，VR)终端设备、增强现实(Augmented Reality，AR)终端设备、工业控制(industrial control)中的无线终端、无人驾驶(self driving)中的无线终端、远程医疗(remote medical)中的无线终端、智能电网(smart grid)中的无线终端、运输安全(transportation safety)中的无线终端、智慧城市(smart city)中的无线终端、智慧家庭(smart home)中的无线终端等等。本申请的实施例对应用场景不做限定。
在通信系统100中，网络设备102可以与多个终端设备(例如包括图中所示的终端设备104)通信。终端设备104也可以与多个网络设备(例如包括图中所示的网络设备102)通信。图1中所示的网络设备102与终端设备104通信的场景仅为本申请所提供的通信方法所适用的一种可能的场景，本申请所提供的通信方法还可适用于更多的场景，例如，多点协作(Coordination Multiple Point，CoMP)传输场景、设备到设备(device to device，D2D)通信场景等，图1中仅为便于理解而示例，并未予以画出。
为了便于理解本申请实施例，下面结合图2简单说明在物理层的处理过程。
应理解，图2中所示出的对信号的处理过程可以由网络设备执行，也可以由终端设备执行，本申请对此不做限定。
如图2所示，通信设备#1(例如可以为图1中所示的网络设备102或终端设备104)在发送信息数据时，可以根据系统支持的传输块的大小，将来自上层(例如，媒体接入层控制(media access control，MAC)层)的信息数据分割为多个传输块(transport block，TB)，并对每一传输块a 0,a 1,a 2,a 3,...,a A-1增加CRC校验p 0,p 1,p 2,p 3,...,p L-1得到序列b 0,b 1,b 2,b 3,...,b B-1，其中B＝A+L，a 0,a 1,a 2,a 3,...,a A-1也称为传输块的载荷(payload)。如果添加校验后的传输块b 0,b 1,b 2,b 3,...,b B-1大小超过最大码块长，则需要将传输块划分为若干码块(code block，CB)。其中，每个码块可包括传输块中的若干比特，还可以包括这些比特的CRC校验比特，例如长度为24比特的CRC校验比特。码块中还可以包括填充比特，以使码块长度满足块长要求，例如以LPDC编码为例，码块长度满足扩展因子Z的整数倍。
通信设备#1可对每个码块进行信道编码，例如，采用LDPC编码，得到相应的编码码块。在本申请中，有时也将码块称为信息序列。每个编码码块中可包括码块中多个编码前的信息比特和编码生成的校验比特，在本申请中可统称为编码比特，多个编码比特所构成的序列可称为编码比特序列。
通信设备#1可将上述编码比特序列保存在通信设备#1的循环缓存中进行速率匹配。通信设备#1可从循环缓存中选取一段编码比特，经过交织处理后，进行调制处理，映射为调制符号，并发送包括该调制符号的信号。
在本申请实施例中，编码比特序列的长度可以是指传输块经码块分割以及LDPC编码后输出的比特序列长度。更具体地，传输块经码块分割、LDPC编码后会存入循环缓存器，然后从该缓存器的指定位置，连续读出指定长度的比特数据，遇到填充比特自动跳过。
通信设备#2对接收到的调制符号进行解调处理、解交织处理后，可将接收到的编码比特的软值保存在软信息缓存中相应位置。如果发生重传，通信设备#2将每次重传的编码比特的软值合并保存在软信息缓存中，这里的合并是指，如果两次接收到的编码比特的位置相同，则将两次接收到的该编码比特的软值合并。
通信设备#2可直接对软信息缓存中的所有软值进行译码，例如，LDPC译码，得到相应的信息序列，例如，采用LDPC译码，得到相应的信息序列。信道译码所得到的信息序列可被发送至上层(例如，MAC层)。
应理解，通信设备#2对接收到的调制符号进行处理得到信息序列的过程可视为通信设备#1对待发送的信息数据进行处理得到编码比特序列的过程的逆过程。其中，通信设备#1和通信设备#2可采用无线技术进行通信。例如，当通信设备#1发送信号时，通信设备#1为发送设备，在本申请实施例中，发送端设备可称为编码设备；通信设备#2接收信号时，通信设备#2为接收设备，在本申请实施例中，接收端设备可称为译码(或者称，解码)设备。比如，通信设备#1可以为图1中所示的网络设备102或配置于网络设备102中的芯片，通信设备#2可以为图1中所示的终端设备104或配置于终端设备104中的芯片，或者，通信设备#1可以为图1中所示的终端设备104或配置于终端设备104中的芯片，通信设备#2可以为图1中所示的网络设备102或配置于网络设备102中的芯片。
为了便于理解，首先对本申请涉及的相关概念作简单介绍。
1、低密度奇偶校验(LDPC)码：一类具有稀疏校验矩阵的线性分组码，即校验矩阵中非零元素的密度比较低，也就是要求校验矩阵中零元素远远多于非零元素。一个[N，K]线性分组码，可理解为将长度为K的信息序列，通过编码得到码长为N的编码比特。
2、编码码率：在信道编码过程中，用于表示信息码字占总码字的比率。例如，信息序列的长度为K，编码比特序列的长度为N，则编码码率为K/N。在本申请实施例中，可将每一次LDPC编码前的序列长度与编码后得到的序列长度的比值记作编码码率。例如，对于第一次LDPC编码而言，编码码率为第一次LDPC编码前的信息序列的长度与编码后得到的第一编码比特序列的长度之比，在本申请实施例中，为便于区分和说明，可将第一次LDPC编码的码率称为第一编码码率；对于第二次LDPC编码而言，编码码率可以为第二次LDPC编码前的第一编码比特序列的长度与编码后得到的第二编码比特序列的长度之比，在本申请实施例中，为便于区分和说明，可将第二次LDPC编码的码率称为第二编码码率。对于整个信道编码而言，编码码率可以为第一次LDPC编码前的信息序列的长度与第二次LDPC编码后得到的第二编码比特序列的长度之比。
3、准循环低密度奇偶校验(QC-LDPC)码：LDPC的一个子类。QC-LDPC的校验矩阵(parity check matrix)是对一个基矩阵进行扩展得到的。为便于区分，在下文示出的实施例中，可将基矩阵记作H b，将校验矩阵记作H。
4、基图：基图可以表示成m×n的矩阵，包括零元素和非零元素，其中零元素可以用0、-1或null等表示，非零元素可以用1表示，可以用于指示一个或多个LDPC基矩阵中非零元素的位置，也就是非零元素在矩阵中的行、列位置。在有些实现方法中也可以简化的表示成指示非零元素的行、列位置的表格。通常，基图的前两列被称为内置打孔列。
5、基矩阵：可用于构造QC-LDPC码的校验矩阵H。基矩阵H b的大小可以为m×n，与基图相同，相应的校验矩阵H的大小为(m·Z)×(n·Z)，其中，将Z称作校验矩阵的扩 展因子(lifting size)，m、n、Z均为正整数。扩展因子取值以及集合划分的示例可参考表一所示：
表一
Figure PCTCN2019078583-appb-000001
QC-LDPC中基矩阵的表达式可以如下所示，其中，与基图中非零元素对应的位置的元素取值大于或者等于0，与零元素对应的位置的元素取值可以为-1或者null：
Figure PCTCN2019078583-appb-000002
6、校验矩阵：QC-LDPC中校验矩阵的表达式可以如下所示：
Figure PCTCN2019078583-appb-000003
该校验矩阵H中的每一个元素I(p i,j)(0≤i≤m-1，0≤j≤n-1)可以是零矩阵或者是循环移位矩阵。其中，若p i,j大于或者等于0，循环移位矩阵(例如，I(p i,j))可以是对维度为Z×Z的单位矩阵循环移位p i,j位得到的。因此，也将p i,j称作循环移位矩阵的移位因子。p i,j的取值范围可以是-1≤p i,j＜Z。
换句话说，基矩阵中的每个非零元素p i,j(0≤i≤m-1，0≤j≤n-1)可用于指示其所构造的校验矩阵中对应的单位矩阵需要进行循环移位的位数。例如，p 0,0可用于指示校验矩阵的左上角维度为Z×Z的单位矩阵I(p 0,0)需要循环移位的位数为p 0,0。若将I(p 0,0)看做一个整体，I(p 0,0)在校验矩阵中的位置与p 0,0在基矩阵的位置是相同的，即，第0行第0列。而基图或基矩阵中零元素则是用Z×Z的零矩阵替换。
若信息序列用c 0,c 1,c 2,c 3,...,c K-1表示，校验矩阵H的基图中前两列为内置打孔比特列，扩展因子为Z，则相应的内置打孔比特的个数为2Z，即c 0,c 1,c 2,c 3,...,c 2Z-1。经校验矩阵H编码后得到的编码比特序列为d＝d 0,d 1,d 2,...,d N-1，编码比特序列d包括信息序列中K-2Z个比特c 2Z,c 2Z+1,...,c K-1，以及校验比特序列w＝[w 0,w 1,w 2,...,w N+2Z-K-1] T中的校验比特，基 于校验矩阵H，校验比特序列w和信息序列c满足
Figure PCTCN2019078583-appb-000004
其中c＝[c 0,c 1,c 2,...,c K-1] T，0是全0的列向量。
基矩阵中的每个元素的取值可以参考现有技术确定，例如，可根据NR协议TS 38.212中定义的表5.3.2-2LDPC基图1(H BG)及其矩阵(V i,j)(可参见后文中的表三)和表5.3.2-3LDPC基图2(H BG)及其矩阵(V i,j)(可参见后文中的表二)，由于扩展因子Z取值范围不同使得p i,j的取值范围也不尽相同，因此p i,j也可以通过p i,j＝mod(V i,j,Z)给出。一个基图往往可以对应多个基矩阵或者校验矩阵，这些矩阵中非零元素的值可以根据扩展因子Z的集合索引确定。
应理解，上文列举的用于指示基矩阵与奇偶校验矩阵的对应关系的表仅为示例性说明，而不应对本申请构成任何限定，本申请对用于确定基矩阵的具体方法和过程不做限定。
如果校验矩阵H是满秩矩阵，则可以在基矩阵的(n-m)列放置(n-m)·Z个信息比特，基矩阵中用于放置该(n-m)·Z个信息比特的(n-m)列可以称为信息列，并令k b＝n-m。
在采用QC-LDPC编码时，如果信息序列的长度K被k b整除，那么在扩展后的每一个信息比特位置都用来放置信息比特。如果K不被k b整除，导致Z·k b>K，则在扩展后LDPC的校验矩阵H中会有(Z·k b-K)个多余的信息比特位置，可称作填充比特，填充比特可以用0或者null表示。
图3是采用LDPC码和极化(Polar)码的译码性能对比图。具体地，图3以信息序列长度K＝94、编码码长N＝420、调制模式为正交相移键控(Quadrature Phase Shift Keyin，QPSK)为例，以加性高斯白噪声(Additive White Gaussian Noise，AWGN)为噪声模型，通过性能仿真，示出了采用LDPC码和Polar码的符号信噪比与BLER关系的性能对比图。由图可以看到，当采用Polar码时，BLER随符号信噪比的增大呈下降趋势，曲线未发生明显的浮动；当采用LDPC编码时，BLER在处于10 0至约10 -3范围(具体可对应于图中A至B范围)时时BLER随符号信噪比增大而下降的趋势(例如，可通过斜率k 1表征)，与BLER在处于约10 -3至10 -6范围(具体可对应于图中B至C范围)时BLER随符号信噪比增大而下降的趋势(例如，可通过斜率k 2表征)相比，发生了明显的浮动，曲线在BLER处于约10 -3至10 -6范围时发生了明显的翘起，也就是说，BLER在处于约10 -3至10 -6范围(具体可对应于图中B至C范围)时，BLER随信噪比的增大下降的趋势变得平缓，使得译码性能下降。
图3中示出的LDPC译码性能图中，由于在BLER处于约10 -3至10 -6范围时，BLER随信噪比的增大而降低的趋势发生了明显的浮动，造成了译码性能的下降，可认为BLER在约10 -3至10 -6范围出现了错误平层(error floor)。错误平层可理解为：从低/中等信噪比瀑布区域到高信噪比区域误码性能曲线的突然降低。
在一种可能的实现方式中，可以根据信噪比-BLER的译码性能曲线中不同BLER范围内的斜率变化来确定是否出现了错误平层。例如，当两个连续的BLER范围内的斜率的差值或比值大于预设门限，则认为出现错误平层；否则，认为未出现错误平层。其中，该预设门限可以是预先定义的，其取值可基于对错误平层的判决的严格程度来决定。
然而，在一些系统中，要求误码率是极低的，例如，超可靠低延迟通信(Ultra-Reliable and Low Latency Communication，URLLC)要求误码率在10 -5以下。因此，如何降低LDPC 码的错误平层是LDPC在实际应用中的关键问题之一。
有鉴于此，本申请提供一种通信方法，以避免错误平层的出现，提高LDPC译码性能。
下面将结合附图详细说明本申请实施例提供的通信方法。
需要说明的是，本申请实施例中，“预先定义”可以通过在设备(例如，包括终端设备和网络设备)中预先保存相应的代码、表格或其他可用于指示相关信息的方式来实现，本申请对于其具体的实现方式不做限定。比如预先定义可以是指协议中定义的。
还需要说明的是，本申请实施例中涉及的“保存”，可以是指的保存在一个或者多个存储器中。所述一个或者多个存储器，可以是单独的设置，也可以是集成在编码器或者译码器，处理器、或通信装置中。所述一个或者多个存储器，也可以是一部分单独设置，一部分集成在译码器、处理器、或通信装置中。存储器的类型可以是任意形式的存储介质，本申请并不对此限定。
还需要说明的是，“协议”可以指通信领域的标准协议，例如可以包括LTE协议、NR协议以及应用于未来的通信系统中的相关协议，本申请对此不做限定。
还需要说明的是，本申请实施例中，名词“网络”和“系统”经常交替使用，但本领域的技术人员可以理解其含义。信息(information)，信号(signal)，消息(message)，信道(channel)有时可以混用，应当指出的是，在不强调其区别时，其所要表达的含义是一致的。“的(of)”，“相应的(corresponding，relevant)”和“对应的(corresponding)”有时可以混用，应当指出的是，在不强调其区别时，其所要表达的含义是一致的。
还需要说明的是，在下文示出的实施例中，第一、第二等仅为便于区分不同的对象，而不应对本申请构成任何限定。例如，区分不同的校验矩阵，不同的编码比特序列等。
还需要说明的是，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。“至少一个”是指一个或一个以上；“A和B中的至少一个”，类似于“A和/或B”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和B中的至少一个，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。
应理解，本申请提供的通信方法可适用于无线通信系统，例如，图1中所示的无线通信系统100。其中，编码设备可以对应于(例如，可以配置于或本身即为)图1中的网络设备102，译码设备可以对应(例如，可以配置于或本身即为)图1中的终端设备104；或者，编码设备可以对应(例如，可以配置于或本身即为)于图1中的终端设备104，译码设备可以对应(例如，可以配置于或本身即为)于图1中的网络设备102，本申请对此不做限定。另外，图1中所示的无线通信系统并不应对本申请提供的通信方法所适用的场景构成限定。
以下，不失一般性，以一个编码设备和一个译码设备之间的交互过程为例详细说明本申请实施例。可以理解，一个编码设备可以基于相同的方法，与具有无线通信连接的一个或多个译码设备进行通信，一个译码设备也可以基于相同的方法，与具有无线通信连接的一个或多个编码设备进行通信。本申请对此不做限定。
图4是从设备交互的角度示出的本申请实施例提供的通信方法200的示意性流程图。如图所示，图4中所示的方法200可以包括步骤210至步骤260。下面结合图4对方法200 进行详细描述。
在步骤210中，编码设备基于第一校验矩阵对信息序列进行LDPC编码，得到第一编码比特序列。
在本申请实施例中，为便于区分和说明，将第一次LDPC编码时所基于的校验矩阵称为第一校验矩阵。基于第一校验矩阵对信息序列进行第一次LDPC编码后得到的编码比特序列可称为第一编码比特序列。步骤210中编码设备基于第一校验矩阵对信息序列进行LDPC编码的过程可记作第一次LDPC编码，与此对应的编码码率可记作第一编码码率。
可选地，第一编码比特序列的长度L 1与信息序列的长度K满足：K/L 1≥0.9。
换句话说，第一编码码率大于或等于0.9。
编码设备可根据编码码率的要求，控制第一编码后输出第一编码比特序列的长度L 1。例如，当编码码率较低，不满足第一编码码率时，可通过打孔的方式来降低第一编码比特序列的长度，以达到提高码率的效果。
可选地，第一编码比特序列的长度L 1与信息序列的长度K满足：L 1＝αK+β，其中，α≥0.9，β为修正值。
也就是说，第一编码码率为
Figure PCTCN2019078583-appb-000005
在本申请实施例中，可以考虑将LDPC编码码率设计成可调的，即，可随信息序列的长度调整。比如，信息序列的长度较长时，编码码率可相应提高；信息序列的长度较短时，编码码率可相应降低。上式中当α和K确定后，便可通过修正值β来调整编码码率，以达到预期值。可选地，β的取值为-Z≤β≤Z，且β为整数。
在一种可能的设计中，第一编码码率为预先定义的。例如，第一编码码率为协议定义。
在这种设计中，编码设备和译码设备可预先保存第一编码码率。该编码码率可以被设计为一个固定值，例如，0.9；也可以被设计成可调的，例如对于不同的信息序列的长度可定义不同的编码码率，比如，当信息序列的长度为100至300时，对应的编码码率为0.93；当信息序列的长度为300至500时，对应的编码码率为0.95。应理解，这里所列举的编码码率的值以及信息序列的长度与编码码率的对应关系仅为示例性说明，而不应对本申请构成任何限定。
在另一种可能的设计中，第一编码码率由发送端设备确定，并可通过信令通知接收端设备。
则可选地，该方法200还包括：
步骤220，编码设备发送指示信息，该指示信息用于指示第一编码码率。
由于在信息序列的长度确定的情况下，可根据信息序列的长度和第一编码码率确定第一编码比特序列的长度。反之，根据信息序列的长度和第一编码比特序列的长度，可确定第一编码码率。
故，该指示信息可直接指示第一编码码率，或者，该指示信息也可指示第一编码比特序列的长度。
可选地，该指示信息可携带在高层信令中。
作为示例而非限定，高层信令例如可包括：无线资源控制(radio resource control，RRC)消息或媒体接入控制(media access control，MAC)控制元素(control element，CE)。可选地，该指示信息可携带在物理层信令中。
作为示例而非限定，物理层信令例如可以包括下行控制信息。该下行控制信息可以为NR协议中的DCI(downlink control information)，或者，也可以为物理下行控制信道中传输的其他可用于承载下行控制信息的信令。
应理解，这里所说的物理下行控制信道可以是NR协议中定义的PDCCH(physical downlink control channel，物理下行控制信道)、增强物理下行控制信道(enhanced PDCCH，EPDCCH)，也可以是NR中的PDCCH，以及随着网络演变而定义的具有上述功能的其他下行信道。
例如，该指示信息可通过下行控制信息中的调制编码方式(modulation and coding scheme，MCS)字段承载。
在本申请实施例中，编码设备基于第一校验矩阵对信息序列进行LDPC编码的过程可通过以下步骤实现：
编码设备根据第一校验矩阵的基图确定第一校验矩阵；
编码设备基于第一校验矩阵对待编码的信息序列进行LDPC编码，得到第一编码比特序列。
在一种可能的设计中，第一校验矩阵的基图为新空口NR协议TS38.212中的基图1BG1。
在另一种可能的设计中，第一校验矩阵的基图为NR协议TS38.212中的基图2BG2。
不论是BG1还是BG2，均通过不同的索引值定义基矩阵中的各个元素，即通过不同的索引值指示了多个不同形式的基矩阵，进而可根据基矩阵和扩展因子构造校验矩阵。BG1和BG2具体可参看后文中的表二和表三。
在一种可能的实现方式中，可预先定义第一校验矩阵的基图类型。例如，在协议中预先定义了第一校验矩阵的基图类型。例如，预先定义第一校验矩阵的基图为BG2，或者，预先定义第一校验矩阵的基图为BG1。
在另一种可能的实现方式中，可以参考NR协议基图选择方式确定第一校验矩阵的基图。即，可选地，该方法200还包括：确定第一校验矩阵的基图。
具体地，若信息序列对应的传输块中信息载荷的长度A≤292，或者，信息序列对应的传输块中信息载荷的长度A≤3824且编码码率R≤0.67，或者，编码码率R≤0.25，则采用BG2作为校验矩阵的基图；否则，采用BG1作为校验矩阵的基图。
其中，在确定用于第一次LDPC编码的第一校验矩阵时，该编码码率可以为第一编码码率；与此相应，在确定用于第二次LDPC编码的第二校验矩阵时，该编码码率可以为第二编码码率。
例如：第一校验矩阵的基图可以根据信息序列对应的传输块中信息载荷的大小或者第一编码码率中至少一种确定。
当采用了其中一种基图(例如，BG1或BG2)来确定第一校验矩阵，即可基于信息序列的长度来确定第一校验矩阵的扩展因子，进而基于基图和第一校验矩阵的扩展因子确定第一校验矩阵。应理解，上文列举的BG1和BG2仅为示例性说明，而不应对本申请构成任何限定，本申请并不排除在未来的协议中对现有的基图(例如，BG1或BG2)进行修改的可能，也不排除在未来的协议中定义其他形式的基图的可能。
下面分别以BG1和BG2为例，详细说明根据信息序列的长度确定第一校验矩阵的扩 展因子，以及基于第一校验矩阵的基图和扩展因子构造第一校验矩阵的具体过程。
具体过程可包括下文列举的步骤i至步骤iii。在以下示例中，假设信息序列的长度为K。
步骤i、根据信息序列的长度确定信息列数k b。
若第一校验矩阵的基图为BG1，k b取值为BG1中对应信息比特的列数，BG1中对应信息比特的列数为22，故k b＝22；
若第一校验矩阵的基图为BG2，则可通过执行以下代码来确定k b：
Figure PCTCN2019078583-appb-000006
步骤ii、根据信息列数k b确定第一校验矩阵的扩展因子Z 1。
根据步骤i中确定的信息列数k b以及信息序列的长度K，确定扩展因子(lifting size)Z 1，Z 1的值取自前述表一中所列举的扩展因子集合，且Z 1为满足k b·Z 1≥K的最小值。
步骤iii、根据第一校验矩阵的基图和扩展因子Z 1确定第一校验矩阵。
根据扩展因子Z 1可确定集合索引i LS，由于基图中每个非零元素对于不同索引i LS对应的循环移位值不同，因此可以根据索引确定每个非零元素对应的循环移位值V i,j，并且根据p i,j＝mod(V i,j,Z 1)确定p i,j，对于基图中每个零元素用Z 1×Z 1的零矩阵替换，对于基图中每个非零元素用循环右移p i,j次的Z 1×Z 1单位矩阵替换。表二示出了NR协议TS38.212中定义的BG2，基图中非零元素的位置以表二中行列索引指示，其他未示出的位置为零元素所在的位置。
表二
Figure PCTCN2019078583-appb-000007
Figure PCTCN2019078583-appb-000008
Figure PCTCN2019078583-appb-000009
Figure PCTCN2019078583-appb-000010
Figure PCTCN2019078583-appb-000011
Figure PCTCN2019078583-appb-000012
表二可用于确定八种可能的基矩阵，分别对应于索引值(i LS)为1至8的情况。每个基矩阵的维度为42×52，也就是说，每个基矩阵都可以为42行52列的矩阵。其中，用于 承载信息比特列(即，信息列)数可以为10，也可以为小于10的整数，例如，9、8或6等。当信息列数小于10时，可将本用作信息列的10列中的部分列截取掉，不用于承载信息比特。
举例而言，假设Z 1＝3，则i LS＝2。参看表二，当i＝0，j＝0时，V i,j所对应的元素V 0,0为174，不为0，则说明V 0,0为非零元素，进一步对3取模后可得0，则表示对维度为3×3的单位矩阵向右循环移位的移位因子为0，也就是不移位；当i＝0，j＝1时，V i,j所对应的元素V 0,1为97，不为0，则说明V 0,0为非零元素，进一步对3取模后可得1，则表示对维度为3×3的单位矩阵向右循环移位的移位因子为1；当i＝0，j＝10时，V i,j所对应的元素V 0,10为0，则说明V 0,10为零元素。
以BG2为例，第一校验矩阵维度为42Z 1×52Z 1。
仍以步骤iii中的举例来说明，假设Z 1＝3，当i＝0，j＝0时，所对应的第一校验矩阵中的元素可以为
Figure PCTCN2019078583-appb-000013
当i＝0，j＝1时，所对应的第一校验矩阵中的元素可以为
Figure PCTCN2019078583-appb-000014
当i＝0，j＝10时，所对应的第一校验矩阵中的元素可以为
Figure PCTCN2019078583-appb-000015
基于上述步骤，可以确定出第一校验矩阵。
表三示出了NR协议TS38.212中定义的BG1，基图中非零元素的位置以表三中行列索引指示，其他未示出的位置为零元素所在的位置。
表三
Figure PCTCN2019078583-appb-000016
Figure PCTCN2019078583-appb-000017
Figure PCTCN2019078583-appb-000018
Figure PCTCN2019078583-appb-000019
Figure PCTCN2019078583-appb-000020
Figure PCTCN2019078583-appb-000021
Figure PCTCN2019078583-appb-000022
Figure PCTCN2019078583-appb-000023
Figure PCTCN2019078583-appb-000024
表三可用于确定八种可能的基矩阵，分别对应于索引值(i LS)为1至8的情况。每个基矩阵的维度为46×68，也就是说，每个基矩阵都可以为46行68列的矩阵。其中，用于 承载信息比特列(即，信息列)数可以为22。
应理解，根据BG1和扩展因子Z 1确定第一校验矩阵的具体过程与上文步骤iii中根据BG2和扩展因子确定第一校验矩阵的具体过程相似，为了简洁，这里不再举例详述。可以理解的是，第一校验矩阵的基图为BG1时，第一校验矩阵的维度可以为46Z 1×68Z 1。
应理解，上文中为了便于理解和说明，列举了NR协议TS38.212中的多个表项来说明扩展因子的取值以及第一校验矩阵的构造等的具体过程。但这不应对本申请构成任何限定，本申请对于扩展因子的取值、第一基矩阵的确定方法以及第一校验矩阵的构造方法并不做限定。同时，本申请也并不排除在未来的协议中对上文列举的表一、表二和表三中的任意一个表项作出修改的可能，也不排除以其他可能的形式来代替上述表一、表二和表三中任意一个表项的可能。
编码设备在确定了第一校验矩阵之后，便可基该第一校验矩阵对信息序列进行LDPC编码，以得到第一编码比特序列。
由上文确定第一校验矩阵的具体过程可以看到，该第一校验矩阵为由0和1构成的稀疏矩阵。或者说，校验矩阵可以为由0和1构成的稀疏矩阵。校验矩阵中的每一行可构造出一个校验方程，每一列的值可用于指示信息序列中的比特在校验方程中是否出现，例如，“1”代表出现，“0”代表不出现。例如，校验矩阵中的某一行为[1,1,1,1,0,1,0,0,0,0]，假设前5个比特为信息比特，后5个比特为校验比特，则可得到校验方程为：
Figure PCTCN2019078583-appb-000025
或者写成，v 1+v 2+v 3+v 4＝v 5。其中，v 1至v 4表示信息比特中的第一至第四个比特，v 5表示校验比特中的第一个比特。通过该校验方程可求解得到校验比特中的第一个比特，也就是输出的编码比特序列中的第一个比特。该校验方程中也可能存在多个待求解的校验比特，这种情况可通过多个校验方程来求解得到。
应理解，这里仅为便于理解和说明，举例说明了基于校验矩阵确定编码比特序列的方法，基于校验矩阵确定编码比特序列的具体过程可参考现有技术，本申请对于基于校验矩阵确定编码比特序列的具体方法不做限定。
在本申请实施例中，根据上述基于校验矩阵对信息序列进行LDPC编码的方法，编码设备可对长度为K的信息序列进行LDPC编码。例如，可通过k b·Z个比特来放置长度为K的信息序列，当K＞k b·Z时，可将剩余的(K-k b·Z)个比特来放置填充比特。
需要说明的是，在上文中已经说明，编码设备在对信息序列进行信道编码之前，可以根据系统支持的传输块的大小，对来自上层的传输块进行码块分割。这里，系统支持的传输块的大小即可理解为信息序列的长度，该长度的大小可以是预先定义的，例如，协议定义。
在步骤230中，编码设备基于第二校验矩阵和第一编码比特序列进行LDPC编码，得到第二编码比特序列。
在本申请实施例中，为了便于区分和说明，将第二次LDPC编码时所基于的校验矩阵称为第二校验矩阵。基于第二校验矩阵对信息序列和第一编码比特序列进行第二次LDPC编码后得到的编码比特序列可称为第二编码比特序列。步骤210中编码设备基于第二校验矩阵和第一编码比特序列进行LDPC编码的过程可记作第二次LDPC编码，与此对应的编码码率可记作第二编码码率。
一种可能的实现方式中，编码设备可以基于第二校验矩阵对第一编码比特序列进行 LDPC编码。
又一种可能的实现方式中，编码设备可以对第一编码比特序列进行处理，例如：进行交织，或加扰，或交织和加扰等处理，然后对经过处理后的第一编码比特序列进行LDPC编码。其中，交织处理可以是对第一编码比特序列中各比特的位置进行改变或交换。加扰处理可以是对第一编码比特序列使用特定的扰码序列或者随机序列进行加扰运算。
换句话说，步骤230可包括：
编码设备基于第二校验矩阵对第一编码比特序列进行LDPC编码，得到第二编码比特序列；或者
编码设备基于第二校验矩阵对经过交织或加扰的第一编码比特序列进行LDPC编码，得到第二编码比特序列。
通过对第一编码比特序列进行交织或加扰，可以将信号传输过程中可能遭遇的突发干扰、规律性干扰等随机地分散在编码比特，便于通过纠错技术恢复数据，从而可以提高信号传输的抗干扰能力，提高解调性能。
在本申请实施例中，步骤230可通过以下步骤实现：
编码设备基于第二校验矩阵的基图确定第二校验矩阵；
编码设备基于第二校验矩阵和第一编码比特序列进行LDPC编码，得到第二编码比特序列。
与确定第一校验矩阵的基图的方法相似地，第二校验矩阵的基图可以预先定义，例如，在协议中预先定义第二校验矩阵的基图类型。或者，第二校验矩阵的基图也可以根据待进行第二次LDPC编码的编码比特序列(例如可以为第一编码比特序列或者经过交织或加扰的第一编码比特序列)的长度或者信息序列对应的传输块的编码码率中至少一种确定。即，可选地，该方法200还包括：确定第二校验矩阵的基图。
需要说明的是，若对第一编码比特序列进行了交织或加扰处理，则该交织或加扰处理后的第一编码比特序列的长度可根据第一次LDPC编码后输出的第一编码比特序列的长度以及预先定义好的交织算法或加扰序列确定，本申请对于确定交织或加扰处理后的第一编码比特序列的长度的具体方法不做限定。
还需要说明的是，第二编码码率可以预先定义，也可以根据预先定义的编码码率(即，信息序列的长度与经LDPC编码后输出的编码比特序列的长度之比)以及第一编码码率计算得到，本申请对此不做限定。
第二校验矩阵的扩展因子Z 2也可以根据待进行第二次LDPC编码的编码比特序列的长度L 1重新确定。Z 2的值例如可取自前述表一中所列举的扩展因子集合，且Z 2为满足k b·Z 2≥L 1的最小值。这里，需要注意的是，待进行第二次LDPC编码的编码比特序列可以为第一编码比特序列本身，也可以为经过交织或加扰的第一编码比特序列，第一编码比特序列的长度与经过交织或加扰的第一编码比特序列的长度可以相同或不同，本申请对此不做限定。
在一种可能的设计中，第二校验矩阵的基图为新空口NR协议TS38.212中的BG1。
在另一种可能的设计中，第二校验矩阵的基图为NR协议TS38.212中的BG2。
应理解，在步骤210中已经结合具体的例子详细说明了根据待编码的序列长度确定第二校验矩阵的扩展因子，以及基于基图和第二校验矩阵的扩展因子构造校验矩阵的具体过 程，在步骤230中，根据第一编码比特序列的长度或经过处理的第一编码比特序列的长度确定第二校验矩阵的扩展因子，以及基于基图和第二校验矩阵的扩展因子构造第二校验矩阵的具体过程与上述步骤210中的具体过程相似，为了简洁，这里省略对该具体过程的详细说明。
还应理解，该第一校验矩阵的基图与第二校验矩阵的基图可以相同或不同，本申请对此不做限定。
本领域的技术人员可以理解，在步骤210中，输入可以为待编码的信息序列，输出可以为第一编码比特序列，在步骤230中，输入可以为该第一编码比特序列，或，经过交织或加扰后的第一编码比特序列，输出可以为第二编码比特序列，也就是说，可将步骤210的输出作为步骤230的输入，或对步骤210的输出做处理后作为步骤230的输入。
在一种可能的设计中，步骤210和步骤230可以由两个独立的编码器执行，该两个独立的编码器可通过执行程序代码，对输入的序列进行LDPC编码。具体地，对于编码器#1来说，可将待编码的信息序列作为输入，将第一编码比特序列作为输出，对于编码器#2来说，可将第一编码比特序列或经过处理后的第一编码比特序列作为输入，将第二编码比特序列作为输出。可以理解的是，在编码器#1输出该第一编码比特序列之后，可以用于对新输入的待编码的信息序列进行LDPC编码；在编码器#1输出该第一编码比特序列之前，编码器#2也可用于对之前输入的其他编码比特序列进行LDPC编码，本申请对此不做限定。
在另一种可能的设计中，步骤210和步骤230也可以由一个编码器的两个编码单元来执行，该两个独立的编码单元可通过执行程序代码，对输入的序列进行LDPC编码。具体地，对于编码单元#1来说，可将待编码的信息序列作为输入，将第一编码比特序列作为输出，对于编码单元#2来说，可将第一编码比特序列或经过处理后的第一编码比特序列作为输入，将第二编码比特序列作为输出。可以理解的是，在编码单元#1输出该第一编码比特序列之后，可以用于对新输入的待编码的信息序列进行LDPC编码；在编码单元#1输出该第一编码比特序列之前，编码单元#2也可用于对之前输入的其他编码比特序列进行LDPC编码，本申请对此不做限定。
在另一种可能的设计中，步骤210和步骤230也可以由一个编码器的同一编码单元来执行。将待编码的信息序列作为输入，在得到第一编码比特序列后，将得到的第一编码比特序列或经过处理后的第一编码比特序列重新作为输入，直至得到第二编码比特序列并输出。
需要说明的是，在本申请实施例中，可将对信息序列进行多次LDPC编码的方法可称为级联LDPC编码。例如，对信息序列进行了两次LDPC编码，则称级联次数为2。
应理解，本申请实施例仅为便于理解和说明，以两次LDPC编码的过程为例详细说明了编码设备对信息序列进行LDPC编码的过程，但这不应对本申请构成任何限定，本申请对于LDPC编码的级联次数不做限定，例如，还可将第二编码比特序列作为下一次LDPC编码的输入，以输出第三编码比特序列，该第三编码比特序列可作为待发送给译码设备的编码比特序列，也可作为再一次LDPC编码的输入，本申请对此不做限定。并且，对编码比特序列再一次进行LDPC编码的具体过程与上文步骤210中所描述的具体过程相似，为了简洁，这里不再赘述。
在本申请实施例中，为便于理解和说明，假设编码设备做了两次LDPC编码，则可选地，该方法200还包括：步骤240，编码设备发送第二编码比特序列。
相对应地，在步骤240中，译码设备接收第二编码比特序列。
应理解，编码设备在发送第二编码比特序列(为便于区分和说明，将编码设备发送的第二编码比特序列称为原始的第二编码比特序列)时，可进一步对该第二编码比特序列进行速率匹配、交织、调制等处理，以将该第二编码比特序列以符号的形式通过天线发送给译码设备。译码设备所接收到的信号可以是由该第二编码比特序列经交织、调制等处理得到的符号，译码设备可先对该符号进行解调、解交织、解速率匹配等处理，以得到第二编码比特序列的软值信息或硬值信息(为便于区分和说明，将译码设备恢复出的第二编码比特序列称为恢复的第二编码比特序列)，然后对该第二编码比特序列的软值信息或硬值信息进行译码。
在解调或译码过程中，根据使用的方法不同，得到软值信息或硬值信息。以比特序列A为例，若比特序列A经过编码、速率匹配、交织以及调制等操作后得到可以发送的信号，对该信号进行解调可以得到比特序列A的解调软值信息或解调硬值信息，对比特序列A的解调软值信息或解调硬值信息进行译码可以得到比特序列A的译码软值信息或译码硬值信息。其中，在解调或译码时采用的是硬判决，则得到的是相应的比特序列的硬值信息，对该比特序列的每一比特判决为0或1的值；又例如，在解调或译码时采用的是软判决，则可以得到相应的比特序列的软值信息，软值可以包括信息可靠度的度量，还可以包括硬值的信息，以便译码时根据这些信息判决为相应的比特。例如，对信号S进行解调后，软值信息可以是序列r＝[-11.2，4.7，9，-3]，其中软值信息中正负号表示相应地硬值，相应地硬值信息可以是序列y＝[0，1，1，0]，软值信息中数字大小表示度量值。需要说明的是，此处仅为举例，并不以此为限。编码设备对信道编码后的编码比特序列进行处理的具体过程以及译码设备对接收到的信号进行处理以得到待译码的编码比特序列的具体过程可以参考现有技术，为了简洁，这里省略对该具体过程的详细说明。
本领域的技术人员可以理解，由于编码设备对原始的第二编码比特序列进行了速率匹配、交织、调制等处理后通过物理信道传输给译码设备，译码设备在对接收到的符号进行解调、解交织、解速率匹配等处理后得到的软值信息或硬值信息对应的恢复的第二编码比特序列有可能与原始的第二编码比特序列不完全相同，但这不应对本申请构成任何限定。在本申请中，将原始的第二编码比特序列和恢复的第二编码比特序列均称为第二编码比特序列。
在本申请实施例中，只要编码设备采用了上述级联LDPC编码的方式对信息序列进行LDPC编码，译码设备就可以采用与此相对应的方式对接收到的编码比特序列进行LDPC译码。与级联LDPC编码相对应地，译码设备进行LDPC译码的方式可称为级联LDPC译码。
在步骤250中，译码设备基于第二校验矩阵对第二编码比特序列的软值信息或硬值信息进行LDPC译码，得到第三编码比特序列的软值信息或硬值信息。
具体地，译码设备对编码比特进行LDPC译码的过程可视为编码端对信息序列进行LDPC编码的过程的逆过程。即，对于译码设备来说，第二编码比特序列的软值信息或硬值信息可作为第一次LDPC译码的输入，其输出可以为第三编码比特序列的软值信息或硬 值信息，该第三编码比特序列的软值信息或硬值信息可作为第二次LDPC译码的输入，其输出可以为信息序列，也就是译码设备希望通过译码恢复出的编码设备发送的信息序列。
在本申请实施例中，为便于区分和说明，将第一次LDPC译码得到的软值信息或硬值信息对应的编码比特序列记作第三编码比特序列。步骤250中译码设备基于第二校验矩阵对第二编码比特序列的软值信息或硬值信息进行LDPC译码的过程可记作第一次LDPC译码。
步骤250中经过第一次LDPC译码得到的软值信息或硬值信息对应的第三编码比特序列可以与步骤230中的待进行第二次LDPC编码的编码比特序列对应。若步骤230中基于第二校验矩阵直接对第一编码比特序列进行LDPC编码，则该第三编码比特序列可理解为经LDPC译码得到的第一编码比特序列；若步骤230中基于第二校验矩阵对经过交织或加扰后的第一编码比特序列进行LDPC编码，则该第三编码比特序列可理解为经LDPC译码得到的经过交织或加扰的第一编码比特序列。在本实施例中，将译码得到的第一编码比特序列和译码得到的经过交织或加扰的第一编码比特序列统称为第三编码比特序列。
可选地，步骤250具体包括：
译码设备根据第二校验矩阵的基图确定第二校验矩阵；
译码设备基于第二校验矩阵对第二编码比特序列进行LDPC译码，得到第三编码比特序列的软值信息或硬值信息。
具体地，基于第二校验矩阵的基图确定第二校验矩阵的具体方法可以与步骤230中基于第二基矩阵确定第二校验矩阵的具体方法相同。译码设备可根据第三编码比特序列的长度确定第二校验矩阵的扩展因子，并基于基图和第二矩阵的扩展因子确定该第二校验矩阵。其中，若该第三编码比特序列为经LDPC译码得到的第一编码比特序列，则该第三编码比特序列的长度例如可以由译码设备根据第一编码码率(例如可以是预先定义或者编码设备指示)和预先定义的信息序列的长度确定，或者，也可以由编码设备通过信令指示；若该第三编码比特序列为经LDPC译码得到的经过交织或加扰的第一编码比特序列，则该第三编码比特序列的长度可以由译码设备根据第一编码码率、预先定义的交织算法、预先定义的加扰序列以及预先定义的信息序列的长度确定，或者，也可以由编码设备通过信令指示。本申请对于确定第三编码比特序列的长度的具体方法不做限定。
译码设备可采用现有的译码算法对第二编码比特序列的软值信息或硬值信息进行第一次LDPC译码，以得到第一编码比特序列的软值信息或硬值信息。作为示例而非限定，LDPC译码算法例如可以包括置信传输(Belief Propagation)算法、分层偏移最小和(layered offset min-sum，LOMS)算法、分层归一化最小和(layered normalized min-sum，LNMS)算法等。这些算法都是基于消息传递算法(Message Passing Algorithm)演进而来，都是在校验节点和比特节点之间做迭代计算。
应理解，通过采用译码算法进行LDPC译码的具体过程可参考现有技术，为了简洁，这里省略对该具体过程的详细说明。
在步骤260中，译码设备基于第一校验矩阵和第三编码比特序列的软值信息或硬值信息进行LDPC译码，得到信息序列。
为便于区分和说明，可将步骤260中译码设备基于第一校验矩阵和第三编码比特序列的软值信息或硬值信息进行LDPC译码的过程记作第二次LDPC译码。
如前所述，该第三编码比特序列可以为第一编码比特序列，也可以为经过交织或加扰的第一编码比特序列，则在一种可能的实现方式中，译码设备可以基于第一校验矩阵对第三编码比特序列的软值信息或硬值信息进行LDPC译码；在另一种可能的实现方式中，译码设备可以基于第一校验矩阵对解交织或解扰后的第三编码比特序列的软值信息或硬值信息进行LDPC译码。
换句话说，步骤260可包括：
译码设备基于第一校验矩阵对第三编码比特序列的软值信息或硬值信息进行LDPC译码，得到信息序列；或者
译码设备基于第一校验矩阵对解交织或解扰后的第三编码比特序列的软值信息或硬值信息进行LDPC译码，得到信息序列。
可以理解，译码设备进行第二次LDPC译码的对象可以取决于编码设备在第二次LDPC编码前是否对第一编码比特序列做了交织或加扰处理。通过对第一编码比特序列进行交织或加扰，可以将信号传输过程中可能遭遇的突发干扰、规律性干扰等随机地分散在编码比特，便于通过纠错技术恢复数据，从而可以提高信号传输的抗干扰能力，提高解调性能。
可选地，步骤260具体包括：
译码设备基于第一校验矩阵的基图确定第一校验矩阵；
译码设备基于第一校验矩阵和第三编码比特序列的软值信息或硬值信息进行LDPC译码，得到信息序列的软值信息或硬值信息；
译码设备对信息序列的软值信息或硬值信息进行判决，得到信息序列。
具体地，基于第一校验矩阵的基图确定第一校验矩阵的具体方法可以与步骤210中基于第一校验矩阵的基图确定第一校验矩阵的具体方法相同。译码设备可根据信息序列的长度确定第一校验矩阵的扩展因子，并基于基图和第一校验矩阵的扩展因子确定该第一校验矩阵。
与步骤250相似地，译码设备可采用译码算法对第三编码比特序列的软值信息或硬值信息进行第二次LDPC译码，以得到信息序列的软值信息或硬值信息，并可进一步对该信息序列的软值信息或硬值信息进行判决，以得到该信息序列。通过采用译码算法进行LDPC译码的具体过程可参考现有技术，为了简洁，这里省略对该具体过程的详细说明。
在一种可能的设计中，步骤250和步骤260可以由两个独立的译码器执行，该两个独立的译码器可通过执行程序代码，对输入的序列进行LDPC译码。具体地，对于译码器#1来说，可将待译码的第二编码比特序列的软值信息或硬值信息作为输入，将第三编码比特序列作的软值信息或硬值信息为输出，对于译码器#2来说，可将第三编码比特序列的软值信息或硬值信息或经过交织或加扰处理的第三编码比特序列的软值信息或硬值信息作为输入，将信息序列作为输出。可以理解的是，在译码器#1输出该第一编码比特序列的软值信息或硬值信息之后，可以用于对新输入的待译码的编码比特序列的软值信息或硬值信息进行LDPC译码；在译码器#1输出该第一译码比特序列的软值信息或硬值信息之前，译码器#2也可用于对之前输入的其他编码比特序列的软值信息或硬值信息进行LDPC译码，本申请对此不做限定。
在另一种可能的设计中，步骤250和步骤260也可以由一个译码器的两个译码单元来 执行，该两个独立的译码单元可通过执行程序代码，对输入的序列进行LDPC译码。具体地，对于译码单元#1来说，可将待译码的第二编码比特序列的软值信息或硬值信息作为输入，将第三编码比特序列的软值信息或硬值信息作为输出，对于译码单元#2来说，可将第三编码比特序列的软值信息或硬值信息或经过交织或加扰处理的第三编码比特序列的软值信息或硬值信息作为输入，将信息序列作为输出。可以理解的是，在译码单元#1输出该第一编码比特序列的软值信息或硬值信息之后，可以用于对新输入的待译码的编码比特序列的软值信息或硬值信息进行LDPC译码；在译码单元#1输出该第一译码比特序列的软值信息或硬值信息之前，译码单元#2也可用于对之前输入的其他编码比特序列的软值信息或硬值信息进行LDPC译码，本申请对此不做限定。
在另一种可能的设计中，步骤250和步骤260也可以由一个译码器的同一译码单元来执行。将待译码的第二编码比特序列的软值信息或硬值信息作为输入，在得到第三编码比特序列的软值信息或硬值信息后，将得到的第三编码比特序列的软值信息或硬值信息或经过处理后的第三编码比特序列的软值信息或硬值信息重新作为输入，直至得到信息序列并输出。
本领域的技术人员可以理解，编码设备想要发送的、未经过LDPC编码的信息序列(为便于区分和说明，将未经过LDPC编码的信息序列称为原始的信息序列)与经译码设备LDPC译码得到的信息序列(为便于区分和说明，将经过译码设备LDPC译码得到的信息序列称为恢复的信息序列)可能并不完全相同，本申请提供的方法旨在提高恢复的信息序列与原始的信息序列的相似度。
其中，两个二进制序列的相似度可以通过该两个二进制序列的汉明距离来表征。这里，汉明距离可以是指两个二进制序列不一样位置的总数。例如，对于二进制码“110”和“111”，汉明距离是1；对于二进制码“000”和“111”，汉明距离是3；对于二进制码“101”和“101”，汉明距离是0。因此，汉明距离越小，则相似度越高。
需要说明的是，译码设备进行LDPC译码的级联次数与编码设备进行LDPC编码的级联次数是相同的。并且，通过仿真可知，在提高第一编码码率的情况下，可以尽可能的减小级联LDPC编码可能带来的性能损失。例如，将第一编码码率控制在0.9附近。
图5示出了当前技术中采用LDPC编解码与采用本申请实施例提供的通信方法进行LDPC编码和译码的性能对比图。如图5所示，若仅进行一次LDPC编码和译码，在BLER小于10 -3范围内出现了错误平层；若采用本申请所提供通信方法进行两次级联LDPC编码和译码，在BLER小于10 -3范围内，BLER与符号信噪比的曲线未发生明显浮动，BLER随信噪比的增大而降低的趋势未发生明显变化，也就是在BLER小于10 -3范围没有出现明显的错误平层，因此，有利于提高译码性能。具体地，图5中以信息序列长度为420，第一编码比特序列长度为108、第二编码比特序列长度为94为例，分别示出了第一校验矩阵和第二校验矩阵均基于BG2确定，以及第一校验矩阵基于BG2确定、第二校验矩阵基于BG1确定的情形。
基于上述技术方案，通过编码设备对信息序列进行级联LDPC编码，译码设备对第二编码比特序列进行级联LDPC译码，可避免BLER在10 0至10 -6范围内出现明显的错误平层，即，有利于在较高的信噪比范围保证较低的BLER，从而可以在更大的信噪比范围内获得较好的译码性能。并且，通过将第一次LDPC编码码率控制在较高值，可以减小多次 LDPC编码带来的性能损失，从整体上看，有利于提高系统性能，使得该传输系统能够满足不同业务类型的需求。
应理解，在本申请实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
以上，结合图3至图5详细说明了本申请实施例提供的通信方法。以下，结合图6至图9详细说明本申请实施例提供的通信装置。
图6是本申请实施例提供的通信装置的示意性框图。如图6所示，该通信装置300可以包括：编码单元310。
在一种可能的设计中，该通信装置300可以为编码设备，或配置于编码设备中的芯片。该编码设备可以为无线传输中的发送设备。例如，该编码设备可以为下行传输中的网络设备，也可以为上行传输中的终端设备，还可以为D2D传输中的终端设备等，本申请对此不做限定。
具体地，该编码单元310可用于基于第一校验矩阵对待编码的信息序列进行低密度奇偶校验LDPC编码，得到第一编码比特序列；
该编码单元310还可用于基于第二校验矩阵和该第一编码比特序列进行LDPC编码，得到第二编码比特序列。
可选地，该编码单元310具体用于：
基于第二校验矩阵对第一编码比特序列进行LDPC编码；或者
基于第二校验矩阵对经过交织或加扰的第一编码比特序列进行LDPC编码。
可选地，该信息序列的长度K与该第一编码比特序列的长度L 1满足：
K/L 1≥0.9。
可选地，该信息序列的长度K与该第一编码比特序列的长度L 1满足：
L 1＝αK+β，
其中，α≥0.9，β为修正值。
可选地，该通信装置300还包括通信单元320，用于发送指示信息，该指示信息用于指示该第一编码比特序列的长度。
可选地，该通信装置300还包括确定单元330，用于根据该信息序列的长度和预先定义的编码码率确定该第一编码比特序列的长度。
可选地，该通信装置300还包括确定单元330，用于确定所述第一校验矩阵的基图；和/或，确定所述第二校验矩阵的基图。
可选地，第一校验矩阵的基图为新空口NR协议中的基图1BG1，第二校验矩阵的基图为NR协议中的基图2BG2；或者
第一校验矩阵的基图为BG2，第二校验矩阵的基图为BG1；或者
第一校验矩阵的基图为BG1，第二校验矩阵的基图为BG1；或者
第一校验矩阵的基图为BG2，第二校验矩阵的基图为BG2；
其中，BG1用于确定维度为46Z×68Z的校验矩阵，BG2用于确定维度为42Z×52Z的校验矩阵，Z为扩展因子。
应理解，该通信装置300可对应于根据本发明实施例的通信方法200中的编码设备， 该通信装置300可以包括用于执行图2中通信方法200的编码设备执行的方法的单元。并且，该通信装置300中的各单元和上述其他操作和/或功能分别为了实现图2中通信方法200的相应流程，具体地，该编码单元310用于执行方法200中的步骤210和步骤230，该通信单元320用于执行方法200中的步骤220和步骤240，各单元执行上述相应步骤的具体过程在方法200中已经详细说明，为了简洁，在此不再赘述。
图7是本申请实施例提供的通信装置的另一示意性框图。如图7所示，该通信装置400可以包括：译码单元410。
在一种可能的设计中，该通信装置300可以为译码设备，或配置于译码设备中的芯片。该译码设备可以为无线传输中的接收设备。例如，该译码设备可以为下行传输中的终端设备，也可以为上行传输中的网络设备，还可以为D2D传输中的终端设备等，本申请对此不做限定。
具体地，该译码单元410可用于基于第二校验矩阵对待译码的第二编码比特序列的软值信息或硬值信息进行低密度奇偶校验LDPC译码，得到第三编码比特序列的软值信息或硬值信息；
该译码单元410还可用于基于第一校验矩阵和该第三编码比特序列的软值信息或硬值信息进行LDPC译码，得到信息序列。
可选地，第三编码比特序列为第一编码比特序列，或者，第三编码比特序列为经过交织或加扰的第一编码比特序列，
若第三编码比特序列为第一编码比特序列，该译码单元410具体用于基于第一校验矩阵对第一编码比特序列的软值信息或硬值信息进行LDPC译码；
若第三编码比特序列为经过交织或加扰的第一编码比特序列，该译码单元410具体用于基于第一校验矩阵对经过解交织或解扰的第一编码比特序列的软值信息或硬值信息进行LDPC译码。
可选地，该信息序列的长度K与该第一编码比特序列的长度L 1满足：
K/L 1≥0.9。
可选地，该信息序列的长度K与该第一编码比特序列的长度L 1满足：
L 1＝αK+β，
其中，α≥0.9，β为修正值。
可选地，该通信装置400还包括通信单元420，用于接收指示信息，该指示信息用于指示该第一编码比特序列的长度。
可选地，该通信装置400还包括确定单元430，用于根据该信息序列的长度和预先定义的编码码率确定该第一编码比特序列的长度。
可选地，该通信装置400还包括确定单元430，用于确定所述第一校验矩阵的基图；和/或，确定所述第二校验矩阵的基图。
可选地，第一校验矩阵的基图为新空口NR协议中的基图1BG1，第二校验矩阵的基图为NR协议中的基图2BG2；或者
第一校验矩阵的基图为BG2，第二校验矩阵的基图为BG1；或者
第一校验矩阵的基图为BG1，第二校验矩阵的基图为BG1；或者
第一校验矩阵的基图为BG2，第二校验矩阵的基图为BG2；
其中，BG1用于确定维度为46Z×68Z的校验矩阵，BG2用于确定维度为42Z×52Z的校验矩阵，Z为扩展因子。
应理解，该通信装置400可对应于根据本发明实施例的通信方法200中的译码设备，该通信装置400可以包括用于执行图2中通信方法200的译码设备执行的方法的单元。并且，该通信装置400中的各单元和上述其他操作和/或功能分别为了实现图2中通信方法200的相应流程，具体地，该译码单元410用于执行方法200中的步骤250和步骤260，该通信单元420用于执行方法200中的步骤220和步骤240，各单元执行上述相应步骤的具体过程在方法200中已经详细说明，为了简洁，在此不再赘述。
图8是本申请实施例提供的网络设备500的结构示意图。如图8所示，该网络设备500包括处理器500和收发器520。可选地，该网络设备500还包括存储器530。其中，处理器510、收发器520和存储器530之间通过内部连接通路互相通信，传递控制和/或数据信号，该存储器530用于存储计算机程序，该处理器510用于从该存储器530中调用并运行该计算机程序，以控制该收发器520收发信号。
上述处理器510和存储器530可以合成一个处理装置，处理器510用于执行存储器530中存储的程序代码来实现上述功能。具体实现时，该存储器530也可以集成在处理器510中，或者独立于处理器510。
上述网络设备500还可以包括天线540，用于将收发器520输出的下行数据或下行控制信令通过无线信号发送出去。
具体地，该网络设备500可对应于根据本申请实施例的通信方法200中的编码设备，也可对应于本申请实施例的通信方法200中的译码设备。
当网络设备500对应于本申请实施例的通信方法200中的编码设备时，该网络设备500可以包括用于执行图2中通信方法200的编码设备执行的方法的模块。并且，该网络设备500中的各模块和上述其他操作和/或功能分别为了实现图2中通信方法200的相应流程。具体地，该存储器530用于存储程序代码，使得处理器510在执行该程序代码时，执行方法200中的步骤210和步骤230，并控制该收发器520通过天线540执行方法200中的步骤220和步骤240。各模块执行上述相应步骤的具体过程在方法200中已经详细说明，为了简洁，在此不再赘述。
在某些可能的实现方式中，图6中的编码单元310和确定单元330可对应于(例如，可以配置于或本身即为)图8中的处理器510，图6中的通信单元320可对应于(例如，可以配置于或本身即为)图8中的收发器520。
当网络设备500对应于本申请实施例的通信方法200中的译码设备时，该网络设备500可以包括用于执行图2中通信方法200的译码设备执行的方法的模块。并且，该网络设备500中的各模块和上述其他操作和/或功能分别为了实现图2中通信方法200的相应流程。具体地，该存储器530用于存储程序代码，使得处理器510在执行该程序代码时，执行方法200中的步骤250和步骤260，并控制该收发器520通过天线540执行方法200中的步骤220和步骤240。各模块执行上述相应步骤的具体过程在方法200中已经详细说明，为了简洁，在此不再赘述。
在某些可能的实现方式中，图7中的译码单元410和确定单元430可对应于(例如，可以配置于或本身即为)图4中的处理器510，图7中的通信单元420可对应于(例如， 可以配置于或本身即为)图8中的收发器520。
图9是本申请实施例提供的终端设备600的结构示意图。如图6所示，该终端设备600包括：处理器601和收发器602，可选地，该终端设备600还包括存储器603。其中，其中，处理器601、收发器602和存储器603之间通过内部连接通路互相通信，传递控制和/或数据信号，该存储器603用于存储计算机程序，该处理器601用于从该存储器603中调用并运行该计算机程序，以控制该收发器602收发信号。
上述处理器601和存储器603可以合成一个处理装置604，处理器601用于执行存储器603中存储的程序代码来实现上述功能。具体实现时，该存储器603也可以集成在处理器601中，或者独立于处理器601。上述终端设备600还可以包括天线610，用于将收发器602输出的上行数据或上行控制信令通过无线信号发送出去。
具体地，终端设备600可以对应于根据本申请实施例的通信方法200中的译码设备，该也可对应于本申请实施例的通信方法200中的编码设备。
当终端设备600对应于本申请实施例的通信方法200中的译码设备时，该通信设备600可以包括用于执行图2中通信方法200的译码设备执行的方法的模块，并且，该终端设备600中的各模块和上述其他操作和/或功能分别为了实现图2中通信方法200的相应流程。具体地，该存储器603用于存储程序代码，使得处理器601在执行该程序代码时，执行方法200中的步骤250和步骤260，并控制收发器602执行方法200中的步骤220和步骤240。各模块执行上述相应步骤的具体过程在方法200中已经详细说明，为了简洁，在此不再赘述。
上述处理器601可以用于执行前面方法实施例中描述的由译码设备内部实现的动作，而收发器602可以用于执行前面方法实施例中描述的译码设备接收编码设备传输或者发送的信号的动作。具体请见前面方法实施例中的描述，此处不再赘述。
在某些可能的实现方式中，图7中的译码单元410和确定单元430可对应于(例如，可以配置于或本身即为)图9中的处理器601，图7中的通信单元420可对应于(例如，可以配置于或本身即为)图9中的收发器602。
当终端设备600对应于本申请实施例的通信方法200中的编码设备时，该终端设备600可以包括用于执行图2中通信方法200的编码设备执行的方法的模块，并且，该终端设备600中的各模块和上述其他操作和/或功能分别为了实现图2中通信方法200的相应流程。具体地，该存储器603用于存储程序代码，使得处理器601在执行该程序代码时，执行方法200中的步骤210和步骤230，并控制该收发器602通过天线610执行方法200中的步骤220和步骤240。各模块执行上述相应步骤的具体过程在方法200中已经详细说明，为了简洁，在此不再赘述。
上述处理器601可以用于执行前面方法实施例中描述的由编码设备内部实现的动作，而收发器602可以用于执行前面方法实施例中描述的编码设备向译码设备传输或者发送信号的动作。具体请见前面方法实施例中的描述，此处不再赘述。
在某些可能的实现方式中，图6中的编码单元310和确定单元330可对应于(例如，可以配置于或本身即为)图9中的处理器601，图6中的通信单元320可对应于(例如，可以配置于或本身即为)图9中的收发器602。
需要说明的是，上述处理器601和存储器603可以集成为一个处理装置，处理器601 用于执行存储器603中存储的程序代码来实现上述功能。具体实现时，该存储器603也可以集成在处理器601中。
上述终端设备600还可以包括电源605，用于给终端中的各种器件或电路提供电源。
除此之外，为了使得终端设备的功能更加完善，该终端设备600还可以包括输入单元614，显示单元616，音频电路618，摄像头620和传感器622等中的一个或多个，所述音频电路还可以包括扬声器6182，麦克风6184等。
应理解，本申请实施例中，该处理器可以为中央处理单元(central processing unit，CPU)，该处理器还可以是其他通用处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现成可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
还应理解，本申请实施例中的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的随机存取存储器(random access memory，RAM)可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。
根据本申请实施例提供的方法，本申请还提供一种计算机程序产品，该计算机程序产品包括：计算机程序代码，当该计算机程序代码在计算机上运行时，使得该计算机执行图2所示实施例中的方法。
根据本申请实施例提供的方法，本申请还提供一种计算机可读介质，该计算机可读解释存储有程序代码，当该程序代码在计算机上运行时，使得该计算机执行图2所示实施例中的方法。
根据本申请实施例提供的方法，本申请还提供一种系统，其包括前述的一个或多个编码设备以及一个或多个译码设备。
上述实施例，可以全部或部分地通过软件、硬件、固件或其他任意组合来实现。当使用软件实现时，上述实施例可以全部或部分地以计算机程序产品的形式实现。该计算机程序产品包括一个或多个计算机指令。在计算机上加载或执行该计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。该计算机可以为通用计算机、专用计算机、计算机网络、或者其他可编程装置。该计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，该计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如红外、无线、微波等) 方式向另一个网站站点、计算机、服务器或数据中心进行传输。该计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集合的服务器、数据中心等数据存储设备。该可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质。半导体介质可以是固态硬盘。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (25)

  1. 一种通信方法，其特征在于，包括：
    基于第一校验矩阵对信息序列进行低密度奇偶校验LDPC编码，得到第一编码比特序列；
    基于第二校验矩阵和所述第一编码比特序列进行LDPC编码，得到第二编码比特序列。
  2. 根据权利要求1所述的方法，其特征在于，所述基于第二校验矩阵和所述第一编码比特序列进行LDPC编码，包括：
    基于所述第二校验矩阵对所述第一编码比特序列进行LDPC编码；或者
    基于所述第二校验矩阵对经过交织或加扰的第一编码比特序列进行LDPC编码。
  3. 一种通信方法，其特征在于，包括：
    基于第二校验矩阵对第二编码比特序列的软值信息或硬值信息进行低密度奇偶校验LDPC译码，得到第三编码比特序列的软值信息或硬值信息；
    基于第一校验矩阵和所述第三编码比特序列的软值信息或硬值信息进行LDPC译码，得到信息序列。
  4. 根据权利要求3所述的方法，其特征在于，所述第三编码比特序列为第一编码比特序列，或者，所述第三编码比特序列为经过交织或加扰的第一编码比特序列，以及
    所述基于第一校验矩阵和所述第三编码比特序列的软值信息或硬值信息进行LDPC译码，包括：
    若所述第三编码比特序列为所述第一编码比特序列，基于所述第一校验矩阵对所述第三编码比特序列的软值信息或硬值信息进行LDPC译码；或者
    若所述第三编码比特序列为经过交织或加扰的第一编码比特序列，基于所述第一校验矩阵对经过解交织或解扰的第三编码比特序列的软值信息或硬值信息进行LDPC译码。
  5. 根据权利要求1至4中任一项所述的方法，其特征在于，所述信息序列的长度K与所述第一编码比特序列的长度L 1满足：
    K/L 1≥0.9。
  6. 根据权利要求1至4中任一项所述的方法，其特征在于，所述信息序列的长度K与所述第一编码比特序列的长度L 1满足：
    L 1＝αK+β，
    其中，α≥0.9，β为修正值。
  7. 根据权利要求1、2、5或6中任一项所述的方法，其特征在于，所述方法还包括：
    发送指示信息，所述指示信息用于指示所述第一编码比特序列的长度。
  8. 根据权利要求3至6中任一项所述的方法，其特征在于，所述方法还包括：
    接收指示信息，所述指示信息用于指示所述第一编码比特序列的长度。
  9. 根据权利要求1至8中任一项所述的方法，其特征在于，所述方法还包括：
    根据所述信息序列的长度和预先定义的编码码率确定所述第一编码比特序列的长度。
  10. 根据权利要求1至9中任一项所述的方法，其特征在于，所述方法还包括：
    确定所述第一校验矩阵的基图；和/或
    确定所述第二校验矩阵的基图。
  11. 根据权利要求1至10中任一项所述的方法，其特征在于，所述第一校验矩阵的基图为新空口NR协议中的基图1BG1，所述第二校验矩阵的基图为NR协议中的基图2BG2；或者
    所述第一校验矩阵的基图为所述BG2，所述第二校验矩阵的基图为所述BG1；或者
    所述第一校验矩阵的基图为所述BG1，所述第二校验矩阵的基图为所述BG1；或者
    所述第一校验矩阵的基图为所述BG2，所述第二校验矩阵的基图为所述BG2；
    其中，所述BG1用于确定维度为46Z×68Z的校验矩阵，所述BG2用于确定维度为42Z×52Z的校验矩阵，Z为扩展因子。
  12. 一种通信装置，包括：
    编码单元，用于基于第一校验矩阵对待编码的信息序列进行低密度奇偶校验LDPC编码，得到第一编码比特序列；
    所述编码单元，还用于基于第二校验矩阵和所述第一编码比特序列进行LDPC编码，得到第二编码比特序列。
  13. 根据权利要求12所述的装置，其特征在于，所述编码单元具体用于：
    基于所述第二校验矩阵对所述第一编码比特序列进行LDPC编码；或者
    基于所述第二校验矩阵对经过交织或加扰的第一编码比特序列进行LDPC编码。
  14. 一种通信装置，包括：
    译码单元，用于基于第二校验矩阵对待译码的第二编码比特序列的软值信息或硬值信息进行低密度奇偶校验LDPC译码，得到第三编码比特序列的软值信息或硬值信息；
    所述译码单元，还用于基于第一校验矩阵和所述第三编码比特序列的软值信息或硬值信息进行LDPC译码，得到信息序列。
  15. 根据权利要求14所述的装置，其特征在于，所述第三编码比特序列为第一编码比特序列，或者，所述第三编码比特序列为经过交织或加扰的第一编码比特序列，
    若所述第三编码比特序列为第一编码比特序列，所述译码单元具体用于基于所述第一校验矩阵对所述第三编码比特序列的软值信息或硬值信息进行LDPC译码；
    若所述第三编码比特序列为经过交织或加扰的第一编码比特序列，所述译码单元具体用于基于所述第一校验矩阵对经过解交织或解扰的第三编码比特序列的软值信息或硬值信息进行LDPC译码。
  16. 根据权利要求12至15中任一项所述的装置，其特征在于，所述信息序列的长度K与所述第一编码比特序列的长度L 1满足：
    K/L 1≥0.9。
  17. 根据权利要求12至15中任一项所述的装置，其特征在于，所述信息序列的长度K与所述第一编码比特序列的长度L 1满足：
    L 1＝αK+β，
    其中，α≥0.9，β为修正值。
  18. 根据权利要求12、13、16或17中任一项所述的装置，其特征在于，所述装置还包括：
    通信单元，用于发送指示信息，所述指示信息用于指示所述第一编码比特序列的长度。
  19. 根据权利要求14至17中任一项所述的装置，其特征在于，所述装置还包括：
    通信单元，用于接收指示信息，所述指示信息用于指示所述第一编码比特序列的长度。
  20. 根据权利要求12至19中任一项所述的装置，其特征在于，所述装置还包括：
    确定单元，用于根据所述信息序列的长度和预先定义的编码码率确定所述第一编码比特序列的长度。
  21. 根据权利要求12至20中任一项所述的装置，其特征在于，所述装置还包括确定单元，所述确定单元用于：
    确定所述第一校验矩阵的基图；和/或
    确定所述第二校验矩阵的基图。
  22. 根据权利要求12至21中任一项所述的装置，其特征在于，所述第一校验矩阵的基图为新空口NR协议中的基图1BG1，所述第二校验矩阵的基图为NR协议中的基图2BG2；或者
    所述第一校验矩阵的基图为所述BG2，所述第二校验矩阵的基图为所述BG1；或者
    所述第一校验矩阵的基图为所述BG1，所述第二校验矩阵的基图为所述BG1；或者
    所述第一校验矩阵的基图为所述BG2，所述第二校验矩阵的基图为所述BG2；
    其中，所述BG1用于确定维度为46Z×68Z的校验矩阵，所述BG2用于确定维度为42Z×52Z的校验矩阵，Z为扩展因子。
  23. 一种通信装置，包括：
    处理器，用于执行存储器中存储的计算机程序，以使得所述装置执行如权利要求1至11中任一项所述的方法。
  24. 一种可读存储介质，包括程序或指令，当所述程序或指令在计算机上运行时，如权利要求1至11中任意一项所述的方法被执行。
  25. 一种计算机程序产品，当其在计算机上运行时，使得计算机执行权利要求1至11任一项所述的方法。
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