WO2019174380A1 - 一种时间宽度检测电路及其控制方法 - Google Patents

一种时间宽度检测电路及其控制方法 Download PDF

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Publication number
WO2019174380A1
WO2019174380A1 PCT/CN2019/070641 CN2019070641W WO2019174380A1 WO 2019174380 A1 WO2019174380 A1 WO 2019174380A1 CN 2019070641 W CN2019070641 W CN 2019070641W WO 2019174380 A1 WO2019174380 A1 WO 2019174380A1
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Prior art keywords
circuit
output
resistor
charging
capacitor
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PCT/CN2019/070641
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English (en)
French (fr)
Inventor
李树佳
刘改
冯刚
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广州金升阳科技有限公司
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Publication of WO2019174380A1 publication Critical patent/WO2019174380A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1588—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a time width detecting circuit for use as a driving auxiliary circuit for processing a driving waveform in a switching power supply.
  • the invention also relates to a method of controlling the circuit.
  • a synchronous rectifier is usually used instead of the unidirectional diode.
  • the conduction of the synchronous rectifier can replace the unidirectional diode, eliminating the unidirectional diode voltage drop and functioning as a synchronous rectification, but the current can also be reversed from the output via the synchronous rectifier.
  • the flyback converter that is, the buck converter with synchronous rectification has both current output and current consumption.
  • Figure 1 shows a conventional non-isolated DC-DC buck converter, usually consisting of input capacitor 1, power switch 2, energy storage inductor 3, freewheeling diode 4 and output capacitor 5. These devices are The connection mode shown in FIG. 1 is connected between the input voltage Vin and the output voltage Vo.
  • the power switch 2 is a typical electronic switch, such as a MOSFET, which is controlled by a control circuit, such as a PWM controller (not shown) responsive to the output voltage Vo.
  • a control circuit such as a PWM controller (not shown) responsive to the output voltage Vo.
  • the power switch tube 2 When the power switch tube 2 is turned on, the output terminal capacitor 5 is charged by the input voltage Vin through the power switch tube 2 and the energy storage inductor 3 to obtain an output voltage Vo lower than the input voltage Vin.
  • the power switch tube 2 is turned off, the flow is performed. The current through the energy storage inductor 3 is maintained by the freewheeling diode 4.
  • a power MOS transistor is usually used instead of the diode, as shown in the MOS tube 6 in Fig. 1, which is usually defined as synchronization.
  • the rectifier tube is connected at both ends as shown by the dotted line in the figure.
  • the synchronous rectifier 6 is used to allow the current to flow bidirectionally, that is, the current can flow from the position 8 to the position 7 and the position 7 to the position 8, so the circuit does not allow the power switch 2 and
  • the synchronous rectifier 6 is simultaneously turned on, which causes the input terminal to be short-circuited to ground.
  • the synchronous rectifier tube 6 is usually driven by a control signal complementary to the control signal of the power switch tube 2.
  • the duty cycle of the power switch tube 2 is generally increased from small when the control circuit is started, because the drive level of the synchronous rectifier 6 is complementary to the drive signal of the power switch tube.
  • the driving signal of the synchronous rectifier 6 will appear as a high level for a long time.
  • the typical circuit of the drive regulation circuit usually used to adjust the drive level is shown in Figure 2.
  • the main structure of the circuit of Figure 2 is a low-pass filter composed of a resistor R and a capacitor C, which delays the climb time of the rising edge of the Vin drive signal. The time during which the power switch tube 2 and the synchronous rectifier tube 6 are not turned on is controlled.
  • the technical problem to be solved by the present invention is to solve the problem of damage caused by the continuous conduction of the synchronous rectifier 6 and provide a time width detecting circuit capable of limiting the continuous conduction time of the synchronous rectifier, that is, capable of limiting Synchronous rectifier reverse current to prevent circuit damage.
  • the inventive concept of the present application is to provide a time width detecting circuit and a control method thereof.
  • the application block diagram is as shown in FIG. 3, and the driving adjusting circuit connected in parallel with FIG. 2 can detect the driving signal in real time and assist the driving adjusting circuit.
  • the output signal of the output end meets the required driving voltage; when the driving signal is detected to be a continuous high level exceeding the set time, the output circuit outputs a low level, the driving signal is pulled low, the synchronous rectifier is turned off; when the driving is detected When the signal is not higher than the set time, the output circuit is suspended, and the drive signal is adjusted by the drive adjustment circuit to control the synchronous rectifier to work normally.
  • the invention itself only turns off the long-term high-level driving signal or the abnormal-output large-duty-cycle driving signal of the abnormal output during the startup process or other conditions, and does not affect the driving signal of the synchronous rectifier during normal operation.
  • a time width detecting circuit is applied to a switching power supply including a driving adjusting circuit, and is characterized by comprising: a determining circuit, a charging circuit, a capacitor C1, a discharging circuit and an output circuit;
  • the input end of the judging circuit is an input end of the time width detecting circuit
  • the first output end of the judging circuit is connected to the input end of the charging circuit
  • the second output end of the judging circuit is connected to the input end of the discharging circuit
  • the output end of the charging circuit the capacitor C1
  • One end of the discharge circuit is connected to the output end of the output circuit, and the other end of the capacitor C1 is grounded, and the output end of the output circuit is the output end of the time width detecting circuit;
  • the input end of the time width detecting circuit is connected to the input end of the driving adjusting circuit, and the output end of the time width detecting circuit is connected to the output end of the driving adjusting circuit;
  • the determining circuit performs voltage sampling on the input signal of the input end of the driving adjustment circuit, and determines whether the input signal is a timing signal logic
  • the capacitor C1 is charged by the charging circuit and the discharging circuit when the input signal is the timing signal logic, and is discharged when the input signal is the non-timed signal logic;
  • Capacitor C1 also clocks the duration of the input signal being the timing signal logic
  • the output circuit determines whether to adjust the output signal of the output of the drive regulation circuit according to the magnitude of the voltage at one end of the capacitor C1.
  • the determining circuit comprises a first resistor, a second resistor and a first NPN transistor; one end of the first resistor R1 is an input end of the determining circuit, and the other end of the first resistor is connected to a base of the first NPN transistor; the second resistor One end is connected to the collector of the first NPN transistor, the connection point is the second output end of the judging circuit, and the other end of the second resistor is the first output end of the judging circuit; the emitter of the first NPN transistor is grounded.
  • the determining circuit comprises a first resistor, a second resistor and a first N-MOS transistor; one end of the first resistor R1 is an input end of the determining circuit, and the other end of the first resistor is connected to the gate of the first N-MOS tube One end of the second resistor is connected to the drain of the first N-MOS transistor, the connection point is the second output end of the judging circuit, and the other end of the second resistor is the first output end of the judging circuit; the first N-MOS tube The source is grounded.
  • the charging circuit comprises a first PNP transistor and a third resistor; the emitter of the first PNP transistor is connected to the supply voltage, the base of the first PNP transistor is at the input end of the charging circuit, and the emitter of the first PNP transistor is connected to the third resistor One end; the other end of the third resistor is the output of the charging circuit.
  • the discharge circuit comprises a first N-MOS transistor; the gate of the first N-MOS transistor is an input end of the discharge circuit, the source of the first N-MOS transistor is grounded, and the drain of the first N-MOS transistor is a discharge circuit The output.
  • the output circuit comprises a fourth resistor, a fifth resistor and a second NPN transistor; one end of the fourth resistor is an input end of the output circuit, and the other end of the fourth resistor is connected to a base of the second NPN transistor; One end is connected to the base of the second NPN transistor, and the other end of the fifth resistor is grounded; the emitter of the second NPN transistor is grounded, and the collector of the second NPN transistor is the output end of the time width detecting circuit.
  • the output circuit comprises a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first operational amplifier and a first diode; one end of the fourth resistor is an input end of the output circuit, and the fourth resistor is another One end is connected to the reverse input end of the first operational amplifier; one end of the fifth resistor is connected to the reverse input end of the first operational amplifier, and the other end of the fifth electrical resistance is grounded; one end of the sixth resistor is grounded, and the other end of the sixth resistor is connected a same input end of the first operational amplifier; one end of the seventh resistor is connected to the power supply voltage, and the other end of the seventh resistor is connected to the same input end of the first operational amplifier; the output end of the first operational amplifier is connected to the first diode The cathode; the anode of the first diode is the output of the time width detecting circuit.
  • the ground of the time width detecting circuit is common to the external power supply device and the front and rear stage circuits.
  • a control method for the above time width detecting circuit characterized in that:
  • the control for the charging circuit and the discharging circuit is:
  • the charging circuit is controlled to operate, and the discharging circuit is turned off, at which time the capacitor C1 is in a charging state;
  • the control discharging circuit works, the charging circuit is turned off, and the capacitor C1 is in a discharging state; if the charging circuit works When the charging current is lower than the discharging current when the discharging circuit is working, the discharging circuit is controlled to operate, and the charging circuit is turned off or continues to operate, and the capacitor C1 is also in a discharging state;
  • the control for the output circuit is:
  • the control output circuit When the charging time exceeds the set time, the voltage at one end of the capacitor C1 will be higher than the determination value, and the control output circuit outputs a low level signal, thereby turning off the output signal of the output of the driving adjustment circuit.
  • the present invention has the following remarkable effects:
  • the time width detecting circuit of the present invention is when the input signal is the timing signal logic and the duration does not exceed the set time, the voltage of the charging terminal of the capacitor C1 will be lower than the determination value, and the output end of the output circuit will be suspended, so that the time width detecting circuit will not be affected.
  • the normal operation of the driving adjustment circuit when the input signal is the timing signal logic and the charging time exceeds the set time, the voltage of the charging terminal of the capacitor C1 will be higher than the determination value, and the output circuit will output a low level signal to realize the output of the shutdown driving adjustment circuit. output signal.
  • the timing of the signal adjustment of the present invention is adjustable.
  • the invention itself has extremely low loss and low cost, and does not impose an unnecessary burden on the circuit design.
  • Figure 1 is a conventional non-isolated DC-DC buck converter using an N-MOS transistor as a synchronous rectifier
  • Figure 2 is a conventional drive adjustment circuit
  • FIG. 3 is a block diagram of an application principle of the present invention.
  • Figure 4 is a schematic block diagram of the present invention.
  • Figure 5 is a schematic diagram of the application of the first embodiment of the present invention.
  • Figure 6 is a schematic circuit diagram of a first embodiment of the present invention.
  • Figure 7 is a schematic circuit diagram of a second embodiment of the present invention.
  • Figure 8 is a circuit diagram of a third embodiment of the present invention.
  • FIG. 9 is a circuit diagram 1 of a circuit test according to a first embodiment of the present invention.
  • FIG. 10 is a circuit diagram 2 of a circuit test according to a first embodiment of the present invention.
  • Figure 11 is a circuit diagram 3 of the circuit test waveform of the first embodiment of the present invention.
  • Figure 4 shows a block diagram of the connection following the initial technical solution described above.
  • the features of the control method of the time width detecting circuit of the present invention are re-combed.
  • the three working states of the present invention are as follows:
  • the power supply device works normally.
  • the input signal Vin is the timing signal logic, and the charging time exceeds the set time, the voltage of the charging terminal of the capacitor C1 will be higher than the determination value, and the output circuit will output a low level signal.
  • the width detection circuit will implement an output signal that turns off the output of the drive regulation circuit.
  • the power supply device works normally, when the input signal Vin is the timing signal logic, and the charging time does not exceed the set time, the voltage of the charging terminal of the capacitor C1 will be lower than the determination value, and the output end of the output circuit will be suspended, the time width of the invention
  • the detection circuit will not affect the normal operation of the drive regulation circuit.
  • the application principle diagram of the time width detecting circuit of the first embodiment of the present invention is shown in FIG. 5, wherein the control circuit is a DC-DC buck converter control chip with complementary drive control, and the HD and LD are respectively corresponding power switch tubes of the control circuit output.
  • the LD is also an input signal of a parallel circuit of the time width detecting circuit and the driving adjusting circuit; the driving circuit is a power amplifying circuit for enhancing the driving power of the control circuit, and HI and LI are driving circuits.
  • LI is an output signal processed by a parallel circuit of the time width detecting circuit and the driving adjusting circuit, that is, a driving signal input to the input end of the driving circuit;
  • HO and LO are output ends of the driving circuit, respectively The drive signal of the power switch tube and the synchronous rectifier tube in the complementary drive-controlled DC-DC buck converter.
  • the time width detecting circuit of the present invention in FIG. 5 is separately drawn as shown in FIG. 6, including a determining circuit, a charging circuit, a capacitor C1, a discharging circuit, and an output circuit, and the components and connections of the modules in the circuit.
  • the relationship is described as follows:
  • the determining circuit includes a first resistor R1, a second resistor R2 and a first NPN transistor Q1; one end of the first resistor R1 is connected as an input terminal to the input signal Vin, and the other end of the first resistor R1 is connected to the base of the first NPN transistor Q1; One end of the second resistor R2 is connected to the collector of the first NPN transistor Q1 as an input terminal of the discharge circuit, and the other end of the second resistor R2 is used as an input terminal of the charging circuit; the emitter of the first NPN transistor Q1 is grounded.
  • the charging circuit comprises a first PNP transistor Q2 and a third resistor R3; the emitter of the first PNP transistor Q2 is connected to the supply voltage Vcc, the base of the first PNP transistor Q2 serves as the input of the charging circuit, and the emitter of the first PNP transistor Q2 One end of the third resistor R3 is connected; the other end of the third resistor R3 is connected to the capacitor C1 as an output end of the charging circuit.
  • the discharge circuit includes a first N-MOS transistor Q3; a gate of the first N-MOS transistor serves as an input terminal of the discharge circuit, a source of the first N-MOS transistor Q3 is grounded, and a drain of the first N-MOS transistor Q3 serves as a drain
  • the output of the discharge circuit is connected to the capacitor C1.
  • One end of the capacitor C1 is connected to the output end of the charging circuit and the output end of the discharging circuit, and the other end of the capacitor C1 is grounded.
  • the output circuit includes a fourth resistor R4, a fifth resistor R5 and a second NPN transistor Q4; one end of the fourth resistor R4 serves as a control terminal of the output circuit, and the other end of the fourth resistor R4 is coupled to the base of the second NPN transistor Q4; One end of the fifth resistor R5 is connected to the base of the second NPN transistor Q4, the other end of the fifth resistor R5 is grounded; the emitter of the second NPN transistor Q4 is grounded, and the collector of the second NPN transistor Q4 is used as the output end of the time width detecting circuit .
  • the charging time of the capacitor C1 in the embodiment is basically determined by the time constant between the third resistor R3 and the capacitor C1; the voltage at one end of the capacitor C1 is used as the timing result judgment signal.
  • the output circuit determines whether to turn off the output of the drive regulation circuit by determining the voltage at the capacitor charging terminal.
  • FIG. 9 is a waveform diagram of the whole process of adjusting the input signal Vin in conjunction with the driving adjustment circuit in the start-up process time width detecting circuit of the first embodiment.
  • the time width detecting circuit of the present invention does not count, The capacitor C1 does not store electrical energy, and the output of the time width detecting circuit is suspended; when the input signal Vin continues to a high level signal, the time width detecting circuit of the present invention starts counting, and when the charging time of the capacitor C1 is not reached, the time width detecting The output of the circuit is suspended without output, and the driving adjustment circuit outputs a pulse signal normally; when the input signal Vin continues to a high level signal exceeding a set time of the charging time of the capacitor C1, the time width detecting circuit of the present invention outputs a low level, and the driving is turned off. Adjusting the circuit output; when the input signal returns to the periodic signal of the normal pulse width, the time width detecting circuit of the present invention does not function, and the driving adjusting circuit operates normally.
  • the power supply device works normally, when the input signal Vin is the timing signal logic, and the charging time exceeds the set time, the voltage of the charging terminal of the capacitor C1 will be higher than the determination value, and the output circuit will output a low level signal, the present invention
  • the time width detection circuit will implement an output signal that turns off the output of the drive regulation circuit.
  • the power supply device works normally.
  • the first NPN transistor Q1 is saturatingly turned on, and the base voltage of the first PNP transistor Q2 is pulled down, so that the first PNP transistor Q2 is saturated and turned on, and the charging circuit
  • the first N-MOS transistor Q3 is turned off, the discharge circuit is turned off; the capacitor C1 starts to charge; when the timing signal duration (ie, the charging time of the capacitor C1) exceeds the set time, the voltage of the charging terminal of the capacitor C1 will be higher than the determination value.
  • the second NPN transistor Q4 is saturated and turned on, the output circuit outputs a low level signal, and the output signal voltage of the output of the driving adjustment circuit is pulled down, and the output signal of the output of the driving adjustment circuit is turned off; as shown in FIG. 10, when the input signal Vin (That is, when the LD waveform display signal is a continuous high level higher than the set time, the interval time width detecting circuit exceeding the set time continuously outputs a low level signal (such as an LI waveform display signal), so that the output signal at the output end of the driving circuit is Low level signal (ie LO waveform display signal).
  • a low level signal such as an LI waveform display signal
  • the first PNP transistor Q2 When the input signal Vin is a low-level non-timed signal, the first PNP transistor Q2 is turned off, the first N-MOS transistor Q3 is saturated, the charging circuit is turned off, the discharge circuit starts to work, the capacitor C1 is discharged, and when the discharge energy is much lower than Charging energy, the second NPN transistor Q4 continues to saturate and conduct, the output voltage of the output circuit is continuously pulled down, and the output signal of the output of the driving adjustment circuit continues to be turned off; as shown in the waveform of the first half of Fig.
  • the display signal is an abnormally large duty cycle periodic drive signal
  • the high level time is higher than the set time
  • the low level time is far less than the high level time
  • the output circuit The output signal of the output terminal is continuously pulled down (such as the LI waveform display signal), so that the output signal of the output of the rear stage drive adjustment circuit is a low level signal (ie, the LO waveform display signal).
  • the power supply device works normally, when the input signal Vin is the timing signal logic, and the charging time does not exceed the set time, the voltage of the charging terminal of the capacitor C1 will be lower than the determination value, and the output end of the output circuit will be suspended, the present invention
  • the time width detection circuit will not affect the normal operation of the normal drive regulation circuit.
  • the power supply device works normally.
  • the first NPN transistor Q1 is saturatingly turned on, and the base voltage of the first PNP transistor Q2 is pulled down, so that the first PNP transistor Q2 is saturated and turned on, and the charging circuit
  • the first N-MOS transistor Q3 is turned off, the discharge circuit is turned off; the capacitor C1 starts to charge; when the timing signal duration does not exceed the set time, and the capacitor C1 charging terminal voltage is lower than the determination value, the second NPN transistor Q4 is turned off.
  • the output circuit does not operate, and the output terminal of the output circuit is suspended, which does not affect the normal operation of the external drive adjustment circuit.
  • the first PNP transistor Q2 When the input signal Vin is a low-level non-timed signal, the first PNP transistor Q2 is turned off, and the first N-MOS transistor Q3 is saturated.
  • the charging circuit is cut off, the discharge circuit starts to work, the capacitor C1 is discharged, the second NPN transistor Q4 continues to be cut off, the output terminal of the output circuit continues to float, and the external drive regulation circuit still works normally.
  • the input signal Vin ie, the LD waveform display signal
  • the input signal Vin is a periodic signal that is continuously high for a period of time lower than the set time, and the low level time is sufficient for the capacitor C1 discharge time
  • the capacitor C1 The energy is not stored in each cycle, and the output end of the output circuit is continuously suspended, which does not affect the normal output signal of the drive adjustment circuit (such as the LI waveform display signal), so that the output signal of the output of the rear stage adjustment circuit is normal output signal (ie, the LO waveform display signal).
  • the power supply device works normally, and the timing time when the input signal Vin is the timing signal logic is adjustable.
  • the charging circuit begins to charge the capacitor C1, and the charging time is determined by the resistance of the third resistor R3 and the capacitance of the first capacitor C1.
  • the second embodiment of the present invention can be obtained by modifying the output circuit.
  • FIG. 7 below specifically describes the difference between the features of the second embodiment and the first embodiment as follows:
  • the judging circuit, the charging circuit, the capacitor C1, the discharge circuit composition and the connection thereof according to the present invention are identical to the first embodiment.
  • the output circuit includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first operational amplifier U1A and a first diode D1; and one end of the fourth resistor R4 is connected to one end of the capacitor C1, and the fourth resistor The other end of R4 is connected to the reverse input terminal of the first operational amplifier U1A; the fifth resistor R5 is connected to the first operational amplifier U1A inverting input terminal, the fifth resistor R5 is connected to the other end of the grounding terminal; the sixth resistor R6 is grounded at one end, and the sixth resistor R6 is connected to the other end.
  • the cathode of the diode D1; the anode of the first diode D1 serves as the output terminal Vo of the time width detecting circuit.
  • the voltage at one end of the capacitor C1 is divided by the fourth resistor R4 and the fifth resistor R5 as an input signal of the inverting input terminal of the first operational amplifier U1A, and the seventh resistor R7 and the sixth resistor R6 divide the power supply voltage VCC as the first
  • the input signal of the U1A non-inverting input terminal when the input signal Vin is a high-level timing signal and the duration exceeds the set time, the reverse input signal of the first operational amplifier U1A is higher than the same reference voltage, the first operation Put U1A output low level, pull the output signal voltage of the output of the control circuit to be low; when the input signal Vin is high level timing signal and the duration is lower than the set time, the reverse input signal of the first operational amplifier U1A is low.
  • the output of the first operational amplifier U1A is high, the first diode D1 is turned off, and the output terminal is suspended.
  • the third embodiment of the present invention can be obtained by modifying the discharge circuit.
  • the following describes the difference between the features of the third embodiment and the first embodiment as follows:
  • the judging circuit, the charging circuit, the capacitor C1 and the output circuit composition and the connection thereof according to the present invention are identical to the first embodiment.
  • the third embodiment of the present patent can be obtained by replacing the N-MOS transistor used in the discharge circuit of the first embodiment with an NPN transistor having a magnification factor larger than that of the first PNP transistor.
  • the first NPN transistor When the judging circuit judges that the input signal Vin is non-timed signal logic, the first NPN transistor is turned off; since the discharge circuit is replaced by an NPN transistor, the base thereof maintains a certain base current during operation, and the first NPN transistor is turned off, first The base current of the PNP transistor is the same as the base current of the NPN transistor used in the discharge circuit, and the charging circuit continues to operate; since the selected NPN transistor amplification factor ⁇ is larger than the first PNP transistor, the charging current is less than the discharge current when the charging circuit operates. The current, the capacitor C1 is discharged, and the output voltage Vo of the output circuit is adjusted following the voltage at one end of the capacitor C1, and the circuit performance is consistent with the first embodiment.
  • the first NPN transistor Q1 can be directly replaced by an N-MOS tube, and the function of sampling timing signals can also be realized, which is easily implemented by those skilled in the art, and will not be described herein.

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  • Dc-Dc Converters (AREA)
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Abstract

一种时间宽度检测电路及其控制方法，通过对满足计时逻辑的信号进行采样，并根据其时间宽度输出对应的输出信号；该电路可用于开关电源中，与处理驱动波形的驱动调节电路并联使用，控制驱动电路输入的驱动信号；当输入信号Vin为计时信号逻辑且持续时间不超过设定时间，电容C1充电端电压将低于判定值，输出电路输出端将悬空，不会影响驱动调节电路的正常工作；当输入信号Vin为计时信号逻辑且充电时间超过设定时间，电容C1充电端电压将高于判定值，输出电路将输出低电平信号，关断驱动调节电路输出信号；电容C1充电端电压的判定值可调，设定时间可调。该电路损耗小，成本低，不会对电路正常设计造成负担。

Description

一种时间宽度检测电路及其控制方法 技术领域
本发明涉及一种时间宽度检测电路，用作开关电源中处理驱动波形的驱动辅助电路。本发明还涉及该电路的控制方法。
背景技术
在非隔离式DC-DC降压变换器中，为了提高转换器的效率，通常采用同步整流管代替单向二极管。在电流经过同步整流管流向输出端时，同步整流管的导通能够代替单向二极管，消除单向二极管压降，起到同步整流的作用，但电流也能够经同步整流管从输出端反向流回变换器，即具有同步整流的降压变换器具有电流输出和电流消耗两种能力。
如图1所示为传统非隔离式DC-DC降压变换器，通常由输入端电容1、功率开关管2、储能电感3、续流二极管4及输出端电容5组成，这些器件以如图1所示的连接方式连接在输入电压Vin与输出电压Vo之间。功率开关管2为典型的电子开关，比如为一个MOSFET，该功率开关管受控于一个控制电路，比如为一个响应于输出电压Vo的PWM控制器(图中未给出)。当功率开关管2导通时，输出端电容5由输入电压Vin通过功率开关管2及储能电感3进行充电，得到低于输入电压Vin的输出电压Vo，当功率开关管2截止时，流经储能电感3的电流通过续流二极管4得以维持。
在储能电感3释放能量的过程中，由于续流二极管4存在二极管压降，为减小其损耗，通常采用功率MOS管代替二极管，在图1中如MOS管6所示，通常定义为同步整流管，其两端连接方式如图中虚线所示。在同步整流管6工作时，降低了续流二极管4两端的压降。与采用续流二极管4所不同的是，采用同步整流管6允许电流双向流动，即电流既可以从位置8流向位置7，又可以从位置7流向位置8，所以电路不允许功率开关管2与同步整流管6同时导通，这样会造成输入端对地短路。为了防止因功率开关管2与同步整流管6共通导致输入端Vin对地GND短路，同步整流管6通常采用与功率开关管2控制信号互补的控制信号进行驱动。
采用互补型驱动控制的DC-DC降压变换器中，通常在控制电路启动时，功率开关管2驱动信号占空比从小增大，由于同步整流管6驱动电平与功率开关管驱动信号互补，在电路启动时同步整流管6的驱动信号会表现为持续较长时间的高电平。而通常应用于调节驱动电平的驱动调节电路典型电路如图2所示，图2电路主体结构是由电阻R与电容C构成的一个低通滤波器，通过延缓Vin驱动信号上升沿的爬升时间控制功率开关管2与同步整 流管6不同时导通的时间，然而图2电路并未能去除同步整流管6的长时间高电平。当应用在给电池等储能设备供电场合中时，由于同步整流管6的驱动信号保持为持续的高电平，输出储能设备中的电压会经同步整流管6反向给储能电感3充电；由于持续时间长，持续增大的电流会烧坏同步整流管6，并在同步整流管6关断时，储能电感的电流会经功率开关管2反向流回至输入端Vin中，过大的电流会导致功率开关管2损坏。
当采用互补型驱动的具有同步整流功能的非隔离式DC-DC降压变换器应用在给电池、电容等储能设备充电场合，或在输出端电容5电压未下降为0V时重新启机，或因热插拔等任何能够导致同步整流管6持续导通状态现象存在时，都有导致电路损坏的风险。
发明内容
有鉴如此，本发明要解决的技术问题是：解决因同步整流管6持续导通引起的损坏问题，提供一种时间宽度检测电路，该电路能够限制同步整流管持续导通时间，即能够限制同步整流管反向电流的大小，以防止电路损坏。
本申请的发明构思为：提出一种时间宽度检测电路及其控制方法，应用框图如图3所示，并联于图2中的驱动调节电路，能够对驱动信号进行实时检测，并辅助驱动调节电路输出端的输出信号符合要求的驱动电压；当检测到驱动信号为超过设定时间的持续高电平时，输出电路输出低电平，将驱动信号拉低，使同步整流管关断；当检测到驱动信号为不超过设定时间的高电平时，输出电路悬空，驱动信号由驱动调节电路进行调节，控制同步整流管正常工作。
本发明本身只对启动过程或者其他情况下异常输出的长期高电平驱动信号或异常输出的大占空比驱动信号起关断作用，不影响正常工作时同步整流管的驱动信号。
本发明所述的一种时间宽度检测电路技术方案如下：
一种时间宽度检测电路，应用于包含有驱动调节电路的开关电源中，其特征在于：包括判断电路、充电电路、电容C1，放电电路及输出电路；
判断电路的输入端为时间宽度检测电路的输入端，判断电路的第一输出端连接充电电路的输入端，判断电路的第二输出端连接放电电路的输入端，充电电路的输出端、电容C1的一端及放电电路的输出端相连接后连接至输出电路的输入端，电容C1的另一端接地，输出电路的输出端为时间宽度检测电路的输出端；
时间宽度检测电路的输入端连接驱动调节电路的输入端，时间宽度检测电路的输出端连接驱动调节电路的输出端；
判断电路对驱动调节电路输入端的输入信号进行电压采样，并判断输入信号是否为计 时信号逻辑；
电容C1通过充电电路和放电电路实现在输入信号是计时信号逻辑时充电，在输入信号为非计时信号逻辑时放电；
电容C1同时还对输入信号是计时信号逻辑的持续时间进行计时；
输出电路依据电容C1一端电压的大小决定是否对驱动调节电路输出端的输出信号进行调节。
优选的，判断电路包括第一电阻、第二电阻及第一NPN三极管；第一电阻R1的一端为判断电路的输入端，第一电阻的另一端连接第一NPN三极管的基极；第二电阻的一端连接第一NPN三极管的集电极，连接点为判断电路的的第二输出端，第二电阻的另一端为判断电路的第一输出端；第一NPN三极管的发射极接地。
优选的，判断电路包括第一电阻、第二电阻及第一N-MOS管；第一电阻R1的一端为判断电路的输入端，第一电阻的另一端连接第一N-MOS管的栅极；第二电阻的一端连接第一N-MOS管的漏极，连接点为判断电路的的第二输出端，第二电阻的另一端为判断电路的第一输出端；第一N-MOS管的源极接地。
优选的，充电电路包括第一PNP三极管及第三电阻；第一PNP三极管的发射极连接供电电压，第一PNP三极管的基极为充电电路的输入端，第一PNP三极管的发射极连接第三电阻的一端；第三电阻的另一端为充电电路的输出端。
优选的，放电电路包括第一N-MOS管；第一N-MOS管的栅极为放电电路的输入端，第一N-MOS管的源极接地，第一N-MOS管的漏极为放电电路的输出端。
优选的，输出电路包括第四电阻、第五电阻及第二NPN三极管；第四电阻的一端为输出电路的输入端，第四电阻的另一端连接第二NPN三极管的基极；第五电阻的一端连接第二NPN三极管的基极，第五电阻的另一端接地；第二NPN三极管的发射极接地，第二NPN三极管的集电极为时间宽度检测电路的输出端。
优选的，输出电路包括第四电阻、第五电阻、第六电阻、第七电阻、第一运放及第一二极管；第四电阻的一端为输出电路的输入端，第四电阻的另一端连接第一运放的反向输入端；第五电阻的一端连接第一运放的反向输入端，第五电阻的另一端接地；第六电阻的一端接地，第六电阻的另一端连接第一运放的同向输入端；第七电阻的一端连接供电电压，第七电阻的另一端连接第一运放的同向输入端；第一运放的输出端连接第一二极管的阴极；第一二极管的阳极为时间宽度检测电路的输出端。
优选的，时间宽度检测电路的地与外部供电装置、前后级电路共地。
本发明上述时间宽度检测电路的控制方法技术方案如下：
一种上述时间宽度检测电路的控制方法，其特征在于：
针对充电电路和放电电路的控制为：
当输入信号是计时信号逻辑时，控制充电电路工作，放电电路截止，此时电容C1处于充电状态；
当输入信号为非计时信号逻辑时，如果充电电路工作时的充电电流大于或等于放电电路工作时的放电电流，控制放电电路工作，充电电路截止，此时电容C1处于放电状态；如果充电电路工作时充电电流小于放电电路工作时的放电电流，控制放电电路工作，充电电路截止或继续工作均可，此时电容C1也处于放电状态；
针对输出电路的控制为：
当充电时间不超过设定时间时，电容C1一端的电压将低于判定值，控制输出电路不工作，输出电路无输出，从而不影响驱动调节电路的正常工作；
当充电时间超过设定时间，电容C1一端的电压将高于判定值，控制输出电路输出低电平信号，从而关断驱动调节电路输出端的输出信号。
与现有技术相比，本发明具有如下的显著效果：
1、本发明时间宽度检测电路当输入信号为计时信号逻辑且持续时间不超过设定时间，电容C1充电端电压将低于判定值，输出电路输出端将悬空，使得时间宽度检测电路不会影响驱动调节电路的正常工作；当输入信号为计时信号逻辑且充电时间超过设定时间，电容C1充电端电压将高于判定值，输出电路将输出低电平信号，实现关断驱动调节电路输出端的输出信号。
2、当输入信号为计时信号逻辑时，本发明对信号的计时时间可调。
3、本发明本身损耗极低，成本低，不会对电路设计造成多余负担。
附图说明
图1为使用N-MOS管作同步整流管的传统非隔离式DC-DC降压变换器；
图2为传统的驱动调节电路；
图3为本发明的应用原理框图；
图4为本发明的原理框图；
图5为本发明第一实施例的应用原理图；
图6为本发明第一实施例的电路原理图；
图7为本发明第二实施例的电路原理图；
图8为本发明第三实施例的电路原理图；
图9为本发明第一实施例的电路测试波形图一；
图10为本发明第一实施例的电路测试波形图二；
图11为本发明第一实施例的电路测试波形图三。
具体实施方式
图4示出了原理框图，遵循上述初始的技术方案的连接关系。为了方便理解，将本发明时间宽度检测电路的控制方法的特征进行了重新梳理，针对输入信号Vin的不同信号逻辑及输入情况，本发明具有的3个工作状态如下：
工作状态1、供电装置正常工作，当输入信号Vin为计时信号逻辑，且充电时间超过设定时间时，电容C1充电端电压将高于判定值，输出电路将输出低电平信号，本发明时间宽度检测电路将实现关断驱动调节电路输出端的输出信号。
工作状态2、供电装置正常工作，当输入信号Vin为计时信号逻辑，且充电时间不超过设定时间时，电容C1充电端电压将低于判定值，输出电路输出端将悬空，本发明时间宽度检测电路将不会影响驱动调节电路的正常工作。
工作状态3、供电装置正常工作，输入信号Vin为计时信号逻辑时的计时时间可调。
第一实施例
本发明第一实施例的时间宽度检测电路应用原理图如图5，其中控制电路为互补型驱动控制的DC-DC降压变换器控制芯片，HD、LD分别为控制电路输出的对应功率开关管与同步整流管的驱动逻辑信号，在实施例中LD还为时间宽度检测电路与驱动调节电路并联电路的输入信号；驱动电路为增强控制电路驱动信号功率的功率放大电路，HI、LI为驱动电路的输入端，在实施例中LI为经过时间宽度检测电路与驱动调节电路并联电路处理后的输出信号，即为驱动电路输入端输入的驱动信号；HO、LO为驱动电路的输出端，分别为互补型驱动控制的DC-DC降压变换器中功率开关管与同步整流管的驱动信号。
针对每个电路模块，将图5中本发明的时间宽度检测电路单独绘制后如图6所示，包括判断电路、充电电路、电容C1、放电电路及输出电路，电路中各模块的组成及连接关系具体说明如下：
判断电路包括第一电阻R1、第二电阻R2及第一NPN三极管Q1；第一电阻R1的一端作为输入端连接输入信号Vin，第一电阻R1的另一端连接第一NPN三极管Q1的基极；第二电阻R2的一端连接第一NPN三极管Q1的集电极作为放电电路的输入端，第二电阻R2的另一端作为充电电路的输入端；第一NPN三极管Q1的发射极接地。
充电电路包括第一PNP三极管Q2及第三电阻R3；第一PNP三极管Q2的发射极连接供电电压Vcc，第一PNP三极管Q2的基极作为充电电路的输入端，第一PNP三极管Q2的发射极连接第三电阻R3的一端；第三电阻R3的另一端作为充电电路的输出端连接电容C1。
放电电路包括第一N-MOS管Q3；第一N-MOS管的栅极作为放电电路的输入端，第一N-MOS管Q3的源极接地，第一N-MOS管Q3的漏极作为放电电路的输出端连接电容C1。
电容C1的一端连接充电电路的输出端及放电电路的输出端，电容C1的另一端接地。
输出电路包括第四电阻R4、第五电阻R5及第二NPN三极管Q4；第四电阻R4的一端作为输出电路的控制端，第四电阻R4的另一端连接第二NPN三极管Q4的基极；第五电阻R5的一端连接第二NPN三极管Q4的基极，第五电阻R5的另一端接地；第二NPN三极管Q4的发射极接地，第二NPN三极管Q4的集电极作为时间宽度检测电路的输出端。
需要说明的是：在供电电源Vcc不变的情况下，本实施例中电容C1的充电时间基本由第三电阻R3与电容C1之间的时间常数决定；电容C1一端电压作为计时结果判断信号，输出电路通过判断电容充电端电压决定是否关断驱动调节电路输出。
图9是第一实施例启机过程时间宽度检测电路结合驱动调节电路对输入信号Vin进行调节的全过程波形图，当输入信号Vin为低电平信号，本发明的时间宽度检测电路不计时，电容C1不存储电能，时间宽度检测电路输出端悬空；当输入信号Vin持续高电平信号开始时，本发明的时间宽度检测电路开始计时，电容C1充电时间未到设定时间时，时间宽度检测电路输出端悬空无输出，驱动调节电路正常输出脉冲信号；当输入信号Vin持续高电平信号超过电容C1充电时间的设定时间时，本发明的时间宽度检测电路输出低电平，关断驱动调节电路输出；当输入信号恢复为正常脉宽的周期信号时，本发明的时间宽度检测电路不起作用，驱动调节电路正常工作。
下面结合图6、图10、图11对本发明的工作过程详细说明如下：
针对工作状态1：供电装置正常工作，当输入信号Vin为计时信号逻辑，且充电时间超过设定时间时，电容C1充电端电压将高于判定值，输出电路将输出低电平信号，本发明时间宽度检测电路将实现关断驱动调节电路输出端的输出信号。
供电装置正常工作，当输入信号Vin为高电平计时信号时，第一NPN三极管Q1饱和导通，将第一PNP三极管Q2基极电压被下拉，使得第一PNP三极管Q2饱和导通，充电电路工作；同时第一N-MOS管Q3截止，放电电路截止；电容C1开始充电；当计时信号持续时间(即电容C1的充电时间)超过设定时间，电容C1充电端电压将高于判定值，第二NPN三极管Q4饱和导通，输出电路输出低电平信号，驱动调节电路输出端的输出信号电压被下 拉，驱动调节电路输出端的输出信号被关断；如图10所示，当输入信号Vin(即LD波形显示信号)为高于设定时间的持续高电平时，超过设定时间的区间时间宽度检测电路持续输出低电平信号(如LI波形显示信号)，使得驱动电路输出端的输出信号为低电平信号(即LO波形显示信号)。
当输入信号Vin为低电平非计时信号时，第一PNP三极管Q2截止，第一N-MOS管Q3饱和导通，充电电路截止，放电电路开始工作，电容C1放电，当放电能量远低于充电能量，第二NPN三极管Q4继续饱和导通，输出电路输出端电压持续被下拉，驱动调节电路输出端的输出信号继续关断；如图11前半部分波形所示，当输入信号Vin(即LD波形显示信号)为异常大占空比的周期驱动信号，持续高电平时间高于设定时间，且低电平时间远远小于高电平时间时，当放电能量远低于充电能量，输出电路输出端的输出信号持续被下拉(如LI波形显示信号)，使得后级驱动调节电路输出端的输出信号为低电平信号(即LO波形显示信号)。
针对工作状态2：供电装置正常工作，当输入信号Vin为计时信号逻辑，且持充电时间不超过设定时间时，电容C1充电端电压将低于判定值，输出电路输出端将悬空，本发明时间宽度检测电路将不会影响正常驱动调节电路的正常工作。
供电装置正常工作，当输入信号Vin为高电平计时信号时，第一NPN三极管Q1饱和导通，将第一PNP三极管Q2基极电压被下拉，使得第一PNP三极管Q2饱和导通，充电电路工作；同时第一N-MOS管Q3截止，放电电路截止；电容C1开始充电；当计时信号持续时间不超过设定时间，电容C1充电端电压低于判定值时，第二NPN三极管Q4截止，输出电路不动作，输出电路输出端悬空，不影响外接驱动调节电路正常工作；当输入信号Vin为低电平非计时信号，第一PNP三极管Q2截止，第一N-MOS管Q3饱和导通，充电电路截止，放电电路开始工作，电容C1放电，第二NPN三极管Q4继续截止，输出电路输出端继续悬空，外接驱动调节电路仍然正常工作。
如图11后半部分波形所示，当输入信号Vin(即LD波形显示信号)为持续高电平时间低于设定时间的周期信号，且低电平时间足够电容C1放电时间时，电容C1每个周期不存储能量，输出电路输出端持续悬空，不影响驱动调节电路正常输出信号(如LI波形显示信号)，使得后级驱动调节电路输出端正常输出信号(即LO波形显示信号)。
针对工作状态3：供电装置正常工作，输入信号Vin为计时信号逻辑时的计时时间可调。
当输入信号Vin为高电平计时信号，充电电路开始对电容C1充电，充电时间由第三电阻R3的阻值与第一电容C1的容值共同决定。
第二实施例
在第一实施例的基础上，将输出电路进行改动可得到本发明的第二实施例，下面附图7对第二实施例与第一实施例的特征区别进行具体说明如下：
本发明所述的判断电路、充电电路、电容C1、放电电路组成及其连接情况与第一实施例一致。
输出电路包括第四电阻R4、第五电阻R5、第六电阻R6、第七电阻R7、第一运放U1A及第一二极管D1；第四电阻R4一端连接电容C1的一端，第四电阻R4另一端连接第一运放U1A反向输入端；第五电阻R5一端连接第一运放U1A反向输入端，第五电阻R5另一端接地；第六电阻R6一端接地，第六电阻R6另一端连接第一运放U1A同向输入端；第七电阻R7一端连接供电电压VCC，第七电阻R7另一端连接连接第一运放U1A同向输入端；第一运放U1A输出端连接第一二极管D1的阴极；第一二极管D1的阳极作为时间宽度检测电路的输出端Vo。
下面结合图7对本发明的工作过程差异说明如下：
电容C1一端的电压经过第四电阻R4及第五电阻R5分压后作为第一运放U1A反向输入端的输入信号，第七电阻R7及第六电阻R6对供电电压VCC进行分压作为第一运放U1A同向输入端的输入信号，当输入信号Vin为高电平计时信号时且持续时间超过设定时间时，第一运放U1A的反向输入信号高于同向基准电压，第一运放U1A输出低电平，将驱动调节电路输出端的输出信号电压拉低；当输入信号Vin为高电平计时信号且持续时间低于设定时间时，第一运放U1A的反向输入信号低于同向基准电压，第一运放U1A的输出高电平，第一二极管D1截止，输出端悬空。
第三实施例
在第一实施例的基础上，将放电电路进行改动可得到本发明的第三实施例，下面附图8对第三实施例与第一实施例的特征区别进行具体说明如下：
本发明所述的判断电路、充电电路、电容C1及输出电路组成及其连接情况与第一实施例一致。
将第一实施例中放电电路所用的N-MOS管换为放大倍数β大于第一PNP三极管的NPN三极管，可得到本专利的第三实施例。
下面结合图8对本发明的工作过程差异说明如下：
当判断电路判断输入信号Vin为非计时信号逻辑时，第一NPN三极管截止；由于放电电路换作NPN三极管，其基极在工作过程保持一定的基极电流，并且第一NPN三极管截止，第一PNP三极管的基极电流与放电电路所用的NPN三极管的基极电流一致，充电电路持续工作；由于所选取NPN三极管放大倍数β大于第一PNP三极管，充电电路工作时充电电流小于所述放电电路放电电流，电容C1放电，输出电路的输出电压Vo跟随电容C1一端的电压进行调节，电路性能与第一实施例一致。
此外，还可以将第一NPN三极管Q1直接换成N-MOS管，也可以实现采样计时信号的作用，这是本领域的技术人员容易实现的，在此不赘述。
以上仅是本发明的优选实施方式，应当指出的是，上述优选实施方式不应视为本发明的限制，在本发明图4原理框图的基础上，对于本技术领域的普通技术人员来说，在不脱离本发明的精神和范围内，还可以做出另外的改进及润饰，这些改进及润饰也在本发明的保护范围，这里不再用实施例赘述，本发明的保护范围应当以权利要求所限定的范围为准。

Claims (9)

  1. 一种时间宽度检测电路，应用于包含有驱动调节电路的开关电源中，其特征在于：包括判断电路、充电电路、电容C1，放电电路及输出电路；
    判断电路的输入端为时间宽度检测电路的输入端，判断电路的第一输出端连接充电电路的输入端，判断电路的第二输出端连接放电电路的输入端，充电电路的输出端、电容C1的一端及放电电路的输出端相连接后连接至输出电路的输入端，电容C1的另一端接地，输出电路的输出端为时间宽度检测电路的输出端；
    时间宽度检测电路的输入端连接驱动调节电路的输入端，时间宽度检测电路的输出端连接驱动调节电路的输出端；
    判断电路对驱动调节电路输入端的输入信号进行电压采样，并判断输入信号是否为计时信号逻辑；
    电容C1通过充电电路和放电电路实现在输入信号是计时信号逻辑时充电，在输入信号为非计时信号逻辑时放电；
    电容C1同时还对输入信号是计时信号逻辑的持续时间进行计时；
    输出电路依据电容C1一端电压的大小决定是否对驱动调节电路输出端的输出信号进行调节。
  2. 根据权利要求1所述的时间宽度检测电路，其特征在于：判断电路包括第一电阻、第二电阻及第一NPN三极管；第一电阻R1的一端为判断电路的输入端，第一电阻的另一端连接第一NPN三极管的基极；第二电阻的一端连接第一NPN三极管的集电极，连接点为判断电路的的第二输出端，第二电阻的另一端为判断电路的第一输出端；第一NPN三极管的发射极接地。
  3. 根据权利要求1所述的时间宽度检测电路，其特征在于：判断电路包括第一电阻、第二电阻及第一N-MOS管；第一电阻R1的一端为判断电路的输入端，第一电阻的另一端连接第一N-MOS管的栅极；第二电阻的一端连接第一N-MOS管的漏极，连接点为判断电路的的第二输出端，第二电阻的另一端为判断电路的第一输出端；第一N-MOS管的源极接地。
  4. 根据权利要求1所述的时间宽度检测电路，其特征在于：充电电路包括第一PNP三极管及第三电阻；第一PNP三极管的发射极连接供电电压，第一PNP三极管的基极为充电电路的输入端，第一PNP三极管的发射极连接第三电阻的一端；第三电阻的另一端为充电电路的输出端。
  5. 根据权利要求1所述的时间宽度检测电路，其特征在于：放电电路包括第一N-MOS管；第一N-MOS管的栅极为放电电路的输入端，第一N-MOS管的源极接地，第一N-MOS管的漏极为放电电路的输出端。
  6. 根据权利要求1所述的时间宽度检测电路，其特征在于：输出电路包括第四电阻、第五电阻及第二NPN三极管；第四电阻的一端为输出电路的输入端，第四电阻的另一端连接第二NPN三极管的基极；第五电阻的一端连接第二NPN三极管的基极，第五电阻的另一端接地；第二NPN三极管的发射极接地，第二NPN三极管的集电极为时间宽度检测电路的输出端。
  7. 根据权利要求1所述的时间宽度检测电路，其特征在于：输出电路包括第四电阻、第五电阻、第六电阻、第七电阻、第一运放及第一二极管；第四电阻的一端为输出电路的输入端，第四电阻的另一端连接第一运放的反向输入端；第五电阻的一端连接第一运放的反向输入端，第五电阻的另一端接地；第六电阻的一端接地，第六电阻的另一端连接第一运放的同向输入端；第七电阻的一端连接供电电压，第七电阻的另一端连接第一运放的同向输入端；第一运放的输出端连接第一二极管的阴极；第一二极管的阳极为时间宽度检测电路的输出端。
  8. 根据权利要求1所述的时间宽度检测电路，其特征在于：时间宽度检测电路的地与外部供电装置、前后级电路共地。
  9. 一种权利要求1至8任一项时间宽度检测电路的控制方法，其特征在于：
    针对充电电路和放电电路的控制为：
    当输入信号是计时信号逻辑时，控制充电电路工作，放电电路截止，此时电容C1处于充电状态；
    当输入信号为非计时信号逻辑时，如果充电电路工作时的充电电流大于或等于放电电路工作时的放电电流，控制放电电路工作，充电电路截止，此时电容C1处于放电状态；如果充电电路工作时充电电流小于放电电路工作时的放电电流，控制放电电路工作，充电电路截止或继续工作均可，此时电容C1也处于放电状态；
    针对输出电路的控制为：
    当充电时间不超过设定时间时，电容C1一端的电压将低于判定值，控制输出电路不工作，输出电路无输出，从而不影响驱动调节电路的正常工作；
    当充电时间超过设定时间，电容C1一端的电压将高于判定值，控制输出电路输出低电平信号，从而关断驱动调节电路输出端的输出信号。
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