WO2019174308A1 - 阵列基板、其制造方法、以及显示装置 - Google Patents

阵列基板、其制造方法、以及显示装置 Download PDF

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WO2019174308A1
WO2019174308A1 PCT/CN2018/118122 CN2018118122W WO2019174308A1 WO 2019174308 A1 WO2019174308 A1 WO 2019174308A1 CN 2018118122 W CN2018118122 W CN 2018118122W WO 2019174308 A1 WO2019174308 A1 WO 2019174308A1
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Prior art keywords
layer
electrode
thin film
film transistor
light emitting
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PCT/CN2018/118122
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English (en)
French (fr)
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龙春平
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京东方科技集团股份有限公司
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Priority to EP18852790.7A priority Critical patent/EP3767675B1/en
Priority to US16/335,453 priority patent/US11251223B2/en
Publication of WO2019174308A1 publication Critical patent/WO2019174308A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • the present application relates to the field of display technologies, and in particular, to an array substrate, a method of manufacturing the same, and a display device.
  • a Micro Light-Emitting Diode is a light-emitting device using an inorganic material such as gallium nitride as a light-emitting material, and has a typical size in the range of, for example, 10 ⁇ m to 15 ⁇ m.
  • the display device using the Micro LED as a light-emitting device has the advantages of high brightness, fast response, and high stability.
  • an array of thin film transistors is generally formed on a glass substrate, and a plurality of micro LEDs are formed on the single crystal silicon substrate; the single crystal silicon substrate is then diced to obtain a plurality of independent micros. LED; finally, each Micro LED is transferred to a corresponding area on the array substrate.
  • an array substrate including: a substrate substrate; a thin film transistor disposed on the substrate, the thin film transistor including: a gate connected to the gate line; an active layer; a gate insulating layer insulating the gate from the active layer; a first pole connected to the data line; and a second pole spaced apart from the first pole space; and a micro light emitting diode disposed in the On the base substrate, the micro light emitting diode includes a first electrode, a first buffer layer, a light emitting layer and a second electrode which are disposed in a stack, and the first buffer layer is disposed in the same layer as the active layer.
  • the second electrode of the thin film transistor is connected to one of a first electrode of the micro light emitting diode and a second electrode of the micro light emitting diode.
  • the micro light emitting diode further includes: a first semiconductor layer disposed between the light emitting layer and the first buffer layer, and a first electrode disposed on the light emitting layer and the micro light emitting diode A second semiconductor layer between the two electrodes.
  • the micro light emitting diode further includes a second buffer layer disposed between the first semiconductor layer and the first buffer layer, the first buffer layer and the active layer being the same Made of materials.
  • the material of the first buffer layer comprises at least one of graphene, zinc oxide, zinc sulfide, silicon carbide, and aluminum nitride
  • the material of the second buffer layer includes gallium nitride, At least one of gallium arsenide, aluminum gallium arsenide, aluminum gallium nitride, and indium phosphide.
  • the thin film transistor is a top gate structure, wherein a first electrode of the micro light emitting diode, a first pole of the thin film transistor, and a second pole of the thin film transistor are disposed in a same layer, a second pole of the thin film transistor is connected to a second electrode of the micro light emitting diode through a first contact via disposed in the gate insulating layer, and a first electrode of the micro light emitting diode is configured to receive a common electrode voltage .
  • the thin film transistor is a top gate structure, wherein a first electrode of the micro light emitting diode, a first pole of the thin film transistor, and a second pole of the thin film transistor are disposed in a same layer,
  • the second electrode of the thin film transistor is integral with the first electrode of the micro light emitting diode, and the second electrode of the micro light emitting diode is configured to receive a common electrode voltage.
  • the thin film transistor is a bottom gate structure, wherein a first electrode of the micro light emitting diode is disposed in the same layer and spaced apart from the gate, and the array substrate further includes a thin film transistor disposed The first pole and the second pole are away from the passivation layer on one side of the base substrate.
  • a second pole of the thin film transistor is connected to a second electrode of the micro light emitting diode through a second contact via disposed in the passivation layer, and a first electrode of the micro light emitting diode is configured to receive a common Electrode voltage.
  • the thin film transistor is a bottom gate structure, wherein a first electrode of the micro light emitting diode is disposed in the same layer and spaced apart from the gate, and the thin film transistor further includes a cathode layer disposed on the active layer A protective layer away from one side of the base substrate.
  • a first pole and a second pole of the thin film transistor are disposed on a side of the protective layer away from the base substrate, and a first pole of the thin film transistor passes through a first via in the protective layer
  • An active layer is connected, a second pole of the thin film transistor is connected to the active layer through a second via in the protective layer, and a second pole of the thin film transistor is further passed through a third of the protective layer
  • a contact via is coupled to the first electrode of the miniature light emitting diode, and a second electrode of the miniature light emitting diode is configured to receive a common electrode voltage.
  • a method of fabricating an array substrate comprising: forming a thin film transistor and a micro light emitting diode on a base substrate, the thin film transistor including: a gate connected to a gate line; an active layer a gate insulating layer insulating the gate from the active layer; a first pole connected to the data line; and a second pole spaced apart from the first pole space, the miniature light emitting diode comprising a stack a first electrode, a first electrode, a first buffer layer, a light emitting layer and a second electrode, wherein the first buffer layer is formed in the same layer as the active layer; and the second electrode of the thin film transistor is connected And to the first electrode of the micro light emitting diode and one of the second electrodes of the micro light emitting diode.
  • the micro light emitting diode further includes a first semiconductor layer and a second semiconductor layer. Forming the micro light emitting diode includes sequentially forming a first electrode of the micro light emitting diode, a first buffer layer, the first semiconductor layer, the light emitting layer, and the second in a direction away from the substrate a semiconductor layer and a second electrode of the micro light emitting diode.
  • the method before forming the first semiconductor layer, further includes forming a second buffer layer on a side of the first buffer layer away from the substrate substrate.
  • the first semiconductor layer is formed on a side of the second buffer layer away from the base substrate, and the first buffer layer and the active layer are formed of the same material.
  • the thin film transistor is a top gate structure.
  • the forming the thin film transistor and the micro light emitting diode includes integrally forming a second electrode of the thin film transistor and a first electrode of the micro light emitting diode by one patterning process.
  • the thin film transistor is a top gate structure.
  • the method further includes forming a first contact via extending through the gate insulating layer to expose the second electrode of the thin film transistor.
  • a second electrode of the micro light emitting diode is formed after the first contact via is formed, and is connected to the second electrode of the thin film transistor through the first contact via.
  • the thin film transistor is a bottom gate structure.
  • Forming the thin film transistor and the micro light emitting diode includes forming a first electrode and the gate of the micro light emitting diode in the same layer by one patterning process.
  • the method further includes: forming a passivation layer on a side of the first and second poles of the thin film transistor away from the substrate; and forming a through A second contact via of the passivation layer exposes a second pole of the thin film transistor.
  • a second electrode of the micro light emitting diode is formed after the contact via is formed, and is connected to the second electrode of the thin film transistor through the second contact via.
  • the method further includes: forming a protective layer on a side of the active layer away from the base substrate; and forming a first layer in the protective layer A via hole and a second via hole expose the active layer and expose the first electrode of the micro light emitting diode by forming a third contact via in the protective layer.
  • a first pole and a second pole of the thin film transistor are formed on a side of the protective layer away from the base substrate, and a first pole of the thin film transistor is connected to the active layer through the first via
  • the second pole of the thin film transistor is connected to the active layer through the second via and is connected to the first electrode of the micro light emitting diode through the third contact via.
  • a display device comprising any one of the array substrates as described above.
  • FIG. 1 is a schematic cross-sectional view of an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 2A is a schematic cross-sectional view of an array substrate according to another embodiment of the present disclosure.
  • FIG. 2B is a schematic cross-sectional view of a variation of the array substrate of FIG. 2A;
  • FIG. 2C is a schematic plan view showing the structure of the array substrate of FIG. 2A;
  • 3A is a schematic cross-sectional view of an array substrate in accordance with another embodiment of the present disclosure.
  • 3B is a schematic cross-sectional view of a variation of the array substrate of FIG. 3A;
  • FIG. 4 is a flow chart of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 5A is a flowchart of a method of manufacturing an array substrate according to another embodiment of the present disclosure.
  • 5B is a schematic cross-sectional view showing a structure obtained by forming a metal thin film on a base substrate
  • 5C is a schematic cross-sectional view showing a first electrode of a thin film transistor, a second electrode of a thin film transistor, and a first electrode of a Micro LED obtained by patterning the metal thin film of FIG. 5B;
  • 5D is a schematic cross-sectional view showing a structure obtained by forming a graphene layer on each electrode of FIG. 5C;
  • 5E is a schematic view showing formation of an active layer and a first buffer layer using the graphene layer of FIG. 5D;
  • 5F is a schematic cross-sectional view showing a structure obtained by forming a gate insulating layer on the active layer of FIG. 5E;
  • 5G is a schematic cross-sectional view showing a structure obtained by forming a second buffer layer, a first semiconductor layer, a light emitting layer, and a second semiconductor layer on the first buffer layer of FIG. 5F;
  • 5H is a schematic cross-sectional view showing a structure obtained by forming a gate electrode on the gate insulating layer of FIG. 5G;
  • 5I is a schematic cross-sectional view showing a structure obtained by forming a passivation layer on the gate and gate insulating layers of FIG. 5H and forming a first contact via in the passivation layer and the gate insulating layer;
  • FIG. 6A is a flowchart of a method of fabricating an array substrate according to another embodiment of the present disclosure.
  • FIG. 6B is a flowchart of a method of manufacturing an array substrate according to another embodiment of the present disclosure.
  • FIG. 7 is a schematic block diagram of a display device in accordance with an embodiment of the present disclosure.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/ Some should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer Thus, a first element, component, region, layer, or section, which is discussed below, may be referred to as a second element, component, region, layer or section without departing from the teachings of the disclosure.
  • under and under can encompass both the ⁇ RTIgt; Terms such as “before” or “before” and “after” or “following” may be used, for example, to indicate the order in which light passes through the elements.
  • the device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • a layer is referred to as “between two layers,” it may be a single layer between the two layers, or one or more intermediate layers may be present.
  • FIG. 1 is a schematic cross-sectional view of an array substrate in accordance with an embodiment of the present disclosure.
  • the array substrate can include a plurality of pixels arranged in an array, although only a single pixel is shown for convenience of illustration.
  • a pixel includes a thin film transistor 10 and a micro LED 20 disposed on a base substrate BS.
  • the thin film transistor 10 is used to drive the micro LED 20 to emit light.
  • the thin film transistor 10 includes a gate electrode 12, an active layer 11, a gate insulating layer 15 that insulates the gate electrode 12 from the active layer 11, a first electrode 13, and a second electrode 14 that is spaced apart from the first electrode 13.
  • the active layer 11 is filled between the first pole 13 and the second pole 14, and in this example also covers at least a portion of the first pole 13 and at least a portion of the second pole 14.
  • the micro LED 20 includes a first electrode 21, a first buffer layer 22, a light emitting layer 23, and a second electrode 24 which are disposed one on another.
  • the first buffer layer 22 may be disposed in the same layer as the active layer 11.
  • the gate electrode 12 of the thin film transistor 10 is connected to a gate line (not shown in FIG. 1), the first electrode 13 of the thin film transistor 10 is connected to a data line (not shown in FIG. 1), and the thin film transistor 10 is
  • the diode 14 is connected to the first electrode 21 or the second electrode 24.
  • One of the first electrode 21 and the second electrode 24 that is not connected to the second electrode 14 of the thin film transistor 10 may receive a common electrode voltage as a common electrode, and may be referred to as a cathode, and the first electrode 21 and the second electrode 24
  • the other electrode connected to the second pole 14 of the thin film transistor 10 may be referred to as an anode.
  • the second electrode 14 of the thin film transistor 10 is connected to the second electrode 24 of the micro LED 20, and the first electrode 21 of the micro LED 20 can be connected to a common electrode line (not shown) for reception.
  • Common electrode voltage The first electrode 13 of the thin film transistor 10 may be a source, and the second electrode 14 of the thin film transistor 10 may be a drain. Alternatively, the first pole 13 can be a drain and the second pole 14 can be a source.
  • the first electrode 21 of the micro LED 20 may be an N-type electrode, and the second electrode 24 of the micro LED 20 may be a P-type electrode.
  • the micro LEDs of the individual pixels can share the anode, ie the anodes of the micro LEDs of each pixel can be the same electrode.
  • the light-emitting layer 23 in the micro LED 20 may be formed of a material of a group III-V compound (including a binary compound, a ternary compound, or a quaternary compound, etc.).
  • the III-V compound refers to a compound formed of a group III element and a group V element of the periodic table, and the group III element includes boron (B), aluminum (Al), gallium (Ga), and indium (In), etc., V Group elements include nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb).
  • the III-V compound generally includes gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), and the like.
  • the semiconductor light-emitting layer formed of the III-V compound material has high luminous efficiency, good stability, and long life.
  • the common electrode voltage applied to the cathode electrode (in this example, the first electrode 21) through the common electrode line may be different from the common electrode voltage of the conventional display device.
  • the common electrode voltage in the conventional display device may be 0 volt (V), or near 0 V, for example, -5 V to 5 V; and in the array substrate of the embodiment of the present disclosure, the voltage applied to the cathode electrode may not be limited. In the above range.
  • the applied cathode voltage ranges from -20V to 20V, typically not 0V.
  • FIG. 2A is a schematic cross-sectional view of an array substrate in accordance with another embodiment of the present disclosure.
  • the same elements as in FIG. 1 are denoted by the same reference numerals and will not be described in detail herein.
  • the micro LED 20 further includes: a first semiconductor layer 25 disposed between the light emitting layer 23 and the first buffer layer 22, and a first portion disposed between the light emitting layer 23 and the second electrode 24.
  • Two semiconductor layers 26 In this example, the first semiconductor layer 25 may be an N-type semiconductor layer, and the second semiconductor layer 26 may be a P-type semiconductor layer.
  • the N-type semiconductor layer may be made of a III-V compound material doped with a Group IV element, for example, a GaN material doped with silicon (Si) atoms.
  • the P-type semiconductor layer may be made of a Group III-V compound material doped with a Group II element, for example, may be made of a GaN material doped with magnesium (Mg) atoms.
  • the micro LED further includes a second buffer layer 27 disposed between the first semiconductor layer 25 and the first buffer layer 22.
  • the first buffer layer 22 and the active layer 11 may be made of the same material.
  • the first buffer layer 22 is doped with ions, for example, may be doped with phosphorus ions, boron ions or arsenic ions.
  • the second buffer layer 27 and the first buffer layer 22 are made of different materials, and the difference between the lattice constant of the material of the second buffer layer 27 and the lattice constant of the material of the first buffer layer 22 is less than Set the threshold. That is, the crystal structures of the materials of the two buffer layers are the same or similar, so that the first buffer layer 22 can facilitate the epitaxial growth of the second buffer layer 27, and ensure the epitaxial growth quality of the second buffer layer 27.
  • the active layer 11 and the first buffer layer 22 may be made of graphene, zinc oxide (ZnO), zinc sulfide (ZnS), silicon carbide (SiC), or aluminum nitride (AlN), or any combination thereof.
  • the second buffer layer 27 may be made of gallium nitride (GaN), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), aluminum gallium nitride (AlGaN) or indium phosphide (InP) or any It is made of a combination of a III-V compound material. Because of its tens to thousands to thousands times migration with respect to materials such as amorphous silicon, oxides, and polysilicon, graphene can provide a more stable threshold voltage for thin film transistors, which helps to ensure the lifetime of the array substrate.
  • the thin film transistor 10 is a top gate structure in which the active layer 11 is disposed on a side of the first electrode 13 and the second electrode 14 away from the base substrate BS, and the gate insulating layer 15 is disposed at The active layer 11 is away from the side of the base substrate BS, and the gate electrode 12 is disposed on a side of the gate insulating layer 15 away from the substrate substrate BS.
  • the first electrode 21 of the micro LED 20, the first electrode 13 of the thin film transistor 10, and the second electrode 14 of the thin film transistor 10 are disposed in the same layer.
  • a first contact via CV1 capable of exposing the second pole 14 is formed in the gate insulating layer 15 such that the second pole 14 can be connected to the second electrode 24 through the first contact via CV1.
  • the passivation layer 02 is disposed on the side of the second electrode 14 of the thin film transistor 10 away from the substrate substrate BS, the first contact via CV1 also penetrates the passivation layer 02.
  • FIG. 2B is a schematic cross-sectional view of a variation of the array substrate of FIG. 2A.
  • the same elements as in FIG. 2A are denoted by the same reference numerals and will not be described in detail herein.
  • the second electrode 14 of the thin film transistor 10 and the first electrode 21 of the micro LED 20 are an integral structure formed by one patterning process, that is, a portion of the first structure in contact with the active layer 14.
  • the second electrode 14 of the thin film transistor 10 is formed, and the portion of the unitary structure that is in contact with the first buffer layer 22 constitutes the first electrode 21 of the micro LED 20.
  • the second electrode 24 of the micro LED 20 can function as a common electrode and receive a common electrode voltage.
  • FIG. 2C is a schematic plan view of the structure of the array substrate of FIG. 2A.
  • the second pole 14 is connected to the second electrode 24 through the first contact via CV1.
  • the first electrode 13 of the thin film transistor 10 is connected to the data line 130, and the gate electrode 12 of the thin film transistor 10 is connected to the gate line 120.
  • FIG. 3A is a schematic cross-sectional view of an array substrate in accordance with another embodiment of the present disclosure.
  • the thin film transistor 10 is a bottom gate structure in which a gate electrode 12 is disposed on a base substrate BS, a gate insulating layer 15 is disposed on the base substrate BS and covers the gate electrode 12, and the first electrode 13 and The second electrode 14 is disposed on a side of the gate insulating layer 15 away from the substrate substrate BS and is in contact with the active layer 11.
  • the first electrode 21 of the micro LED 20 is disposed in the same layer and spaced apart from the gate 12 of the thin film transistor 10.
  • the passivation layer 02 is disposed on a side of the second electrode 14 of the thin film transistor 10 away from the substrate substrate BS and is provided with a second contact via CV2.
  • the second pole 14 can be connected to the second electrode 24 of the micro LED 20 through the second contact via CV2.
  • FIG. 3B is a schematic cross-sectional view of an array substrate in accordance with another embodiment of the present disclosure.
  • the same elements as in FIG. 3A are denoted by the same reference numerals and will not be described in detail herein.
  • the thin film transistor 10 further includes a protective layer 16 disposed on a side of the active layer 11 away from the substrate substrate BS, and the first and third electrodes 13 and 14 of the thin film transistor 10 are disposed on the protective layer. 16 is away from the side of the substrate substrate BS.
  • the first pole 13 is connected to the active layer 11 through the first via hole V1
  • the second pole 14 is connected to the active layer 11 through the second via hole V2
  • the second pole 14 is also passed through the third contact via hole CV3.
  • the first electrode 21 is connected.
  • a portion of the first electrode 21 may protrude from other respective film layers in the micro LED 20, such that the second The pole 14 may be in contact with a portion of the first electrode 21 that is convex.
  • the micro LED 20 can be formed simultaneously in the process of forming the thin film transistor 10, simplifying the array.
  • the manufacturing process of the substrate reduces the manufacturing cost of the display device.
  • FIGS. 1 to 3B are flow charts of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure. This method can be used to fabricate the array substrate shown in FIGS. 1 to 3B.
  • a thin film transistor and a micro light emitting diode are formed on the base substrate.
  • the micro LED includes a first electrode, a first electrode, a first buffer layer, a light emitting layer, and a second electrode that are stacked one on another.
  • the first buffer layer is formed in the same layer as the active layer of the thin film transistor.
  • the second electrode of the thin film transistor is coupled to the first or second electrode of the micro LED. It will be understood that although steps 101 and 102 in Figure 4 are illustrated as being separate from each other, they may be a one-piece process.
  • the thin film transistor and the micro LED can be simultaneously formed in the manufacturing process, thereby effectively simplifying the manufacturing process of the array substrate and reducing the manufacturing cost of the display device.
  • the manufacturing method provided by the embodiments of the present disclosure can have a shorter process time and a higher yield than a conventional transfer process.
  • the process of forming the micro LED may include sequentially forming the first electrode, the first buffer layer, the first semiconductor layer, the light emitting layer, the second semiconductor layer, and the second electrode in a direction away from the base substrate.
  • the method may further include: forming a second buffer layer on a side of the first buffer layer away from the substrate substrate.
  • the first semiconductor layer can be formed on a side of the second buffer layer away from the substrate.
  • the first buffer layer and the active layer are formed of the same material, and the first buffer layer is doped with ions.
  • the second buffer layer and the first buffer layer are formed of different materials, and a difference between a lattice constant of a material of the second buffer layer and a lattice constant of a material of the first buffer layer is less than a preset threshold, that is, forming
  • a preset threshold that is, forming
  • the crystal structures of the materials of the two buffer layers are the same or similar.
  • the first buffer layer may be made of a material such as graphene, ZnO, ZnS, SiC or AlN
  • the second buffer layer may be made of a material such as GaN, GaAs, AlGaAs, AlGaN or InP. .
  • the method for manufacturing the array substrate provided by the embodiment of the present disclosure is described in detail below by taking the thin film transistor of the top gate structure shown in FIG. 2A as an example.
  • the method can include the following steps.
  • Step 1011a forming first and second poles of the thin film transistor and a first electrode of the micro LED on the base substrate.
  • the base substrate may be a glass substrate.
  • the first pole and the second pole of the thin film transistor and the first electrode of the micro LED are spaced apart from each other.
  • the first electrode of the micro LED is located in an effective display area of the array substrate, and the first pole and the second pole of the thin film transistor are located in a non-pixel area (ie, a non-display area) of the array substrate.
  • a metal thin film 200 having a thickness of 200 nm (nm) to 500 nm may be deposited on the glass substrate BS by magnetron sputtering.
  • the material forming the metal thin film 200 may be copper (Cu) or a copper alloy.
  • the coating can be carried out by DC magnetron sputtering or AC magnetron sputtering.
  • the target was cleaned for 2 minutes (min) in a plasma generated by Ar gas having a purity of 99.99% before the sputter coating was started.
  • the sputtering power is adjusted to 100 watts (W) to prepare the metal film.
  • W watts
  • the texture of the copper film first increases and then decreases as the sputtering gas pressure P and the plating distance D increase.
  • the sputtering gas pressure is 0.5 Pa and the plating distance is 200 mm (mm)
  • the copper film obtained by sputtering has the strongest texture, and the crystal grains are fine, and the film density and flatness are high.
  • the metal thin film 200 may be formed using an electroplating process.
  • the electroplating copper solution used in forming the copper film may include: copper salt: 120 g per liter (g/L) to 300 g/L; acid: 10 g/L to 200 g/L; chloride ion: 30 g/L to 80 mg/L; sulfur-containing compound: 0.001 g/L to 0.3 g/L; polyoxyether compound: 0.5 g/L to 10 g/L; polyethylene glycol: 0.05 g/L to 5 g/L; quaternary ammonium salt : 0.001 g / L to 0.2 g / L.
  • the process parameters of the electroplating method may be: a bath temperature of 10 degrees Celsius (° C.) to 50° C., and a current density of 0.2 amps per square decimeter (A/dm 2 ) to 20 A/dm 2 .
  • a patterned photoresist mask may be formed on the surface of the metal thin film 200 by a single photolithography process, and the metal thin film 200 not covered by the photoresist mask may be etched to obtain spatial separation.
  • the metal thin film 200 may be etched at a temperature of 50 ° C using an iron chloride (FeCl 3 ) etching solution.
  • FeCl 3 iron chloride
  • Step 1012a forming a spatially separated active layer and a first buffer layer on the base substrate, the active layer being in contact with the first and second poles of the thin film transistor.
  • the active layer is located in an active region of the thin film transistor and is in contact with the first pole and the second pole.
  • the first buffer layer is located in the pixel region and covers a side of the first electrode of the micro LED that is away from the substrate.
  • the material forming the active layer and the first buffer layer may be graphene, ZnO, ZnS, SiC or AlN, etc., and the first buffer layer is further doped with ions, for example, may be doped with N+ ions, such as phosphorus ions. , boron ion or arsenic ion.
  • the metal thin film is used as a copper thin film, and the material for forming the active layer and the first buffer layer is graphene, and the manufacturing process of the active layer and the first buffer layer is described.
  • the base substrate on which the first pole, the second pole and the first electrode are formed is ultrasonically cleaned in acetone and deionized water for 15 minutes, respectively, to remove contaminants such as oil stains on the surface of the copper film.
  • the substrate substrate can then be placed in a constant temperature zone in the reaction chamber for graphene growth.
  • the growth process of the graphene is as follows. In the first step, the reaction chamber is evacuated to a vacuum and filled with oxygen. This operation was repeated three times or so to allow the air in the reaction chamber to be discharged, and the reaction chamber was filled with an oxygen atmosphere.
  • the temperature of the reaction chamber is raised to 500 ° C in an oxygen atmosphere with a flow rate of 300 standard milliliters per minute (sccm), and then kept at a constant temperature of 20 mim, and the oxide on the surface of the copper film is reduced by high temperature annealing;
  • the temperature of the reaction chamber can be adjusted to the temperature required for growth, and the flow rate of oxygen is also adjusted to the flow rate required for growth, and at the same time, 80 sccm of argon gas is introduced, and the temperature is kept constant for 20 minutes.
  • the flow rate of other gases is kept constant, and 7 sccm of methane is introduced, and the graphite thinning starts to grow.
  • the methane feed time is 15 min.
  • the methane was stopped, and the temperature of the reaction chamber was started to be cooled at a temperature decreasing rate of 10 ° C / min until room temperature.
  • the argon flow rate remains unchanged, and the oxygen flow rate is reduced by 30 sccm to avoid the excessive candle flow rate on the resultant graphene film.
  • the copper film can be used as a catalyst for graphene growth.
  • the surface of the base substrate BS may be covered with a layer of graphene 100.
  • a patterned photoresist mask can be formed on the surface of the graphene 100 by a photolithography process, which can cover the graphene in the active region and the graphene in the pixel region.
  • the portion of the graphene that is not covered by the photoresist mask may be removed by an etching process to obtain the active layer and the graphene film layer located in the pixel region.
  • the etching process may be a dry etching process of hydrogen plasma, wherein the hydrogen flow rate is controlled to 50 sccm, the substrate temperature is 300 ° C, the plasma power is 100 W, and the etching rate is within 5 nm/min.
  • impurities are introduced into the graphene film layer by means of N+ ion implantation, thereby obtaining the first buffer layer 22.
  • a sink voltage of 20 kiloelectron volts (keV) clusters of N+ ions at a dose of 8 ⁇ 10 15 /cm 2 are implanted into graphite.
  • the injected sample is rapidly thermally annealed in an ammonia atmosphere, for example, it can be annealed at a temperature of 450 ° C for 50 min, and the vacuum is maintained at 0.1 Pa.
  • the temperature of the annealing furnace is naturally cooled to 200 ° C (cooling rate is 58 ° C / min to 8 ° C / min), the substrate substrate BS can be pulled out into the air.
  • Step 1014a forming a gate insulating layer on a side of the active layer away from the base substrate.
  • a gate insulating film layer is deposited on the surface of the base substrate BS on which the active layer 11 and the first buffer layer 22 are formed. Then, the gate insulating film layer on the surface of the first buffer layer 22 is removed by a photolithography process, thereby obtaining the gate insulating layer 15. For example, referring to FIG. 5F, the gate insulating layer 15 does not cover the surface of the first buffer layer 22.
  • the gate insulating film layer may be an oxide of silicon (SiO x ), a nitride of silicon (SiN x ), an oxide of hafnium (HfO x ), a nitrogen oxide of silicon (SiON), and an oxide of aluminum (AlO).
  • the gate insulating film layer may be a two-layer film composed of silicon oxide (SiO 2 ) having a thickness of 30 nm to 100 nm, and silicon nitride (SiN) having a thickness of 20 nm to 100 nm.
  • the SiO 2 film is on the top layer, and the SiN film is on the bottom layer, that is, the SiO 2 film is formed on the side of the SiN film away from the substrate.
  • Step 1015a forming a second buffer layer, a first semiconductor layer, a light emitting layer, and a second semiconductor layer in this order on a side of the first buffer layer away from the base substrate.
  • a GaN film is deposited on the surface of the first buffer layer as a second buffer layer by a Metal-organic Chemical Vapor Deposition (MOCVD) method, and then a first semiconductor layer is formed in sequence, and then a light is formed.
  • MOCVD Metal-organic Chemical Vapor Deposition
  • the second buffer layer can improve the epitaxial lattice quality of the semiconductor layer to be formed subsequently.
  • the first semiconductor layer may be an N-type semiconductor layer, and the second semiconductor layer may be a P-type semiconductor layer. According to the color of the micro LED, it is possible to select materials such as InGaN, InAlGaP, GaP, GaAsP or AlGaAs.
  • a light emitting layer is formed.
  • the luminescent layer can also be referred to as a quantum well.
  • the substrate in order to remove impurities such as oil stain adhered to the surface of the first buffer layer in the base substrate, the substrate may be washed several times with absolute ethanol, and then the substrate is sequentially placed in acetone. Ultrasonic ethanol and deionized water were respectively ultrasonically cleaned for 10 minutes, then rinsed repeatedly with deionized water, and finally dried with high purity nitrogen (N 2 ).
  • trimethylgallium can be used as the gallium source.
  • the TMGa bubbler is placed in a cold trap to maintain a temperature of -12.6 degrees Celsius, and H 2 is used as a carrier gas, and a purity of 5N (ie, 99.999%) of high purity N 2 is used as a nitrogen source.
  • Low temperature deposition (deposition temperature less than 500 degrees Celsius) is performed on the underlying substrate of the gate insulating layer.
  • the microwave source power is fixed at 650W.
  • the background vacuum is better than 5.0 ⁇ 10 -4 Pa and the deposition time is 30 min.
  • a GaN low temperature buffer layer having a thickness of about 20 nm was deposited in an environment of 300 degrees Celsius under the conditions of a flow rate of TMsc and nitrogen of 0.4 sccm and 80 sccm, respectively, and a deposition time of 5 min.
  • the substrate temperature was raised to 430 ° C, the flow rates of TMGa and nitrogen were also 0.4 sccm and 80 sccm, respectively, and the deposition time was increased to 30 min.
  • the second buffer layer may also be formed using a material such as GaAs or InP.
  • the graphene used to form the first buffer layer has the same crystal structure as a material such as GaAs and GaN, and thus is advantageous for epitaxial growth. Although its lattice constant and thermal expansion coefficient do not match the III-V semiconductor material that needs epitaxial growth, graphene has a low cost and a light transmittance of 90%, which is suitable for the laser heating process.
  • the first semiconductor layer 25, the light emitting layer 23, and the second semiconductor layer 26 may be sequentially formed on the surface of the second buffer layer 27 by an MOCVD process.
  • the base substrate may be heated to a high temperature of about 600 degrees Celsius, and a TMGa and an ammonia (NH 3 ) precursor are simultaneously introduced into the reaction chamber, thereby sequentially forming an N-type GaN semiconductor on the surface of the second buffer layer 27.
  • Layer 25, InGaN or GaN quantum well 23, and P-type GaN semiconductor layer 26 may be sequentially formed on the surface of the second buffer layer 27 by an MOCVD process.
  • the base substrate may be heated to a high temperature of about 600 degrees Celsius, and a TMGa and an ammonia (NH 3 ) precursor are simultaneously introduced into the reaction chamber, thereby sequentially forming an N-type GaN semiconductor on the surface of the second buffer layer 27.
  • Layer 25, InGaN or GaN quantum well 23, and P-type GaN semiconductor layer 26 may be sequentially formed on the surface of the second buffer layer 27 by
  • the first semiconductor layer 25 and the second semiconductor layer 26 may be formed using an in-situ deposition state doping technique.
  • This formation process can be as follows. Add silicon precursors such as silane (SiH 4 ), disilane (Si 2 H 6 ), dimethylsilane (SiCH 8 ) or dichlorodihydrosilane (SiH 2 Cl 2 ) while introducing TMGa and NH 3 into the reaction chamber.
  • the GaN is doped with 10 17 to 10 20 cm -3 of Si (i.e., 10 17 to 10 20 Si atoms are doped per cubic centimeter of GaN), thereby depositing an N-type GaN semiconductor layer 25.
  • an organic precursor of magnesium such as magnesium pentoxide (Cp 2 Mg) is added to the reaction chamber so that Mg of 10 17 to 10 20 cm -3 is doped into the GaN, thereby forming the P-type GaN semiconductor layer 26.
  • an organic precursor of magnesium such as magnesium pentoxide (Cp 2 Mg) is added to the reaction chamber so that Mg of 10 17 to 10 20 cm -3 is doped into the GaN, thereby forming the P-type GaN semiconductor layer 26.
  • a nano-thickness wide band gap material and a narrow band gap semiconductor material may be continuously alternately deposited by an MOCVD process, for example, alternating deposition of a wide band gap material aluminum gallium nitride (AlGaN) And a narrow bandgap material, GaN, to form a variety of single quantum well or multiple quantum well structures.
  • the wide bandgap material in the quantum well material matches the lattice constant of the narrow bandgap material and the band is matched (the band difference of the two materials is kept within a certain range (for example, 1 eV)), so that the emission can be modulated. wavelength.
  • the quantum well structure also has the advantages of high recombination efficiency and low interfacial recombination rate.
  • the thickness of the second buffer layer 27 may be between 0.1 and 5 micrometers
  • the thickness of the first semiconductor layer 25 and the second semiconductor layer 26 may be between 0.1 and 0.5 micrometers
  • the thickness of the quantum well 23 is Between 0.1 and 0.5 microns.
  • Step 1016a forming a gate on a side of the gate insulating layer away from the base substrate.
  • a metal thin film is deposited on the surface of the gate insulating layer, and then the metal thin film can be processed by a patterning process to obtain a gate of the thin film transistor.
  • a metal thin film having a thickness of 200 to 500 nm is deposited on the surface of the base substrate by magnetron sputtering.
  • the metal film may be a film layer formed of one of molybdenum (Mo), molybdenum-niobium alloy (MoNb), Al, aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu), or may be A single or multiple layer composite laminate formed from a plurality of materials of the above materials.
  • a Mo film layer or an Al film layer may be formed on the surface of the base substrate, or a single layer film layer or a multilayer composite film layer composed of an alloy of Mo and Al may be formed.
  • a patterned photoresist mask can be formed on the surface of the substrate by a photolithography process to define the gate region of the thin film transistor.
  • the region of the metal film not covered by the photoresist mask can be etched, and as shown in FIG. 5H, the gate electrode 12 of the thin film transistor can be obtained.
  • Step 1017a forming a passivation layer on a side of the gate from the base substrate.
  • a passivation layer 02 is formed on a side of the gate electrode 12 away from the substrate substrate BS.
  • the passivation layer 02 may be a SiN x layer or may be composed of a SiO x layer and a SiN x layer stack.
  • Step 1018a forming a first contact via penetrating the passivation layer and the gate insulating layer on the base substrate to expose the second pole of the thin film transistor.
  • the passivation layer 02 and the gate insulating layer 15 may be processed in a single photolithography process to form a first contact via 021 in the passivation layer 02 and the gate insulating layer 15.
  • the first contact via 021 may expose a contact region of the second electrode 14 of the thin film transistor 10.
  • the passivation layer formed in the above step 1017a may be overlaid on the surface of the base substrate BS, and the portion of the passivation layer overlying the second semiconductor layer 26 may be simultaneously removed in step 1018a. Thereby, the passivation layer 02 is formed only in the non-display area.
  • Step 1019 a second electrode is formed on a side of the second semiconductor layer away from the substrate, and the second electrode is connected to the second electrode of the thin film transistor through the first contact via.
  • a metal thin film may be deposited on the surface of the passivation layer and the second semiconductor layer, and then the metal thin film is patterned by a photolithography process to form a second electrode of the micro LED.
  • the second electrode can be in contact with the second electrode 14 of the thin film transistor 10 through the first contact via CV1 to achieve connection of the second electrode and the second electrode.
  • FIG. 2A A schematic cross-sectional view of the finally formed array substrate can be referred to FIG. 2A.
  • the metal thin film may be formed of any one of metal materials such as Cu, Al, Mo, Ti, chromium (Cr), or tungsten (W).
  • the metal film may also be a multilayer metal film structure composed of a plurality of metal materials.
  • the metal film may be a three-layer metal film, and the metal material forming the three-layer metal film may be Mo, Al, and Mo, or Ti, Al, and Ti, or Ti, Cu, Ti, or Mo, Cu, and Ti.
  • the first electrode of the micro LED formed in the above step 1011a and the second electrode of the thin film transistor may have a unitary structure. Accordingly, the above step 1018a can be deleted.
  • the second electrode of the micro LED may be formed only on the surface of the second semiconductor layer, and the second electrode is connected to the common electrode line.
  • the method for fabricating the array substrate provided by the embodiment of the present disclosure is described in detail below by taking the thin film transistor of the bottom gate structure shown in FIG. 3A as an example.
  • the method of manufacturing the array substrate includes the following steps.
  • Step 1011b forming a gate of the thin film transistor spaced apart from each other and a first electrode of the micro LED on the base substrate.
  • Step 1012b forming a gate insulating layer on a side of the gate away from the base substrate.
  • the gate insulating layer does not cover the surface of the first electrode.
  • Step 1013b the active layer on the side of the gate insulating layer away from the substrate substrate and the first buffer layer on the side of the first electrode of the micro LED away from the substrate substrate are formed by one patterning process.
  • Step 1014b forming a second buffer layer, a first semiconductor layer, a light emitting layer, and a second semiconductor layer in this order on a side of the first buffer layer away from the substrate.
  • Step 1015b forming first and second poles of the thin film transistor respectively contacting the active layer on a side of the gate insulating layer away from the base substrate.
  • Step 1016b forming a passivation layer on a side of the first and second electrodes of the thin film transistor remote from the substrate.
  • Step 1017b forming a second contact via extending through the passivation layer on the base substrate to expose the second pole of the thin film transistor.
  • Step 1018b forming a second electrode of the micro LED on a side of the second semiconductor layer away from the substrate, and a second electrode of the micro LED is connected to the second electrode of the thin film transistor through the second contact via.
  • the structure of the finally formed array substrate is as shown in FIG. 3A.
  • steps 1011b to 1018b reference may be made to the corresponding steps described above with respect to FIG. 5A, and details are not described herein again.
  • the method for fabricating the array substrate provided by the embodiment of the present disclosure is described in detail below by taking the thin film transistor of the bottom gate structure shown in FIG. 3B as an example.
  • the method of manufacturing the array substrate includes the following steps.
  • Step 1011c forming a gate of the thin film transistor and a first electrode of the micro LED on the substrate.
  • Step 1012c forming a gate insulating layer on a side of the gate away from the substrate.
  • the gate insulating layer does not cover the surface of the first electrode of the micro LED.
  • Step 1013c forming, by a patterning process, the active layer on a side of the gate insulating layer away from the substrate substrate and a first buffer layer on a side of the first electrode of the micro LED away from the substrate.
  • Step 1014c sequentially forming a second buffer layer, a first semiconductor layer, a light emitting layer, and a second semiconductor layer on a side of the first buffer layer away from the substrate.
  • Step 1015c forming a protective layer on a side of the active layer away from the substrate.
  • Step 1016c forming a first via and a second via for exposing the active layer in the protective layer, and a third contact via for exposing the first electrode of the micro LED.
  • Step 1017c forming a first pole and a second pole of the thin film transistor on a side of the protective layer away from the base substrate, wherein a first pole of the thin film transistor is connected to the active layer through the first via, the thin film transistor The second pole is connected to the active layer through the second via, and the second pole of the thin film transistor is further connected to the first electrode through the third contact via.
  • Step 1018c forming a passivation layer on a side of the first and second electrodes of the thin film transistor remote from the substrate.
  • Step 1019c forming a second electrode of the micro LED on a side of the second semiconductor layer away from the substrate.
  • step 1014a may also be performed after step 1015a.
  • FIG. 7 is a schematic block diagram of a display device in accordance with an embodiment of the present disclosure.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device includes a timing controller 710, a scan driver 720, a data driver 730, and a display substrate 750.
  • Timing controller 710 receives the synchronization signals and video signals R, G, and B from the system interface.
  • the synchronization signal includes a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a main clock signal MCLK, and a data enable signal DE.
  • the video signals R, G, and B contain luminance information of each of the plurality of pixels PX.
  • the timing controller 710 generates the first driving control signal CONT1, the second driving control signal CONT2, and the image data according to the video signals R, G, and B, the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, the data enable signal DE, and the main clock signal MCLK.
  • Signal DAT the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, the data enable signal DE, and the main clock signal MCLK.
  • the display substrate 750 includes pixels PX that are substantially arranged in a matrix form.
  • a plurality of substantially parallel scan lines S1 to Sn extend in the row direction
  • a plurality of substantially parallel data lines D1 to Dm extend in the column direction.
  • the scan lines S1 to Sn and the data lines D1 to Dm are coupled to the pixel PX.
  • Display substrate 750 can take the form of any of the array substrate embodiments described above with respect to Figures 1 through 3B.
  • the scan driver 720 is coupled to the scan lines S1-Sn, and generates a corresponding plurality of scan signals S[1] to S[n] according to the first drive control signal CONT1.
  • the scan driver 720 can sequentially apply the scan signals S[1]-S[n] to the scan lines S1-Sn.
  • the data driver 730 is coupled to the data lines D1-Dm, samples and holds the image data signal DAT according to the second driving control signal CONT2, and applies a plurality of data signals D[1] to D[m] to the data lines D1 to Dm, respectively. .
  • the data driver 730 can program the data to the pixel PX by applying the data signals D[1] to D[m] to the data lines D1 to Dm in synchronization with the scan signals S[1] to S[n].

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Abstract

一种阵列基板，包括：衬底基板；薄膜晶体管，设置在所述衬底基板上，所述薄膜晶体管包括：与栅线连接的栅极；有源层；将所述栅极与所述有源层相绝缘的栅绝缘层；与数据线连接的第一极；以及与所述第一极空间相隔的第二极；以及微型发光二极管，设置在所述衬底基板上，所述微型发光二极管包括层叠设置的第一电极、第一缓冲层、发光层和第二电极，所述第一缓冲层与所述有源层同层设置。所述薄膜晶体管的第二极连接到所述微型发光二极管的第一电极和所述微型发光二极管的第二电极之一。

Description

阵列基板、其制造方法、以及显示装置
相关申请的交叉引用
本申请要求2018年3月16日提交的中国专利申请No.201810220601.1的优先权，其全部公开内容通过引用合并于此。
技术领域
本申请涉及显示技术领域，特别涉及一种阵列基板、其制造方法、以及显示装置。
背景技术
微型发光二极管(Micro Light-Emitting Diode，Micro LED)是一种采用无机材料(例如氮化镓)作为发光材料的发光器件，具有例如10μm至15μm范围内的典型尺寸。采用Micro LED作为发光器件的显示装置的具有亮度高、响应速度快以及稳定性高等优点。
在制造Micro LED显示装置时，一般在玻璃基板上形成阵列排布的薄膜晶体管，并在单晶硅基板上形成多个Micro LED；之后对该单晶硅基板进行切割，得到独立的多个Micro LED；最后将各个Micro LED转印至阵列基板上的对应区域。
发明内容
根据本公开的一方面，提供了一种阵列基板，包括：衬底基板；薄膜晶体管，设置在所述衬底基板上，所述薄膜晶体管包括：与栅线连接的栅极；有源层；将所述栅极与所述有源层相绝缘的栅绝缘层；与数据线连接的第一极；以及与所述第一极空间相隔的第二极；以及微型发光二极管，设置在所述衬底基板上，所述微型发光二极管包括层叠设置的第一电极、第一缓冲层、发光层和第二电极，所述第一缓冲层与所述有源层同层设置。所述薄膜晶体管的第二极连接到所述微型发光二极管的第一电极和所述微型发光二极管的第二电极之一。
在一些实施例中，所述微型发光二极管还包括：设置在所述发光层与所述第一缓冲层之间的第一半导体层，以及设置在所述发光层和所述微型发光二极管的第二电极之间的第二半导体层。
在一些实施例中，所述微型发光二极管还包括设置在所述第一半导体层和所述第一缓冲层之间的第二缓冲层，所述第一缓冲层和所述有源层由同种材料制成。
在一些实施例中，所述第一缓冲层的材料包括石墨烯、氧化锌、硫化锌、碳化硅和氮化铝中的至少一种，并且所述第二缓冲层的材料包括氮化镓、砷化镓、铝砷化镓、铝镓氮和磷化铟中的至少一种。
在一些实施例中，所述薄膜晶体管为顶栅结构，其中所述微型发光二极管的第一电极、所述薄膜晶体管的第一极、和所述薄膜晶体管的第二极同层设置，所述薄膜晶体管的第二极通过设置在所述栅绝缘层中的第一接触过孔与所述微型发光二极管的第二电极连接，并且所述微型发光二极管的第一电极被配置成接收公共电极电压。
在一些实施例中，所述薄膜晶体管为顶栅结构，其中所述微型发光二极管的第一电极、所述薄膜晶体管的第一极、和所述薄膜晶体管的第二极同层设置，所述薄膜晶体管的第二极与所述微型发光二极管的第一电极为一体结构，并且所述微型发光二极管的第二电极被配置成接收公共电极电压。
在一些实施例中，所述薄膜晶体管为底栅结构，其中所述微型发光二极管的第一电极与所述栅极同层且空间相隔设置，所述阵列基板还包括设置在所述薄膜晶体管的第一极和第二极远离所述衬底基板的一侧的钝化层。所述薄膜晶体管的第二极通过设置在所述钝化层中的第二接触过孔与所述微型发光二极管的第二电极连接，并且所述微型发光二极管的第一电极被配置成接收公共电极电压。
在一些实施例中，所述薄膜晶体管为底栅结构，其中所述微型发光二极管的第一电极与所述栅极同层且空间相隔设置，所述薄膜晶体管还包括设置在所述有源层远离所述衬底基板的一侧的保护层。所述薄膜晶体管的第一极和第二极设置在所述保护层远离所述衬底基板的一侧，所述薄膜晶体管的第一极通过所述保护层中的第一过孔与所述有源层连接，所述薄膜晶体管的第二极通过所述保护层中的第二过孔与所述有源层连接，所述薄膜晶体管的第二极还通过所述保护层中的第三接触过孔与所述微型发光二极管的第一电极连接，并且所述微型发光二极管的第二电极被配置成接收公共电极电压。
根据本公开的另一方面，提供了一种制造阵列基板的方法，包括： 在衬底基板上形成薄膜晶体管和微型发光二极管，所述薄膜晶体管包括：与栅线连接的栅极；有源层；将所述栅极与所述有源层绝缘的所述栅绝缘层；与数据线连接的第一极；以及与所述第一极空间相隔的第二极，所述微型发光二极管包括层叠设置的第一电极、第一电极、第一缓冲层、发光层和第二电极，其中所述第一缓冲层与所述有源层同层形成；并且将所述薄膜晶体管的第二极连接到所述微型发光二极管的第一电极和所述微型发光二极管的第二电极之一。
在一些实施例中，所述微型发光二极管还包括第一半导体层和第二半导体层。形成微型发光二极管包括在远离所述衬底基板的方向上依次形成所述微型发光二极管的第一电极、所述第一缓冲层、所述第一半导体层、所述发光层、所述第二半导体层以及所述微型发光二极管的第二电极。
在一些实施例中，在形成所述第一半导体层之前，所述方法还包括：在所述第一缓冲层远离所述衬底基板的一侧形成第二缓冲层。所述第一半导体层形成在所述第二缓冲层远离所述衬底基板的一侧，所述第一缓冲层和所述有源层由同种材料形成。
在一些实施例中，所述薄膜晶体管为顶栅结构。所述形成薄膜晶体管和微型发光二极管包括通过一次构图工艺一体地形成所述薄膜晶体管的第二极与所述微型发光二极管的第一电极。
在一些实施例中，所述薄膜晶体管为顶栅结构。在形成所述薄膜晶体管之后，所述方法还包括：形成贯穿所述栅绝缘层的第一接触过孔以将所述薄膜晶体管的第二极露出。所述微型发光二极管的第二电极在所述第一接触过孔形成之后形成，并且通过所述第一接触过孔与所述薄膜晶体管的第二极连接。
在一些实施例中，所述薄膜晶体管为底栅结构。形成所述薄膜晶体管和所述微型发光二极管包括通过一次构图工艺同层形成所述微型发光二极管的第一电极与所述栅极。
在一些实施例中，在形成所述薄膜晶体管之后，所述方法还包括：在所述薄膜晶体管的第一极和第二极远离所述衬底基板的一侧形成钝化层；并且形成贯穿所述钝化层的第二接触过孔以将所述薄膜晶体管的第二极露出。所述微型发光二极管的第二电极在所述接触过孔形成之后形成，并且通过所述第二接触过孔与所述薄膜晶体管的第二极连 接。
在一些实施例中，在形成所述有源层之后，所述方法还包括：在所述有源层远离所述衬底基板的一侧形成保护层；并且通过在所述保护层中形成第一过孔和第二过孔来露出所述有源层并且通过在所述保护层中形成第三接触过孔来露出所述微型发光二极管的第一电极。所述薄膜晶体管的第一极和第二极形成在所述保护层远离所述衬底基板的一侧，所述薄膜晶体管的第一极通过所述第一过孔与所述有源层连接，所述薄膜晶体管的第二极通过所述第二过孔与所述有源层连接且通过所述第三接触过孔与所述微型发光二极管的第一电极连接。
根据本公开的又另一方面，提供了一种显示装置，包括如上所述的阵列基板中的任一个。
附图说明
图1是根据本公开实施例的阵列基板的示意性截面图；
图2A是根据本公开另一实施例的种阵列基板的示意性截面图；
图2B是图2A的阵列基板的变型的示意性截面图；
图2C是图2A的阵列基板的结构的示意性俯视图；
图3A是根据本公开另一实施例的阵列基板的示意性截面图；
图3B是图3A的阵列基板的变型的示意性截面图；
图4是根据本公开实施例的制造阵列基板的方法的流程图；
图5A是根据本公开另一实施例的制造阵列基板的方法的流程图；
图5B是示出通过在衬底基板上形成金属薄膜而得到的结构的示意性截面图；
图5C是示出通过对图5B的金属薄膜进行图形化而得到的薄膜晶体管的第一极、薄膜晶体管的第二极和Micro LED的第一电极的示意性截面图；
图5D是示出通过在图5C的各电极上形成石墨烯层而得到的结构的示意性截面图；
图5E是示出利用图5D的石墨烯层形成有源层和第一缓冲层的示意图；
图5F是示出通过在图5E的有源层上形成栅绝缘层而得到的结构的示意性截面图；
图5G是示出通过在图5F的第一缓冲层上形成第二缓冲层、第一半导体层、发光层以及第二半导体层而得到的结构的示意性截面图；
图5H是示出通过在图5G的栅绝缘层上形成栅极而得到的结构的示意性截面图；
图5I是在示出通过在图5H的栅极和栅绝缘层上形成钝化层并且在钝化层和栅绝缘层中形成第一接触过孔而得到的结构的示意性截面图；
图6A是根据本公开另一实施例的制造阵列基板的方法的流程图；
图6B是根据本公开另一实施例的制造阵列基板的方法的流程图；并且
图7是根据本公开实施例的显示装置的示意性框图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
将理解的是，尽管术语第一、第二、第三等等在本文中可以用来描述各种元件、部件、区、层和/或部分，但是这些元件、部件、区、层和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件、区、层或部分与另一个区、层或部分相区分。因此，下面讨论的第一元件、部件、区、层或部分可以被称为第二元件、部件、区、层或部分而不偏离本公开的教导。
诸如“在...下面”、“在...之下”、“较下”、“在...下方”、“在...之上”、“较上”等等之类的空间相对术语在本文中可以为了便于描述而用来描述如图中所图示的一个元件或特征与另一个(些)元件或特征的关系。将理解的是，这些空间相对术语意图涵盖除了图中描绘的取向之外在使用或操作中的器件的不同取向。例如，如果翻转图中的器件，那么被描述为“在其他元件或特征之下”或“在其他元件或特征下面”或“在其他元件或特征下方”的元件将取向为“在其他元件或特征之上”。因此，示例性术语“在...之下”和“在...下方”可以涵盖在...之上和在...之下的取向两者。诸如“在...之前”或“在...前”和“在...之后”或“接着是”之类的术语可以类似地例如用来指示光穿过元件所依的次序。器件可以取向为其他方式(旋转90 度或以其他取向)并且相应地解释本文中使用的空间相对描述符。另外，还将理解的是，当层被称为“在两个层之间”时，其可以是在该两个层之间的唯一的层，或者也可以存在一个或多个中间层。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述及特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。
将理解的是，当元件或层被称为“在另一个元件或层上”、“连接到另一个元件或层”、“耦合到另一个元件或层”或“邻近另一个元件或层”时，其可以直接在另一个元件或层上、直接连接到另一个元件或层、直接耦合到另一个元件或层或者直接邻近另一个元件或层，或者可以存在中间元件或层。相反，当元件被称为“直接在另一个元件或层上”、“直接连接到另一个元件或层”、“直接耦合到另一个元件或层”、“直接邻近另一个元件或层”时，没有中间元件或层存在。然而，在任何情况下“在...上”或“直接在...上”都不应当被解释为要求一个层完全覆盖下面的层。
本文中参考本公开的理想化实施例的示意性图示(以及中间结构)描述本公开的实施例。正因为如此，应预期例如作为制造技术和/或公差的结果而对于图示形状的变化。因此，本公开的实施例不应当被解释为限于本文中图示的区的特定形状，而应包括例如由于制造导致的形状偏差。因此，图中图示的区本质上是示意性的，并且其形状不意图图示器件的区的实际形状并且不意图限制本公开的范围。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本 文中明确地如此定义。
图1是根据本公开实施例的阵列基板的示意性截面图。该阵列基板可以包括阵列排布的多个像素，尽管为了图示的方便仅示出了单个像素。
参考图1，像素包括设置在衬底基板BS上的薄膜晶体管10和微型LED 20。该薄膜晶体管10用于驱动该微型LED 20发光。薄膜晶体管10包括栅极12、有源层11、将栅极12与有源层11相绝缘的栅绝缘层15、第一极13、以及与第一极13空间相隔的第二极14。如图1中所示，有源层11填充在第一极13和第二极14之间，并且在该示例中还覆盖第一极13的至少一部分和第二极14的至少一部分。该微型LED 20包括彼此层叠设置的第一电极21、第一缓冲层22、发光层23和第二电极24。该第一缓冲层22可以与有源层11同层设置。
该薄膜晶体管10的栅极12与栅线(图1中未示出)连接，该薄膜晶体管10的第一极13与数据线(图1中未示出)连接，并且该薄膜晶体管10的第二极14与该第一电极21或该第二电极24连接。该第一电极21和第二电极24中未与薄膜晶体管10的第二极14连接的一个电极可以作为公共电极接收公共电极电压，并且可以称为阴极，而第一电极21和第二电极24中与薄膜晶体管10的第二极14连接的另一个电极可以称为阳极。
在图1的示例中，该薄膜晶体管10的第二极14与微型LED 20的第二电极24连接，并且该微型LED 20的第一电极21可以与公共电极线(未示出)连接以接收公共电极电压。该薄膜晶体管10的第一极13可以为源极，并且薄膜晶体管10的第二极14可以为漏极。替换地，第一极13可以为漏极，并且第二极14可以为源极。该微型LED 20的第一电极21可以为N型电极，并且微型LED 20的第二电极24可以为P型电极。在一些实施例中，各个像素的微型LED可以共用阳极，即各个像素的微型LED的阳极可以为同一个电极。
该微型LED 20中的发光层23可以由III-V族化合物(包括二元化合物、三元化合物或四元化合物等)材料形成。III-V族化合物是指由元素周期表中III族元素与V族元形成的化合物，该III族元素包括硼(B)、铝(Al)、镓(Ga)和铟(In)等，V族元素包括氮(N)、磷(P)、砷(As)和锑(Sb)等。该III-V族化合物一般包括镓化砷 (GaAs)、磷化铟(InP)和氮化镓(GaN)等。该III-V族化合物材料形成的半导体发光层具有高的发光效率，良好的稳定性和长的寿命。
在操作中，通过该公共电极线施加到阴极电极(在该示例中，第一电极21)的公共电极电压可以与传统显示装置的公共电极电压不同。例如，传统显示装置中的公共电极电压可以是0伏特(V)，或者0V附近，例如-5V至5V之间；而在本公开实施例的阵列基板中，施加到阴极电极的电压可以不局限于上述范围。根据微型LED的工作需求(发光亮度或发光效率)，所施加的阴极电压的范围在-20V至20V之间，通常不为0V。
图2A是根据本公开另一实施例的种阵列基板的示意性截面图。与图1中相同的元件由相同的附图标记指示，并且在此不再详细描述。
参考图2A，该微型LED 20还包括：设置在该发光层23与该第一缓冲层22之间的第一半导体层25，以及设置在该发光层23和该第二电极24之间的第二半导体层26。在该示例中，该第一半导体层25可以为N型半导体层，并且第二半导体层26可以为P型半导体层。该N型半导体层可以由掺杂有IV族元素的III-V族化合物材料制成，例如可以由掺杂有硅(Si)原子的GaN材料制成。该P型半导体层可以由掺杂有II族元素的III-V族化合物材料制成，例如可以由掺杂有镁(Mg)原子的GaN材料制成。
继续参考图2A，该微型LED还包括设置在该第一半导体层25和该第一缓冲层22之间的第二缓冲层27。该第一缓冲层22和该有源层11可以由同种材料制成。该第一缓冲层22中掺杂有离子，例如可以掺杂有磷离子、硼离子或者砷离子。该第二缓冲层27与该第一缓冲层22由不同材料制成，且该第二缓冲层27的材料的晶格常数与该第一缓冲层22的材料的晶格常数的差值小于预设阈值。即该两个缓冲层的材料的晶体结构相同或类似，使得该第一缓冲层22能够有利于第二缓冲层27的外延生长，保证该第二缓冲层27的外延生长质量。
作为示例而非限制，该有源层11和第一缓冲层22可以由石墨烯、氧化锌(ZnO)、硫化锌(ZnS)、碳化硅(SiC)或氮化铝(AlN)或其任意组合制成，并且该第二缓冲层27可以由氮化镓(GaN)、砷化镓(GaAs)、铝砷化镓(AlGaAs)、铝镓氮(AlGaN)或磷化铟(InP)或其任意组合等III-V族化合物材料制成。由于其相对于非晶硅、氧化 物和多晶硅等材料的高达数十倍至数千倍的迁移率，石墨烯能够为薄膜晶体管提供更加稳定的阈值电压，有利于保证阵列基板的使用寿命。
此外，如图2A所示，该薄膜晶体管10为顶栅结构，其中该有源层11设置在第一极13和第二极14远离该衬底基板BS的一侧，栅绝缘层15设置在该有源层11远离该衬底基板BS的一侧，并且该栅极12设置在该栅绝缘层15远离述衬底基板BS的一侧。该微型LED 20的第一电极21、该薄膜晶体管10的第一极13和该薄膜晶体管10的第二极14同层设置。栅绝缘层15中形成有能够将第二极14露出的第一接触过孔CV1，使得该第二极14可以通过该第一接触过孔CV1与该第二电极24连接。在该示例中，由于钝化层02设置在该薄膜晶体管10的第二极14远离衬底基板BS的一侧，所以该第一接触过孔CV1还贯穿该钝化层02。
图2B是图2A的阵列基板的变型的示意性截面图。与图2A中相同的元件由相同的附图标记指示，并且在此不再详细描述。
如图2B所示，该薄膜晶体管10的第二极14与该微型LED 20的第一电极21为通过一次构图工艺形成的一体结构，即该第一结构的与该有源层14接触的部分构成该薄膜晶体管10的第二极14，并且该一体结构的与第一缓冲层22接触的部分构成该微型LED 20的第一电极21。在这种情况下，该微型LED 20的第二电极24可以作为公共电极并且接收公共电极电压。
图2C是图2A的阵列基板的结构的示意性俯视图。参考图2A和图2C，该该第二极14通过第一接触过孔CV1与第二电极24连接。此外，从图2C可以看出，薄膜晶体管10的第一极13与数据线130连接，薄膜晶体管10的栅极12与栅线120连接。
图3A是根据本公开另一实施例的阵列基板的示意性截面图。
如图3A所示，该薄膜晶体管10为底栅结构，其中栅极12设置在衬底基板BS上，栅绝缘层15设置在衬底基板BS上且覆盖栅极12，并且第一极13和第二极14设置在栅绝缘层15远离衬底基板BS的一侧且均与该有源层11接触。该微型LED 20的第一电极21与该薄膜晶体管10的栅极12同层且空间相隔设置。
钝化层02设置在该薄膜晶体管10的第二极14远离衬底基板BS的一侧并且设置有第二接触过孔CV2。该第二极14可以通过第二接触 过孔CV2与该微型LED 20的第二电极24连接。
图3B是根据本公开另一实施例的阵列基板的示意性截面图。与图3A中相同的元件由相同的附图标记指示，并且在此不再详细描述。
如图3B所示，该薄膜晶体管10还包括设置在有源层11远离衬底基板BS的一侧的保护层16，并且薄膜晶体管10的第一极13和第二极14设置在该保护层16远离衬底基板BS的一侧。该第一极13通过第一过孔V1与有源层11连接，第二极14通过第二过孔V2与有源层11连接，且该第二极14还通过第三接触过孔CV3与该第一电极21连接。
为了便于实现薄膜晶体管的第二极14与第一电极21的连接，如图3B所示，该第一电极21的一部分可以凸出于该微型LED 20中的其他各个膜层，使得该第二极14可以与该第一电极21中凸出的部分接触。
在各实施例中，通过将该微型LED 20的第一缓冲层22与薄膜晶体管10的有源层11同层设置，该微型LED 20可以在形成薄膜晶体管10的过程中同步形成，简化了阵列基板的制造工艺，降低了显示装置的制造成本。
图4是根据本公开实施例的制造阵列基板的方法的流程图。该方法可以用于制造图1至图3B所示的阵列基板。
在步骤101处、在衬底基板上形成薄膜晶体管和微型发光二极管(LED)。该微型LED包括彼此层叠设置的第一电极、第一电极、第一缓冲层、发光层和第二电极。该第一缓冲层与该薄膜晶体管的有源层同层形成。在步骤102处，将该薄膜晶体管的第二极与该微型LED的第一电极或第二电极连接。将理解的是，虽然图4中步骤101和102被图示为彼此分离，但是它们可以是一个整体的过程。
通过将该微型LED的缓冲层与薄膜晶体管的有源层同层形成，可以在制造过程中同步形成薄膜晶体管以及微型LED，从而有效简化了阵列基板的制造工艺，降低了显示装置的制造成本。并且相比于常规的转印工艺，本公开实施例提供的制造方法可以具有的较短工艺时间和较高的良率。
上述步骤101中，形成微型LED的过程可以包括在远离该衬底基板的方向上依次形成第一电极、第一缓冲层、第一半导体层、发光层、 第二半导体层以及第二电极。在形成第一半导体层之前，该方法还可以包括：在该第一缓冲层远离该衬底基板的一侧形成第二缓冲层。在这种情况下，该第一半导体层即可形成在该第二缓冲层远离该衬底基板的一侧。如前所述，该第一缓冲层和该有源层由同种材料形成，且该第一缓冲层中掺杂有离子。该第二缓冲层与该第一缓冲层由不同材料形成，且该第二缓冲层的材料的晶格常数与该第一缓冲层的材料的晶格常数的差值小于预设阈值，即形成该两个缓冲层的材料的晶体结构相同或类似。
作为示例而非限制，该第一缓冲层可以由由石墨烯、ZnO、ZnS、SiC或AlN等材料制成，并且该第二缓冲层可以由GaN、GaAs、AlGaAs、AlGaN或InP等材料制成。
下面以图2A所示的顶栅结构的薄膜晶体管为例，详细介绍本公开实施例提供的阵列基板的制造方法。
参考图5A，该方法可以包括以下步骤。
步骤1011a、在衬底基板上形成薄膜晶体管的第一极和第二极，以及微型LED的第一电极。该衬底基板可以为玻璃基板。该薄膜晶体管的第一极、第二极和该微型LED的第一电极空间相隔设置。该微型LED的第一电极位于阵列基板的有效显示区域，并且该薄膜晶体管的第一极和第二极则位于阵列基板的非像素区域(即非显示区域)。
在实施例中，如图5B所示，可以先在玻璃基板BS上通过磁控溅射的方式沉积一层厚度为200纳米(nm)至500nm的金属薄膜200。形成该金属薄膜200的材料可以为铜(Cu)或者铜合金。可以采用直流磁控溅射或者交流磁控溅射的方式进行镀膜。在开始溅射镀膜前，先在纯度为99.99％的Ar气产生的等离子体中清洗靶材2分钟(min)。在环境温度下，当工作气压为2.7帕(Pa)、Ar气的流量为标准状况下36毫升每分钟(mL/min)时，将溅射功率调整为100瓦特(W)以制备该金属薄膜，例如铜薄膜。该铜薄膜的织构随溅射气压P和镀距D的增加先升高而后下降。在溅射气压为0.5Pa、镀距为200毫米(mm)时，溅射得到的铜薄膜具有最强的织构，且晶粒细小，薄膜致密度和平整度高。
替换地，可以使用电镀工艺形成金属薄膜200。例如，在形成铜薄膜时所采用的电镀铜溶液可以包括：铜盐：120克每升(g/L)至300g/L； 酸：10g/L至200g/L；氯离子：30g/L至80mg/L；含硫化合物：0.001g/L至0.3g/L；聚氧醚类化合物：0.5g/L至10g/L；聚乙二醇：0.05g/L至5g/L；季铵盐：0.001g/L至0.2g/L。电镀方法的工艺参数可以为：镀液温度为10摄氏度(℃)至50℃，电流密度为0.2安培每平方分米(A/dm 2)至20A/dm 2。
进一步的，可以采用一次光刻工艺在该金属薄膜200的表面形成图形化的光刻胶掩膜，并对未被该光刻胶掩膜覆盖的金属薄膜200进行刻蚀，从而得到空间相隔的薄膜晶体管的第一极13、薄膜晶体管的第二极14以及微型LED的第一电极21。例如，可以采用氯化铁(FeCl3)腐蚀液在50℃的温度下对金属薄膜200进行刻蚀。步骤1011a结束之后所形成的阵列基板的示意性截面图可以参考图5C。
步骤1012a、在衬底基板上形成空间相隔的有源层和第一缓冲层，该有源层与该薄膜晶体管的第一极和第二极接触。有源层位于薄膜晶体管的有源区，且与该第一极和该第二极接触。该第一缓冲层位于像素区域，且覆盖在该微型LED的第一电极远离衬底基板的一侧。形成该有源层和第一缓冲层的材料可以为石墨烯、ZnO、ZnS、SiC或AlN等，且该第一缓冲层中还掺杂有离子，例如可以掺杂有N+离子，诸如磷离子、硼离子或者砷离子。
下面以该金属薄膜为铜薄膜，并且形成该有源层和第一缓冲层的材料为石墨烯为例，介绍该有源层和第一缓冲层的制造工艺。
首先，先将形成有第一极、第二极和第一电极的衬底基板在丙酮和去离子水中分别超声清洗15min，以除去铜薄膜表面的油污等污染物。
然后即可将衬底基板置于反应室中的恒温区进行石墨烯生长。该石墨烯的生长过程如下。第一步，将反应室内抽至真空后填充氧气。该操作重复三次左右，使反应室内空气被排出，反应室内为氧气氛围填充。第二步，在流量为300标准毫升/分钟(sccm)的氧气气氛中，将反应室的温度升温直至500℃，然后再保持恒温20mim，以高温退火处理还原铜薄膜表面的氧化物；随后即可将反应室的温度调至生长所需的温度，氧气的流量也调至生长所需的流量，并同时通入80sccm的氩气，继续保持恒温20min。第三步，保持其它气体的流量不变，并通入7sccm的甲烷，石墨稀开始生长。甲烷的通入时间为15min。第四步， 停止通入甲烷，同时将反应室的温度以10℃/min的降温速率开始冷却，直至室温。在该降温的过程中，氩气流量保持不变，氧气流量调小30sccm，避免氧气流量过大对合成的石墨烯薄膜的刻烛作用。在该石墨烯的生成过程中，铜薄膜可以做为石墨烯生长的催化剂。
石墨烯生长完成后，如图5D所示，该衬底基板BS的表面即可整层覆盖一层石墨烯100。接下来，可以采用一次光刻工艺在该石墨烯100的表面形成图形化的光刻胶掩膜，该光刻胶掩膜可以覆盖位于有源区的石墨烯，以及位于像素区的石墨烯。之后可以采用刻蚀工艺去除该石墨烯中未被光刻胶掩膜覆盖的部分，进而得到该有源层，以及位于像素区域的石墨烯膜层。该刻蚀工艺可以为氢等离子体的干法刻蚀工艺，其中控制氢气流量为50sccm，衬底温度为300℃，等离子体功率为100W，刻蚀速率为5nm/min以内。
最后，参考图5E，采用N+离子注入的方式在该石墨烯膜层中引入杂质，从而得到该第一缓冲层22。例如，在20千电子伏特(keV)的吸极电压下，将剂量为8×10 15/cm 2的团簇N+离子注入石墨稀。之后，注入的样品在氨气氛围下快速热退火，例如可以在450℃的温度下退火50min，真空度维持在0.1Pa。当退火炉的温度自然冷却至200℃(冷却速率为58℃/min至8℃/min)时，即可将衬底基板BS拉出到空气中。
步骤1014a、在该有源层远离该衬底基板的一侧形成栅绝缘层。在形成有该有源层11和第一缓冲层22的衬底基板BS的表面沉积一层栅绝缘薄膜层。然后通过光刻工艺去除位于第一缓冲层22表面的栅绝缘薄膜层，从而得到该栅绝缘层15。示例的，参考图5F，该栅绝缘层15未覆盖在第一缓冲层22的表面。
该栅绝缘薄膜层可以是由硅的氧化物(SiO x)、硅的氮化物(SiN x)、铪的氧化物(HfO x)、硅的氮氧化物(SiON)和铝的氧化物(AlO x)等中的任一种材料形成的单层膜，或者是由上述材料中的多种材料形成的多层复合膜。例如，在实施例中，该栅绝缘膜层可以是由厚度为30nm至100nm的二氧化硅(SiO 2)，以及厚度为20nm至100nm的氮化硅(SiN)组成的双层薄膜。SiO 2薄膜位于顶层，SiN薄膜位于底层，即该SiO 2薄膜形成在SiN薄膜远离衬底基板的一侧。
步骤1015a、在该第一缓冲层远离该衬底基板的一侧依次形成第二缓冲层、第一半导体层、发光层以及第二半导体层。
在实施例中，采用金属有机化学气相沉积(Metal-organic Chemical Vapor Deposition，MOCVD)法在第一缓冲层的表面沉积一层GaN薄膜作为第二缓冲层，然后再依次形成第一半导体层、发光层以及第二半导体层。该第二缓冲层可以提高后续待形成的半导体层的外延晶格质量。该第一半导体层可以为N型半导体层，该第二半导体层可以为P型半导体层。根据微型LED的发光颜色，可以选择氮化铟镓(InGaN)、磷化铝铟镓(InAlGaP)、磷化镓(GaP)、磷化砷镓(GaAsP)或砷化铝镓(AlGaAs)等材料形成发光层。该发光层也可以称为量子阱。在实施例中，为了去除衬底基板中第一缓冲层表面粘附的油污等杂质，可以先采用无水乙醇对该衬底基板进行多次冲洗，然后再将该衬底基板依次放入丙酮、无水乙醇和去离子水中分别用超声波清洗10分钟，之后再用去离子水反复冲洗干净，最后用高纯氮气(N 2)吹干。
在采用MOCVD沉积第二缓冲层时，可以采用三甲基镓(TMGa)作为镓源。将TMGa的鼓泡器放置在冷阱中，使其温度维持在-12.6摄氏度，并以H 2作为载气，以纯度为5N(即99.999％)的高纯N 2为氮源，在形成有栅绝缘层的衬底基板上进行低温沉积(沉积温度小于500摄氏度)。微波源功率固定在650W，GaN薄膜的沉积过程中，本底真空度优于5.0×10 -4Pa，沉积时间为30min。在300摄氏度的环境中沉积厚度约为20nm的GaN低温缓冲层，沉积条件为TMGa和氮气的流量分别为0.4sccm和80sccm，沉积时间为5min。GaN薄膜的沉积过程中，将衬底温度升高到430摄氏度，TMGa与氮气的流量也分别为0.4sccm和80sccm，沉积时间增加到30min。
在一些实施例中，代替采用GaN形成第二缓冲层，还可以采用GaAs或InP等材料形成该第二缓冲层。用于形成第一缓冲层的石墨烯与GaAs和GaN等材料的晶体结构相同，并且因此有利于外延生长。虽然其晶格常数和热膨胀系数不匹配于需要外延生长的III-V半导体材料，但是石墨烯成本较低，透光率可达90％，适合于激光加热工艺。
进一步地，参考图5G，可以采用MOCVD工艺在该第二缓冲层27的表面依次形成第一半导体层25、发光层23以及第二半导体层26。具体地，可以先将衬底基板加热至600摄氏度左右的高温，并向反应室同时引入TMGa和氨(NH 3)前驱物，从而在该第二缓冲层27的表面依次形成N型的GaN半导体层25、InGaN或GaN量子阱23以及P 型GaN半导体层26。
在一些实施例中，可以使用原位的沉积态掺杂技术形成该第一半导体层25以及第二半导体层26。该形成过程可以如下。在反应室通入TMGa和NH 3的同时加入硅烷(SiH 4)、乙硅烷(Si 2H 6)、二甲基硅烷(SiCH 8)或二氯二氢硅(SiH 2Cl 2)等硅前驱物，使得该GaN中掺入10 17至10 20cm -3的Si(即在每立方厘米的GaN中掺入10 17至10 20个Si原子)，从而沉积形成N型GaN半导体层25。之后在反应室加入镁的有机先驱物例如二茂镁(Cp 2Mg)，使得GaN中掺入10 17至10 20cm -3的Mg，从而形成P型GaN半导体层26。在形成该N型半导体层25和P型半导体层26之间，可以通过MOCVD工艺连续交替沉积纳米厚度的宽禁带材料和窄禁带半导体材料，例如交替沉积宽禁带材料铝镓氮(AlGaN)和窄禁带材料GaN，从而形成多种单量子阱或多量子阱结构。该量子阱材料中的宽禁带材料与窄禁带材料的晶格常数相匹配，且能带相匹配(两种材料的能带差异保持在一定范围(例如1eV)以内)，从而能够调制发射波长。量子阱结构也具有复合效率高和界面复合率低的优点。
在实施例中，该第二缓冲层27的厚度可以在0.1至5微米之间，第一半导体层25和第二半导体层26的厚度可以在0.1至0.5微米之间，量子阱23的厚度在0.1至0.5微米之间。在形成该第二缓冲层、第一半导体层、发光层以及第二半导体层时，可以先在衬底基板的表面形成整层覆盖的第二缓冲层、第一半导体层、发光层以及第二半导体层，然后再通过一次光刻工艺，将上述膜层中位于非显示区域的部分去除，仅保留位于像素区域的部分膜层。
步骤1016a、在该栅绝缘层远离该衬底基板的一侧形成栅极。在该栅绝缘层的表面沉积一层金属薄膜，然后可以通过一次构图工艺对该金属薄膜进行处理，从而得到该薄膜晶体管的栅极。
在实施例中，采用磁控溅射的方式在衬底基板的表面沉积一层厚度为200至500nm的金属薄膜。该金属薄膜可以是由钼(Mo)、钼铌合金(MoNb)、Al、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种材料形成的膜层，或者可以是由上述材料中的多种材料形成的单层或多层复合叠层。例如，可以在衬底基板表面形成Mo膜层或Al膜层，或者，形成含有Mo和Al的合金组成的单层膜层或多层复合膜层。之 后，可以采用一次光刻工艺在衬底基板的表面形成图形化的光刻胶掩膜，定义出薄膜晶体管的栅极区域。最后可以对该金属薄膜上未被光刻胶掩膜覆盖的区域进行刻蚀，则如图5H所示，可以得到薄膜晶体管的栅极12。
步骤1017a、在该栅极离该衬底基板的一侧形成钝化层。如图5I所示，在该栅极12远离衬底基板BS的一侧形成钝化层02。该钝化层02可以为SiN x层，或者可以由SiO x层与SiN x层堆叠组成。
步骤1018a、在该衬底基板上形成贯穿该钝化层和该栅绝缘层的第一接触过孔，以将该薄膜晶体管的第二极露出。继续参考图5I，可以采用一次光刻工艺对该钝化层02和栅绝缘层15进行处理，以在该钝化层02和栅绝缘层15中形成第一接触过孔021。该第一接触过孔021可以将薄膜晶体管10的第二极14的接触区露出。
将理解的是，上述步骤1017a中形成的钝化层可以整层覆盖在衬底基板BS的表面，并且在步骤1018a中可以同步将该钝化层中覆盖在第二半导体层26上方的部分去除，从而使得该钝化层02仅形成在非显示区域。
步骤1019a、在该第二半导体层远离衬底基板的一侧形成第二电极，该第二电极通过该第一接触过孔与该薄膜晶体管的第二极连接。可以先在该钝化层以及第二半导体层的表面沉积金属薄膜，然后采用一道光刻工艺对该金属薄膜进行图形化处理，形成微型LED的第二电极。该第二电极可以通过该第一接触过孔CV1与薄膜晶体管10的第二极14接触，从而实现第二电极与第二极的连接。最终形成的阵列基板的示意性截面图可以参考图2A。
上述步骤中，金属薄膜可以由Cu、Al、Mo、Ti、铬(Cr)或钨(W)等金属材料中的任一种金属材料形成。替换地该金属薄膜也可以是由多种金属材料组成的多层金属薄膜结构。例如，该金属薄膜可以为三层金属薄膜，形成该三层金属薄膜的金属材料可以为Mo、Al和Mo，或者Ti、Al和Ti，或者Ti、Cu、Ti，或者Mo、Cu和Ti。
在替换实施例中，上述步骤1011a中形成的微型LED的第一电极与该薄膜晶体管的第二极可以为一体结构。相应地，上述步骤1018a可以删除。上述步骤1019a中，微型LED的第二电极可以仅形成在第二半导体层的表面，且该第二电极与公共电极线连接。
下面以图3A所示的底栅结构的薄膜晶体管为例，详细介绍本公开实施例提供的阵列基板的制造方法。
参考图6A，该阵列基板的制造方法包括以下步骤。
步骤1011b、在衬底基板上形成空间相隔的薄膜晶体管的栅极以及微型LED的第一电极。
步骤1012b、在栅极远离该衬底基板的一侧形成栅绝缘层。该栅绝缘层未覆盖在第一电极的表面。
步骤1013b、通过一次构图工艺，形成在栅绝缘层远离该衬底基板的一侧的该有源层和在该微型LED的第一电极远离衬底基板的一侧的第一缓冲层。
步骤1014b、在该第一缓冲层远离衬底基板的一侧依次形成第二缓冲层、第一半导体层、发光层和第二半导体层。
步骤1015b、在栅绝缘层远离该衬底基板的一侧形成分别与该有源层接触的薄膜晶体管的第一极和第二极。
步骤1016b、在该薄膜晶体管的第一极和第二极远离该衬底基板的一侧形成钝化层。
步骤1017b、在该衬底基板上形成贯穿该钝化层的第二接触过孔，以将该薄膜晶体管的第二极露出。
步骤1018b、在该第二半导体层远离衬底基板的一侧形成该微型LED的第二电极，该微型LED的第二电极通过该第二接触过孔与该薄膜晶体管的第二极连接。
该最终形成的阵列基板的结构如图3A所示。上述步骤1011b至步骤1018b的具体实现过程可以参考上面关于图5A所描述的对应步骤，此处不再赘述。
下面以图3B所示的底栅结构的薄膜晶体管为例，详细介绍本公开实施例提供的阵列基板的制造方法。
参考图6B，该阵列基板的制造方法包括以下步骤。
步骤1011c、在衬底基板上间隔形成薄膜晶体管的栅极以及微型LED的第一电极。
步骤1012c、在栅极远离该衬底基板的一侧形成栅绝缘层。该栅绝缘层未覆盖在微型LED的第一电极的表面。
步骤1013c、通过一次构图工艺，形成在栅绝缘层远离该衬底基板 的一侧的该有源层和在该微型LED的第一电极远离衬底基板的一侧的第一缓冲层。
步骤1014c、在该第一缓冲层远离衬底基板的一侧依次形成第二缓冲层、第一半导体层、发光层和第二半导体层。
步骤1015c、在有源层远离衬底基板的一侧形成保护层。
步骤1016c、在该保护层中形成用于露出该有源层的第一过孔和第二过孔，以及用于露出该微型LED的第一电极的第三接触过孔。
步骤1017c、在该保护层远离该衬底基板的一侧形成薄膜晶体管的第一极和第二极，该薄膜晶体管的第一极通过该第一过孔与该有源层连接，该薄膜晶体管的第二极通过该第二过孔与该有源层连接，且该薄膜晶体管的第二极还通过该第三接触过孔与该第一电极连接。
步骤1018c、在该薄膜晶体管的第一极和第二极远离该衬底基板的一侧形成钝化层。
步骤1019c、在该第二半导体层远离衬底基板的一侧形成该微型LED的第二电极。
上述步骤1011c至步骤1019c的具体实现过程可以参考上面关于图5A所描述的对应步骤，此处不再赘述。
在各实施例中，通过将该微型LED的缓冲层与薄膜晶体管的有源层同层形成，可以在制造过程中同步形成薄膜晶体管以及微型LED，从而有效简化了阵列基板的制造工艺，降低了显示装置的制造成本。将理解的是，在各实施例中，步骤可以以不同于所描述的那样执行，并且步骤中的一些甚至也可以酌情省略。例如步骤1014a也可以在步骤1015a之后执行。
图7是根据本公开实施例的显示装置的示意性框图。该显示装置可以为：液晶面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
参照图7，显示装置包括时序控制器710、扫描驱动器720、数据驱动器730和显示基板750。
时序控制器710从系统接口接收同步信号和视频信号R、G和B。同步信号包括水平同步信号Hsync、垂直同步信号Vsync、主时钟信号MCLK以及数据使能信号DE。视频信号R、G和B包含多个像素PX中每个的亮度信息。时序控制器710根据视频信号R、G和B、水平同 步信号Hsync、垂直同步信号Vsync、数据使能信号DE以及主时钟信号MCLK生成第一驱动控制信号CONT1、第二驱动控制信号CONT2和图像数据信号DAT。
显示基板750包括有基本以矩阵形式排列的像素PX。在显示基板750中，多个基本平行的扫描线S1至Sn沿着行方向延伸，并且多个基本平行的数据线D1至Dm沿着列方向延伸。扫描线S1至Sn和数据线D1至Dm被耦合到像素PX。显示基板750可以采取上面关于图1至图3B描述的阵列基板实施例中的任一个的形式。
扫描驱动器720被耦合到扫描线S1-Sn，并且根据第一驱动控制信号CONT1生成对应的多个扫描信号S[1]至S[n]。扫描驱动器720可以将扫描信号S[1]-S[n]依次施加到扫描线S1-Sn。
数据驱动器730被耦合到数据线D1-Dm，根据第二驱动控制信号CONT2采样和保持图像数据信号DAT，并且分别将多个数据信号D[1]至D[m]施加到数据线D1至Dm。通过与扫描信号S[1]至S[n]同步地将数据信号D[1]至D[m]施加到数据线D1至Dm，数据驱动器730可以将数据编程到像素PX。
以上所述仅为本申请的特定实施例，并不用以限制本申请。本领域普通技术人可以对所描述的实施例作出修改、等同替换或改进而不脱离本申请的范围。

Claims (17)

  1. 一种阵列基板，包括：
    衬底基板；
    薄膜晶体管，设置在所述衬底基板上，所述薄膜晶体管包括：与栅线连接的栅极；有源层；将所述栅极与所述有源层相绝缘的栅绝缘层；与数据线连接的第一极；以及与所述第一极空间相隔的第二极；以及
    微型发光二极管，设置在所述衬底基板上，所述微型发光二极管包括层叠设置的第一电极、第一缓冲层、发光层和第二电极，所述第一缓冲层与所述有源层同层设置，
    其中所述薄膜晶体管的第二极连接到所述微型发光二极管的第一电极和所述微型发光二极管的第二电极之一。
  2. 根据权利要求1所述的阵列基板，其中所述微型发光二极管还包括：设置在所述发光层与所述第一缓冲层之间的第一半导体层，以及设置在所述发光层和所述微型发光二极管的第二电极之间的第二半导体层。
  3. 根据权利要求2所述的阵列基板，其中所述微型发光二极管还包括设置在所述第一半导体层和所述第一缓冲层之间的第二缓冲层，其中所述第一缓冲层和所述有源层由同种材料制成。
  4. 根据权利要求3所述的阵列基板，其中所述第一缓冲层的材料包括石墨烯、氧化锌、硫化锌、碳化硅和氮化铝中的至少一种，并且其中所述第二缓冲层的材料包括氮化镓、砷化镓、铝砷化镓、铝镓氮和磷化铟中的至少一种。
  5. 根据权利要求1至4中任一项所述的阵列基板，其中所述薄膜晶体管为顶栅结构，其中所述微型发光二极管的第一电极、所述薄膜晶体管的第一极、和所述薄膜晶体管的第二极同层设置，其中所述薄膜晶体管的第二极通过设置在所述栅绝缘层中的第一接触过孔与所述微型发光二极管的第二电极连接，并且其中所述微型发光二极管的第一电极被配置成接收公共电极电压。
  6. 根据权利要求1至4中任一项所述的阵列基板，其中所述薄膜晶体管为顶栅结构，其中所述微型发光二极管的第一电极、所述薄膜 晶体管的第一极、和所述薄膜晶体管的第二极同层设置，其中所述薄膜晶体管的第二极与所述微型发光二极管的第一电极为一体结构，并且其中所述微型发光二极管的第二电极被配置成接收公共电极电压。
  7. 根据权利要求1至4中任一项所述的阵列基板，其中所述薄膜晶体管为底栅结构，其中所述微型发光二极管的第一电极与所述栅极同层且空间相隔设置，其中所述阵列基板还包括设置在所述薄膜晶体管的第一极和第二极远离所述衬底基板的一侧的钝化层，其中：
    所述薄膜晶体管的第二极通过设置在所述钝化层中的第二接触过孔与所述微型发光二极管的第二电极连接，并且
    所述微型发光二极管的第一电极被配置成接收公共电极电压。
  8. 根据权利要求1至4中任一项所述的阵列基板，其中所述薄膜晶体管为底栅结构，其中所述微型发光二极管的第一电极与所述栅极同层且空间相隔设置，其中所述薄膜晶体管还包括设置在所述有源层远离所述衬底基板的一侧的保护层，其中：
    所述薄膜晶体管的第一极和第二极设置在所述保护层远离所述衬底基板的一侧，
    所述薄膜晶体管的第一极通过所述保护层中的第一过孔与所述有源层连接，
    所述薄膜晶体管的第二极通过所述保护层中的第二过孔与所述有源层连接，
    所述薄膜晶体管的第二极还通过所述保护层中的第三接触过孔与所述微型发光二极管的第一电极连接，并且
    所述微型发光二极管的第二电极被配置成接收公共电极电压。
  9. 一种制造阵列基板的方法，包括：
    在衬底基板上形成薄膜晶体管和微型发光二极管，所述薄膜晶体管包括：与栅线连接的栅极；有源层；将所述栅极与所述有源层绝缘的所述栅绝缘层；与数据线连接的第一极；以及与所述第一极空间相隔的第二极，所述微型发光二极管包括层叠设置的第一电极、第一缓冲层、发光层和第二电极，其中所述第一缓冲层与所述有源层同层形成；并且
    将所述薄膜晶体管的第二极连接到所述微型发光二极管的第一电极和所述微型发光二极管的第二电极之一。
  10. 根据权利要求9所述的方法，其中所述微型发光二极管还包括第一半导体层和第二半导体层，并且其中形成微型发光二极管包括：在远离所述衬底基板的方向上依次形成所述微型发光二极管的第一电极、所述第一缓冲层、所述第一半导体层、所述发光层、所述第二半导体层以及所述微型发光二极管的第二电极。
  11. 根据权利要求10所述的方法，其中在形成所述第一半导体层之前，所述方法还包括：
    在所述第一缓冲层远离所述衬底基板的一侧形成第二缓冲层，
    其中所述第一半导体层形成在所述第二缓冲层远离所述衬底基板的一侧，并且
    其中所述第一缓冲层和所述有源层由同种材料形成。
  12. 根据权利要求9至11中任一项所述的方法，其中所述薄膜晶体管为顶栅结构，并且其中所述形成薄膜晶体管和微型发光二极管包括通过一次构图工艺一体地形成所述薄膜晶体管的第二极与所述微型发光二极管的第一电极。
  13. 根据权利要求9至11中任一项所述的方法，其中所述薄膜晶体管为顶栅结构，并且其中在形成所述薄膜晶体管之后，所述方法还包括：
    形成贯穿所述栅绝缘层的第一接触过孔以将所述薄膜晶体管的第二极露出，
    其中所述微型发光二极管的第二电极在所述第一接触过孔形成之后形成，并且通过所述第一接触过孔与所述薄膜晶体管的第二极连接。
  14. 根据权利要求9至11中任一项所述的方法，其中所述薄膜晶体管为底栅结构，并且其中形成所述薄膜晶体管和所述微型发光二极管包括通过一次构图工艺同层形成所述微型发光二极管的第一电极与所述栅极。
  15. 根据权利要求14所述的方法，其中在形成所述薄膜晶体管之后，所述方法还包括：
    在所述薄膜晶体管的第一极和第二极远离所述衬底基板的一侧形成钝化层；并且
    形成贯穿所述钝化层的第二接触过孔以将所述薄膜晶体管的第二极露出，
    其中所述微型发光二极管的第二电极在所述接触过孔形成之后形成，并且通过所述第二接触过孔与所述薄膜晶体管的第二极连接。
  16. 根据权利要求14所述的方法，其中在形成所述有源层之后，所述方法还包括：
    在所述有源层远离所述衬底基板的一侧形成保护层；并且
    通过在所述保护层中形成第一过孔和第二过孔来露出所述有源层并且通过在所述保护层中形成第三接触过孔来露出所述微型发光二极管的第一电极，
    其中所述薄膜晶体管的第一极和第二极形成在所述保护层远离所述衬底基板的一侧，所述薄膜晶体管的第一极通过所述第一过孔与所述有源层连接，所述薄膜晶体管的第二极通过所述第二过孔与所述有源层连接且通过所述第三接触过孔与所述微型发光二极管的第一电极连接。
  17. 一种显示装置，包括如权利要求1至8任一所述的阵列基板。
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