WO2019174290A1 - 阵列基板、其制造方法、以及显示装置 - Google Patents

阵列基板、其制造方法、以及显示装置 Download PDF

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Publication number
WO2019174290A1
WO2019174290A1 PCT/CN2018/115793 CN2018115793W WO2019174290A1 WO 2019174290 A1 WO2019174290 A1 WO 2019174290A1 CN 2018115793 W CN2018115793 W CN 2018115793W WO 2019174290 A1 WO2019174290 A1 WO 2019174290A1
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Prior art keywords
electrode
light emitting
thin film
film transistor
layer
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PCT/CN2018/115793
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English (en)
French (fr)
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龙春平
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京东方科技集团股份有限公司
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Priority to US16/461,419 priority Critical patent/US11139339B2/en
Publication of WO2019174290A1 publication Critical patent/WO2019174290A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • the present application relates to the field of display technologies, and in particular, to an array substrate, a method of manufacturing the same, and a display device.
  • a Micro Light-Emitting Diode is a light-emitting device using an inorganic material such as gallium nitride as a light-emitting material, and has a typical size in the range of, for example, 10 ⁇ m to 15 ⁇ m.
  • the display device using the Micro LED as a light-emitting device has the advantages of high brightness, fast response, and high stability.
  • an array-arranged thin film transistor is generally formed on a glass substrate, and a plurality of micro LEDs are formed on a single single crystal silicon substrate; then the single crystal silicon substrate is cut to obtain an independent multi-layer Micro LEDs; finally, each Micro LED is transferred to a corresponding area on the array substrate.
  • an array substrate including: a substrate substrate; a thin film transistor disposed on the substrate, the thin film transistor including: a gate connected to the gate line; an active layer; a gate insulating layer insulating the gate from the active layer; a first pole connected to the data line; and a second pole spaced apart from the first pole space; a micro light emitting diode disposed at the gate
  • the insulating layer is away from the side of the substrate, the micro light emitting diode comprises a first electrode, a light emitting layer and a second electrode; and a common electrode.
  • the second pole of the thin film transistor is connected to one of the first electrode and the second electrode of the micro light emitting diode.
  • the other of the first electrode and the second electrode of the micro light emitting diode is connected to a common electrode.
  • the micro light emitting diode further includes: a first semiconductor layer disposed on a side of the light emitting layer adjacent to the substrate substrate, and disposed between the light emitting layer and the second electrode a second semiconductor layer, the first semiconductor layer being in contact with the first electrode of the micro light emitting diode.
  • the micro light emitting diode further includes a buffer layer disposed between the first semiconductor layer and the gate insulating layer, and the buffer layer and the first electrode of the micro light emitting diode All are located on a side of the gate insulating layer away from the substrate.
  • the gate insulating layer is made of a metal oxide material including aluminum oxide, iron oxide, chromium oxide, titanium oxide, vanadium oxide, and titanate. Iron, magnesium titanate, cerium oxide, antimony trioxide, gallium oxide, antimony oxide, antimony oxide, antimony trioxide, antimony trioxide, antimony oxide, antimony trioxide, antimony oxide, antimony oxide, antimony oxide, antimony oxide At least one selected from the group consisting of antimony trioxide.
  • the thin film transistor is a structure selected from the group consisting of a top gate structure and a bottom gate structure, wherein the gate and the micro light emitting diode are in the top gate structure
  • An electrode is disposed in the same layer and spaced apart from each other, wherein the second electrode of the thin film transistor forms an integral structure with the first electrode of the micro light emitting diode or with the micro light emitting diode The second electrode is connected.
  • the thin film transistor is a top gate structure.
  • the array substrate further includes an interlayer dielectric layer disposed on a side of the gate away from the substrate.
  • the gate insulating layer is disposed on a side of the gate adjacent to the substrate;
  • the active layer is disposed on a side of the gate insulating layer adjacent to the substrate; and the thin film transistor
  • One and a second pole are disposed on a side of the interlayer dielectric layer away from the base substrate, and the first pole of the thin film transistor passes through a first via disposed in the interlayer dielectric layer Connected to the active layer, the second pole of the thin film transistor is connected to the active layer through a second via provided in the interlayer dielectric layer.
  • the second pole of the thin film transistor is connected to the first electrode of the micro light emitting diode through a first contact via disposed in the interlayer dielectric layer, and The second electrode of the miniature light emitting diode is connected to the common electrode.
  • the second electrode of the thin film transistor is in contact with the second electrode of the micro light emitting diode, and the first electrode of the micro light emitting diode is connected to the common electrode.
  • the thin film transistor is a bottom gate structure in which the second electrode of the thin film transistor and the first electrode of the micro light emitting diode form the integrated structure.
  • One end of the unitary structure is in contact with the active layer to form the second pole of the thin film transistor, and the other end of the unitary structure constitutes the first electrode of the micro light emitting diode.
  • the thin film transistor is a bottom gate structure in which the second electrode of the thin film transistor and the first electrode of the micro light emitting diode form the integral structure.
  • the array substrate further includes a protective layer disposed on a side of the active layer away from the base substrate, and wherein the first pole of the thin film transistor and the integral structure are disposed away from the protective layer One side of the base substrate.
  • the first pole of the thin film transistor is connected to the active layer through a third via provided in the protective layer; one end of the unitary structure passes through a fourth via provided in the protective layer Connecting to the active layer to form the second pole of the thin film transistor; and the other end of the unitary structure constitutes the first electrode of the micro light emitting diode.
  • the common electrode is disposed in the same layer as the first electrode of the micro light emitting diode.
  • the second electrode of the thin film transistor is connected to the first electrode of the micro light emitting diode
  • the first electrode and the common electrode of the micro light emitting diode are spatially spaced apart from each other.
  • the second electrode of the micro light emitting diode is in contact with the connection electrode, and the connection electrode is connected to the common electrode through a third contact via.
  • the first electrode of the micro light emitting diode and the common electrode form a unitary structure.
  • the common electrode is disposed on a side of the second electrode of the micro light emitting diode away from the base substrate, and the array substrate further includes a common electrode disposed on the common electrode An insulating layer between the two electrodes.
  • the common electrode passes through a fourth contact via provided in the insulating layer and the micro The second electrode of the light emitting diode is connected.
  • the common electrode passes through a fifth contact via penetrating the insulating layer and the micro light emitting diode The first electrode is connected.
  • a method of fabricating an array substrate comprising: forming a thin film transistor on a base substrate, and forming a micro on a side of the thin film transistor whose gate insulating layer is away from the base substrate a light emitting diode, wherein the thin film transistor comprises: a gate connected to a gate line; an active layer; the gate insulating layer insulating the gate from the active layer; and a first pole connected to the data line; And a second pole spaced apart from the first pole space, and the micro light emitting diode includes a first electrode, a light emitting layer and a second electrode; and a second pole connecting the thin film transistor to the micro light emitting diode One of the first electrode and the second electrode; and the other of the first electrode and the second electrode of the micro light emitting diode is connected to the common electrode.
  • forming the micro light emitting diode includes: sequentially forming a first semiconductor layer, the light emitting layer, and a second semiconductor layer on a side of the gate insulating layer away from the base substrate; and the gate insulating layer Forming a first electrode of the micro light emitting diode in contact with the first semiconductor layer on a side away from the base substrate; and forming the micro on a side of the second semiconductor layer away from the base substrate The second electrode of the light emitting diode.
  • the method before forming the first semiconductor layer, further includes forming a buffer layer on a side of the gate insulating layer away from the substrate substrate.
  • the first semiconductor layer is formed on a side of the buffer layer away from the base substrate and is in contact with the first electrode of the micro light emitting diode.
  • the thin film transistor is a top gate structure in which the gate is in the same layer as the first electrode of the micro light emitting diode and is spaced apart from each other.
  • the forming a thin film transistor includes: forming the active layer on the base substrate; forming the gate insulating layer on a side of the active layer away from the base substrate; away from the gate insulating layer Forming the gate on one side of the substrate; forming an interlayer dielectric layer on a side of the gate away from the substrate; forming a dielectric across the interlayer on the substrate a first via and a second via of the gate and the gate insulating layer; and forming the first pole of the thin film transistor and the side of the interlayer dielectric layer away from the substrate a second pole, wherein the first pole of the thin film transistor is connected to the active layer through the first via, and the second pole of the thin film transistor passes through the second via Active layer connection.
  • the method before forming the first pole and the second pole of the thin film transistor, the method further includes: forming a first contact via in the interlayer dielectric layer to The first electrode is exposed.
  • the second pole of the thin film transistor is connected to the first electrode of the micro light emitting diode through the first contact via, and the second electrode of the micro light emitting diode is connected to the common electrode .
  • the thin film transistor is a bottom gate structure in which the second electrode of the thin film transistor and the first electrode of the micro light emitting diode form the integral structure.
  • Forming the thin film transistor includes: sequentially forming a gate, a gate insulating layer, and an active layer of the thin film transistor on the base substrate; and forming the first of the thin film transistor on the base substrate And a unitary structure, wherein one end of the unitary structure is in contact with the active layer to form the second pole of the thin film transistor, and the other end of the unitary structure constitutes a micro-light emitting diode The first electrode is described.
  • the thin film transistor is a bottom gate structure in which the second electrode of the thin film transistor and the first electrode of the micro light emitting diode form the integral structure.
  • Forming the thin film transistor includes: sequentially forming a gate of the thin film transistor, a gate insulating layer, and an active layer on the base substrate; forming a protective layer on a side of the active layer away from the base substrate Forming a third via hole and a fourth via hole for exposing the active layer, and a second contact via for exposing the first semiconductor layer of the micro light emitting diode in the protective layer; Forming the first pole of the thin film transistor and the integrated structure from a side of the protective layer away from the substrate, wherein the first pole of the thin film transistor passes through the third via An active layer connection, one end of the unitary structure being connected to the active layer through the fourth via to form the second pole of the thin film transistor, and the other end of the unitary structure passes through A second contact via is connected to the first semiconductor layer to form the first electrode of the micro light emitting
  • the forming the miniature light emitting diode comprises forming the first electrode of the common electrode and the micro light emitting diode in the same layer by one patterning process.
  • the method further includes: forming a third contact via to expose the common electrode; and forming a connection electrode, the connection electrode passing the third contact A via connects the second electrode of the micro light emitting diode to the common electrode.
  • the method further includes forming an insulating layer on a side of the second electrode of the micro light emitting diode away from the substrate.
  • the method further includes: forming a fourth contact via in the insulating layer to The second electrode of the micro light emitting diode is exposed; and the common electrode is formed on the insulating layer, wherein the common electrode is connected to the second electrode through the fourth contact via.
  • the method further includes: forming a fifth contact via to expose the first electrode;
  • the common electrode is formed on the insulating layer, wherein the common electrode is connected to the first electrode through the fifth contact via.
  • a display device comprising the array substrate as described above.
  • FIG. 1 is a schematic cross-sectional view of a structure of an array substrate according to an embodiment of the present disclosure
  • FIG. 2A is a schematic cross-sectional view of a structure of an array substrate according to another embodiment of the present disclosure
  • 2B is a schematic cross-sectional view of a structure of an array substrate according to still another embodiment of the present disclosure
  • FIG. 2C is a schematic plan view showing the structure of the array substrate of FIG. 2A;
  • 3A is a schematic cross-sectional view showing a structure of an array substrate according to still another embodiment of the present disclosure.
  • 3B is a schematic cross-sectional view of a structure of an array substrate according to still another embodiment of the present disclosure.
  • 3C is a schematic cross-sectional view of a structure of an array substrate according to still another embodiment of the present disclosure.
  • FIG. 4A is a schematic cross-sectional view of a structure of an array substrate according to still another embodiment of the present disclosure.
  • 4B is a schematic cross-sectional view of a structure of an array substrate according to still another embodiment of the present disclosure.
  • 5A is a schematic cross-sectional view of a structure of an array substrate according to still another embodiment of the present disclosure.
  • 5B is a schematic cross-sectional view of a structure of an array substrate according to still another embodiment of the present disclosure.
  • FIG. 6 is a flow chart of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 7A is a flowchart of a method of fabricating an array substrate in accordance with another embodiment of the present disclosure.
  • 7B is a schematic cross-sectional view showing a structure obtained by forming an active layer on a base substrate
  • FIG. 7C is a schematic view showing polishing of the active layer of FIG. 7B;
  • FIG. 7D is a schematic cross-sectional view showing a structure obtained by forming a gate insulating layer on the active layer of FIG. 7C;
  • FIG. 7E is a schematic cross-sectional view showing a structure obtained by forming a buffer layer, a first semiconductor layer, a light emitting layer, and a second semiconductor layer on the gate insulating layer of FIG. 7D;
  • FIG. 7F is a schematic cross-sectional view showing a structure obtained by removing a film layer on a gate insulating layer located in a non-pixel region from the structure of FIG. 7E;
  • FIG. 7G is a schematic cross-sectional view showing a structure obtained by forming a gate electrode, a first electrode, and a second electrode on the structure of FIG. 7F;
  • FIG. 7H is a schematic cross-sectional view showing a structure obtained by forming a via hole in the structure of FIG. 7G;
  • FIG. 8A is a flow chart of a method of fabricating a thin film transistor in accordance with an embodiment of the present disclosure
  • FIG. 8B is a flowchart of a method of fabricating a thin film transistor according to another embodiment of the present disclosure.
  • FIG. 9 is a schematic block diagram of a display device in accordance with an embodiment of the present disclosure.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/ Some should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer Thus, a first element, component, region, layer, or section, which is discussed below, may be referred to as a second element, component, region, layer or section without departing from the teachings of the disclosure.
  • under and under can encompass both the ⁇ RTIgt; Terms such as “before” or “before” and “after” or “following” may be used, for example, to indicate the order in which light passes through the elements.
  • the device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • a layer is referred to as “between two layers,” it may be a single layer between the two layers, or one or more intermediate layers may be present.
  • FIG. 1 is a schematic cross-sectional view of a structure of an array substrate according to an embodiment of the present disclosure.
  • the array substrate can include a plurality of pixels arranged in an array, although only a single pixel is shown for convenience of illustration.
  • the pixel includes a thin film transistor 10 disposed on a base substrate 00.
  • the thin film transistor 10 includes a gate electrode 12 connected to a gate line (not shown in FIG. 1), an active layer 15, a gate insulating layer 11 that insulates the gate electrode from the active layer 15, and a data line (FIG. 1)
  • the first pole 13 connected and the second pole 14 spaced apart from the first pole 13 are not shown.
  • the pixel further includes a micro LED 20 disposed on a side of the gate insulating layer 11 away from the base substrate 00.
  • the micro LED 20 includes a first electrode 21, a light emitting layer 22, and a second electrode 23.
  • the second electrode 14 of the thin film transistor 10 is connected to the first electrode 21, and the second electrode 23 is connected to a common electrode (not shown in Fig. 1) for receiving a common voltage.
  • the second electrode 14 of the thin film transistor 10 can be connected to the second electrode 23, and the first electrode 21 can be connected to the common electrode.
  • An electrode of the micro LED 20 connected to the second pole 14 of the thin film transistor 10 (in this example, the first electrode 21) may be referred to as an anode, and an electrode of the micro LED 20 connected to the common electrode (in this example, the second electrode) 23) can be called a cathode.
  • the thin film transistor 10 is used to drive the micro LED 20 to emit light.
  • the first pole 13 can be a source and the second pole 14 can be a drain.
  • the first pole 13 can be a drain and the second pole 14 can be a source.
  • the first electrode 21 may be an N-type electrode
  • the second electrode 23 may be a P-type electrode.
  • the micro LEDs of the individual pixels may share the anode, ie the anodes of the micro LEDs of each pixel may be the same electrode.
  • the light-emitting layer 22 in the micro LED 20 may be formed of a material of a group III-V compound (including a binary compound, a ternary compound, or a quaternary compound, etc.).
  • the III-V compound refers to a compound formed of a group III element and a group V element of the periodic table, and the group III element includes boron (B), aluminum (Al), gallium (Ga), and indium (In), etc.
  • V Group elements include nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb).
  • the III-V compound generally includes gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), and the like.
  • the semiconductor light-emitting layer formed of the III-V compound material has high luminous efficiency, good stability, and long life.
  • the voltage applied to the common electrode of the array substrate may be different from the common electrode voltage of a conventional display device.
  • the common electrode voltage in the conventional display device may be 0 volt (V), or near 0 V, for example, -5 V to 5 V; and in the array substrate of the embodiment of the present disclosure, the voltage applied to the common electrode may not be limited. In the above range.
  • the cathode voltage applied to the common electrode ranges from -20V to 20V, typically not 0V.
  • FIG. 2A is a schematic cross-sectional view of a structure of an array substrate according to another embodiment of the present disclosure.
  • the same elements as in FIG. 1 are denoted by the same reference numerals and will not be described in detail herein.
  • the micro LED 20 further includes: a first semiconductor layer 24 disposed on a side of the light emitting layer 22 adjacent to the substrate 00, and a second semiconductor disposed between the light emitting layer 22 and the second electrode 23.
  • the first electrode 21 is in contact with the first semiconductor layer 24.
  • the second semiconductor layer 25 in contact with the second electrode 23 (cathode) may be an N-type semiconductor layer
  • the first semiconductor layer 24 in contact with the first electrode 21 (anode) may be a P-type semiconductor layer.
  • the N-type semiconductor layer may be made of a III-V compound material doped with a Group IV element, for example, a GaN material doped with silicon (Si) atoms.
  • the P-type semiconductor layer may be made of a Group III-V compound material doped with a Group II element, for example, may be made of a GaN material doped with magnesium (Mg) atoms.
  • the micro LED 20 further includes a buffer layer 26 disposed between the first semiconductor layer 24 and the gate insulating layer 11.
  • the first electrode 21 and the buffer 26 layer are both located on a side of the gate insulating layer 11 away from the substrate 00.
  • the buffer layer 26 and the first semiconductor layer 24 have convex portions compared to other film layers in the micro LED 20, and the first electrode 21 covers the protrusion of the first semiconductor layer 24. Partially, thereby achieving effective contact with the first semiconductor layer 24.
  • the gate insulating layer 11 may be made of a metal oxide material including: aluminum oxide (Al 2 O 3 ), iron oxide (Fe 2 O 3 ), chromium oxide ( cr 2 O 3), titanium trioxide (Ti 2 O 3), vanadium oxide (V 2 O 3), iron titanate (FeTiO 3), magnesium titanate (MgTiO 3), lanthanum oxide (La 2 O 3 ), antimony trioxide (Ce 2 O 3 ), gallium oxide (Ga 2 O 3 ), antimony oxide (Sc 2 O 3 ), antimony oxide (Sm 2 O 3 ), antimony trioxide (Eu 2 O 3 ) , antimony trioxide (Tb 2 O 3 ), antimony oxide (Dy 2 O 3 ), antimony trioxide (Y 2 O 3 ), antimony oxide (Ho 2 O 3 ), antimony oxide (Tm 2 O 3 ), Any one or a combination of lanthanum oxide (Lu 2 O 3 ) and antimony trioxid
  • a base buffer layer 01 may be disposed on the base substrate 00.
  • the thin film transistor 10 and the micro LED 20 are both disposed on a side of the base buffer layer 01 away from the substrate 00.
  • the base buffer layer 01 may be a composite film structure composed of a silicon nitride (SiN) film and a silicon dioxide (SiO 2 ) film.
  • FIG. 2B is a schematic cross-sectional view of a structure of an array substrate according to still another embodiment of the present disclosure.
  • the same elements as in FIG. 2A are denoted by the same reference numerals and will not be described in detail herein.
  • the second electrode 14 of the thin film transistor 10 is in direct contact with the second electrode 23 of the micro LED 20.
  • a side of the second pole 14 adjacent to the base substrate 00 is in contact with a side of the second electrode 23 away from the base substrate 00.
  • the first electrode 21 may be connected to a common electrode (not shown in FIG. 2B).
  • the thin film transistor 10 is a top gate structure in which the gate insulating layer 11 is disposed on a side of the gate electrode 12 close to the substrate substrate 00, and the active layer 15 is disposed on the gate insulating layer. 11 is adjacent to one side of the base substrate 00.
  • the first electrode 21 of the micro LED 20 is disposed in the same layer as the gate 12 and spaced apart from each other.
  • an interlayer dielectric layer 03 is further disposed on a side of the gate 12 away from the base substrate 00, and the first pole 13 and the second pole 14 of the thin film transistor 10 are spatially spaced apart from each other.
  • the layer 03 is away from the side of the base substrate 00.
  • FIG. 2C is a top plan view of the structure shown in FIG. 2A.
  • the first pole 13 is connected to the active layer 15 through a first via V1
  • the second pole 14 is connected to the active layer 15 through a second via V2
  • the second pole 14 passes
  • the first contact via CV1 is connected to the first electrode 21.
  • the first electrode 13 of the thin film transistor is connected to the data line 130
  • the gate electrode 12 of the thin film transistor is connected to the gate line 120.
  • FIG. 3A is a schematic cross-sectional view of a structure of an array substrate according to still another embodiment of the present disclosure.
  • the thin film transistor 10 has a bottom gate structure, and the first electrode 21 of the micro LED 20 and the second electrode 14 of the thin film transistor 10 form a unitary structure.
  • the portion of the unitary structure that is in contact with the active region 15 constitutes the second pole 14 of the thin film transistor 10.
  • the portion of the unitary structure that is in contact with the first semiconductor layer 24 constitutes the first electrode 21 of the micro LED 20.
  • the second electrode 23 of the micro LED 20 is connected to a common electrode (not shown).
  • the gate insulating layer 11 is disposed on a side of the gate electrode 12 away from the substrate substrate 00, and the active layer 15 is disposed on the gate insulating layer 11 away from the substrate 00.
  • the first electrode 13 of the thin film transistor 10 and the integral structure are disposed on a side of the gate insulating layer 11 away from the substrate 00, and both are in contact with the active layer 15.
  • the first semiconductor layer 24 and the buffer layer 26 have convex portions compared to the other respective film layers of the micro LED 20.
  • One end of the unitary structure covers a convex portion of the first semiconductor layer 24, thereby achieving effective contact with the first semiconductor layer 24.
  • FIG. 3B is a schematic cross-sectional view of a structure of an array substrate according to still another embodiment of the present disclosure.
  • the same elements as in FIG. 3A are denoted by the same reference numerals and will not be described in detail herein.
  • a protective layer 16 is further disposed on a side of the active layer 15 away from the base substrate 00.
  • the integral structure of the first electrode 13 and the second electrode 14 of the thin film transistor 10 and the first electrode 21 is disposed on a side of the protective layer 16 away from the substrate 00.
  • the first pole 13 is connected to the active layer 15 through a third via hole V3.
  • One end of the unitary structure is connected to the active layer 15 through the fourth via hole V4 to constitute the second electrode 14 of the thin film transistor 10.
  • the other end of the unitary structure is connected to the first semiconductor layer 24 through the second contact via CV2 to constitute the first electrode 21 of the micro LED 20.
  • the first semiconductor layer 24 has a convex portion compared to the light emitting layer 22 and the second semiconductor layer 25, so that the integrated structure can The convex portion of the first semiconductor layer 24 is in contact.
  • FIG. 3C is a schematic cross-sectional view of a structure of an array substrate according to still another embodiment of the present disclosure.
  • the same elements as in FIG. 3A are denoted by the same reference numerals and will not be described in detail herein.
  • the second electrode 14 of the thin film transistor 10 is in direct contact with the second electrode 23 of the micro LED 20.
  • the side of the second electrode 14 close to the substrate 00 is in contact with the side of the second electrode 23 away from the substrate 00.
  • the first electrode 21 of the micro LED 20 may be connected to a common electrode (not shown).
  • FIG. 4A is a schematic cross-sectional view of a structure of an array substrate according to still another embodiment of the present disclosure.
  • the same elements as in FIG. 2A are denoted by the same reference numerals and will not be described in detail herein.
  • the common electrode 30 is disposed in the same layer as the first electrode 21.
  • the second electrode 14 of the thin film transistor 10 is connected to the first electrode 21 of the micro LED.
  • the side of the second electrode 23 remote from the substrate 00 is further provided with a connection electrode 31 which is connected to the common electrode 30 via a third contact via CV3 provided in the interlayer dielectric layer 03.
  • the connection electrode 31 is disposed in the same layer as the first pole 13 and the second pole 14, and thus can be formed by one patterning process.
  • FIG. 4B is a schematic cross-sectional view of a structure of an array substrate according to still another embodiment of the present disclosure.
  • the same elements as in FIG. 4A are denoted by the same reference numerals and will not be described in detail herein.
  • the second electrode 14 of the thin film transistor 10 is directly connected to the second electrode 23 of the micro LED, and the common electrode 30 forms a unitary structure with the first electrode 21 of the micro LED.
  • the unitary structure is in direct contact with the first semiconductor layer 24, and the portion of the unitary structure that is in contact with the first semiconductor layer 24 constitutes the first electrode 21 of the micro LED 20.
  • FIG. 5A is a schematic cross-sectional view of a structure of an array substrate according to still another embodiment of the present disclosure.
  • the same elements as in FIG. 2A are denoted by the same reference numerals and will not be described in detail herein.
  • the common electrode 30 is disposed on a side of the second electrode 23 away from the base substrate 00, and an insulating layer 32 is formed between the common electrode 30 and the second electrode 23.
  • the second electrode 14 of the thin film transistor 10 is connected to the first electrode 21 of the micro LED 20, and the common electrode 30 is connected to the second electrode 23 of the micro LED 20 through a fourth contact via CV4 provided in the insulating layer 32.
  • the active layer 15 in the thin film transistor 10 covers the entire substrate in a layer.
  • FIG. 5B is a schematic cross-sectional view of a structure of an array substrate according to still another embodiment of the present disclosure.
  • the same elements as in FIG. 5A are denoted by the same reference numerals and will not be described in detail herein.
  • the common electrode 30 can pass through the fifth contact via CV5 disposed in the insulating layer 32 and the interlayer dielectric layer 03. It is connected to the first electrode 21.
  • the active layer 15 is disposed only in the active region of the thin film transistor 10.
  • the micro LED can be formed simultaneously in the process of forming a thin film transistor, simplifying the manufacturing process of the array substrate. The manufacturing cost of the display device is reduced.
  • FIG. 6 is a flow chart of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure. The method can be used to fabricate the array substrate shown in any of Figures 1 to 5B.
  • a thin film transistor is formed on the base substrate, and a micro light emitting diode LED is formed on a side of the thin film transistor whose gate insulating layer is away from the base substrate.
  • the thin film transistor includes a gate connected to a gate line, an active layer, the gate insulating layer insulating the gate from the active layer, a first pole connected to the data line, and the first The second pole separated by the pole space.
  • the micro LED includes a first electrode, a light emitting layer, and a second electrode.
  • the second electrode of the thin film transistor is coupled to one of the first electrode and the second electrode of the micro light emitting diode.
  • step 103 the other of the first electrode and the second electrode of the micro light emitting diode is connected to the common electrode. It will be understood that although steps 101 through 103 in Figure 6 are illustrated as being separate from each other, they may be a one-piece process.
  • the manufacturing methods provided by embodiments of the present disclosure have shorter process times and higher yields than conventional transfer processes.
  • the process of forming the micro LED may include: sequentially forming a first semiconductor layer, a light emitting layer, and a second semiconductor layer on a side of the gate insulating layer away from the substrate substrate; and then moving away from the gate insulating layer One side of the base substrate forms a first electrode in contact with the first semiconductor layer, and a second electrode is formed on a side of the second semiconductor layer away from the base substrate.
  • the manufacturing method may further include forming a buffer layer on a side of the gate insulating layer away from the base substrate before forming the first semiconductor layer.
  • the first semiconductor layer may be formed on a side of the buffer layer away from the base substrate, and the first semiconductor layer may have a convex portion compared to other film layers of the micro LED.
  • the subsequently formed first electrode may overlie the portion of the first semiconductor layer that is convex to ensure effective contact with the first semiconductor layer.
  • the method can include the following steps.
  • Step 1011a forming a basic buffer layer on the base substrate.
  • the base substrate may be a glass substrate.
  • the base buffer layer may be a composite film structure composed of a silicon nitride (SiN) film and a silicon dioxide (SiO 2 ) film.
  • the substrate substrate when the basic buffer layer is formed, the substrate substrate may be initially cleaned to remove impurity particles on the surface of the substrate substrate, and then the plasma enhanced chemical vapor deposition (PECVD) method is used on the substrate.
  • PECVD plasma enhanced chemical vapor deposition
  • the surface is sequentially formed into a SiN film and a SiO 2 film, thereby obtaining the base buffer layer.
  • the thickness of the SiN film may be from 50 nanometers (nm) to 100 nm, and the thickness of the SiO 2 film may be from 100 nm to 400 nm.
  • the SiN film has strong diffusion barrier property, and can inhibit the influence of metal ions in the glass substrate on the polysilicon film to be formed later; and the SiO 2 film and the polysilicon film have an excellent interface, and can prevent the defects of the SiN film from being on the quality of the polysilicon film. Damage.
  • Step 1012a forming an active layer on a side of the base buffer layer away from the base substrate.
  • An active layer may be formed on the surface of the underlying buffer layer by a PECVD method.
  • the active layer may be formed of an amorphous silicon (a-Si) material, a polysilicon material, or indium gallium zinc oxide (IGZO).
  • a layer of a-Si film having a thickness of 40 nm to 100 nm may be continuously deposited on the base buffer layer 01 by PECVD, and then the a-Si film may be dehydrogenated using a heat treatment furnace. Process to prevent hydrogen explosion during crystallization. The a-Si crystallization process can then be performed to form a polysilicon film.
  • the a-Si film can usually be crystallized by laser annealing, metal induced crystallization or solid phase crystallization. For example, as shown in FIG. 7B, the a-Si film may be subjected to laser annealing crystallization using a laser beam.
  • the polysilicon film can be cleaned by using diluted hydrofluoric acid to reduce the surface roughness of the polysilicon film to reduce defects of the thin film transistor.
  • ion implantation or ion cloud implantation may be used to perform channel doping of the thin film transistor on the polysilicon film to obtain the active layer.
  • the doping ions doped by the channel are generally a mixed gas of phosphine (PH 3 ) and hydrogen (H 2 ), or a mixed gas of diborane (B2H6) and H2.
  • the ion implantation dose is between 10 11 and 10 13 ions/cm 2 (ions/cm 2 is the negative ion concentration measurement unit, which refers to the number of negative ions per square centimeter), and the implantation energy is between 10 and 100 keV (KeV). .
  • Channel doping can effectively adjust the threshold voltage of the thin film transistor and improve the switching characteristics of the thin film transistor.
  • a sacrificial layer may also be deposited on the surface of the polysilicon film.
  • a layer of silicon nitride (SiNx) may be deposited as a sacrificial layer.
  • the sacrificial layer and the polysilicon film may be ground using a chemical mechanical polishing apparatus 40 having a grinding disc 41 and a polishing pad 42.
  • the grinding process can include two stages, wherein the first stage is for removing the sacrificial layer and the second stage is for simultaneously removing the polysilicon film and the residual sacrificial layer.
  • the upper surface of the polysilicon film ie, the side away from the substrate 00
  • the chemical mechanical polishing apparatus 40 is ground, SiNx is continuously thinned, and part of the surface of the polysilicon film is exposed.
  • the surface of the SiNx and the polysilicon film are simultaneously exposed to the action of the chemical mechanical polishing liquid and the mechanical polishing, and since the chemical mechanical polishing liquid has a stronger etching ability for the polycrystalline silicon, the polycrystalline silicon is preferentially etched and removed. Thereby, the convex portion of the rough polysilicon surface can be smoothed.
  • the chemical mechanical polishing liquid can be an alkaline silica polishing liquid.
  • a silicon oxide (SiOx) film may be deposited on the surface of the polysilicon film as a sacrificial layer.
  • the SiOx film may have a thickness of 800 to 120 angstroms, for example, 90 to 110 angstroms.
  • a SiOx film may be formed on the surface of the polysilicon film by a dry oxidation process in which oxygen may be introduced into the reaction chamber to cause oxidation of the polysilicon to SiOx at a high temperature. The temperature and time of oxidation can be adjusted depending on the situation. The process is relatively mature and easy to process design.
  • a SiOx film can also be deposited by chemical vapor deposition.
  • a SiOx film can be deposited by a PECVD method.
  • the efficiency and cost control of the PECVD method is relatively good.
  • other well known thin film deposition or epitaxial methods can be used to form SiOx films on the surface of the polysilicon film.
  • the process of chemical mechanical polishing using a SiOx film as a sacrificial layer is similar to the process of chemical mechanical polishing using a SiNx film as a sacrificial layer, and the specific process thereof will not be described again.
  • the surface of the polysilicon film may be wet-etched using an etching solution to remove residual sacrificial layer material on the surface of the polysilicon film, and residual particles generated by the chemical mechanical polishing process, thereby further reducing the roughness of the surface of the polysilicon film.
  • Step 1013a forming a gate insulating layer on a side of the active layer away from the base substrate.
  • a metal oxide film may be formed on the surface of the active layer as a gate insulating layer by a magnetron sputtering process, for example, an Al 2 O 3 film may be formed as a gate insulating layer.
  • the chemically mechanically polished polycrystalline silicon film may be cleaned by ultrasonic cleaning using acetone, ethanol, and deionized water prior to coating. Then, in the ultrahigh vacuum magnetron sputtering system, an aluminum oxide film is deposited on the surface of the polished active layer by radio frequency reactive magnetron sputtering to obtain a gate insulating layer 11 as shown in FIG. 7D.
  • high purity (purity: 99.998%) argon (Ar) can be used as a sputtering gas, and high purity (purity: 99.995%) oxygen (O 2 ) is used as a reaction gas.
  • the two gases are precisely controlled by a gas mass flow meter and are passed into the vacuum chamber at different ratios.
  • the total pressure of the mixed gas of Ar and O 2 in the vacuum chamber can be displayed by a vacuum gauge, and the total pressure can be controlled by a vacuum valve.
  • the sputtering target was high purity (purity of 99.99%) of Al, and an oxide layer was present on the surface of the high purity Al target. At the time of sputtering, it may be pre-sputtered in pure Ar for 20 to 30 minutes to remove contaminants from the surface of the Al target.
  • the sputtering parameters were an Ar gas flow rate of 20 standard milliliters per minute (sccm), a working gas pressure of 2.0 Pa (Pa), a sputtering power of 100 watts (W), and a substrate substrate heated to 450 degrees Celsius.
  • sccm standard milliliters per minute
  • Pa working gas pressure
  • W sputtering power
  • the background vacuum before sputtering should be higher than 5 ⁇ 10 -5 Pa, wherein the background vacuum means that the vacuum pumping system uses a vacuum pumping system to achieve a certain degree of vacuum in a certain space.
  • the sample baffle is turned away for formal sputtering.
  • the sample was annealed in situ under an oxygen atmosphere in a vacuum chamber.
  • the working atmosphere has a pressure of 0.5 Pa, which is advantageous for crystallizing the deposited film to form a hexagonal crystal structure (corundum).
  • a small cooling rate can generate a small internal stress, and oxygen can supplement the oxygen vacancy due to sputtering in the aluminum oxide film, the aluminum oxide film can be made better with the substrate (ie, the active layer). ) Attached.
  • the gate insulating layer may be formed of a metal oxide material, which may be Al 2 O 3 , Fe 2 O 3 , Cr 2 O 3 , Ti 2 O 3 , V 2 O 3 , FeTiO 3 , MgTiO 3 , La 2 O 3 , Ce 2 O 3 , Ga 2 O 3 , Sc 2 O 3 , Sm 2 O 3 , Eu 2 O 3 , Tb 2 O 3 , Dy 2 O 3 Any one of Y 2 O 3 , Ho 2 O 3 , Tm 2 O 3 , Lu 2 O 3 and Nd 2 O 3 .
  • a metal oxide material which may be Al 2 O 3 , Fe 2 O 3 , Cr 2 O 3 , Ti 2 O 3 , V 2 O 3 , FeTiO 3 , MgTiO 3 , La 2 O 3 , Ce 2 O 3 , Ga 2 O 3 , Sc 2 O 3 , Sm 2 O 3 , Eu 2 O 3 , Tb 2 O 3 , Dy 2 O 3 Any one of
  • Step 1014a forming a buffer layer on a side of the gate insulating layer away from the base substrate.
  • a metal organic chemical vapor deposition (MOCVD) method may be used to deposit a GaN film on the surface of the gate insulating layer as a buffer layer, which may improve the epitaxial lattice quality of the semiconductor layer to be formed subsequently.
  • MOCVD metal organic chemical vapor deposition
  • the base substrate on which the base buffer layer, the active layer and the gate insulating layer are formed may be firstarily used with absolute ethanol. Rinse, and then the substrate was sequentially placed in acetone, absolute ethanol and deionized water for ultrasonic cleaning for 10 minutes, then repeatedly rinsed with deionized water, and finally dried with high purity nitrogen (N 2 ).
  • N 2 high purity nitrogen
  • the TMGa bubbler is placed in a cold trap to maintain a temperature of -12.6 degrees Celsius, and H 2 is used as a carrier gas, and a purity of 5N (ie, 99.999%) of high purity N 2 is used as a nitrogen source.
  • Low temperature deposition (deposition temperature less than 500 degrees Celsius) is performed on the underlying substrate of the gate insulating layer.
  • the microwave source power can be fixed at 650 W
  • the background vacuum is better than 5.0 ⁇ 10 -4 Pa
  • a GaN low-temperature buffer layer with a thickness of about 20 nm is deposited first in an environment of 300 degrees Celsius, and the deposition conditions are flow rates of TMGa and nitrogen.
  • the deposition time was 5 minutes for each of 0.4 sccm and 80 sccm.
  • the substrate temperature was then raised to 430 degrees Celsius, the flow rates of TMGa and nitrogen were 0.4 sccm and 80 sccm, respectively, and the deposition time was increased to 30 min.
  • the buffer layer may be formed using a material such as GaAs or InP. Since the material alumina for forming the gate insulating layer has the same structure as that of the material crystals such as GaAs and GaN, it is advantageous for epitaxial growth. Although the lattice constant and thermal expansion coefficient do not match the III-V semiconductor material that needs epitaxial growth, the cost is low and the light transmittance is up to 90%, which is suitable for the laser heating process.
  • Step 1015a forming a first semiconductor layer, the light emitting layer, and a second semiconductor layer in this order on a side of the buffer layer away from the base substrate.
  • the first semiconductor layer may be an N-type semiconductor layer
  • the second semiconductor layer may be a P-type semiconductor layer. According to the color of the micro LED, InGaN, InAlGaP, GaP, GaAsP or AlGaAs can be selected.
  • the luminescent layer can also be referred to as a quantum well.
  • the first semiconductor layer 24, the light-emitting layer 22, and the second semiconductor layer 25 may be sequentially formed on the surface of the buffer layer 26 by an MOCVD process.
  • the base substrate may be heated to a high temperature of about 600 degrees Celsius, and a TMGa and an ammonia (NH 3 ) precursor are simultaneously introduced into the reaction chamber, thereby sequentially forming an N-type GaN semiconductor layer 24 on the surface of the buffer layer 26.
  • a TMGa and an ammonia (NH 3 ) precursor are simultaneously introduced into the reaction chamber, thereby sequentially forming an N-type GaN semiconductor layer 24 on the surface of the buffer layer 26.
  • InGaN or GaN quantum well 22 and P-type GaN semiconductor layer 25 are sequentially formed on the surface of the buffer layer 26 by an MOCVD process.
  • the first semiconductor layer 24 and the second semiconductor layer 25 may be formed using an in-situ deposition state doping technique.
  • the forming process may include adding silane (SiH 4 ), disilane (Si 2 H 6 ), dimethylsilane (SiCH 8 ) or dichlorodihydrosilane (SiH 2 ) while introducing TMGa and NH 3 into the reaction chamber.
  • cl 2 as silicon precursor, so that the GaN incorporation 1017 to 1020 cm & lt -3 of Si (i.e., incorporated in the GaN of 10 17 per cubic centimeter to 1020 Si atoms), thereby depositing an N-type GaN semiconductor layer 24.
  • an organic precursor of magnesium such as magnesium pentoxide (Cp 2 Mg) is added to the reaction chamber so that Mg of 10 17 to 10 20 cm -3 is doped into the GaN, thereby forming the P-type GaN semiconductor layer 25.
  • an organic precursor of magnesium such as magnesium pentoxide (Cp 2 Mg) is added to the reaction chamber so that Mg of 10 17 to 10 20 cm -3 is doped into the GaN, thereby forming the P-type GaN semiconductor layer 25.
  • a nano-thickness wide band gap material and a narrow band gap semiconductor material may be successively alternately deposited by an MOCVD process, for example, alternating deposition of a wide band gap material aluminum gallium nitride (AlGaN) And a narrow bandgap material, GaN, to form a variety of single quantum well or multiple quantum well structures.
  • the wide bandgap material in the quantum well material has a matching lattice constant and energy band with a narrow bandgap material (the band difference of the two materials is kept within a certain range (for example, 1 eV)), thereby being able to modulate the emission wavelength.
  • the quantum well structure also has the advantages of high recombination efficiency and low interfacial recombination rate.
  • the thickness of the buffer layer 26 may be between 0.1 and 5 micrometers
  • the thickness of the first semiconductor layer 24 and the second semiconductor layer 25 may be between 0.1 and 0.5 micrometers
  • the thickness of the quantum well 22 is Between 0.1 and 0.5 microns.
  • Step 1016a removing the second semiconductor layer, the light emitting layer, the first semiconductor layer, and the buffer layer of the non-pixel region.
  • a photolithography process may be employed to form a patterned photoresist mask on the surface of the substrate to define pixel regions and non-pixel regions.
  • the pixel area is the area for setting the micro LED, that is, the effective display area of the array substrate.
  • the non-pixel area is a non-display area.
  • the pixel region may include a P region of a micro LED, a multiple quantum well (MQW) region, and an N region, and the orthographic projections of the P region, the MQW region, and the N region on the substrate substrate coincide.
  • MQW multiple quantum well
  • a portion of the second semiconductor layer, the light-emitting layer, the first semiconductor layer, and the buffer layer that are not covered by the photoresist mask may be etched using an Inductive Coupled Plasma Emission Spectrometer (ICP) etch.
  • the etch depth can be 1.3 microns.
  • the etching gas used in the ICP etching machine may be chlorine gas (Cl 2 ) and boron trichloride (BCl 3 ).
  • the buffer layer 26 and the first semiconductor layer 24 may have convex portions which constitute electrode contact regions as compared with other film layers in the micro LEDs 20. It can also be seen with reference to FIG. 7F that the gate insulating layer 11 of the non-pixel region is exposed after the etching process.
  • Step 1017a forming a gate of the thin film transistor on a side of the gate insulating layer away from the substrate, and a first electrode of the micro LED contacting the first semiconductor layer, and forming a side of the second semiconductor layer away from the substrate The second electrode of the micro LED.
  • a metal thin film may be deposited on the surface of the gate insulating layer, and then the metal thin film may be processed by a patterning process to form a gate electrode of the thin film transistor and a first electrode of the micro LED. .
  • the first electrode may overlie the raised first semiconductor layer 24 to achieve effective contact with the first semiconductor layer 24.
  • a metal thin film having a thickness of 200 to 500 nm may be deposited on the surface of the base substrate by magnetron sputtering.
  • the metal film may be a film layer formed of one of molybdenum (Mo), molybdenum-niobium alloy (MoNb), Al, aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu), or may be A single or multiple layer composite laminate formed from a plurality of materials of the above materials.
  • a Mo film layer or an Al film layer may be formed on the surface of the base substrate, or a single layer film layer or a multilayer composite film layer composed of an alloy of Mo and Al may be formed.
  • a patterned photoresist mask can be formed on the surface of the base substrate by a photolithography process to define a gate region of the thin film transistor, a first electrode region of the micro LED, and a second electrode region.
  • the region of the metal film not covered by the photoresist mask may be etched.
  • the gate electrode 12 of the thin film transistor, the first electrode 21 of the micro LED, and the second electrode 23 may be obtained.
  • the second electrode 23 is located on a side of the second semiconductor layer 25 away from the substrate 00, and the first electrode 21 covers the portion of the first semiconductor layer 24 that protrudes.
  • Step 1018a forming an interlayer dielectric layer on a side of the gate away from the substrate.
  • An inter-layer dielectric (ILD) may be formed on the side of the gate away from the substrate by a PECVD process.
  • the interlayer dielectric layer may be an SiOx layer or a SiNx layer, or may be composed of a SiOx layer and a SiNx layer stack.
  • Step 1019a forming a first via and a second via extending through the interlayer dielectric layer and the gate insulating layer on the base substrate.
  • a first via hole V1 and a second via hole 32 may be formed on the base substrate, and the first via hole V1 may leak the source contact region of the active layer 15 and the second via hole 32 The drain contact region of the active layer 15 can be leaked out.
  • the interlayer dielectric layer formed in the above step 1018a may be covered on the surface of the base substrate in a whole layer, and the first via hole and the second via hole are formed by one photolithography process in step 1019a. It is also possible to remove a portion of the interlayer dielectric layer overlying the second electrode 23.
  • Step 1020a forming a first pole and a second pole of the thin film transistor spaced apart from each other on a side of the interlayer dielectric layer away from the base substrate.
  • a metal thin film may be deposited on the surface of the interlayer dielectric layer, and then the metal thin film is patterned by a photolithography process to form a first pole and a second pole of the thin film transistor.
  • the first pole is in contact with the source contact region in the active layer through the first via
  • the second via is in contact with the drain contact region of the active layer through the second via.
  • the metal thin film may be formed of any one of metal materials such as Cu, Al, Mo, Ti, chromium (Cr), or tungsten (W).
  • the metal film may also be a multilayer metal film structure composed of a plurality of metal materials.
  • the metal film may be a three-layer metal film, and the metal material forming the three-layer metal film may be Mo, Al, and Mo, or Ti, Al, and Ti, or Ti, Cu, and Ti, or Mo, Cu, and Ti.
  • the method may further include: forming a first contact via in the interlayer dielectric layer to expose the first electrode.
  • the first contact via may be formed in synchronization with the first via and the second via.
  • a first contact via 33 can be formed.
  • the second electrode of the thin film transistor formed in the above step 1020a may also be connected to the first electrode 21 through the first contact via 33, and the second electrode 23 may be connected to the common electrode 30.
  • the structure of the finally formed array substrate can be referred to FIG. 2A, FIG. 4A or FIG. 5A.
  • the second pole of the thin film transistor formed in the above step 1020a is close to the side of the base substrate, and may be in contact with the side of the micro LED with the second electrode away from the base substrate. That is, the second electrode 14 of the thin film transistor is connected to the second electrode 23 of the micro LED, and the first electrode 21 of the micro LED is connected to the common electrode 30.
  • the structure of the finally formed array substrate can be referred to FIG. 2B, FIG. 4B or FIG. 5B.
  • the gate electrode and the first electrode may be formed first, and then the buffer layer, the first semiconductor layer, the light emitting layer, the second semiconductor layer, and the second electrode in the micro LED may be sequentially formed. That is, the operation of forming the gate electrode and the first electrode in the above step 1017a may be performed before the step 1014a, the operation of forming the second electrode in the above step 1017a may be performed after the step 1016a, and the above step 1016a may be omitted.
  • a method of fabricating an array substrate of a thin film transistor having a bottom gate structure will be described below with reference to FIGS. 8A and 3A.
  • step 1011b the gate electrode 12 is formed on the base substrate 00.
  • Step 1012b forming a gate insulating layer 11 on a side of the gate electrode 12 away from the base substrate 00.
  • Step 1013b the buffer layer 26, the first semiconductor layer 24, the light-emitting layer 22, and the second semiconductor layer 25 in the micro LED 20 are sequentially formed on the side of the gate insulating layer 11 away from the base substrate 00.
  • Step 1014b forming an active layer 15 on a side of the gate insulating layer 11 away from the base substrate 00.
  • Step 1015b forming a first pole 13 and an integral structure in contact with the active layer 15 on a side of the gate insulating layer 11 away from the base substrate 00, and a second semiconductor layer 25 away from the base substrate 00
  • the second electrode 23 is formed on the side.
  • One end of the unitary structure in contact with the active layer 15 constitutes the second pole 14 of the thin film transistor 10.
  • the other end of the unitary structure is in contact with the first semiconductor layer 24 of the micro LED 20 to constitute the first electrode 21 of the micro LED 20.
  • steps 1011b to 1015b may be performed according to the corresponding steps in the embodiment described above with reference to FIG. 7A, and details are not described herein again.
  • a method of manufacturing an array substrate of a thin film transistor having a bottom gate structure will be described below with reference to FIGS. 8B and 3B.
  • step 1011c the gate electrode 12 is formed on the base substrate 00.
  • Step 1012c forming a gate insulating layer 11 on a side of the gate electrode 12 away from the base substrate 00.
  • Step 1013c the buffer layer 26, the first semiconductor layer 24, the light emitting layer 22, and the second semiconductor layer 25 in the micro LED 20 are sequentially formed on the side of the gate insulating layer 11 away from the base substrate 00.
  • Step 1014c forming an active layer 15 on a side of the gate insulating layer 11 away from the base substrate 00.
  • Step 1015c forming a protective layer 16 on a side of the active layer 15 away from the base substrate 00.
  • Step 1016c forming a third via hole V3 and a fourth via hole V4 for exposing the active layer 15 in the protective layer 16, and a second contact via hole CV2 for exposing the first semiconductor layer 24.
  • Step 1017c forming a first pole 13 of the thin film transistor 10 and an integral structure on a side of the protective layer 16 away from the base substrate 00, and forming a second electrode on a side of the second semiconductor layer 25 away from the base substrate 00 twenty three.
  • the first pole 13 is connected to the active layer 15 through the third via hole V3.
  • One end of the unitary structure is connected to the active layer 15 through the fourth via hole V4 to form a second electrode 14 of the thin film transistor 10.
  • the other end of the integrated structure passes through the second contact via CV2 and the first semiconductor.
  • the layers 24 are connected to form the first electrode 21 of the micro LED 20.
  • steps 1011c to 1017c may be performed according to the corresponding steps in the embodiment described above with reference to FIG. 7A, and details are not described herein again.
  • the common electrode 30 and the first electrode 21 of the micro LED 20 may be formed in the same layer by one patterning process.
  • a third contact via CV3 is formed to expose the common electrode 30.
  • the third contact via CV3 may be formed while forming the first contact via CV1 in the interlayer dielectric layer 03.
  • a connection electrode 31 is formed on a side of the second electrode 23 away from the base substrate 00, and the connection electrode 31 is connected to the common electrode 30 through the third contact via CV3.
  • the connection electrode 31 may be formed in the same layer as the first electrode 13 and the second electrode 14 of the thin film transistor 10 by one patterning process.
  • the common electrode 30 and the first electrode 21 of the micro LED 20 may be formed in the same layer by one patterning process.
  • the common electrode 30 and the first electrode 21 may be of a unitary structure, that is, the common electrode 30 may be directly used as the first electrode 21 of the micro LED 20.
  • the common electrode 30 is formed on a side of the second electrode 23 of the micro LED 20 away from the substrate 00, and an insulating layer 32 is formed between the common electrode 30 and the second electrode 23.
  • a fourth contact via CV4 is formed in the insulating layer 32 to expose the second electrode 23.
  • the common electrode 30 is connected to the second electrode 23 through the fourth contact via CV4.
  • an insulating layer 32 is further formed on a side of the second electrode 23 away from the substrate 00.
  • a fifth contact via CV5 for exposing the first electrode 21 is formed in the insulating layer 32 and the interlayer dielectric layer 03.
  • the common electrode 30 is formed on a side of the insulating layer 32 away from the substrate 00, and is connected to the first electrode 21 through the fifth contact via CV5.
  • FIG. 9 is a schematic block diagram of a display device in accordance with an embodiment of the present disclosure.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device includes a timing controller 910, a scan driver 920, a data driver 930, and a display substrate 950.
  • the timing controller 910 receives the synchronization signals and video signals R, G, and B from the system interface.
  • the synchronization signal includes a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a main clock signal MCLK, and a data enable signal DE.
  • the video signals R, G, and B contain luminance information of each of the plurality of pixels PX.
  • the timing controller 910 generates the first driving control signal CONT1, the second driving control signal CONT2, and the image data according to the video signals R, G, and B, the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, the data enable signal DE, and the main clock signal MCLK.
  • Signal DAT the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, the data enable signal DE, and the main clock signal MCLK.
  • the display substrate 950 includes pixels PX arranged substantially in a matrix form.
  • a plurality of substantially parallel scanning lines S1 to Sn extend in the row direction
  • a plurality of substantially parallel data lines D1 to Dm extend in the column direction.
  • the scan lines S1 to Sn and the data lines D1 to Dm are coupled to the pixel PX.
  • Display substrate 950 can take the form of any of the array substrate embodiments described above with respect to Figures 1 through 5B.
  • the scan driver 920 is coupled to the scan lines S1-Sn, and generates a corresponding plurality of scan signals S[1] to S[n] according to the first drive control signal CONT1.
  • the scan driver 920 can sequentially apply the scan signals S[1]-S[n] to the scan lines S1-Sn.
  • the data driver 930 is coupled to the data lines D1-Dm, samples and holds the image data signal DAT according to the second driving control signal CONT2, and applies a plurality of data signals D[1] to D[m] to the data lines D1 to Dm, respectively. .
  • the data driver 930 can program the data to the pixel PX by applying the data signals D[1] to D[m] to the data lines D1 to Dm in synchronization with the scan signals S[1] to S[n].

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Abstract

一种阵列基板，包括：衬底基板；薄膜晶体管，设置在所述衬底基板上，所述薄膜晶体管包括：与栅线连接的栅极；有源层；将所述栅极与所述有源层相绝缘的栅绝缘层；与数据线连接的第一极；以及与所述第一极空间相隔的第二极；微型发光二极管，设置在所述栅绝缘层远离所述衬底基板一侧，所述微型发光二极管包括第一电极、发光层和第二电极；以及公共电极。所述薄膜晶体管的第二极与所述微型发光二极管的所述第一电极和所述第二电极中的一个电极连接。所述微型发光二极管的所述第一电极和所述第二电极中的另一电极与公共电极连接。

Description

阵列基板、其制造方法、以及显示装置
相关申请的交叉引用
本申请要求2018年3月16日提交的中国专利申请No.201810220239.8的优先权，其全部公开内容通过引用合并于此。
技术领域
本申请涉及显示技术领域，特别涉及一种阵列基板、其制造方法、以及显示装置。
背景技术
微型发光二极管(Micro Light-Emitting Diode，Micro LED)是一种采用无机材料(例如氮化镓)作为发光材料的发光器件，具有例如10μm至15μm范围内的典型尺寸。采用Micro LED作为发光器件的显示装置的具有亮度高、响应速度快以及稳定性高等优点。
在制造Micro LED显示装置时，一般在玻璃基板上形成阵列排布的薄膜晶体管，并在单独的单晶硅基板上形成多个Micro LED；之后对该单晶硅基板进行切割，得到独立的多个Micro LED；最后将各个Micro LED转印至阵列基板上的对应区域。
发明内容
根据本公开的一方面，提供了一种阵列基板，包括：衬底基板；薄膜晶体管，设置在所述衬底基板上，所述薄膜晶体管包括：与栅线连接的栅极；有源层；将所述栅极与所述有源层相绝缘的栅绝缘层；与数据线连接的第一极；以及与所述第一极空间相隔的第二极；微型发光二极管，设置在所述栅绝缘层远离所述衬底基板一侧，所述微型发光二极管包括第一电极、发光层和第二电极；以及公共电极。所述薄膜晶体管的第二极与所述微型发光二极管的所述第一电极和所述第二电极中的一个电极连接。所述微型发光二极管的所述第一电极和所述第二电极中的另一电极与公共电极连接。
在一些实施例中，所述微型发光二极管还包括：设置在所述发光层靠近所述衬底基板一侧的第一半导体层，以及设置在所述发光层和 所述第二电极之间的第二半导体层，所述第一半导体层与所述微型发光二极管的所述第一电极接触。
在一些实施例中，所述微型发光二极管还包括设置在所述第一半导体层和所述栅绝缘层之间的缓冲层，并且所述缓冲层与所述微型发光二极管的所述第一电极均位于所述栅绝缘层远离所述衬底基板的一侧。
在一些实施例中，所述栅绝缘层由金属氧化物材料制成，所述金属氧化物材料包括从由氧化铝、氧化铁、三氧化二铬、三氧化二钛、氧化钒、钛酸亚铁、钛酸镁、氧化镧、三氧化二铈、氧化镓、氧化钪、氧化钐、三氧化二铕、三氧化二铽、氧化镝、三氧化二钇、氧化钬、氧化铥、氧化镥以及三氧化二钕所组成的组中选择的至少一个。
在一些实施例中，所述薄膜晶体管为从由顶栅结构和底栅结构所组成的组中选择的结构，在所述顶栅结构中所述栅极与所述微型发光二极管的所述第一电极同层设置且彼此空间相隔，在所述底栅结构中所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第一电极形成一体结构或与所述微型发光二极管的所述第二电极连接。
在一些实施例中，所述薄膜晶体管为顶栅结构。所述阵列基板还包括设置在所述栅极远离所述衬底基板的一侧的层间介电层。所述栅绝缘层设置在所述栅极靠近所述衬底基板的一侧；所述有源层设置在所述栅绝缘层靠近所述衬底基板的一侧；并且所述薄膜晶体管的第一和第二极设置在所述层间介电层远离所述衬底基板的一侧，所述薄膜晶体管的所述第一极通过设置在所述层间介电层中的第一过孔与所述有源层连接，所述薄膜晶体管的所述第二极通过设置在所述层间介电层中的第二过孔与所述有源层连接。
在一些实施例中，所述薄膜晶体管的所述第二极通过设置在所述层间介电层中的第一接触过孔与所述微型发光二极管的所述第一电极连接，并且所述微型发光二极管的所述第二电极与所述公共电极连接。
在一些实施例中，所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第二电极接触，并且所述微型发光二极管的所述第一电极与所述公共电极连接。
在一些实施例中，所述薄膜晶体管为底栅结构，在该底栅结构中所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第一电极 形成所述一体结构，所述一体结构的一端与所述有源层接触以构成所述薄膜晶体管的所述第二极，所述一体结构的另一端构成所述微型发光二极管的所述第一电极。
在一些实施例中，所述薄膜晶体管为底栅结构，在该底栅结构中所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第一电极形成所述一体结构。所述阵列基板还包括设置在所述有源层远离所述衬底基板的一侧的保护层，并且其中所述薄膜晶体管的所述第一极和所述一体结构设置在所述保护层远离所述衬底基板的一侧。所述薄膜晶体管的所述第一极通过设置在所述保护层中的第三过孔与所述有源层连接；所述一体结构的一端通过设置在所述保护层中的第四过孔与所述有源层连接以构成所述薄膜晶体管的所述第二极；并且所述一体结构的另一端构成所述微型发光二极管的所述第一电极。
在一些实施例中，所述公共电极与所述微型发光二极管的所述第一电极同层设置。在所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第一电极连接的情况下，所述微型发光二极管的所述第一电极与所述公共电极彼此空间相隔设置，所述微型发光二极管的所述第二电极与连接电极接触，并且所述连接电极通过第三接触过孔与所述公共电极连接。在所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第二电极连接的情况下，所述微型发光二极管的所述第一电极与所述公共电极形成一体结构。
在一些实施例中，所述公共电极设置在所述微型发光二极管的所述第二电极远离所述衬底基板的一侧，并且所述阵列基板还包括设置在所述公共电极与所述第二电极之间的绝缘层。在所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第一电极连接的情况下，所述公共电极通过设置在所述绝缘层中的第四接触过孔与所述微型发光二极管的所述第二电极连接。在所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第二电极连接的情况下，所述公共电极通过贯穿所述绝缘层的第五接触过孔与所述微型发光二极管的所述第一电极连接。
根据本公开的另一方面，提供了一种制造阵列基板的方法，包括：在衬底基板上形成薄膜晶体管，并在所述薄膜晶体管的栅绝缘层远离所述衬底基板的一侧形成微型发光二极管，其中所述薄膜晶体管包括： 与栅线连接的栅极；有源层；将所述栅极与所述有源层绝缘的所述栅绝缘层；与数据线连接的第一极；以及与所述第一极空间相隔的第二极，并且所述微型发光二极管包括第一电极、发光层和第二电极；将所述薄膜晶体管的第二极连接到所述微型发光二极管的所述第一电极和所述第二电极中的一个电极；并且将所述微型发光二极管的所述第一电极和所述第二电极中的另一电极连接到公共电极。
在一些实施例中，形成微型发光二极管包括：在所述栅绝缘层远离所述衬底基板的一侧依次形成第一半导体层、所述发光层以及第二半导体层；在所述栅绝缘层远离所述衬底基板的一侧形成与所述第一半导体层接触的所述微型发光二极管的第一电极；并且在所述第二半导体层远离所述衬底基板的一侧形成所述微型发光二极管的第二电极。
在一些实施例中，在形成第一半导体层之前，所述方法还包括：在所述栅绝缘层远离所述衬底基板的一侧形成缓冲层。所述第一半导体层形成在所述缓冲层远离所述衬底基板的一侧，且与所述微型发光二极管的所述第一电极接触。
在一些实施例中，所述薄膜晶体管为顶栅结构，在所述顶栅结构中所述栅极与所述微型发光二极管的所述第一电极同层且彼此空间相隔设置。所述形成薄膜晶体管包括：在所述衬底基板上形成所述有源层；在所述有源层远离所述衬底基板的一侧形成所述栅绝缘层；在所述栅绝缘层远离所述衬底基板的一侧形成所述栅极；在所述栅极远离所述衬底基板的一侧形成层间介电层；在所述衬底基板上形成贯穿所述层间介电层和所述栅绝缘层的第一过孔和第二过孔；并且在所述层间介电层远离所述衬底基板的一侧形成所述薄膜晶体管的所述第一极和所述第二极，其中所述薄膜晶体管的所述第一极通过所述第一过孔与所述有源层连接，并且所述薄膜晶体管的所述第二极通过所述第二过孔与所述有源层连接。
在一些实施例中，在形成所述薄膜晶体管的所述第一极和所述第二极之前，所述方法还包括：在所述层间介电层中形成第一接触过孔以将所述第一电极露出。所述薄膜晶体管的所述第二极通过所述第一接触过孔与所述微型发光二极管的所述第一电极连接，并且所述微型发光二极管的所述第二电极与所述公共电极连接。
在一些实施例中，所述薄膜晶体管为底栅结构，在该底栅结构中 所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第一电极形成所述一体结构。所述形成薄膜晶体管包括：在所述衬底基板上依次形成所述薄膜晶体管的栅极、栅绝缘层和有源层；并且在所述衬底基板上形成所述薄膜晶体管的所述第一极和所述一体结构，其中所述一体结构的一端与所述有源层接触以构成所述薄膜晶体管的所述第二极，并且所述一体结构的另一端构成所述微型发光二极管的所述第一电极。
在一些实施例中，所述薄膜晶体管为底栅结构，在该底栅结构中所述薄膜晶体管所述第二极与所述微型发光二极管的所述第一电极形成所述一体结构。所述形成薄膜晶体管包括：在所述衬底基板上依次形成所述薄膜晶体管的栅极、栅绝缘层和有源层；在所述有源层远离所述衬底基板的一侧形成保护层；在所述保护层中形成用于露出所述有源层的第三过孔和第四过孔，以及用于露出所述微型发光二极管的第一半导体层的第二接触过孔；并且在所述保护层远离所述衬底基板的一侧形成所述薄膜晶体管的所述第一极和所述一体结构，其中所述薄膜晶体管的所述第一极通过所述第三过孔与所述有源层连接，所述一体结构的一端通过所述第四过孔与所述有源层连接以构成所述薄膜晶体管的所述第二极，并且所述一体结构的另一端通过所述第二接触过孔与所述第一半导体层连接以构成所述微型发光二极管的所述第一电极。
在一些实施例中，所述形成微型发光二极管包括通过一次构图工艺同层形成所述公共电极和所述微型发光二极管的所述第一电极。在形成所述微型发光二极管的所述第二电极之后，所述方法还包括：形成第三接触过孔以将所述公共电极露出；并且形成连接电极，所述连接电极通过所述第三接触过孔将所述微型发光二极管的所述第二电极与所述公共电极连接。
在一些实施例中，所述方法还包括在所述微型发光二极管的所述第二电极远离所述衬底基板的一侧形成绝缘层。在所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第一电极连接的情况下，所述方法还包括：在所述绝缘层中形成第四接触过孔以将所述微型发光二极管的所述第二电极露出；并且在所述绝缘层上形成所述公共电极，其中所述公共电极通过所述第四接触过孔与所述第二电极连接。在所 述薄膜晶体管的所述第二极与所述微型发光二极管的所述第二电极连接的情况下，所述方法还包括：形成第五接触过孔以将所述第一电极露出；并且在所述绝缘层上形成所述公共电极，其中所述公共电极通过所述第五接触过孔与所述第一电极连接。
根据本公开的又另一方面，提供了一种显示装置，包括如上所述的阵列基板。
附图说明
图1是根据本公开实施例的阵列基板的结构的示意性截面图；
图2A是根据本公开另一实施例的阵列基板的结构的示意性截面图；
图2B是根据本公开又一实施例的阵列基板的结构的示意性截面图；
图2C是图2A的阵列基板的结构的示意性俯视图；
图3A是根据本公开又一实施例的阵列基板的结构的示意性截面图；
图3B是根据本公开又一实施例的阵列基板的结构的示意性截面图；
图3C是根据本公开又一实施例的阵列基板的结构的示意性截面图；
图4A是根据本公开又一实施例的阵列基板的结构的示意性截面图；
图4B是根据本公开又一实施例的阵列基板的结构的示意性截面图；
图5A是根据本公开又一实施例的阵列基板的结构的示意性截面图；
图5B是根据本公开又一实施例的阵列基板的结构的示意性截面图；
图6是根据本公开实施例的制造阵列基板的方法的流程图；
图7A是根据本公开另一实施例的制造阵列基板的方法的流程图；
图7B是示出通过在衬底基板上形成有源层而得到的结构的示意性截面图；
图7C是示出对图7B的有源层进行研磨的示意图；
图7D是示出通过在图7C的有源层上形成栅绝缘层而得到的结构的示意性截面图；
图7E是示出通过在图7D的栅绝缘层上形成缓冲层、第一半导体层、发光层和第二半导体层而得到的结构的示意性截面图；
图7F是示出通过从图7E的结构中去除栅绝缘层上的位于非像素区域的膜层而得到的结构的示意性截面图；
图7G是示出在图7F的结构上形成栅极、第一电极和第二电极而得到的结构的示意性截面图；
图7H是示出在图7G的结构中形成过孔而得到的结构的示意性截面图；
图8A是根据本公开实施例的制造薄膜晶体管的方法的流程图；
图8B是根据本公开另一实施例的制造薄膜晶体管的方法的流程图；并且
图9是根据本公开实施例的显示装置的示意性框图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
将理解的是，尽管术语第一、第二、第三等等在本文中可以用来描述各种元件、部件、区、层和/或部分，但是这些元件、部件、区、层和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件、区、层或部分与另一个区、层或部分相区分。因此，下面讨论的第一元件、部件、区、层或部分可以被称为第二元件、部件、区、层或部分而不偏离本公开的教导。
诸如“在...下面”、“在...之下”、“较下”、“在...下方”、“在...之上”、“较上”等等之类的空间相对术语在本文中可以为了便于描述而用来描述如图中所图示的一个元件或特征与另一个(些)元件或特征的关系。将理解的是，这些空间相对术语意图涵盖除了图中描绘的取向之外在使用或操作中的器件的不同取向。例如，如果翻转图中的器件，那么被描述为“在其他元件或特征之下”或“在其他元件或特征下面”或“在其他元件或特征下方”的元件将取向为“在其他元件或特征之上”。因此，示例性术语“在...之下”和“在...下方”可以涵盖在...之上和在...之下的取向两者。诸如“在...之前”或“在...前”和“在...之后”或“接着是”之类的术语可以类似地例如用来指示光穿过元件所依的次序。器件可以取向为其他方式(旋转90度或以其他取向)并且相应地解释本文中使用的空间相对描述符。另 外，还将理解的是，当层被称为“在两个层之间”时，其可以是在该两个层之间的唯一的层，或者也可以存在一个或多个中间层。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述及特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。
将理解的是，当元件或层被称为“在另一个元件或层上”、“连接到另一个元件或层”、“耦合到另一个元件或层”或“邻近另一个元件或层”时，其可以直接在另一个元件或层上、直接连接到另一个元件或层、直接耦合到另一个元件或层或者直接邻近另一个元件或层，或者可以存在中间元件或层。相反，当元件被称为“直接在另一个元件或层上”、“直接连接到另一个元件或层”、“直接耦合到另一个元件或层”、“直接邻近另一个元件或层”时，没有中间元件或层存在。然而，在任何情况下“在...上”或“直接在...上”都不应当被解释为要求一个层完全覆盖下面的层。
本文中参考本公开的理想化实施例的示意性图示(以及中间结构)描述本公开的实施例。正因为如此，应预期例如作为制造技术和/或公差的结果而对于图示形状的变化。因此，本公开的实施例不应当被解释为限于本文中图示的区的特定形状，而应包括例如由于制造导致的形状偏差。因此，图中图示的区本质上是示意性的，并且其形状不意图图示器件的区的实际形状并且不意图限制本公开的范围。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
图1是根据本公开实施例的阵列基板的结构的示意性截面图。该阵列基板可以包括阵列排布的多个像素，尽管为了图示的方便仅示出了单个像素。
参考图1，像素包括设置在衬底基板00上的薄膜晶体管10。薄膜晶体管10包括与栅线(图1中未示出)连接的栅极12、有源层15、将所述栅极与有源层15相绝缘的栅绝缘层11、与数据线(图1中未示出)连接的第一极13、以及与第一极13空间相隔的第二极14。
像素还包括设置在栅绝缘层11远离该衬底基板00一侧的微型LED 20。该微型LED 20包括第一电极21、发光层22和第二电极23。在该实施例中，该薄膜晶体管10的第二极14与该第一电极21连接，并且该第二电极23与用于接收公共电压的公共电极(图1中未示出)连接。在其他实施例中，该薄膜晶体管10的第二极14可以与该第二电极23连接，并且该第一电极21可以与公共电极连接。微型LED 20的与薄膜晶体管10的第二极14连接的电极(在该示例中第一电极21)可以称为阳极，微型LED 20的与该公共电极连接的电极(在该示例中第二电极23)可以称为阴极。
该薄膜晶体管10用于驱动该微型LED 20发光。第一极13可以为源极，第二极14可以为漏极。替换地，第一极13可以为漏极，第二极14可以为源极。该第一电极21可以为N型电极，第二电极23可以为P型电极。在一些示例中，各个像素的微型LED可以共用阳极，即各个像素的微型LED的阳极可以为同一个电极。
该微型LED 20中的发光层22可以由III-V族化合物(包括二元化合物、三元化合物或四元化合物等)材料形成。III-V族化合物是指由元素周期表中III族元素与V族元形成的化合物，该III族元素包括硼(B)、铝(Al)、镓(Ga)和铟(In)等，V族元素包括氮(N)、磷(P)、砷(As)和锑(Sb)等。该III-V族化合物一般包括镓化砷(GaAs)、磷化铟(InP)和氮化镓(GaN)等。该III-V族化合物材料形成的半导体发光层具有高的发光效率，良好的稳定性和长的寿命。
在操作中，施加到阵列基板的该公共电极的电压可以与传统显示装置的公共电极电压不同。例如，传统显示装置中的公共电极电压可以是0伏特(V)，或者0V附近，例如-5V至5V之间；而在本公开实施例的阵列基板中，施加到公共电极的电压可以不局限于上述范围。 根据微型LED的工作需求(发光亮度需求或发光效率需求)，施加到该公共电极的阴极电压的范围在-20V至20V之间，通常不为0V。
图2A是根据本公开另一实施例的阵列基板的结构的示意性截面图。与图1中相同的元件由相同的附图标记指示，并且在此不再详细描述。
参考图2A，该微型LED 20还包括：设置在该发光层22靠近衬底基板00一侧的第一半导体层24，以及设置在该发光层22和该第二电极23之间的第二半导体层25。该第一电极21与该第一半导体层24接触。在该示例中，与第二电极23(阴极)接触的第二半导体层25可以为N型半导体层，与第一电极21(阳极)接触的第一半导体层24可以为P型半导体层。该N型半导体层可以由掺杂有IV族元素的III-V族化合物材料制成，例如可以由掺杂有硅(Si)原子的GaN材料制成。该P型半导体层可以由掺杂有II族元素的III-V族化合物材料制成，例如可以由掺杂有镁(Mg)原子的GaN材料制成。
继续参考图2A，该微型LED 20还包括设置在该第一半导体层24和该栅绝缘层11之间的缓冲层26。该第一电极21与该缓冲26层均位于该栅绝缘层11远离该衬底基板00的一侧。在图2A的示例中，该缓冲层26和第一半导体层24与该微型LED20中的其他膜层相比具有凸出部分，并且该第一电极21覆盖在该第一半导体层24的凸出部分，从而实现与该第一半导体层24的有效接触。
作为示例而非限制，该栅绝缘层11可以由金属氧化物材料制成，该金属氧化物材料包括：氧化铝(Al 2O 3)、氧化铁(Fe 2O 3)、三氧化二铬(Cr 2O 3)、三氧化二钛(Ti 2O 3)、氧化钒(V 2O 3)、钛酸亚铁(FeTiO 3)、钛酸镁(MgTiO 3)、氧化镧(La 2O 3)、三氧化二铈(Ce 2O 3)、氧化镓(Ga 2O 3)、氧化钪(Sc 2O 3)、氧化钐(Sm 2O 3)、三氧化二铕(Eu 2O 3)、三氧化二铽(Tb 2O 3)、氧化镝(Dy 2O 3)、三氧化二钇(Y 2O 3)、氧化钬(Ho 2O 3)、氧化铥(Tm 2O 3)、氧化镥(Lu 2O 3)以及三氧化二钕(Nd 2O 3)中的任一种或其组合。该缓冲层26可以由GaN、GaAs或InP等材料形成。
此外，如图2A所示，该衬底基板00上还可以设置有基础缓冲层01。该薄膜晶体管10以及该微型LED 20均设置在该基础缓冲层01远离衬底基板00的一侧。该基础缓冲层01可以是由氮化硅(SiN)薄膜 和二氧化硅(SiO 2)薄膜组成的复合膜结构。
图2B是根据本公开又一实施例的阵列基板的结构的示意性截面图。与图2A中相同的元件由相同的附图标记指示，并且在此不再详细描述。
参考图2B，该薄膜晶体管10的第二极14与该微型LED 20的第二电极23直接接触。在该示例中，该第二极14靠近该衬底基板00的一侧与该第二电极23远离该衬底基板00的一侧接触。另外，该第一电极21可以与公共电极(图2B中未示出)连接。
在图2A和图2B的示例中，该薄膜晶体管10为顶栅结构，其中该栅绝缘层11设置在栅极12靠近衬底基板00的一侧，并且有源层15设置在该栅绝缘层11靠近该衬底基板00的一侧。该微型LED 20的第一电极21与该栅极12同层且空间相隔设置。另外，该栅极12远离该衬底基板00的一侧还设置有层间介电层03，并且薄膜晶体管10的第一极13和第二极14彼此空间相隔地设置在该层间介电层03远离衬底基板00的一侧。
图2C为图2A所示结构的俯视图。参考图2A和图2C，该第一极13通过第一过孔V1与有源层15连接，该第二极14通过第二过孔V2与该有源层15连接，并且第二极14通过第一接触过孔CV1与该第一电极21连接。此外，从图2C可以看出，薄膜晶体管的第一极13与数据线130连接，薄膜晶体管的栅极12与栅线120连接。
图3A是根据本公开又一实施例的阵列基板的结构的示意性截面图。
如图3A所示，该薄膜晶体管10为底栅结构，且该微型LED 20的第一电极21与该薄膜晶体管10的第二极14形成一体结构。该一体结构与有源区15接触的部分构成该薄膜晶体管10的第二极14，该一体结构与第一半导体层24接触的部分构成该微型LED 20的第一电极21。该微型LED 20的第二电极23与公共电极(图中未示出)连接。
对于该底栅结构的薄膜晶体管10，该栅绝缘层11设置在该栅极12远离该衬底基板00的一侧，有源层15设置在该栅绝缘层11远离该衬底基板00的一侧，并且该薄膜晶体管10的第一极13和该一体结构均设置在该栅绝缘层11远离该衬底基板00的一侧，且均与该有源层15接触。
在该微型LED 20中，第一半导体层24和缓冲层26与该微型LED 20的其他各个膜层相比具有凸出部分。该一体结构的一端覆盖在该第一半导体层24的凸出部分，从而实现与该第一半导体层24的有效接触。
图3B是根据本公开又一实施例的阵列基板的结构的示意性截面图。与图3A中相同的元件由相同的附图标记指示，并且在此不再详细描述。
如图3B所示，该有源层15远离该衬底基板00的一侧还设置有保护层16。该薄膜晶体管10的第一极13以及第二极14与第一电极21的该一体结构均设置在该保护层16远离该衬底基板00的一侧。该第一极13通过第三过孔V3与该有源层15连接。该一体结构的一端通过第四过孔V4与该有源层15连接，构成该薄膜晶体管10的第二极14。该一体结构的另一端通过第二接触过孔CV2与该第一半导体层24连接，构成该微型LED 20的第一电极21。
为了便于实现一体结构与第一半导体层24的连接，如图3B所示，该第一半导体层24与发光层22和第二半导体层25相比具有凸出部分，使得该一体结构可以与该第一半导体层24的该凸出部分接触。
图3C是根据本公开又一实施例的阵列基板的结构的示意性截面图。与图3A中相同的元件由相同的附图标记指示，并且在此不再详细描述。
如图3C所示，该薄膜晶体管10的第二极14直接与该微型LED 20的第二电极23接触。在该示例中，第二极14靠近衬底基板00的一侧与该第二电极23远离衬底基板00的一侧接触。微型LED 20的第一电极21可以与公共电极(图中未示出)连接。
图4A是根据本公开又一实施例的阵列基板的结构的示意性截面图。与图2A中相同的元件由相同的附图标记指示，并且在此不再详细描述。
如图4A所示，公共电极30与该第一电极21同层设置。该薄膜晶体管10的第二极14与微型LED的第一电极21连接。该第二电极23远离衬底基板00的一侧还设置有连接电极31，该连接电极31通过设置在层间介电层03中的第三接触过孔CV3与该公共电极30连接。在该示例中，该连接电极31与该第一极13和第二极14同层设置，并且因此可以通过一次构图工艺形成。
图4B是根据本公开又一实施例的阵列基板的结构的示意性截面图。与图4A中相同的元件由相同的附图标记指示，并且在此不再详细描述。
如图4B所示，该薄膜晶体管10的第二极14与微型LED的第二电极23直接连接，并且该公共电极30与微型LED的该第一电极21形成一体结构。该一体结构直接与第一半导体层24接触，并且该一体结构与该第一半导体层24接触的部分构成该微型LED 20的第一电极21。
图5A是根据本公开又一实施例的阵列基板的结构的示意性截面图。与图2A中相同的元件由相同的附图标记指示，并且在此不再详细描述。
图5A所示，该公共电极30设置在该第二电极23远离该衬底基板00的一侧，且该公共电极30与该第二电极23之间形成有绝缘层32。该薄膜晶体管10的第二极14与微型LED 20的第一电极21连接，并且该公共电极30通过设置在绝缘层32中的第四接触过孔CV4与微型LED 20的该第二电极23连接。在该示例中，该薄膜晶体管10中的有源层15整层覆盖衬底基板。
图5B是根据本公开又一实施例的阵列基板的结构的示意性截面图。与图5A中相同的元件由相同的附图标记指示，并且在此不再详细描述。当该薄膜晶体管10的第二极14与第二电极23连接时，如图5B所示，该公共电极30可以通过设置在绝缘层32以及层间介电层03中的第五接触过孔CV5与第一电极21连接。在该示例中，该有源层15仅设置在薄膜晶体管10的有源区中。
在各实施例中，通过在衬底基板上设置薄膜晶体管并且在该薄膜晶体管的栅绝缘层上设置微型LED，该微型LED可以在形成薄膜晶体管的过程中同步形成，简化了阵列基板的制造工艺，降低了显示装置的制造成本。
图6是根据本公开实施例的制造阵列基板的方法的流程图。该方法可以用于制造图1至图5B任一所示的阵列基板。
在步骤101处，在衬底基板上形成薄膜晶体管，并在该薄膜晶体管的栅绝缘层远离该衬底基板的一侧形成微型发光二极管LED。该薄膜晶体管包括与栅线连接的栅极、有源层、将所述栅极与所述有源层绝缘的所述栅绝缘层、与数据线连接的第一极、以及与所述第一极空间相隔的第二极。该微型LED包括第一电极、发光层和第二电极。在步骤102处，将薄膜晶体管的第二极连接到微型发光二极管的第一电 极和第二电极中的一个电极。在步骤103处，将微型发光二极管的第一电极和第二电极中的另一电极连接到公共电极。将理解的是，虽然图6中步骤101至103被图示为彼此分离，但是它们可以是一个整体的过程。
通过在衬底基板上形成薄膜晶体管并且在该薄膜晶体管的栅绝缘层上形成微型LED，可以在制造过程中同步形成薄膜晶体管以及微型LED，从而有效简化了阵列基板的制造工艺，降低了显示装置的制造成本。有利地，相比于常规的转印工艺，本公开实施例提供的制造方法具有较短的工艺时间和较高的良率。
一般而言，上述步骤101中，形成微型LED的过程可以包括：在该栅绝缘层远离衬底基板的一侧依次形成第一半导体层、发光层以及第二半导体层；然后在栅绝缘层远离该衬底基板的一侧形成与该第一半导体层接触的第一电极，并在该第二半导体层远离该衬底基板的一侧形成第二电极。在形成第一半导体层之前，该制造方法还可以包括：在栅绝缘层远离所述衬底基板的一侧形成缓冲层。该第一半导体层可以形成在该缓冲层远离所述衬底基板的一侧，且该第一半导体层与该微型LED的其他膜层相比可以具有凸出部分。后续形成的第一电极的可以覆盖在第一半导体层凸出的部分的上方，以保证与第一半导体层的有效接触。
以图2A、图2B、图4A和图4B所示的具有顶栅结构的薄膜晶体管的阵列基板为例，下面详细介绍本公开实施例提供的阵列基板的制造方法。
参考图7A，该方法可以包括以下步骤。
步骤1011a、在衬底基板上形成基础缓冲层。该衬底基板可以为玻璃基板。该基础缓冲层可以是由氮化硅(SiN)薄膜和二氧化硅(SiO 2)薄膜组成的复合膜结构。
在实施例中，在形成该基础缓冲层时，可以先对衬底基板进行初始清洗，以清除衬底基板表面的杂质粒子，然后采用等离子体增强化学气相沉积(PECVD)法在该衬底基板的表面依次形成SiN薄膜和SiO 2薄膜，从而得到该基础缓冲层。SiN薄膜的厚度可以为50纳米(nm)至100nm，SiO 2薄膜的厚度可以为100nm至400nm。该SiN薄膜具有较强的扩散阻挡特性，可以抑制玻璃基板中的金属离子对于后续待形 成的多晶硅薄膜的影响；而SiO 2薄膜与多晶硅薄膜具有优良的界面，可以防止SiN薄膜缺陷对多晶硅薄膜质量的损害。
步骤1012a、在该基础缓冲层远离衬底基板的一侧形成有源层。可以采用PECVD法在该基础缓冲层的表面形成有源层。该有源层可以由非晶硅(a-Si)材料、多晶硅材料或者铟镓锌氧化物(IGZO)形成。
在实施例中，在形成该有源层时，可以通过PECVD法在基础缓冲层01上连续沉积一层厚度为40nm至100nm的a-Si薄膜，然后使用热处理炉对a-Si薄膜进行脱氢工艺处理，以防止结晶过程中的氢爆。之后即可进行a-Si结晶工艺以形成多晶硅薄膜。通常可以使用激光退火结晶、金属诱导结晶或固相结晶等方法对a-Si薄膜进行结晶。例如图7B所示，可以采用激光束对该a-Si薄膜进行激光退火结晶。进一步的，可以采用稀释的氢氟酸对该多晶硅薄膜进行清洗，降低多晶硅薄膜的表面粗糙度，以减少薄膜晶体管的缺陷。最后可以采用离子注入或者离子云注入的方法，对多晶硅薄膜进行薄膜晶体管的沟道掺杂从而得到该有源层。沟道掺杂的掺杂离子一般为磷化氢(PH 3)与氢气(H 2)的混合气体，或者乙硼烷(B2H6)与H2的混合气体。离子注入剂量在10 11至10 13ions/cm 2之间(ions/cm 2为负离子浓度计量单位，指每平方厘米的负离子个数)，注入能量在10至100千电子伏特(KeV)之间。沟道掺杂可以有效调整薄膜晶体管的阈值电压，改善薄膜晶体管的开关特性。
在实施例中，在沉积多晶硅薄膜之后，还可以在该多晶硅薄膜的表面沉积一层牺牲层，例如，可以沉积一层氮化硅(SiNx)作为牺牲层。进一步地，如图7C所示，可以采用具有研磨盘41和抛光垫42的化学机械抛光设备40对该牺牲层和多晶硅薄膜进行研磨。该研磨过程可以包括两个阶段，其中第一阶段用于去除牺牲层，第二阶段用于同时去除多晶硅薄膜和残余的牺牲层。由于多晶硅薄膜上表面(即远离衬底基板00的一侧)凸凹不平(多晶硅薄膜表面的凹陷处沉积的SiNx的厚度较大，多晶硅薄膜表面的凸起处沉积的SiNx的厚度较小)，因此在该第一阶段中，随着化学机械抛光设备40的研磨，SiNx被不断减薄，多晶硅薄膜的部分表面暴露出来。然后进入第二阶段，该SiNx和多晶硅薄膜的部分表面同时暴露于化学机械抛光液和机械抛光的作用之下，并且由于化学机械抛光液对多晶硅的蚀刻能力更强，因而多晶 硅被优先蚀刻去除，从而可以将粗糙的多晶硅表面的凸起部分磨平。化学机械抛光液可以采用碱性的二氧化硅抛光液。
在本公开实施例中，除了SiNx，也可以在多晶硅薄膜表面沉积一层氧化硅(SiOx)薄膜作为牺牲层。该SiOx薄膜的厚度可以为800至120埃，例如可以为90至110埃。可选地，可以通过干法氧化工艺在多晶硅薄膜表面形成SiOx薄膜，在该干法氧化工艺中可以在反应腔室内通入氧气，使得多晶硅在高温下氧化形成SiOx。氧化的温度和时间可以根据情况进行调节。该工艺较为成熟，便于工艺设计。此外，还可以选用化学气相沉积的方法沉积SiOx薄膜。例如可以采用PECVD的方法沉积SiOx薄膜。该PECVD法的效率和成本控制相对较好。本领域技术人员应该理解，可以采用其他熟知的薄膜沉积或外延方法在多晶硅薄膜表面形成SiOx薄膜。采用SiOx薄膜作为牺牲层进行化学机械抛光的过程，与采用SiNx薄膜作为牺牲层时的化学机械抛光的过程类似，其具体过程不再赘述。
进一步地，可以使用蚀刻溶液湿法刻蚀多晶硅薄膜的表面，以去除多晶硅薄膜表面残余的牺牲层材料，以及化学机械研磨处理过程产生的残留颗粒，由此进一步降低多晶硅薄膜表面的粗糙度。
步骤1013a、在该有源层远离该衬底基板的一侧形成栅绝缘层。可以采用磁控溅射工艺在有源层表面形成一层金属氧化物薄膜作为栅绝缘层，例如可以形成一层Al 2O 3薄膜作为栅绝缘层。
在实施例中，在镀膜前可以使用丙酮、乙醇和去离子水，通过超声波清洁经过化学机械研磨的多晶硅薄膜。之后即可在超高真空磁控溅射系统中，采用射频反应磁控溅射法在该抛光后的有源层表面沉积氧化铝薄膜，得到如图7D所示的栅绝缘层11。在形成该氧化铝薄膜的过程中，可以采用高纯(纯度为99.998％)氩气(Ar)作为溅射气体，并采用高纯(纯度为99.995％)氧气(O 2)作为反应气体。该两种气体经气体质量流量计精确控制后以不同比例通入真空室。真空室内Ar和O 2混合气体的总压强可以由真空计显示，且该总压强可以由真空阀控制。溅射靶材为高纯(纯度为99.99％)的Al，该高纯Al靶表面存在氧化层。在溅射时，可以先在纯Ar中预溅射20至30分钟，以除去Al靶表面的污染物。溅射参数为Ar气流量20标准毫升/分钟(sccm)，工作气压2.0帕(Pa)，溅射功率100瓦特(W)，衬底基板加热至 450摄氏度。当Al靶表面的辉光由灰蒙蒙逐渐变的明亮清晰且稳定时，可以确定表面已经被清洗干净。
溅射前的本底真空度应当高于5×10 -5Pa，其中本底真空度是指真空镀膜中利用真空抽气系统使在一定的空间内的气体达到一定的真空度。待Al靶面的电流和电压充分稳定后再转开样品挡板进行正式溅射。溅射结束后，样品在真空室内氧气气氛下原位退火。工作气氛的压力为0.5Pa，这样有利于沉积薄膜结晶形成六方晶体结构(刚玉)。并且，由于较小的冷却速率可以产生较小的内应力，同时氧气可以补充氧化铝薄膜中因溅射出现的氧缺位，因此可以使得氧化铝薄膜更好的与衬底(即有源层)附着。
在本公开实施例中，该栅绝缘层可以由金属氧化物材料形成，该金属氧化物材料除了可以为Al 2O 3，还可以为Fe 2O 3、Cr 2O 3、Ti 2O 3、V 2O 3、FeTiO 3、MgTiO 3、La 2O 3、Ce 2O 3、Ga 2O 3、Sc 2O 3、Sm 2O 3、Eu 2O 3、Tb 2O 3、Dy 2O 3、Y 2O 3、Ho 2O 3、Tm 2O 3、Lu 2O 3和Nd 2O 3中的任一种。
步骤1014a、在栅绝缘层远离该衬底基板的一侧形成缓冲层。可以采用金属有机化学气相沉积(MOCVD)法在栅绝缘层的表面沉积一层GaN薄膜作为缓冲层，该缓冲层可以提高后续待形成的半导体层的外延晶格质量。
在实施例中，为了去除衬底基板中栅绝缘层表面粘附的油污等杂质，可以先采用无水乙醇对形成有该基础缓冲层、有源层和栅绝缘层的衬底基板进行多次冲洗，然后再将该衬底基板依次放入丙酮、无水乙醇和去离子水中分别用超声波清洗10分钟，之后再用去离子水反复冲洗干净，最后用高纯氮气(N 2)吹干。在采用MOCVD沉积缓冲层时，可以采用三甲基镓(TMGa)作为镓源。将TMGa的鼓泡器放置在冷阱中，使其温度维持在-12.6摄氏度，并以H 2作为载气，以纯度为5N(即99.999％)的高纯N 2为氮源，在形成有栅绝缘层的衬底基板上进行低温沉积(沉积温度小于500摄氏度)。例如，可以将微波源功率固定在650W，本底真空度优于5.0×10 -4Pa，先在300摄氏度的环境中沉积厚度约为20nm的GaN低温缓冲层，沉积条件为TMGa和氮气的流量分别为0.4sccm和80sccm，沉积时间为5min。之后将衬底温度升高到430摄氏度，TMGa与氮气的流量分别为0.4sccm和80sccm，沉积时间增加到30min。
需要说明的是，除了可以采用GaN形成缓冲层之外，还可以采用GaAs或InP等材料形成该缓冲层。由于用于形成栅绝缘层的材料氧化铝与GaAs和GaN等材料晶体的结构相同，有利于外延生长。虽然晶格常数和热膨胀系数不匹配于需要外延生长的III-V半导体材料，但是其成本较低，且透光率可达90％，适合于激光加热工艺。
步骤1015a、在该缓冲层远离该衬底基板的一侧依次形成第一半导体层、该发光层以及第二半导体层。该第一半导体层可以为N型半导体层，该第二半导体层可以为P型半导体层。根据微型LED的发光颜色可以选择氮化铟镓(InGaN)、磷化铝铟镓(InAlGaP)、磷化镓(GaP)、磷化砷镓(GaAsP)或砷化铝镓(AlGaAs)等材料形成发光层。该发光层也可以称为量子阱。
在实施例中，如图7E所示，可以采用MOCVD工艺在该缓冲层26的表面依次形成第一半导体层24、发光层22以及第二半导体层25。具体地，可以先将衬底基板加热至600摄氏度左右的高温，并向反应室同时引入TMGa和氨(NH 3)前驱物，从而在该缓冲层26的表面依次形成N型的GaN半导体层24、InGaN或GaN量子阱22以及P型GaN半导体层25。
可选的，可以使用原位的沉积态掺杂技术形成该第一半导体层24以及第二半导体层25。该形成过程可以包括：在反应室通入TMGa和NH 3的同时加入硅烷(SiH 4)、乙硅烷(Si 2H 6)、二甲基硅烷(SiCH 8)或二氯二氢硅(SiH 2Cl 2)等硅前驱物，使得该GaN中掺入10 17至10 20cm -3的Si(即在每立方厘米的GaN中掺入10 17至10 20个Si原子)，从而沉积形成N型GaN半导体层24。之后在反应室加入镁的有机先驱物例如二茂镁(Cp 2Mg)，使得GaN中掺入10 17至10 20cm -3的Mg，从而形成P型GaN半导体层25。在形成该N型半导体层24和P型半导体层25之间，可以通过MOCVD工艺连续交替沉积纳米厚度的宽禁带材料和窄禁带半导体材料，例如交替沉积宽禁带材料铝镓氮(AlGaN)和窄禁带材料GaN，从而形成多种单量子阱或多量子阱结构。该量子阱材料中的宽禁带材料与窄禁带材料具有相匹配的晶格常数和能带(两种材料的能带差异保持在一定范围(例如1eV)以内)，从而能够调制发射波长。量子阱结构也具有复合效率高和界面复合率低的优点。
在本公开实施例中，该缓冲层26的厚度可以在0.1至5微米之间， 第一半导体层24和第二半导体层25的厚度可以在0.1至0.5微米之间，量子阱22的厚度在0.1至0.5微米之间。
步骤1016a、去除非像素区域的第二半导体层、发光层、第一半导体层以及缓冲层。
在实施例中，可以采用一次光刻工艺，在该衬底基板的表面形成图形化的光刻胶掩膜，定义出像素区域和非像素区域。该像素区域即为用于设置微型LED的区域，即该阵列基板的有效显示区域。该非像素区域即为非显示区域。该像素区域可以包括微型LED的P区、多重量子阱(multiple quantum well，MQW)区和N区，该P区、MQW区和N区在衬底基板上的正投影重合。之后，可以采用感应耦合等离子体(Inductive Coupled Plasma Emission Spectrometer，ICP)刻蚀机蚀刻掉未被光刻胶掩膜覆盖的第二半导体层、发光层、第一半导体层以及缓冲层的部分。刻蚀深度可以为1.3微米。ICP刻蚀机采用的刻蚀气体可以为氯气(Cl 2)和三氯化硼(BCl 3)。参考图7F，刻蚀后的衬底基板上，该缓冲层26和第一半导体层24与微型LED 20中的其他膜层相比可以具有凸出部分，该凸出部分构成了电极接触区。参考图7F还可以看出，在经过该刻蚀工艺后，非像素区域的栅极绝缘层11露出。
步骤1017a、在栅绝缘层远离衬底基板的一侧形成薄膜晶体管的栅极，以及与第一半导体层接触的微型LED的第一电极，并在第二半导体层远离衬底基板的一侧形成微型LED的第二电极。
在实施例中，可以在该栅绝缘层的表面沉积一层金属薄膜，然后可以通过一次构图工艺对该金属薄膜进行处理，从而形成空间相隔设置的薄膜晶体管的栅极和微型LED的第一电极。该第一电极可以覆盖在凸出的第一半导体层24上，从而实现与第一半导体层24的有效接触。
具体地，可以采用磁控溅射的方式在衬底基板的表面沉积一层厚度为200至500nm的金属薄膜。该金属薄膜可以是由钼(Mo)、钼铌合金(MoNb)、Al、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种材料形成的膜层，或者可以是由上述材料中的多种材料形成的单层或多层复合叠层。例如，可以在衬底基板表面形成Mo膜层或Al膜层，或者，形成含有Mo和Al的合金组成的单层膜层或多层复合膜层。之后，可以采用一次光刻工艺在衬底基板的表面形成图形化的光刻胶掩 膜，定义出薄膜晶体管的栅极区域、微型LED的第一电极区域，以及第二电极区域。最后可以对该金属薄膜上未被光刻胶掩膜覆盖的区域进行刻蚀，则如图7G所示，可以得到薄膜晶体管的栅极12、微型LED的第一电极21以及第二电极23。该第二电极23位于第二半导体层25远离衬底基板00的一侧，该第一电极21覆盖在第一半导体层24凸出的部分的上方。
步骤1018a、在该栅极远离该衬底基板的一侧形成层间介电层。可以采用PECVD工艺在栅极远离衬底基板的一侧形成一层层间介电层(inter-layer dielectric，ILD)。该层间介电层可以为SiOx层或者SiNx层，或者由SiOx层与SiNx层堆叠组成。
步骤1019a、在该衬底基板上形成贯穿该层间介电层和该栅绝缘层的第一过孔和第二过孔。可以通过一道光刻工艺，在该衬底基板上的源极接触区形成贯穿该层间介电层和该栅绝缘层的第一过孔，并在漏极接触区形成贯穿该层间介电层和该栅绝缘层的第二过孔。如图7H所示，可以在衬底基板上形成第一过孔V1和第二过孔32，该第一过孔V1可以将有源层15的源极接触区漏出，该第二过孔32可以将有源层15的漏极接触区漏出。
需要说明的是，在上述步骤1018a中形成的层间介电层可以整层覆盖在衬底基板的表面，并且在步骤1019a中通过一次光刻工艺形成第一过孔和第二过孔的同时，还可以将该层间介电层中覆盖在第二电极23上方的部分去除。
步骤1020a、在该层间介电层远离该衬底基板的一侧形成薄膜晶体管的空间相隔设置的第一极和第二极。在实施例中，可以先在该层间介电层的表面沉积金属薄膜，然后采用一道光刻工艺对该金属薄膜进行图形化处理，形成薄膜晶体管的第一极和第二极。该第一极通过第一过孔与有源层中的源极接触区接触，该第二极通过第二过孔与有源层的漏极接触区接触。
在该步骤中，金属薄膜可以由Cu、Al、Mo、Ti、铬(Cr)或钨(W)等金属材料中的任一种金属材料形成。替换地，该金属薄膜也可以是由多种金属材料组成的多层金属薄膜结构。例如，该金属薄膜可以为三层金属薄膜，形成该三层金属薄膜的金属材料可以为Mo、Al和Mo，或者Ti、Al和Ti，或者Ti、Cu和Ti，或者Mo、Cu和Ti。
作为一种可选的实现方式，在上述步骤1020a之前，该方法还可以包括：在该层间介电层中形成第一接触过孔，以将该第一电极露出。该第一接触过孔可以与第一过孔和第二过孔同步形成。如图7H所示，可以形成第一接触过孔33。在上述步骤1020a中所形成的薄膜晶体管的第二极还可以通过该第一接触过孔33与第一电极21连接，并且该第二电极23可以与公共电极30连接。最终形成的阵列基板的结构可以参考图2A、图4A或图5A。
作为另一种可选的实现方式，上述步骤1020a中形成的薄膜晶体管的第二极靠近该衬底基板的一侧，可以与微型LED的该第二电极远离该衬底基板的一侧接触。也即是，薄膜晶体管的第二极14与微型LED的第二电极23连接，并且微型LED的该第一电极21与公共电极30连接。最终形成的阵列基板的结构可以参考图2B、图4B或图5B。
需要说明的是，上述图7A所示的方法是示例性的，并且这些步骤的先后顺序可以进行适当调整。例如，可以先形成栅极和第一电极，然后再依次形成微型LED中的缓冲层、第一半导体层、发光层、第二半导体层及第二电极。也即是，上述步骤1017a中形成栅极和第一电极的操作可以在步骤1014a之前执行，上述步骤1017a中形成第二电极的操作可以在步骤1016a之后执行，并且上述步骤1016a可以省略。
下面参考图8A和3A描述具有底栅结构的薄膜晶体管的阵列基板的制造方法。
步骤1011b、在衬底基板00上形成栅极12。
步骤1012b、在栅极12远离该衬底基板00的一侧形成栅绝缘层11。
步骤1013b、在栅绝缘层11远离该衬底基板00的一侧依次形成微型LED20中的缓冲层26、第一半导体层24、发光层22和第二半导体层25。
步骤1014b、在该栅绝缘层11远离该衬底基板00的一侧形成有源层15。
步骤1015b、在该栅绝缘层11远离该衬底基板00的一侧形成与该有源层15接触的第一极13和一体结构，并在该第二半导体层25远离衬底基板00的一侧形成第二电极23。
该一体结构与有源层15接触的一端构成薄膜晶体管10的第二极 14，该一体结构的另一端与微型LED 20的第一半导体层24接触，构成该微型LED 20的第一电极21。
上述步骤1011b至步骤1015b可以按照上面参考图7A描述的示实施例中的对应步骤来执行，此处不再赘述。
下面参考图8B和3B描述具有底栅结构的薄膜晶体管的阵列基板的制造方法。
步骤1011c、在衬底基板00上形成栅极12。
步骤1012c、在该栅极12远离该衬底基板00的一侧形成栅绝缘层11。
步骤1013c、在栅绝缘层11远离该衬底基板00的一侧依次形成微型LED20中的缓冲层26、第一半导体层24、发光层22和第二半导体层25。
步骤1014c、在该栅绝缘层11远离该衬底基板00的一侧形成有源层15。
步骤1015c、在该有源层15远离该衬底基板00的一侧形成保护层16。
步骤1016c、在该保护层16中形成用于露出该有源层15的第三过孔V3和第四过孔V4，以及用于露出该第一半导体层24的第二接触过孔CV2。
步骤1017c、在该保护层16远离该衬底基板00的一侧形成薄膜晶体管10的第一极13和一体结构，并在该第二半导体层25远离衬底基板00的一侧形成第二电极23。
该第一极13通过该第三过孔V3与该有源层15连接。该一体结构的一端通过该第四过孔V4与该有源层15连接，构成该薄膜晶体管10的第二极14，该一体结构的另一端通过该第二接触过孔CV2与该第一半导体层24连接，构成该微型LED 20的第一电极21。
上述步骤1011c至步骤1017c可以按照上面参考图7A描述的实施例中的对应步骤来执行，此处不再赘述。
下面参考图4A、4B、5A和5B描述公共电极30的制作。
参考图4A，该公共电极30与该微型LED 20的第一电极21可以通过一次构图工艺同层形成。在形成该微型LED 20的第二电极23之后，形成第三接触过孔CV3，以将该公共电极30露出。在该示例中， 可以在层间介电层03中形成第一接触过孔CV1的同时，形成该第三接触过孔CV3。在该第二电极23远离该衬底基板00的一侧形成连接电极31，该连接电极31通过该第三接触过孔CV3与该公共电极30连接。在该示例中，该连接电极31可以与该薄膜晶体管10的第一极13以及第二极14通过一次构图工艺同层形成。
参考图4B，该公共电极30与该微型LED 20的第一电极21可以通过一次构图工艺同层形成。在该示例中，该公共电极30与该第一电极21可以为一体结构，也即是，可以直接采用该公共电极30作为该微型LED 20的第一电极21。
参考图5A，该公共电极30形成在微型LED 20的第二电极23远离衬底基板00的一侧，且该公共电极30与该第二电极23之间形成有绝缘层32。在绝缘层32中形成第四接触过孔CV4，以将该第二电极23露出。该公共电极30通过该第四接触过孔CV4与该第二电极23连接。
参考图5B，第二电极23远离衬底基板00的一侧还形成有绝缘层32。在该绝缘层32以及层间介电层03中形成有用于露出该第一电极21的第五接触过孔CV5。该公共电极30形成在该绝缘层32远离衬底基板00的一侧，并通过该第五接触过孔CV5与第一电极21连接。
图9是根据本公开实施例的显示装置的示意性框图。该显示装置可以为：液晶面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
参照图9，显示装置包括时序控制器910、扫描驱动器920、数据驱动器930和显示基板950。
时序控制器910从系统接口接收同步信号和视频信号R、G和B。同步信号包括水平同步信号Hsync、垂直同步信号Vsync、主时钟信号MCLK以及数据使能信号DE。视频信号R、G和B包含多个像素PX中每个的亮度信息。时序控制器910根据视频信号R、G和B、水平同步信号Hsync、垂直同步信号Vsync、数据使能信号DE以及主时钟信号MCLK生成第一驱动控制信号CONT1、第二驱动控制信号CONT2和图像数据信号DAT。
显示基板950包括有基本以矩阵形式排列的像素PX。在显示基板950中，多个基本平行的扫描线S1至Sn沿着行方向延伸，并且多个基 本平行的数据线D1至Dm沿着列方向延伸。扫描线S1至Sn和数据线D1至Dm被耦合到像素PX。显示基板950可以采取上面关于图1至图5B描述的阵列基板实施例中的任一个的形式。
扫描驱动器920被耦合到扫描线S1-Sn，并且根据第一驱动控制信号CONT1生成对应的多个扫描信号S[1]至S[n]。扫描驱动器920可以将扫描信号S[1]-S[n]依次施加到扫描线S1-Sn。
数据驱动器930被耦合到数据线D1-Dm，根据第二驱动控制信号CONT2采样和保持图像数据信号DAT，并且分别将多个数据信号D[1]至D[m]施加到数据线D1至Dm。通过与扫描信号S[1]至S[n]同步地将数据信号D[1]至D[m]施加到数据线D1至Dm，数据驱动器930可以将数据编程到像素PX。
以上所述仅为本申请的特定实施例，并不用以限制本申请。本领域普通技术人可以对所描述的实施例作出修改、等同替换或改进而不脱离本申请的范围。

Claims (22)

  1. 一种阵列基板，包括：
    衬底基板；
    薄膜晶体管，设置在所述衬底基板上，所述薄膜晶体管包括：与栅线连接的栅极；有源层；将所述栅极与所述有源层相绝缘的栅绝缘层；与数据线连接的第一极；以及与所述第一极空间相隔的第二极；
    微型发光二极管，设置在所述栅绝缘层远离所述衬底基板一侧，所述微型发光二极管包括第一电极、发光层和第二电极；以及
    公共电极，
    其中所述薄膜晶体管的第二极与所述微型发光二极管的所述第一电极和所述第二电极中的一个电极连接，并且
    其中所述微型发光二极管的所述第一电极和所述第二电极中的另一电极与公共电极连接。
  2. 根据权利要求1所述的阵列基板，其中所述微型发光二极管还包括：设置在所述发光层靠近所述衬底基板一侧的第一半导体层，以及设置在所述发光层和所述第二电极之间的第二半导体层，所述第一半导体层与所述微型发光二极管的所述第一电极接触。
  3. 根据权利要求2所述的阵列基板，其中所述微型发光二极管还包括设置在所述第一半导体层和所述栅绝缘层之间的缓冲层，并且其中所述缓冲层与所述微型发光二极管的所述第一电极均位于所述栅绝缘层远离所述衬底基板的一侧。
  4. 根据权利要求1至3任一所述的阵列基板，其中所述栅绝缘层由金属氧化物材料制成，所述金属氧化物材料包括从由氧化铝、氧化铁、三氧化二铬、三氧化二钛、氧化钒、钛酸亚铁、钛酸镁、氧化镧、三氧化二铈、氧化镓、氧化钪、氧化钐、三氧化二铕、三氧化二铽、氧化镝、三氧化二钇、氧化钬、氧化铥、氧化镥以及三氧化二钕所组成的组中选择的至少一个。
  5. 根据权利要求1至3任一所述的阵列基板，其中所述薄膜晶体管为从由顶栅结构和底栅结构所组成的组中选择的结构，在所述顶栅结构中所述栅极与所述微型发光二极管的所述第一电极同层设置且彼此空间相隔，在所述底栅结构中所述薄膜晶体管的所述第二极与所述 微型发光二极管的所述第一电极形成一体结构或与所述微型发光二极管的所述第二电极连接。
  6. 根据权利要求5所述的阵列基板，其中所述薄膜晶体管为顶栅结构，其中所述阵列基板还包括设置在所述栅极远离所述衬底基板的一侧的层间介电层，其中：
    所述栅绝缘层设置在所述栅极靠近所述衬底基板的一侧；
    所述有源层设置在所述栅绝缘层靠近所述衬底基板的一侧；并且
    所述薄膜晶体管的第一和第二极设置在所述层间介电层远离所述衬底基板的一侧，所述薄膜晶体管的所述第一极通过设置在所述层间介电层中的第一过孔与所述有源层连接，所述薄膜晶体管的所述第二极通过设置在所述层间介电层中的第二过孔与所述有源层连接。
  7. 根据权利要求6所述的阵列基板，其中所述薄膜晶体管的所述第二极通过设置在所述层间介电层中的第一接触过孔与所述微型发光二极管的所述第一电极连接，并且其中所述微型发光二极管的所述第二电极与所述公共电极连接。
  8. 根据权利要求6所述的阵列基板，其中所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第二电极接触，并且其中所述微型发光二极管的所述第一电极与所述公共电极连接。
  9. 根据权利要求5所述的阵列基板，其中所述薄膜晶体管为底栅结构，在该底栅结构中所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第一电极形成所述一体结构，所述一体结构的一端与所述有源层接触以构成所述薄膜晶体管的所述第二极，所述一体结构的另一端构成所述微型发光二极管的所述第一电极。
  10. 根据权利要求5所述的阵列基板，其中所述薄膜晶体管为底栅结构，在该底栅结构中所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第一电极形成所述一体结构，其中所述阵列基板还包括设置在所述有源层远离所述衬底基板的一侧的保护层，并且其中所述薄膜晶体管的所述第一极和所述一体结构设置在所述保护层远离所述衬底基板的一侧，其中：
    所述薄膜晶体管的所述第一极通过设置在所述保护层中的第三过孔与所述有源层连接；
    所述一体结构的一端通过设置在所述保护层中的第四过孔与所述 有源层连接以构成所述薄膜晶体管的所述第二极；并且
    所述一体结构的另一端构成所述微型发光二极管的所述第一电极。
  11. 根据权利要求5所述的阵列基板，其中所述公共电极与所述微型发光二极管的所述第一电极同层设置，其中：
    在所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第一电极连接的情况下，所述微型发光二极管的所述第一电极与所述公共电极彼此空间相隔设置，所述微型发光二极管的所述第二电极与连接电极接触，并且所述连接电极通过第三接触过孔与所述公共电极连接；并且
    在所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第二电极连接的情况下，所述微型发光二极管的所述第一电极与所述公共电极形成一体结构。
  12. 根据权利要求5所述的阵列基板，其中所述公共电极设置在所述微型发光二极管的所述第二电极远离所述衬底基板的一侧，并且其中所述阵列基板还包括设置在所述公共电极与所述第二电极之间的绝缘层，其中：
    在所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第一电极连接的情况下，所述公共电极通过设置在所述绝缘层中的第四接触过孔与所述微型发光二极管的所述第二电极连接；并且
    在所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第二电极连接的情况下，所述公共电极通过贯穿所述绝缘层的第五接触过孔与所述微型发光二极管的所述第一电极连接。
  13. 一种制造阵列基板的方法，包括：
    在衬底基板上形成薄膜晶体管，并在所述薄膜晶体管的栅绝缘层远离所述衬底基板的一侧形成微型发光二极管，其中所述薄膜晶体管包括：与栅线连接的栅极；有源层；将所述栅极与所述有源层绝缘的所述栅绝缘层；与数据线连接的第一极；以及与所述第一极空间相隔的第二极，并且所述微型发光二极管包括第一电极、发光层和第二电极；
    将所述薄膜晶体管的第二极连接到所述微型发光二极管的所述第一电极和所述第二电极中的一个电极；并且
    将所述微型发光二极管的所述第一电极和所述第二电极中的另一 电极连接到公共电极。
  14. 根据权利要求13所述的方法，其中形成微型发光二极管包括：
    在所述栅绝缘层远离所述衬底基板的一侧依次形成第一半导体层、所述发光层以及第二半导体层；
    在所述栅绝缘层远离所述衬底基板的一侧形成与所述第一半导体层接触的所述微型发光二极管的第一电极；并且
    在所述第二半导体层远离所述衬底基板的一侧形成所述微型发光二极管的第二电极。
  15. 根据权利要求14所述的方法，其中在形成第一半导体层之前，所述方法还包括：
    在所述栅绝缘层远离所述衬底基板的一侧形成缓冲层，
    其中所述第一半导体层形成在所述缓冲层远离所述衬底基板的一侧，且与所述微型发光二极管的所述第一电极接触。
  16. 根据权利要求13至15中任一项所述的方法，其中所述薄膜晶体管为顶栅结构，在所述顶栅结构中所述栅极与所述微型发光二极管的所述第一电极同层且彼此空间相隔设置，并且其中所述形成薄膜晶体管包括：
    在所述衬底基板上形成所述有源层；
    在所述有源层远离所述衬底基板的一侧形成所述栅绝缘层；
    在所述栅绝缘层远离所述衬底基板的一侧形成所述栅极；
    在所述栅极远离所述衬底基板的一侧形成层间介电层；
    在所述衬底基板上形成贯穿所述层间介电层和所述栅绝缘层的第一过孔和第二过孔；并且
    在所述层间介电层远离所述衬底基板的一侧形成所述薄膜晶体管的所述第一极和所述第二极，其中所述薄膜晶体管的所述第一极通过所述第一过孔与所述有源层连接，并且所述薄膜晶体管的所述第二极通过所述第二过孔与所述有源层连接。
  17. 根据权利要求16所述的方法，其中在形成所述薄膜晶体管的所述第一极和所述第二极之前，所述方法还包括：
    在所述层间介电层中形成第一接触过孔以将所述第一电极露出，
    其中所述薄膜晶体管的所述第二极通过所述第一接触过孔与所述微型发光二极管的所述第一电极连接，并且其中所述微型发光二极管 的所述第二电极与所述公共电极连接。
  18. 根据权利要求13至15中任一项所述的方法，其中所述薄膜晶体管为底栅结构，在该底栅结构中所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第一电极形成所述一体结构，并且其中所述形成薄膜晶体管包括：
    在所述衬底基板上依次形成所述薄膜晶体管的栅极、栅绝缘层和有源层；并且
    在所述衬底基板上形成所述薄膜晶体管的所述第一极和所述一体结构，其中所述一体结构的一端与所述有源层接触以构成所述薄膜晶体管的所述第二极，并且所述一体结构的另一端构成所述微型发光二极管的所述第一电极。
  19. 根据权利要求13至15中任一项所述的方法，其中所述薄膜晶体管为底栅结构，在该底栅结构中所述薄膜晶体管所述第二极与所述微型发光二极管的所述第一电极形成所述一体结构，并且其中所述形成薄膜晶体管包括：
    在所述衬底基板上依次形成所述薄膜晶体管的栅极、栅绝缘层和有源层；
    在所述有源层远离所述衬底基板的一侧形成保护层；
    在所述保护层中形成用于露出所述有源层的第三过孔和第四过孔，以及用于露出所述微型发光二极管的第一半导体层的第二接触过孔；并且
    在所述保护层远离所述衬底基板的一侧形成所述薄膜晶体管的所述第一极和所述一体结构，其中所述薄膜晶体管的所述第一极通过所述第三过孔与所述有源层连接，所述一体结构的一端通过所述第四过孔与所述有源层连接以构成所述薄膜晶体管的所述第二极，并且所述一体结构的另一端通过所述第二接触过孔与所述第一半导体层连接以构成所述微型发光二极管的所述第一电极。
  20. 根据权利要求13至15中任一项所述的方法，其中所述形成微型发光二极管包括通过一次构图工艺同层形成所述公共电极和所述微型发光二极管的所述第一电极，并且其中在形成所述微型发光二极管的所述第二电极之后，所述方法还包括：
    形成第三接触过孔以将所述公共电极露出；并且
    形成连接电极，所述连接电极通过所述第三接触过孔将所述微型发光二极管的所述第二电极与所述公共电极连接。
  21. 根据权利要求13至15中任一项所述的方法，还包括在所述微型发光二极管的所述第二电极远离所述衬底基板的一侧形成绝缘层，
    其中在所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第一电极连接的情况下，所述方法还包括：
    在所述绝缘层中形成第四接触过孔以将所述微型发光二极管的所述第二电极露出；并且
    在所述绝缘层上形成所述公共电极，其中所述公共电极通过所述第四接触过孔与所述第二电极连接；并且
    其中在所述薄膜晶体管的所述第二极与所述微型发光二极管的所述第二电极连接的情况下，所述方法还包括：
    形成第五接触过孔以将所述第一电极露出；并且
    在所述绝缘层上形成所述公共电极，其中所述公共电极通过所述第五接触过孔与所述第一电极连接。
  22. 一种显示装置，包括如权利要求1至12任一所述的阵列基板。
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