WO2019140946A1 - 一种发光控制电路、发光控制驱动器以及显示装置 - Google Patents

一种发光控制电路、发光控制驱动器以及显示装置 Download PDF

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Publication number
WO2019140946A1
WO2019140946A1 PCT/CN2018/107595 CN2018107595W WO2019140946A1 WO 2019140946 A1 WO2019140946 A1 WO 2019140946A1 CN 2018107595 W CN2018107595 W CN 2018107595W WO 2019140946 A1 WO2019140946 A1 WO 2019140946A1
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Prior art keywords
thin film
film transistor
signal
control unit
control circuit
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PCT/CN2018/107595
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English (en)
French (fr)
Inventor
吴剑龙
胡思明
朱晖
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昆山国显光电有限公司
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Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Priority to KR1020197035935A priority Critical patent/KR102271633B1/ko
Priority to JP2019569419A priority patent/JP6829329B2/ja
Priority to EP18901277.6A priority patent/EP3624100B1/en
Priority to US16/355,282 priority patent/US20190213939A1/en
Publication of WO2019140946A1 publication Critical patent/WO2019140946A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an illumination control circuit, an illumination control driver, and a display device.
  • a plurality of pixels, a data driver, a scan driver, and an illumination control driver may be included in the display device.
  • a data driver is used to supply data voltages to the pixels
  • a scan driver is used to provide scanning signals for the pixels
  • an illumination control driver is used to provide illumination control signals for the pixels
  • the illumination control signals can control the illumination of the pixels.
  • an illumination control driver it can include a multi-level illumination control circuit, and each stage of illumination control circuitry can be used to control the illumination time of a row of pixels.
  • each stage of illumination control circuitry can be used to control the illumination time of a row of pixels.
  • the first-level illumination control circuits which may include a plurality of thin film transistors, an initial signal, a plurality of clock signals, the initial signal and the plurality of clock signals may control the thin film transistor to be in an on state or an on state, thereby enabling the illumination control circuit to The illumination control signal is output.
  • the number of thin film transistors included in each stage of the illumination control circuit in the prior art is usually relatively large (usually more than 20), resulting in a complicated illumination control circuit.
  • an embodiment of the present application provides an illumination control circuit that includes a small number of thin film transistors and a simple structure to simplify the structure of the illumination control circuit.
  • an embodiment of the present application provides an illumination control circuit, including: a first control unit, a second control unit, and an illumination control unit, wherein:
  • the input ends of the first control unit are respectively connected to the initial signal line, the first clock signal line, and the first power source, for outputting the first control signal;
  • the input ends of the second control unit are respectively connected to the first control unit, the second clock signal line and the second power source for outputting the second control signal;
  • An input end of the illumination control unit is respectively connected to the first control unit, the second control unit, the first power source, and the second power source, for the first control signal and the first The illumination control signal is outputted by the second control signal.
  • the illumination control unit includes: a ninth thin film transistor, a tenth thin film transistor, a second capacitor, and a third capacitor, wherein:
  • a source of the ninth thin film transistor is connected to the second power source, a drain of the ninth thin film transistor is connected to a source of the tenth thin film transistor, a gate of the ninth thin film transistor is
  • the second control unit is configured to output an output connection of the second control signal
  • a drain of the tenth thin film transistor is connected to the first power source, and a gate of the tenth thin film transistor is connected to an output end of the first control unit for outputting a first control signal;
  • One end of the second capacitor is connected to an output end of the second control unit for outputting a second control signal, and the other end of the second capacitor is connected to the second power source;
  • One end of the third capacitor is connected to the second clock signal, and the other end of the third capacitor is connected to an output end of the first control unit for outputting a first control signal;
  • drain of the ninth thin film transistor or the source of the tenth thin film transistor is an output end of the light emission control unit, a drain of the ninth thin film transistor or a source output of the tenth thin film transistor
  • the signal is the illumination control signal.
  • the first control signal is used to control the tenth thin film transistor to be in an on or off state
  • the second control signal is used to control the ninth thin film transistor to be in an on or off state
  • the second control signal controls the ninth thin film transistor to be in an off state
  • the second control signal controls the ninth thin film transistor to be in an on state when the first control signal controls the tenth thin film transistor to be in an off state.
  • the first control signal controls the tenth thin film transistor to be in an on state
  • the second control signal controls the ninth thin film transistor to be in an off state
  • the illumination control signal is Describe the voltage of the first power output
  • the first control signal controls the tenth thin film transistor to be in an off state
  • the second control signal controls the ninth thin film transistor to be in an on state
  • the illumination control signal is output by the second power source Voltage.
  • the first control unit includes: a first thin film transistor, a second thin film transistor, and a third thin film transistor, wherein:
  • a gate of the first thin film transistor is respectively connected to a source of the second thin film transistor, a gate of the third thin film transistor, and the first clock signal line, and a drain of the first thin film transistor
  • the initial signal line is connected, and a source of the first thin film transistor is connected to a gate of the second thin film transistor;
  • a drain of the second thin film transistor is connected to a source of the third thin film transistor
  • a drain of the third thin film transistor is connected to the first power source
  • the source of the first thin film transistor is the output end of the first control unit, and the output signal is the first control signal.
  • the second control unit includes: a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, and a first capacitor, wherein:
  • a gate of the fourth thin film transistor is respectively connected to a gate of the sixth thin film transistor and one end of the first capacitor, and a source of the fourth thin film transistor is connected to a source of the fifth thin film transistor a drain of the fourth thin film transistor is respectively connected to a drain of the eighth thin film transistor and the second power source;
  • a gate of the fifth thin film transistor is respectively connected to the second clock signal line, a drain of the sixth thin film transistor, a gate of the seventh thin film transistor, and another end of the first capacitor.
  • a drain of the fifth thin film transistor is respectively connected to a gate of the eighth thin film transistor and a source of the first thin film transistor;
  • a source of the sixth thin film transistor is connected to a source of the seventh thin film transistor, and a drain of the seventh thin film transistor is connected to a source of the eighth thin film transistor;
  • the source of the eighth thin film transistor is the output end of the second control unit, and the output signal is the second control signal.
  • the initial signal line is used to provide an initial signal
  • the first clock signal line is used to provide a first clock signal
  • the second clock signal line is used to provide a second clock signal
  • the voltage output by the first power source is a negative voltage
  • the voltage output by the second power source is a positive voltage
  • the seventh thin film transistor, the eighth thin film transistor, the ninth thin film transistor, and the tenth thin film transistor are all P-type thin film transistors.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, At least one of the seventh thin film transistor, the eighth thin film transistor, the ninth thin film transistor, and the tenth thin film transistor is an N-type thin film transistor.
  • an embodiment of the present application further provides an illumination control driver, where the illumination control driver includes at least two stages of the illumination control circuit described above, wherein:
  • the input signal of the first stage of the illumination control circuit is an initial signal, and the illumination control signal output by the illumination control circuit of the (n-1)th stage is used as an initial signal of the nth stage of the illumination control circuit;
  • the first clock signal of the (n-1)th stage of the light emission control circuit is used as the second clock signal of the nth stage of the light emission control circuit, and the (n-1)th stage of the light emission control circuit
  • the second clock signal is used as the first clock signal of the nth stage of the illumination control circuit, and n is an integer greater than 1.
  • an embodiment of the present application further provides a display device including the illumination control driver described above.
  • the illumination control circuit provided by the embodiment of the present application includes: a first control unit, a second control unit, and an illumination control unit, wherein: the input ends of the first control unit are respectively associated with an initial signal line, a first clock signal line, and a first a power connection for outputting a first control signal; an input end of the second control unit is respectively connected to the first control unit, the second clock signal line, and the second power source, for outputting a second control signal; An input end of the illumination control unit is coupled to the first control unit, the second control unit, the first power source, and the second power source, respectively, for the first control signal and the second control The illumination control signal is output under the action of the signal.
  • the illumination control signal output by the illumination control circuit provided by the embodiment of the present application can control pixel illumination, and the circuit structure of the illumination control circuit is relatively simple.
  • FIG. 1 is a schematic structural diagram of an illumination control circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another illumination control circuit according to an embodiment of the present disclosure.
  • FIG. 3 is a timing diagram of a method for controlling illumination according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of an illumination control driver according to an embodiment of the present application.
  • FIG. 5 is a timing diagram of an illumination control driver according to an embodiment of the present application.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, the The seventh thin film transistor, the eighth thin film transistor, the ninth thin film transistor, and the tenth thin film transistor may all be N-type thin film transistors, or both may be P-type thin film transistors, or at least one of them may be N Thin film transistors, the rest are P-type thin film transistors. There is no specific limit here.
  • FIG. 1 is a schematic structural diagram of an illumination control circuit according to an embodiment of the present application.
  • the illumination control circuit can generate an illumination control signal that can control the illumination time of the pixel.
  • the illumination control circuit is as follows.
  • the illumination control circuit may include: a first control unit 11, a second control unit 12, and an illumination control unit 13, wherein:
  • the input terminals of the first control unit 11 may be respectively connected to the initial signal line, the first clock signal line, and the first power source VGL.
  • the initial signal line may provide an initial signal EIN
  • the first clock signal line may provide a first clock signal CK1
  • the first clock signal CK1 may be a pulse signal
  • the first power source VGL may be a negative voltage, that is, the first The power supply VGL can output a low level.
  • the first control unit 11 can be configured to output the first control signal under the action of the initial signal EIN, the first clock signal CK1, and the first power source VGL.
  • the input terminals of the second control unit 12 may be respectively connected to the first control unit 11, the second clock signal line, and the second power source VGH.
  • the second clock signal line may provide a second clock signal CK2, and the second clock signal CK2 may also be a pulse signal.
  • the second power source VGH may be a positive voltage, that is, the second power source VGH may output a high level.
  • the second control unit 12 can be configured to output a second control signal under the action of the first control unit 11, the second clock signal CK2, and the second power source VGH.
  • the input ends of the illumination control unit 13 can be respectively connected to the first control unit 11, the second control unit 12, the first power source VGL and the second power source VGH, wherein the first control signal and the second control signal can be input.
  • the illumination control unit 13 can be configured to output the illumination control signal EM under the action of the first control signal and the second control signal.
  • the circuit structure of the illumination control circuit provided by the embodiment of the present application is relatively simple, wherein the illumination control unit can output an illumination control signal under the action of the first control unit, the second control unit, the clock signal, and the power supply voltage, and the illumination control signal can be Controls the lighting time of the pixel.
  • the illumination control unit 13 may include: a ninth thin film transistor M9, a tenth thin film transistor M10, a second capacitance C2, and a third capacitance C3, wherein:
  • the source of the ninth thin film transistor M9 is connected to the second power source VGH, the drain of the ninth thin film transistor M9 is connected to the source of the tenth thin film transistor M10, and the gate of the ninth thin film transistor M9 is connected to the second control unit 12 Outputting an output of the second control signal;
  • the drain of the tenth thin film transistor M10 is connected to the first power source VGL, and the gate of the tenth thin film transistor M10 is connected to the output end of the first control unit 11 for outputting the first control signal;
  • One end of the second capacitor C2 is connected to the output end of the second control unit 12 for outputting the second control signal, and the other end of the second capacitor C2 is connected to the second power source VGH;
  • One end of the third capacitor C3 is connected to the second clock signal CK2, and the other end of the third capacitor C3 is connected to the output end of the first control unit 11 for outputting the first control signal;
  • the drain of the ninth thin film transistor M9 or the source of the tenth thin film transistor M10 is the output end of the light emission control unit 13, and the signal output from the drain of the ninth thin film transistor M9 or the source of the tenth thin film transistor M10 is the light emission control. signal.
  • the first control unit 11 shown in FIG. 1 may include: a first thin film transistor, a second thin film transistor, and a third thin film transistor.
  • the second control unit 12 shown in FIG. 1 may include: a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, and the A capacitor.
  • FIG. 2 is a schematic structural diagram of another illuminating control circuit according to an embodiment of the present disclosure, wherein the first control unit 11 includes: a first thin film transistor M1, a second thin film transistor M2, and a third thin film transistor M3;
  • the second control unit 12 includes a fourth thin film transistor M4, a fifth thin film transistor M5, a sixth thin film transistor M6, a seventh thin film transistor M7, an eighth thin film transistor M8, and a first capacitor C1.
  • the light emission control unit 13 includes: The thin film transistor M9, the tenth thin film transistor M10, the second capacitor C2, and the third capacitor C3.
  • the thin film transistors shown in FIG. 2 are all P-type thin film transistors.
  • the circuit structure of the illumination control circuit shown in FIG. 2 is as follows:
  • a gate of the first thin film transistor M1 is respectively connected to a source of the second thin film transistor M2, a gate of the third thin film transistor M3, and the first clock signal line, and a drain of the first thin film transistor M1 and the initial signal a line connection, a source of the first thin film transistor M1 and a gate of the second thin film transistor M2, a drain of the fifth thin film transistor M5, a gate of the eighth thin film transistor M8, a gate of the tenth thin film transistor M10, and a first One end of the three capacitor C3 (the first node N1 shown in FIG. 2) is connected;
  • a drain of the second thin film transistor M2 is connected to a source of the third thin film transistor M3;
  • a drain of the third thin film transistor M3 is connected to the first power source VGL;
  • the gate of the fourth thin film transistor M4 is respectively connected to the gate of the sixth thin film transistor M6 and one end of the first capacitor C1 (the second node N2 shown in FIG. 2), and the source and the fifth thin film of the fourth thin film transistor M4.
  • the source of the transistor M5 is connected, and the drain of the fourth thin film transistor M4 is respectively connected to the drain of the eighth thin film transistor M8 and the second power source VGH;
  • a source of the sixth thin film transistor M6 is connected to a source of the seventh thin film transistor M7;
  • the drain of the seventh thin film transistor M7 is respectively connected to the source of the eighth thin film transistor M8, the gate of the ninth thin film transistor M9, and one end of the second capacitor C2 (the third node N3 shown in FIG. 2);
  • a source of the ninth thin film transistor M9 is connected to the other ends of the second power source VGH and the second capacitor C2, and a drain of the ninth thin film transistor M9 is connected to a source of the tenth thin film transistor M10;
  • the drain of the tenth thin film transistor M10 is connected to the first power source VGL.
  • the signal output from the source of the first thin film transistor M1 (ie, the first node N1 shown in FIG. 2) can be regarded as the first control signal; the source of the eighth thin film transistor M8.
  • the signal output from the pole (ie, the third node N3 shown in FIG. 2) can be regarded as the second control signal; the signal output from the drain of the ninth thin film transistor M9 (or the source of the tenth thin film transistor M10) can be regarded as For the illumination control signal EM.
  • the first control signal may be output to the gate of the tenth thin film transistor M10 and used to control the tenth thin film transistor M10 to be in an on or off state; the second control signal may be output to the gate of the ninth thin film transistor M9 And for controlling the ninth thin film transistor M9 to be in an on or off state, the illumination control signal EM can be outputted into the pixel and used to control the illumination time of the pixel.
  • the ninth thin film transistor M9 and the tenth thin film transistor M10 may select a type of a transistor according to a practical application scenario, for example, a P-type thin film transistor, or a first thin film transistor M1 and a second thin film transistor, as described above.
  • a thin film transistor is an N-type thin film transistor.
  • the first capacitor C1 and the third capacitor C3 may be bootstrap capacitors for raising or lowering the level of the node
  • the second capacitor C2 may be a storage capacitor for maintaining the level of the node
  • One end of the first capacitor C1 (ie, the second node N2 shown in FIG. 2) is respectively connected to the gate of the fourth thin film transistor M4 and the gate of the sixth thin film transistor M6, and the other end is connected to the second clock signal line.
  • the first capacitor C1 can be used to raise or lower the level of the second node N2, thereby controlling the fourth thin film transistor M4 and the sixth thin film transistor M6 to be turned on. Or cutoff status.
  • One end of the second capacitor C2 (ie, the third node N3 shown in FIG. 2) is respectively connected to the source of the eighth thin film transistor M8 and the gate of the ninth thin film transistor M9, and the other end is connected to the second power source VGH.
  • the third node N3 is at a high level
  • the eighth thin film transistor M8 is turned from an on state to an off state
  • the second capacitor C2 is a storage capacitor, the second capacitor C2 can be used.
  • the ninth thin film transistor M9 is still controlled to be in an off state.
  • One end of the third capacitor C3 (ie, the first node N1 shown in FIG. 2) is respectively connected to the gate of the second thin film transistor M2, the gate of the eighth thin film transistor M8, and the gate of the tenth thin film transistor M10, and the other end.
  • the third capacitor C3 Connected to the second clock signal line, when the level of the second clock signal CK2 changes, the third capacitor C3 can be used to raise or lower the level of the first node N1, thereby controlling the second thin film transistor M2.
  • the eighth thin film transistor M8 and the tenth thin film transistor M10 are in an on or off state.
  • the other end of the first capacitor C1 is directly connected to the second clock signal line, so that the delay of the second clock signal CK2 to the first capacitor C1 can be improved, and the The charging time of the first capacitor C1 by the second clock signal CK2 further increases the control efficiency of the first capacitor C1 to the fourth thin film transistor M4 and the sixth thin film transistor M6, so that the illumination control circuit can operate at a higher frequency and output A higher frequency illumination control signal EM.
  • the third capacitor C3 the other end of the third capacitor C3 is directly connected to the second clock signal line, and the delay of the second clock signal CK2 to the third capacitor C3 can be improved, and the third capacitor C3 is improved.
  • the control efficiency of the second thin film transistor M2, the eighth thin film transistor M8, and the tenth thin film transistor M10 further outputs a higher frequency emission control signal EM.
  • the illumination control circuit in order to ensure that the illumination control circuit can normally output the illumination control signal EM, in the embodiment of the present application, when the first control signal controls the tenth thin film transistor M10 to be in an on state, the first The second control signal may control the ninth thin film transistor M9 to be in an off state; or, when the first control signal controls the tenth thin film transistor M10 to be in an off state, the second control signal may control the ninth thin film transistor M9 to be turned on. status.
  • the second power supply VGL can be Outputted to the end of the illumination control signal EM through the tenth thin film transistor M10, that is, the illumination control signal EM outputs the first power source VGL; when the first control signal controls the tenth thin film transistor M10 to be in an off state, and the second control signal is controlled When the ninth thin film transistor M9 is in an on state, the second power source VGH can be output to the end of the light emission control signal EM through the ninth thin film transistor M9, that is, the light emission control signal EM outputs the second power source VGH.
  • FIG. 3 is a timing diagram of a driving method of an illumination control circuit according to an embodiment of the present disclosure.
  • the timing diagram may be a timing diagram corresponding to the first stage illumination control circuit in the illumination control driver, and the timing diagram may be used to drive the illumination control circuit shown in FIG. 2.
  • EIN is an initial signal
  • CK1 is a first clock signal
  • CK2 is a second clock signal
  • EM is an illumination control signal.
  • the first clock signal CK1 and the second clock signal CK2 have the same frequency
  • the second clock signal CK2 is delayed relative to the first clock signal CK1.
  • the specific delay time is T, and T can be the first clock signal CK1.
  • the duration of the high level in the initial signal EIN may be twice the period of the first clock signal CK1.
  • the duty cycle of the timing diagram shown in FIG. 3 can be divided into six phases, namely, a first phase t1, a second phase t2, a third phase t3, a fourth phase t4, a fifth phase t5, and a sixth phase t6.
  • the initial signal EIN outputs a low level
  • the first clock signal CK1 outputs a low level
  • the second clock signal CK2 outputs a high level.
  • the first thin film transistor M1 and the third thin film transistor M3 are turned on, and the initial signal EIN acts on the first node N1 through the first thin film transistor M1, so that the first node N1 is low.
  • the second thin film transistor M2, the eighth thin film transistor M8, and the tenth thin film transistor M10 are turned on.
  • the first clock signal CK1 acts on the second node N2 through the second thin film transistor M2
  • the first power source VGL acts on the second node N2 through the third thin film transistor M3, so that the voltage of the second node N2 is low
  • the four thin film transistors M4 and the sixth thin film transistor M6 are turned on.
  • the fifth thin film transistor M5 and the seventh thin film transistor M7 are turned off. Since the eighth thin film transistor M8 is turned on, the second power source VGH acts on the third node N3 through the eighth thin film transistor M8, so that the third node N3 is at a high level, and the ninth thin film transistor M9 is turned off.
  • the ninth thin film transistor M9 since the ninth thin film transistor M9 is turned off, the tenth thin film transistor M10 is turned on, and therefore, the first power source VGL can be output through the tenth thin film transistor M10 such that the light emission control signal EM is at a low level.
  • the initial signal EIN outputs a low level
  • the first clock signal CK1 outputs a high level
  • the second clock signal CK2 outputs a high level.
  • the first thin film transistor M1 and the third thin film transistor M3 are turned off due to the action of the first clock signal CK1.
  • the first node N1 since the voltage of the second clock signal CK2 at the other end of the third capacitor C3 remains unchanged, the first node N1 will maintain the low level of the first phase t1 unchanged, and the second thin film transistor M2, the eighth thin film transistor M8, and the tenth thin film transistor M10 are still in an on state.
  • the first clock signal CK1 acts on the second node N2 through the second thin film transistor M2 such that the second node N2 is at a high level, and the fourth thin film transistor M4 and the sixth thin film transistor M6 are turned off.
  • the fifth thin film transistor M5 and the seventh thin film transistor M7 are still turned off. Since the eighth thin film transistor M8 is turned on, the third node N3 remains at a high level under the action of the second power source VGH, and the ninth thin film transistor M9 is still turned off.
  • the ninth thin film transistor M9 since the ninth thin film transistor M9 is turned off, the tenth thin film transistor M10 is turned on, and therefore, the first power source VGL can be output through the tenth thin film transistor M10, that is, the light emission control signal EM outputs a low level.
  • the initial signal EIN outputs a low level
  • the first clock signal CK1 outputs a high level
  • the second clock signal CK2 outputs a low level, and then changes from a low level to a high level.
  • the first thin film transistor M1 and the third thin film transistor M3 are turned off due to the action of the first clock signal CK1.
  • the second clock signal CK2 outputs a low level
  • the fifth thin film transistor M5 and the seventh thin film transistor M7 are turned on, and the voltage of the first node N1 is lowered due to the bootstrap action of the third capacitor C3, and becomes the second stage.
  • the lower level of t2 is lower, and the second thin film transistor M2, the eighth thin film transistor M8, and the tenth thin film transistor M10 are turned on.
  • the first clock signal CK1 acts on the second node N2 through the second thin film transistor M2 such that the second node N2 is still at a high level, and the fourth thin film transistor M4 and the sixth thin film transistor M6 are turned off. Since the eighth thin film transistor M8 is turned on, the second power source VGH acts on the third node N3 through the eighth thin film transistor M8, so that the third node N3 is still at the high level, and the ninth thin film transistor M9 is turned off.
  • the ninth thin film transistor M9 is turned off, the tenth thin film transistor M10 is turned on, and therefore, the first power source VGL can be output through the tenth thin film transistor M10, that is, the light emission control signal EM outputs a low level.
  • the fifth thin film transistor M5 and the seventh thin film transistor M7 are turned off.
  • the voltage of the first node N1 rises due to the bootstrap action of the third capacitor C3.
  • the second thin film transistor M2, the eighth thin film transistor M8, and the tenth thin film transistor M10 are still turned on under the action of the first node N1.
  • the first thin film transistor M1 and the third thin film transistor M3 are still in an off state, and the first clock signal CK1 acts on the second node N2 through the second thin film transistor M2, so that the second node N2 is The high level, the fourth thin film transistor M4 and the sixth thin film transistor M6 are turned off.
  • the second power source VGH acts on the third node N3 through the eighth thin film transistor M8 such that the third node N3 is at a high level, and the ninth thin film transistor M9 is still turned off.
  • the ninth thin film transistor M9 is still turned off, the tenth thin film transistor M10 is still turned on, and therefore, the first power source VGL can be output through the tenth thin film transistor M10, that is, the light emission control signal EM outputs a low level.
  • the illumination control signal EM outputs a low level.
  • the initial signal EIN outputs a high level
  • the first clock signal CK1 outputs a low level
  • the second clock signal CK2 outputs a high level
  • the first thin film transistor M1 and the third thin film transistor M3 are turned on, and the initial signal EIN acts on the first node N1 through the first thin film transistor M1, so that the first node N1 is The high level, the second thin film transistor M2, the eighth thin film transistor M8, and the tenth thin film transistor M10 are turned off.
  • the first power source VGL acts on the second node N2 through the third thin film transistor M3 such that the second node N2 is at a low level, and the fourth thin film transistor M4 and the sixth thin film transistor M6 are turned on.
  • the fifth thin film transistor M5 and the seventh thin film transistor M7 are turned off. Since the eighth thin film transistor M8 is turned off, under the storage of the second capacitor C2, the third node N3 maintains the high level of the third phase t3 unchanged, and the ninth thin film transistor M9 is turned off.
  • the ninth thin film transistor M9 and the tenth thin film transistor M10 are both turned off, the light emission control signal EM maintains the low level of the third phase t3 unchanged.
  • the first clock signal CK1 When the first clock signal CK1 outputs a high level, the first thin film transistor M1 and the third thin film transistor M3 are turned off, the first node N1 will remain at a high level, and the second node N2 will remain at a low level, the third The node N3 will remain at a high level.
  • the second thin film transistor M2, the eighth thin film transistor M8, and the tenth thin film transistor M10 are still turned off, and the fourth thin film transistor M4 and the sixth thin film transistor M6 are still turned on, and the ninth The thin film transistor M9 is still turned off. Due to the action of the second clock signal CK2, the fifth thin film transistor M5 and the seventh thin film transistor M7 are turned off.
  • the ninth thin film transistor M9 and the tenth thin film transistor M10 are both turned off, the light emission control signal EM maintains the low level of the third phase t3 unchanged.
  • the illumination control signal EM outputs a low level.
  • the initial signal EIN outputs a high level
  • the first clock signal CK1 outputs a high level, from a high level to a low level, and then from a low level to a high level
  • the second clock signal CK2 outputs a low level
  • the low level changes to a high level, from a high level to a low level, and then from a low level to a high level.
  • the first thin film transistor M1 and the third thin film transistor M3 are turned off, and the fifth thin film transistor M5 and the seventh thin film transistor M7 are turned on. Due to the bootstrap action of the first capacitor C1, the voltage of the second node N2 is lowered to become a lower level than the level of the fourth stage t4, and the fourth thin film transistor M4 and the sixth thin film transistor M6 are turned on.
  • the second clock signal CK2 can act on the third node N3 through the sixth thin film transistor M6 and the seventh thin film transistor M7, so that the third node N3 is low.
  • Level, the ninth thin film transistor M9 is turned on.
  • the second power source VGH acts on the first node N1 through the fourth thin film transistor M4 and the fifth thin film transistor M5, so that the first node N1 is at a high level.
  • the second thin film transistor M2, the eighth thin film transistor M8, and the tenth thin film transistor M10 are turned off.
  • the ninth thin film transistor M9 Since the ninth thin film transistor M9 is turned on, the tenth thin film transistor M10 is turned off, and therefore, the second power source VGH can be output through the ninth thin film transistor M9, that is, the light emission control signal EM outputs a high level.
  • the first node N1 remains at a high level
  • the three-node N3 remains at a low level; when the first clock signal CK1 changes from a high level to a low level, and the second clock signal CK2 still outputs a high level, based on the description of the fourth stage t4 described above, the first Node N1 remains at a high level, and the third node N3 remains at a low level; similarly, when the first clock signal CK1 changes from a low level to a high level, the second clock signal CK2 is driven to a high level. When it becomes low level, and then changes from low level to high level, the first node N1 remains at the high level, and the third node N3 remains at the low level.
  • the ninth thin film transistor M9 is turned on, the tenth thin film transistor M10 is turned off, and the second power source VGH can be output through the ninth thin film transistor M9, that is, the light emission control signal EM outputs a high level.
  • the initial signal EIN outputs a low level
  • the first clock signal CK1 outputs a low level
  • the second clock signal CK2 outputs a high level.
  • the working principle of the illumination control circuit can be referred to the description of the first stage t1 described above, and the description is not repeated here.
  • the illumination control signal EM outputs a low level.
  • the waveform diagram of the output illumination control signal EM can be as shown in FIG.
  • the illuminating control circuit shown in FIG. 2 includes 10 thin film transistors and 3 capacitors. Compared with the illuminating control circuit in the prior art, the number of thin film transistors and the number of capacitors are small, and the circuit structure is relatively simple.
  • FIG. 4 is a schematic structural diagram of an illumination control driver provided by the present application.
  • the light emission control driver may include at least two stages of the light emission control circuit described in Embodiment 1.
  • the n-level illuminating control circuit may be included, respectively, the illuminating control circuit 1, the illuminating control circuit 2, the illuminating control circuit 3, ..., the illuminating control circuit n, wherein the illuminating control The circuit 1 is a first-level illumination control circuit, the illumination control circuit 2 is a second-stage illumination control circuit, the illumination control circuit 3 is a third-level illumination control circuit, ..., the illumination control circuit n is an n-th illumination control circuit, n Is an integer greater than 1.
  • the input signal of the illumination control circuit 1 is an initial signal EIN
  • the illumination control signal EM1 output by the illumination control circuit 1 can be used as an initial signal of the illumination control circuit 2
  • the illumination control signal output by the illumination control circuit 2 can be used as illumination.
  • the initial signal of the control circuit 3 ..., and so on, the light emission control signal EM(n-1) output from the light emission control circuit (n-1) can be used as an initial signal of the light emission control circuit n
  • n is an integer greater than one.
  • the first clock signal of the illumination control circuit 1 can be used as the second clock signal of the illumination control circuit 2, and the second clock signal of the illumination control circuit 1 can be used as the first clock signal of the illumination control circuit 2; the first clock of the illumination control circuit 2
  • the signal can be used as the second clock signal of the illumination control circuit 3
  • the second clock signal of the illumination control circuit 2 can be used as the first clock signal of the illumination control circuit 3
  • the illumination control circuit (n-1) A clock signal can be used as the second clock signal of the illumination control circuit n
  • the second clock signal of the illumination control circuit (n-1) can be used as the first clock signal of the illumination control circuit n, and n is an integer greater than one.
  • FIG. 5 is a timing diagram of an illumination control driver according to an embodiment of the present application.
  • EIN is an initial signal input by the first-stage illumination control circuit
  • CK1-1 is a first clock signal of the illumination control circuit 1
  • CK2-1 is a second clock signal of the illumination control circuit 1
  • the illumination control circuit 1 is
  • the light emission control signal EM1 can be output by the initial signal EIN, the first clock signal CK1-1, and the second clock signal CK2-1.
  • the light emission control signal EM1 can be used as an initial signal of the light emission control circuit 2.
  • CK1-2 is the first clock signal of the illumination control circuit 2
  • CK2-2 is the second clock signal of the illumination control circuit 2
  • the illumination control circuit 2 is at the initial signal EM1, the first clock signal CK1-2, and the second clock signal CK2.
  • the light emission control signal EM2 can be output under the action of -2. It can be seen from FIG. 5 that the first clock signal CK1-2 of the illumination control circuit 2 is the same as the second clock signal CK2-1 of the illumination control circuit 1, and the second clock signal CK2-2 of the illumination control circuit 2 is illuminated.
  • the first clock signal CK1-1 of the control circuit 1 is the same, and the light emission control signal EM2 output from the light emission control circuit 2 is delayed with respect to the light emission control signal EM1 output from the light emission control circuit 1.
  • the illumination control signal EM(n-1) output by the illumination control circuit (n-1) can be used as the initial signal of the illumination control circuit n
  • CK1-n is the first clock signal of the illumination control circuit n
  • CK2-n is the first clock signal of the illumination control circuit n
  • the first clock signal CK1-n may be the same as the second clock signal CK2-1
  • the second clock signal CK2-n may be the same as the first clock signal CK1-1
  • the light emission control signal EMn may be output by the initial signal EM(n-1), the first clock signal CK1-n, and the second clock signal CK2-n.
  • the initial signal EM(n-1), the first clock signal CK1-n, and the second clock signal CK2-n are not shown in FIG. 5.
  • the embodiment of the present application further provides a display device, which may include an illumination control driver as described above.

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Abstract

一种发光控制电路、发光控制驱动器以及显示装置，发光控制电路包括：第一控制单元（11）、第二控制单元（12）以及发光控制单元（13），其中：第一控制单元（11）的输入端分别与初始信号线（EIN）、第一时钟信号线（CK1）以及第一电源（VGL）连接，用于输出第一控制信号（CK1）；第二控制单元（12）的输入端分别与第一控制单元（11）、第二时钟信号线（CK2）以及第二电源（VGH）连接，用于输出第二控制信号（CK2）；发光控制单元（13）的输入端分别与第一控制单元（11）、第二控制单元（12）、第一电源（VGL）以及第二电源（VGH）连接，用于在第一控制信号（CK1）以及第二控制信号（CK2）的作用下输出发光控制信号（EM）。发光控制电路输出的发光控制信号（EM）控制像素发光，且发光控制电路的电路结构较为简单。

Description

一种发光控制电路、发光控制驱动器以及显示装置
本申请要求2018年01月19日提交的申请号为201820093773.2的中国申请的优先权，通过引用将其全部内容并入本文。
技术领域
本发明涉及显示技术领域，具体涉及一种发光控制电路、发光控制驱动器以及显示装置。
发明背景
通常，显示装置中可以包含多个像素、数据驱动器、扫描驱动器以及发光控制驱动器。其中，多个像素用于显示图像，数据驱动器用于为像素提供数据电压，扫描驱动器用于为像素提供扫描信号，发光控制驱动器用于为像素提供发光控制信号，发光控制信号可以控制像素的发光时间。
针对发光控制驱动器而言，其可以包含多级发光控制电路，每一级发光控制电路可以用于控制一行像素的发光时间。其中，针对其中一级发光控制电路，其可以包含多个薄膜晶体管、初始信号、多个时钟信号，初始信号以及多个时钟信号可以控制薄膜晶体管处于导通或开启状态，进而使得发光控制电路可以输出发光控制信号。
然而，现有技术中的每一级发光控制电路中包含的薄膜晶体管的数量通常比较多(通常大于20个)，导致发光控制电路较为复杂。
发明内容
针对上述问题，本申请实施例提供一种发光控制电路，该电路中包含的薄膜晶体管的数量较少且结构简单，以达到简化发光控制电路结构的要求。根据本申请的第一方面，本申请一实施例提供一种发光控制电路，包括：第一控制单元、第二控制单元以及发光控制单元，其中：
所述第一控制单元的输入端分别与初始信号线、第一时钟信号线以及第一电源连接，用于输出第一控制信号；
所述第二控制单元的输入端分别与所述第一控制单元、第二时钟信号线以及第二电源连接，用于输出第二控制信号；
所述发光控制单元的输入端分别与所述第一控制单元、所述第二控制单元、所述第一电源以及所述第二电源连接，用于在所述第一控制信号以及所述第二控 制信号的作用下输出发光控制信号。
在一实施例中，所述发光控制单元包括：第九薄膜晶体管、第十薄膜晶体管、第二电容以及第三电容，其中：
所述第九薄膜晶体管的源极与所述第二电源连接，所述第九薄膜晶体管的漏极与所述第十薄膜晶体管的源极连接，所述第九薄膜晶体管的栅极与所述第二控制单元用于输出第二控制信号的输出端连接；
所述第十薄膜晶体管的漏极与所述第一电源连接，所述第十薄膜晶体管的栅极与所述第一控制单元用于输出第一控制信号的输出端连接；
所述第二电容的一端与所述第二控制单元用于输出第二控制信号的输出端连接，所述第二电容的另一端与所述第二电源连接；
所述第三电容的一端与所述第二时钟信号连接，所述第三电容的另一端与所述第一控制单元用于输出第一控制信号的输出端连接；
其中，所述第九薄膜晶体管的漏极或者所述第十薄膜晶体管的源极为所述发光控制单元的输出端，所述第九薄膜晶体管的漏极或者所述第十薄膜晶体管的源极输出的信号为所述发光控制信号。
在一实施例中，所述第一控制信号用于控制所述第十薄膜晶体管处于导通或截止状态，所述第二控制信号用于控制所述第九薄膜晶体管处于导通或截止状态。
在一实施例中，所述第一控制信号控制所述第十薄膜晶体管处于导通状态时，所述第二控制信号控制所述第九薄膜晶体管处于截止状态；
所述第一控制信号控制所述第十薄膜晶体管处于截止状态时，所述第二控制信号控制所述第九薄膜晶体管处于导通状态。
在一实施例中，所述第一控制信号控制所述第十薄膜晶体管处于导通状态，且所述第二控制信号控制所述第九薄膜晶体管处于截止状态时，所述发光控制信号为所述第一电源输出的电压；
所述第一控制信号控制所述第十薄膜晶体管处于截止状态，且所述第二控制信号控制所述第九薄膜晶体管处于导通状态时，所述发光控制信号为所述第二电源输出的电压。
在一实施例中，所述第一控制单元包括：第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，其中：
所述第一薄膜晶体管的栅极分别与所述第二薄膜晶体管的源极、所述第三薄膜晶体管的栅极以及所述第一时钟信号线连接，所述第一薄膜晶体管的漏极与所述初始信号线连接，所述第一薄膜晶体管的源极与所述第二薄膜晶体管的栅极连接；
所述第二薄膜晶体管的漏极与所述第三薄膜晶体管的源极连接；
所述第三薄膜晶体管的漏极与所述第一电源连接；
所述第一薄膜晶体管的源极为所述第一控制单元的输出端，输出的信号为所述第一控制信号。
在一实施例中，所述第二控制单元包括：第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第一电容，其中：
所述第四薄膜晶体管的栅极分别与所述第六薄膜晶体管的栅极以及所述第一电容的一端连接，所述第四薄膜晶体管的源极与所述第五薄膜晶体管的源极连接，所述第四薄膜晶体管的漏极分别与所述第八薄膜晶体管的漏极以及所述第二电源连接；
所述第五薄膜晶体管的栅极分别与所述第二时钟信号线、所述第六薄膜晶体管的漏极、所述第七薄膜晶体管的栅极以及所述第一电容的另一端连接，所述第五薄膜晶体管的漏极分别与所述第八薄膜晶体管的栅极以及所述第一薄膜晶体管的源极连接；
所述第六薄膜晶体管的源极与所述第七薄膜晶体管的源极连接，所述第七薄膜晶体管的漏极与所述第八薄膜晶体管的源极连接；
所述第八薄膜晶体管的源极为所述第二控制单元的输出端，输出的信号为所述第二控制信号。
在一实施例中，所述初始信号线用于提供初始信号，所述第一时钟信号线用于提供第一时钟信号，所述第二时钟信号线用于提供第二时钟信号；
所述第一电源输出的电压为负电压，所述第二电源输出的电压为正电压。
在一实施例中，其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管、所述第七薄膜晶体管、所述第八薄膜晶体管、所述第九薄膜晶体管和所述第十薄膜晶体管均为P型薄膜晶体管。
在一实施例中，其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管、所述第七薄膜晶体管、所述第八薄膜晶体管、所述第九薄膜晶体管和所述第十薄膜晶体管中至少一个为N型薄膜晶体管。
根据本申请的第二方面，本申请一实施例还提供一种发光控制驱动器，该发光控制驱动器包括至少两级上述记载的所述发光控制电路，其中：
第一级所述发光控制电路的输入信号为初始信号，第(n-1)级所述发光控制电路输出的所述发光控制信号作为第n级所述发光控制电路的初始信号；
第(n-1)级所述发光控制电路的所述第一时钟信号作为第n级所述发光控制电路的所述第二时钟信号，第(n-1)级所述发光控制电路的所述第二时钟信号作 为第n级所述发光控制电路的所述第一时钟信号，n为大于1的整数。
根据本申请的第三方面，本申请一实施例还提供一种显示装置，该显示装置包括上述记载的所述发光控制驱动器。
本申请实施例采用的上述至少一个技术方案能够达到以下有益效果：
本申请实施例提供的发光控制电路包括：第一控制单元、第二控制单元以及发光控制单元，其中：所述第一控制单元的输入端分别与初始信号线、第一时钟信号线以及第一电源连接，用于输出第一控制信号；所述第二控制单元的输入端分别与所述第一控制单元、第二时钟信号线以及第二电源连接，用于输出第二控制信号；所述发光控制单元的输入端分别与所述第一控制单元、所述第二控制单元、所述第一电源以及所述第二电源连接，用于在所述第一控制信号以及所述第二控制信号的作用下输出发光控制信号。本申请实施例提供的发光控制电路输出的发光控制信号可以控制像素发光，且所述发光控制电路的电路结构较为简单。
附图简要说明
图1为本申请实施例提供的一种发光控制电路的结构示意图；
图2为本申请实施例提供的另一种发光控制电路的结构示意图；
图3为本申请实施例提供的一种发光控制方法的时序图；
图4为本申请实施例提供的一种发光控制驱动器的结构示意图；
图5为本申请实施例提供的一种发光控制驱动器的时序图。
实施本发明的方式
为使本发明的目的、技术手段和优点更加清楚明白，以下结合附图对本发明作进一步详细说明。显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管、所述第七薄膜晶体管、所述第八薄膜晶体管、所述第九薄膜晶体管以及所述第十薄膜晶体管可以均为N型薄膜晶体管，也可以均为P型薄膜晶体管，还可以是其中至少一个为N型薄膜晶体管，其余的均为P型薄膜晶体管。这里不做具体限定。
以下结合附图，详细说明本申请各实施例提供的技术方案。
实施例1
图1为本申请实施例提供的一种发光控制电路的结构示意图。所述发光控制 电路可以产生发光控制信号，所述发光控制信号可以控制像素的发光时间。所述发光控制电路如下所述。
如图1所示，本申请实施例提供的所述发光控制电路可以包括：第一控制单元11、第二控制单元12以及发光控制单元13，其中：
第一控制单元11的输入端可以分别与初始信号线、第一时钟信号线以及第一电源VGL连接。其中，所述初始信号线可以提供初始信号EIN，所述第一时钟信号线可以提供第一时钟信号CK1，第一时钟信号CK1可以是脉冲信号，第一电源VGL可以是负电压，即第一电源VGL可以输出低电平。第一控制单元11可以用于在初始信号EIN、第一时钟信号CK1以及第一电源VGL的作用下输出第一控制信号。
第二控制单元12的输入端可以分别与第一控制单元11、第二时钟信号线以及第二电源VGH连接。其中，所述第二时钟信号线可以提供第二时钟信号CK2，第二时钟信号CK2也可以是脉冲信号，第二电源VGH可以是正电压，即第二电源VGH可以输出高电平。第二控制单元12可以用于在第一控制单元11、第二时钟信号CK2以及第二电源VGH的作用下输出第二控制信号。
发光控制单元13的输入端可以分别与第一控制单元11、第二控制单元12、第一电源VGL以及第二电源VGH连接，其中，所述第一控制信号以及所述第二控制信号可以输入至发光控制单元13，发光控制单元13可以用于在所述第一控制信号以及所述第二控制信号的作用下输出发光控制信号EM。
本申请实施例提供的发光控制电路的电路结构较为简单，其中，发光控制单元可以在第一控制单元、第二控制单元、时钟信号以及电源电压的作用下输出发光控制信号，该发光控制信号可以控制像素的发光时间。
在本申请一实施例中，发光控制单元13可以包括：第九薄膜晶体管M9、第十薄膜晶体管M10、第二电容C2以及第三电容C3，其中：
第九薄膜晶体管M9的源极与第二电源连接VGH，第九薄膜晶体管M9的漏极与第十薄膜晶体管M10的源极连接，第九薄膜晶体管M9的栅极与第二控制单元12用于输出第二控制信号的输出端连接；
第十薄膜晶体管M10的漏极与第一电源VGL连接，第十薄膜晶体管M10的栅极与第一控制单元11用于输出第一控制信号的输出端连接；
第二电容C2的一端与第二控制单元12用于输出第二控制信号的输出端连接，第二电容C2的另一端与第二电源VGH连接；
第三电容C3的一端与第二时钟信号CK2连接，第三电容C3的另一端与第一控制单元11用于输出第一控制信号的输出端连接；
其中，第九薄膜晶体管M9的漏极或者第十薄膜晶体管M10的源极为发光控制单元13的输出端，第九薄膜晶体管M9的漏极或者第十薄膜晶体管M10的源 极输出的信号为发光控制信号。
在本申请提供的另一实施例中，图1所示的第一控制单元11可以包括：第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管。
在本申请提供的另一实施例中，图1所示的第二控制单元12可以包括：第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第一电容。
参见图2，图2为本申请实施例提供的另一种发光控制电路的结构示意图，其中，第一控制单元11包括：第一薄膜晶体管M1、第二薄膜晶体管M2以及第三薄膜晶体管M3；第二控制单元12包括：第四薄膜晶体管M4、第五薄膜晶体管M5、第六薄膜晶体管M6、第七薄膜晶体管M7、第八薄膜晶体管M8以及第一电容C1；发光控制单元13包括：第九薄膜晶体管M9、第十薄膜晶体管M10、第二电容C2以及第三电容C3。图2所示的薄膜晶体管均为P型薄膜晶体管。图2所示的发光控制电路的电路结构如下所述：
第一薄膜晶体管M1的栅极分别与第二薄膜晶体管M2的源极、第三薄膜晶体管M3的栅极以及所述第一时钟信号线连接，第一薄膜晶体管M1的漏极与所述初始信号线连接，第一薄膜晶体管M1的源极分别与第二薄膜晶体管M2的栅极、第五薄膜晶体管M5的漏极、第八薄膜晶体管M8的栅极、第十薄膜晶体管M10的栅极以及第三电容C3的一端(图2所示的第一节点N1)连接；
第二薄膜晶体管M2的漏极与第三薄膜晶体管M3的源极连接；
第三薄膜晶体管M3的漏极与第一电源VGL连接；
第四薄膜晶体管M4的栅极分别与第六薄膜晶体管M6的栅极以及第一电容C1的一端(图2所示的第二节点N2)连接，第四薄膜晶体管M4的源极与第五薄膜晶体管M5的源极连接，第四薄膜晶体管M4的漏极分别与第八薄膜晶体管M8的漏极以及第二电源VGH连接；
第五薄膜晶体管M5的栅极分别与所述第二时钟信号线、第六薄膜晶体管M6的漏极、第七薄膜晶体管M7的栅极、第一电容C1的另一端以及第三电容C3的另一端连接；
第六薄膜晶体管M6的源极与第七薄膜晶体管M7的源极连接；
第七薄膜晶体管M7的漏极分别与第八薄膜晶体管M8的源极、第九薄膜晶体管M9的栅极以及第二电容C2的一端(图2所示的第三节点N3)连接；
第九薄膜晶体管M9的源极分别与第二电源VGH以及第二电容C2的另一端连接，第九薄膜晶体管M9的漏极与第十薄膜晶体管M10的源极连接；
第十薄膜晶体管M10的漏极与第一电源VGL连接。
图2所示的发光控制电路中，第一薄膜晶体管M1的源极(即图2所示的第 一节点N1)输出的信号可以视为所述第一控制信号；第八薄膜晶体管M8的源极(即图2所示的第三节点N3)输出的信号可以视为所述第二控制信号；第九薄膜晶体管M9的漏极(或第十薄膜晶体管M10的源极)输出的信号可以视为所述发光控制信号EM。
所述第一控制信号可以输出至第十薄膜晶体管M10的栅极，并用于控制第十薄膜晶体管M10处于导通或截止状态；所述第二控制信号可以输出至第九薄膜晶体管M9的栅极，并用于控制第九薄膜晶体管M9处于导通或截止状态，所述发光控制信号EM可以输出至像素中，并用于控制像素的发光时间。
应当理解，第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第五薄膜晶体管M5、第六薄膜晶体管M6、第七薄膜晶体管M7、第八薄膜晶体管M8、第九薄膜晶体管M9和第十薄膜晶体管M10可以根据实际应用场景来选择晶体管的类型，例如可以如前述所述的均为P型薄膜晶体管，也可以为第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第五薄膜晶体管M5、第六薄膜晶体管M6、第七薄膜晶体管M7、第八薄膜晶体管M8、第九薄膜晶体管M9和第十薄膜晶体管M10至少一个薄膜晶体管为N型薄膜晶体管。
本申请实施例中，第一电容C1以及第三电容C3可以是自举电容，用于抬高或拉低节点的电平，第二电容C2可以是存储电容，用于保持节点的电平。具体地：
第一电容C1的一端(即图2所示的第二节点N2)分别与第四薄膜晶体管M4的栅极以及第六薄膜晶体管M6的栅极连接，另一端与所述第二时钟信号线连接，当第二时钟信号CK2的电平发生变化时，第一电容C1可以用于抬高或拉低第二节点N2的电平，进而控制第四薄膜晶体管M4以及第六薄膜晶体管M6处于导通或截止状态。
第二电容C2的一端(即图2所示的第三节点N3)分别与第八薄膜晶体管M8的源极以及第九薄膜晶体管M9的栅极连接，另一端与第二电源VGH连接，当第八薄膜晶体管M8处于导通状态时，第三节点N3为高电平，当第八薄膜晶体管M8由导通状态变为截止状态时，由于第二电容C2为存储电容，第二电容C2可以用于保持第三节点N3的高电平不变，进而控制第九薄膜晶体管M9仍处于截止状态。
第三电容C3的一端(即图2所示的第一节点N1)分别与第二薄膜晶体管M2的栅极、第八薄膜晶体管M8的栅极以及第十薄膜晶体管M10的栅极连接，另一端与所述第二时钟信号线连接，当第二时钟信号CK2的电平发生变化时，第三电容C3可以用于抬高或拉低第一节点N1的电平，进而控制第二薄膜晶体管M2、第八薄膜晶体管M8以及第十薄膜晶体管M10处于导通或截止状态。
需要说明的是，由于本申请实施例中，第一电容C1的另一端直接与所述第二时钟信号线连接，因此，可以改善第二时钟信号CK2对第一电容C1的延时，缩短第二时钟信号CK2对第一电容C1的充电时间，进而提高第一电容C1对第四薄膜晶体管M4以及第六薄膜晶体管M6的控制效率，使得所述发光控制电路可以工作在更高频率下，输出更高频率的发光控制信号EM。同理，针对第三电容C3，第三电容C3的另一端直接与所述第二时钟信号线连接，也可以改善第二时钟信号CK2对第三电容C3的延时，提高第三电容C3对第二薄膜晶体管M2、第八薄膜晶体管M8以及第十薄膜晶体管M10的控制效率，进而输出更高频率的发光控制信号EM。
本申请实施例中，为了保证所述发光控制电路可以正常输出发光控制信号EM，在本申请实施例中，当所述第一控制信号控制第十薄膜晶体管M10处于导通状态时，所述第二控制信号可以控制第九薄膜晶体管M9处于截止状态；或者，当所述第一控制信号控制第十薄膜晶体管M10处于截止状态时，所述第二控制信号可以控制第九薄膜晶体管M9处于导通状态。
具体地，如图2所示，当所述第一控制信号控制第十薄膜晶体管M10处于导通状态，且所述第二控制信号控制第九薄膜晶体管M9处于截止状态时，第一电源VGL可以通过第十薄膜晶体管M10输出至发光控制信号EM端，即发光控制信号EM输出第一电源VGL；当所述第一控制信号控制第十薄膜晶体管M10处于截止状态，且所述第二控制信号控制第九薄膜晶体管M9处于导通状态时，第二电源VGH可以通过第九薄膜晶体管M9输出至发光控制信号EM端，即发光控制信号EM输出第二电源VGH。
图3为本申请实施例提供的一种发光控制电路的驱动方法的时序图。所述时序图可以是发光控制驱动器中的第一级发光控制电路对应的时序图，所述时序图可以用于驱动图2所示的发光控制电路。
图3中，EIN为初始信号，CK1为第一时钟信号，CK2为第二时钟信号，EM为发光控制信号。其中，第一时钟信号CK1与第二时钟信号CK2具有相同的频率，且，第二时钟信号CK2相对于第一时钟信号CK1延时，具体延时时间为T，T可以为第一时钟信号CK1的周期的一半。初始信号EIN中高电平的持续时间可以为第一时钟信号CK1的周期的2倍。
图3所示的时序图的工作周期可以分为六个阶段，分别为第一阶段t1、第二阶段t2、第三阶段t3、第四阶段t4、第五阶段t5以及第六阶段t6，具体地：
在第一阶段t1：
初始信号EIN输出低电平，第一时钟信号CK1输出低电平，第二时钟信号CK2输出高电平。
此时，由于第一时钟信号CK1的作用，第一薄膜晶体管M1以及第三薄膜晶 体管M3导通，初始信号EIN通过第一薄膜晶体管M1作用在第一节点N1，使得第一节点N1为低电平，第二薄膜晶体管M2、第八薄膜晶体管M8以及第十薄膜晶体管M10导通。第一时钟信号CK1通过第二薄膜晶体管M2作用在第二节点N2，且，第一电源VGL通过第三薄膜晶体管M3作用在第二节点N2，使得第二节点N2的电压为低电平，第四薄膜晶体管M4以及第六薄膜晶体管M6导通。
由于第二时钟信号CK2的作用，第五薄膜晶体管M5以及第七薄膜晶体管M7截止。由于第八薄膜晶体管M8导通，第二电源VGH通过第八薄膜晶体管M8作用在第三节点N3，使得第三节点N3为高电平，第九薄膜晶体管M9截止。
这样，在第一阶段t1，由于第九薄膜晶体管M9截止，第十薄膜晶体管M10导通，因此，第一电源VGL可以通过第十薄膜晶体管M10输出，使得发光控制信号EM为低电平。
在第二阶段t2：
初始信号EIN输出低电平，第一时钟信号CK1输出高电平，第二时钟信号CK2输出高电平。
此时，由于第一时钟信号CK1的作用，第一薄膜晶体管M1以及第三薄膜晶体管M3截止。对于第一节点N1而言，由于第三电容C3另一端的第二时钟信号CK2的电压保持不变，因此，第一节点N1将维持第一阶段t1的低电平不变，第二薄膜晶体管M2、第八薄膜晶体管M8以及第十薄膜晶体管M10仍处于导通状态。第一时钟信号CK1通过第二薄膜晶体管M2作用在第二节点N2，使得第二节点N2为高电平，第四薄膜晶体管M4以及第六薄膜晶体管M6截止。
由于第二时钟信号CK2的作用，第五薄膜晶体管M5以及第七薄膜晶体管M7仍截止。由于第八薄膜晶体管M8导通，第三节点N3在第二电源VGH的作用下保持高电平不变，第九薄膜晶体管M9仍截止。
这样，在第二阶段t2，由于第九薄膜晶体管M9截止，第十薄膜晶体管M10导通，因此，第一电源VGL可以通过第十薄膜晶体管M10输出，即发光控制信号EM输出低电平。
在第三阶段t3：
初始信号EIN输出低电平，第一时钟信号CK1输出高电平，第二时钟信号CK2输出低电平，再由低电平变为高电平。
此时，由于第一时钟信号CK1的作用，第一薄膜晶体管M1以及第三薄膜晶体管M3截止。当第二时钟信号CK2输出低电平时，第五薄膜晶体管M5以及第七薄膜晶体管M7导通，由于第三电容C3的自举作用，第一节点N1的电压降低，并变为比第二阶段t2的电平更低的低电平，第二薄膜晶体管M2、第八薄膜晶体管M8以及第十薄膜晶体管M10导通。第一时钟信号CK1通过第二薄膜晶体管M2作用在第二节点N2，使得第二节点N2仍为高电平，第四薄膜晶体管M4以 及第六薄膜晶体管M6截止。由于第八薄膜晶体管M8导通，第二电源VGH通过第八薄膜晶体管M8作用在第三节点N3，使得第三节点N3仍为高电平，第九薄膜晶体管M9截止。
这样，由于第九薄膜晶体管M9截止，第十薄膜晶体管M10导通，因此，第一电源VGL可以通过第十薄膜晶体管M10输出，即发光控制信号EM输出低电平。
当第二时钟信号CK2由低电平变为高电平时，第五薄膜晶体管M5以及第七薄膜晶体管M7截止，此时，由于第三电容C3的自举作用，第一节点N1的电压升高，但仍为低电平，在第一节点N1的作用下，第二薄膜晶体管M2、第八薄膜晶体管M8以及第十薄膜晶体管M10仍导通。在第一时钟信号CK1的作用下，第一薄膜晶体管M1以及第三薄膜晶体管M3仍处于截止状态，第一时钟信号CK1通过第二薄膜晶体管M2作用在第二节点N2，使得第二节点N2为高电平，第四薄膜晶体管M4以及第六薄膜晶体管M6截止。第二电源VGH通过第八薄膜晶体管M8作用在第三节点N3，使得第三节点N3为高电平，第九薄膜晶体管M9仍截止。
这样，由于第九薄膜晶体管M9仍截止，第十薄膜晶体管M10仍导通，因此，第一电源VGL可以通过第十薄膜晶体管M10输出，即发光控制信号EM输出低电平。
综上所述，在第三阶段t3，发光控制信号EM输出低电平。
在第四阶段t4：
初始信号EIN输出高电平，第一时钟信号CK1输出低电平，再由低电平变为高电平，第二时钟信号CK2输出高电平。
此时，当第一时钟信号CK1输出低电平时，第一薄膜晶体管M1以及第三薄膜晶体管M3导通，初始信号EIN通过第一薄膜晶体管M1作用在第一节点N1，使得第一节点N1为高电平，第二薄膜晶体管M2、第八薄膜晶体管M8以及第十薄膜晶体管M10截止。第一电源VGL通过第三薄膜晶体管M3作用在第二节点N2，使得第二节点N2为低电平，第四薄膜晶体管M4以及第六薄膜晶体管M6导通。
由于第二时钟信号CK2的作用，第五薄膜晶体管M5以及第七薄膜晶体管M7截止。由于第八薄膜晶体管M8截止，在第二电容C2的存储作用下，第三节点N3保持第三阶段t3的高电平不变，第九薄膜晶体管M9截止。
这样，由于第九薄膜晶体管M9以及第十薄膜晶体管M10均截止，因此，发光控制信号EM保持第三阶段t3的低电平不变。
当第一时钟信号CK1输出高电平时，第一薄膜晶体管M1以及第三薄膜晶体管M3截止，第一节点N1将保持高电平不变，第二节点N2将保持低电平不变， 第三节点N3将保持高电平不变，此时，第二薄膜晶体管M2、第八薄膜晶体管M8以及第十薄膜晶体管M10仍截止，第四薄膜晶体管M4以及第六薄膜晶体管M6仍导通，第九薄膜晶体管M9仍截止。由于第二时钟信号CK2的作用，第五薄膜晶体管M5以及第七薄膜晶体管M7截止。
这样，由于第九薄膜晶体管M9以及第十薄膜晶体管M10均截止，因此，发光控制信号EM保持第三阶段t3的低电平不变。
综上所述，在第四阶段t4，发光控制信号EM输出低电平。
在第五阶段t5：
初始信号EIN输出高电平，第一时钟信号CK1输出高电平，由高电平变为低电平，再由低电平变为高电平，第二时钟信号CK2输出低电平，由低电平变为高电平，由高电平变为低电平，再由低电平变为高电平。
当第一时钟信号CK1输出高电平，且第二时钟信号CK2输出低电平时，第一薄膜晶体管M1以及第三薄膜晶体管M3截止，第五薄膜晶体管M5以及第七薄膜晶体管M7导通。由于第一电容C1的自举作用，第二节点N2的电压降低，变为比第四阶段t4的电平更低的低电平，第四薄膜晶体管M4以及第六薄膜晶体管M6导通。由于第六薄膜晶体管M6以及第七薄膜晶体管M7均导通，因此，第二时钟信号CK2可以通过第六薄膜晶体管M6以及第七薄膜晶体管M7作用在第三节点N3，使得第三节点N3为低电平，第九薄膜晶体管M9导通。同时，由于第四薄膜晶体管M4以及第五薄膜晶体管M5导通，第二电源VGH通过第四薄膜晶体管M4以及第五薄膜晶体管M5作用在第一节点N1，使得第一节点N1为高电平，第二薄膜晶体管M2、第八薄膜晶体管M8以及第十薄膜晶体管M10截止。
由于第九薄膜晶体管M9导通，第十薄膜晶体管M10截止，因此，第二电源VGH可以通过第九薄膜晶体管M9输出，即发光控制信号EM输出高电平。
当第二时钟信号CK2由低电平变为高电平，且第一时钟信号CK1仍输出高电平时，根据上述第四阶段t4的描述，第一节点N1仍保持高电平不变，第三节点N3仍保持低电平不变；当第一时钟信号CK1由高电平变为低电平，且第二时钟信号CK2仍输出高电平时，基于上述第四阶段t4的描述，第一节点N1仍保持高电平不变，第三节点N3仍保持低电平不变；同理，当第一时钟信号CK1由低电平变为高电平，第二时钟信号CK2由高电平变为低电平，再由低电平变为高电平时，第一节点N1仍保持高电平不变，第三节点N3仍保持低电平不变。
综上，在第五阶段t5，第一时钟信号CK1的电平以及第二时钟信号CK2的电平均发生变化时，第一节点N1将保持高电平不变，第三节点N3将保持低电平不变，因此，第九薄膜晶体管M9导通，第十薄膜晶体管M10截止，第二电源VGH可以通过第九薄膜晶体管M9输出，即发光控制信号EM输出高电平。
在第六阶段t6：
初始信号EIN输出低电平，第一时钟信号CK1输出低电平，第二时钟信号CK2输出高电平。
在第六阶段t6，所述发光控制电路的工作原理可以参见上述第一阶段t1的描述，这里不再重复说明。
在第六阶段t6，发光控制信号EM输出低电平。
综上所述，在所述发光控制电路的一个工作周期内，输出的发光控制信号EM的波形图可以如图3所示。
图2所示的发光控制电路，包含10个薄膜晶体管以及3个电容，相比于现有技术中的发光控制电路而言，薄膜晶体管的数量以及电容的数量较少，电路结构较为简单。
实施例2
图4为本申请提供的一种发光控制驱动器的结构示意图。所述发光控制驱动器可以包含至少两级实施例1中记载的所述发光控制电路。
在图4所示的发光控制驱动器中，可以包含n级所述发光控制电路，分别为发光控制电路1、发光控制电路2、发光控制电路3、……、发光控制电路n，其中，发光控制电路1为第一级发光控制电路，发光控制电路2为第二级发光控制电路，发光控制电路3为第三级发光控制电路，……，发光控制电路n为第n级发光控制电路，n为大于1的整数。
图4中，所述发光控制电路1的输入信号为初始信号EIN，发光控制电路1输出的发光控制信号EM1可以作为发光控制电路2的初始信号，发光控制电路2输出的发光控制信号可以作为发光控制电路3的初始信号，……，以此类推，发光控制电路(n-1)输出的发光控制信号EM(n-1)可以作为发光控制电路n的初始信号，n为大于1的整数。
发光控制电路1的第一时钟信号可以作为发光控制电路2的第二时钟信号，发光控制电路1的第二时钟信号可以作为发光控制电路2的第一时钟信号；发光控制电路2的第一时钟信号可以作为发光控制电路3的第二时钟信号，发光控制电路2的第二时钟信号可以作为发光控制电路3的第一时钟信号，……以此类推，发光控制电路(n-1)的第一时钟信号可以作为发光控制电路n的第二时钟信号，发光控制电路(n-1)的第二时钟信号可以作为发光控制电路n的第一时钟信号，n为大于1的整数。
图5为本申请实施例提供的一种发光控制驱动器的时序图。
图5中，EIN为第一级发光控制电路输入的初始信号，CK1-1为发光控制电路1的第一时钟信号，CK2-1为发光控制电路1的第二时钟信号，发光控制电路1在初始信号EIN、第一时钟信号CK1-1以及第二时钟信号CK2-1的作用下可以 输出发光控制信号EM1。其中，发光控制信号EM1可以作为发光控制电路2的初始信号。
CK1-2为发光控制电路2的第一时钟信号，CK2-2为发光控制电路2的第二时钟信号，发光控制电路2在初始信号EM1、第一时钟信号CK1-2以及第二时钟信号CK2-2的作用下可以输出发光控制信号EM2。其中，从图5可以看出，发光控制电路2的第一时钟信号CK1-2与发光控制电路1的第二时钟信号CK2-1相同，发光控制电路2的第二时钟信号CK2-2与发光控制电路1的第一时钟信号CK1-1相同，发光控制电路2输出的发光控制信号EM2相对发光控制电路1输出的发光控制信号EM1延时。
以此类推，发光控制电路(n-1)输出的发光控制信号EM(n-1)可以作为发光控制电路n的初始信号，CK1-n为发光控制电路n的第一时钟信号，CK2-n为发光控制电路n的第二时钟信号，第一时钟信号CK1-n可以与第二时钟信号CK2-1相同，第二时钟信号CK2-n可以与第一时钟信号CK1-1相同，发光控制电路n在初始信号EM(n-1)、第一时钟信号CK1-n以及第二时钟信号CK2-n的作用下可以输出发光控制信号EMn。其中，初始信号EM(n-1)、第一时钟信号CK1-n以及第二时钟信号CK2-n均未在图5示出。
实施例3
本申请实施例还提供一种显示装置，所述显示装置可以包括如上述所述的发光控制驱动器。
本领域的技术人员应明白，尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (12)

  1. 一种发光控制电路，包括：第一控制单元、第二控制单元以及发光控制单元，其中：
    所述第一控制单元的输入端分别与初始信号线、第一时钟信号线以及第一电源连接，用于输出第一控制信号；
    所述第二控制单元的输入端分别与所述第一控制单元、第二时钟信号线以及第二电源连接，用于输出第二控制信号；
    所述发光控制单元的输入端分别与所述第一控制单元、所述第二控制单元、所述第一电源以及所述第二电源连接，用于在所述第一控制信号以及所述第二控制信号的作用下输出发光控制信号。
  2. 如权利要求1所述的发光控制电路，其中，所述发光控制单元包括：
    第九薄膜晶体管、第十薄膜晶体管、第二电容以及第三电容，其中：
    所述第九薄膜晶体管的源极与所述第二电源连接，所述第九薄膜晶体管的漏极与所述第十薄膜晶体管的源极连接，所述第九薄膜晶体管的栅极与所述第二控制单元用于输出第二控制信号的输出端连接；
    所述第十薄膜晶体管的漏极与所述第一电源连接，所述第十薄膜晶体管的栅极与所述第一控制单元用于输出第一控制信号的输出端连接；
    所述第二电容的一端与所述第二控制单元用于输出第二控制信号的输出端连接，所述第二电容的另一端与所述第二电源连接；
    所述第三电容的一端与所述第二时钟信号连接，所述第三电容的另一端与所述第一控制单元用于输出第一控制信号的输出端连接；
    其中，所述第九薄膜晶体管的漏极或者所述第十薄膜晶体管的源极为所述发光控制单元的输出端，所述第九薄膜晶体管的漏极或者所述第十薄膜晶体管的源极输出的信号为所述发光控制信号。
  3. 如权利要求2所述的发光控制电路，其中，
    所述第一控制信号用于控制所述第十薄膜晶体管处于导通或截止状态，所述第二控制信号用于控制所述第九薄膜晶体管处于导通或截止状态。
  4. 如权利要求3所述的发光控制电路，其中，
    所述第一控制信号控制所述第十薄膜晶体管处于导通状态时，所述第二控制信号控制所述第九薄膜晶体管处于截止状态；
    所述第一控制信号控制所述第十薄膜晶体管处于截止状态时，所述第二控制信号控制所述第九薄膜晶体管处于导通状态。
  5. 如权利要求4所述的发光控制电路，其中，
    所述第一控制信号控制所述第十薄膜晶体管处于导通状态，且所述第二控制信号控制所述第九薄膜晶体管处于截止状态时，所述发光控制信号为所述第一电源输出的电压；
    所述第一控制信号控制所述第十薄膜晶体管处于截止状态，且所述第二控制信号控制所述第九薄膜晶体管处于导通状态时，所述发光控制信号为所述第二电源输出的电压。
  6. 如权利要求1至5任一所述的发光控制电路，其中，所述第一控制单元包括：第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，其中：
    所述第一薄膜晶体管的栅极分别与所述第二薄膜晶体管的源极、所述第三薄膜晶体管的栅极以及所述第一时钟信号线连接，所述第一薄膜晶体管的漏极与所述初始信号线连接，所述第一薄膜晶体管的源极与所述第二薄膜晶体管的栅极连接；
    所述第二薄膜晶体管的漏极与所述第三薄膜晶体管的源极连接；
    所述第三薄膜晶体管的漏极与所述第一电源连接；
    所述第一薄膜晶体管的源极为所述第一控制单元的输出端，输出的信号为所述第一控制信号。
  7. 如权利要求6所述的发光控制电路，其中，所述第二控制单元包括：第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管以及第一电容，其中：
    所述第四薄膜晶体管的栅极分别与所述第六薄膜晶体管的栅极以及所述第一电容的一端连接，所述第四薄膜晶体管的源极与所述第五薄膜晶体管的源极连接，所述第四薄膜晶体管的漏极分别与所述第八薄膜晶体管的漏极以及所述第二电源连接；
    所述第五薄膜晶体管的栅极分别与所述第二时钟信号线、所述第六薄膜晶体管的漏极、所述第七薄膜晶体管的栅极以及所述第一电容的另一端连接，所述第五薄膜晶体管的漏极分别与所述第八薄膜晶体管的栅极以及所述第一薄膜晶体管的源极连接；
    所述第六薄膜晶体管的源极与所述第七薄膜晶体管的源极连接，所述第七薄膜晶体管的漏极与所述第八薄膜晶体管的源极连接；
    所述第八薄膜晶体管的源极为所述第二控制单元的输出端，输出的信号为所述第二控制信号。
  8. 如权利要求1所述的发光控制电路，其中，
    所述初始信号线用于提供初始信号，所述第一时钟信号线用于提供第一时钟信号，所述第二时钟信号线用于提供第二时钟信号；
    所述第一电源输出的电压为负电压，所述第二电源输出的电压为正电压。
  9. 如权利要求7所述的发光控制电路，其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管、所述第七薄膜晶体管、所述第八薄膜晶体管、所述第九薄膜晶体管和所述第十薄膜晶体管均为P型薄膜晶体管。
  10. 如权利要求7所述的发光控制电路，其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管、所述第七薄膜晶体管、所述第八薄膜晶体管、所述第九薄膜晶体管和所述第十薄膜晶体管中至少一个为N型薄膜晶体管。
  11. 一种发光控制驱动器，包括至少两级如权利要求1至10任一项所述的发光控制电路，其中：
    第一级所述发光控制电路的输入信号为初始信号，第(n-1)级所述发光控制电路输出的所述发光控制信号作为第n级所述发光控制电路的初始信号；
    第(n-1)级所述发光控制电路的所述第一时钟信号作为第n级所述发光控制电路的所述第二时钟信号，第(n-1)级所述发光控制电路的所述第二时钟信号作为第n级所述发光控制电路的所述第一时钟信号，n为大于1的整数。
  12. 一种显示装置，包括如权利要求11所述的发光控制驱动器。
PCT/CN2018/107595 2018-01-19 2018-09-26 一种发光控制电路、发光控制驱动器以及显示装置 WO2019140946A1 (zh)

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JP2019569419A JP6829329B2 (ja) 2018-01-19 2018-09-26 発光制御回路、発光制御ドライバー及び表示装置
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