WO2019127489A1 - 电容器 - Google Patents

电容器 Download PDF

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Publication number
WO2019127489A1
WO2019127489A1 PCT/CN2017/120203 CN2017120203W WO2019127489A1 WO 2019127489 A1 WO2019127489 A1 WO 2019127489A1 CN 2017120203 W CN2017120203 W CN 2017120203W WO 2019127489 A1 WO2019127489 A1 WO 2019127489A1
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WO
WIPO (PCT)
Prior art keywords
capacitor
electrical conductors
electrical
electrically coupled
conductor
Prior art date
Application number
PCT/CN2017/120203
Other languages
English (en)
French (fr)
Inventor
王生荣
徐向明
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2017/120203 priority Critical patent/WO2019127489A1/zh
Priority to EP17936410.4A priority patent/EP3703124A4/en
Priority to CN201780096679.0A priority patent/CN111357103A/zh
Publication of WO2019127489A1 publication Critical patent/WO2019127489A1/zh
Priority to US16/883,223 priority patent/US20200286823A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/10—Metal-oxide dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/38—Multiple capacitors, i.e. structural combinations of fixed capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions

Definitions

  • the present application relates to the field of electronic technologies, and in particular, to a capacitor.
  • MOM metal-oxide-metal
  • MIM metal-insulator-metal
  • the thickness of the metal layer or dielectric layer of the MOM capacitor formed by the advanced fabrication process becomes smaller and smaller, and it becomes more and more difficult to precisely control the thickness of each layer in the fabrication process, which leads to the process of the MOM capacitor.
  • the process corners are getting larger and larger and forming process fluctuations or deviations. This process fluctuation or deviation is also called the non-ideality of the manufacturing process.
  • the MOM capacitors are arranged in the horizontal direction or the vertical direction. If the dielectric thickness of the MOM capacitor is deviated due to the non-ideality of the fabrication process, the capacitance value may be inaccurate, such as being larger or smaller than the preset capacitance. Value, which affects system performance. Therefore, how to reduce the deviation of the capacitance value caused by the fluctuation of the manufacturing process becomes a problem.
  • Embodiments of the present application provide a capacitor to reduce variations in capacitance values caused by fluctuations in manufacturing processes.
  • the first aspect of the present application provides a capacitor including a first end, a second end, a first capacitor, and a second capacitor.
  • the first capacitor includes at least two first electrical conductors and a first medium, the at least two first electrical conductors are arranged in a first direction, and each of the at least two first electrical conductors is adjacent to the first An electrical conductor is separated by the first medium, a portion of the at least two first electrical conductors are electrically coupled to the first end, and the other of the at least two first electrical conductors Two-terminal electrical coupling.
  • the second capacitor includes at least two second electrical conductors and a second medium, the at least two second electrical conductors being arranged in a second direction different from the first direction, the at least two second electrical conductors Each two adjacent second electrical conductors are separated by the second medium, and a portion of the at least two second electrical conductors are electrically coupled to the first end, the at least two second electrical conductors The other portion is electrically coupled to the second end.
  • the capacitance value of the first capacitor arranged in the direction changes according to a certain trend. Since the first capacitor and the second capacitor are arranged in different directions, the lengths of the at least two second conductors of the second capacitor arranged in the other direction also change correspondingly with the thickness variation of the first medium, thereby causing the second capacitor The change in the capacitance value is different from the capacitance value of the first capacitor, which helps to reduce the capacitance value deviation of the entire capacitor caused by the non-ideality of the manufacturing process.
  • each of the two adjacent first electrical conductors includes a third electrical conductor and a fourth electrical conductor, and the third electrical conductor is electrically coupled to the first end, A fourth electrical conductor is electrically coupled to the second end.
  • the plurality of first electrical conductors electrically coupled to the first end and the plurality of first electrical conductors electrically coupled to the second end may form a first interdigitated structure to optimize the first capacitor volume.
  • each of the two adjacent second electrical conductors includes a fifth electrical conductor and a sixth electrical conductor, the fifth electrical conductor being electrically coupled to the first end, A sixth electrical conductor is electrically coupled to the second end.
  • the plurality of second electrical conductors electrically coupled to the first end and the plurality of second electrical conductors electrically coupled to the second end form a second interdigitated structure to optimize the volume of the second capacitor .
  • the at least two first electrical conductors are respectively located on at least two of the plurality of layers, and the plurality of layers are arranged in the first direction.
  • the first direction may be a vertical direction.
  • the first capacitor is a vertical capacitor, and may include, for example, a metal plate capacitor.
  • the first medium is located on at least one of the plurality of layers.
  • the second capacitor penetrates the at least two conductive layers and the at least one dielectric layer.
  • the at least two second electrical conductors extend through at least a portion of the plurality of layers.
  • the at least two second electrical conductors extend through the at least partial layer through at least one through hole (VIA) or a through hole slot (Slot VIA).
  • the second capacitor extends through all or part of the plurality of layers to form a horizontal capacitor.
  • the horizontal capacitor may include a horizontal inter-metal capacitor, and may further optionally include a horizontal inter-hole capacitor or a horizontal via-slot capacitor.
  • the at least one through hole or via groove is located at and through at least one of the at least one of the layers.
  • the second direction is substantially perpendicular to the first direction.
  • the substantially vertical is that the angle between the second direction and the first direction is approximately ninety degrees.
  • the difference between the angle between the second direction and the first direction and ninety degrees is less than a preset threshold.
  • At least a portion of the at least two first electrical conductors are shared with at least a portion of the at least two second electrical conductors.
  • at least a portion of the first capacitor and at least a portion of the second capacitor are shared. That is to say, the first capacitor and the second capacitor have a fused portion. This design helps to reduce the size of the capacitor.
  • the at least two first electrical conductors and the at least two second electrical conductors are independent of each other, ie, there is no fusion.
  • the first capacitor and the second capacitor may be isolated by a third party device. That is, one or more other devices may be included between the first capacitor and the second capacitor. Even if the two capacitors are not directly adjacent, but are separated by other devices, the implementation of the technical solution is not affected.
  • At least one of the at least two first electrical conductors and the at least two second electrical conductors comprises at least one material: a metallic material or a semiconductor material.
  • the first electrical conductor of the lowermost layer of the at least two first electrical conductors comprises a semiconductor material
  • the other first electrical conductors comprise a metallic material, which is realized by the design A capacitor is easier to implement in a process.
  • the at least two first electrical conductors and the at least two second electrical conductors comprise the same material, for example, all of a metallic material.
  • the first medium and the second medium comprise the same dielectric material, such as silicon dioxide.
  • the capacitor is integrated on a semiconductor chip.
  • the semiconductor chip may include a radio frequency chip, and when the above technical solution is applied to the radio frequency field, a better effect than the low frequency signal processing field can be achieved.
  • At least one of the first capacitor and the second capacitor comprises a metal-oxide-metal MOM capacitor.
  • at least one of the first capacitor and the second capacitor may also include a MIM capacitor.
  • at least one of the first capacitor and the second capacitor may also include a MOM capacitor and a Metal-Oxide-Semiconductor (MOS) capacitor.
  • MOS Metal-Oxide-Semiconductor
  • at least one of the first capacitor and the second capacitor may also include a MIM capacitor and a MOS capacitor.
  • a second aspect of the present application provides a chip comprising the capacitor mentioned in the above first aspect or any of the possible implementations.
  • the chip is a radio frequency chip.
  • a third aspect of the present application provides a circuit board comprising the capacitors mentioned in the above first aspect or any of the possible implementations.
  • FIG. 1 is a schematic view of a capacitor built in a semiconductor chip in an embodiment of the present application
  • FIG. 2 is a schematic diagram of a three-dimensional structure of a capacitor in an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a three-dimensional structure of another capacitor in the embodiment of the present application.
  • FIG. 4 is a two-dimensional top view of a through hole and a through hole groove for forming a capacitor in an embodiment of the present application
  • FIG. 5 is a schematic diagram of a three-dimensional structure of another capacitor in the embodiment of the present application.
  • FIG. 6 is a schematic diagram of a three-dimensional structure of another capacitor in the embodiment of the present application.
  • FIG. 7 is a schematic diagram of a three-dimensional structure of another capacitor in the embodiment of the present application.
  • FIG. 8 is a schematic diagram of a three-dimensional structure of another capacitor in the embodiment of the present application.
  • FIG. 9 is a schematic diagram of a three-dimensional structure of another capacitor in the embodiment of the present application.
  • FIG. 10 is a schematic diagram of a three-dimensional structure of another capacitor in the embodiment of the present application.
  • FIG. 11 is a schematic diagram of a three-dimensional structure of another capacitor in the embodiment of the present application.
  • FIG. 12 is a two-dimensional top view of a capacitor in an embodiment of the present application.
  • Figure 13 is a two-dimensional top view of another capacitor in the embodiment of the present application.
  • Figure 14 is a two-dimensional side view of a capacitor in an embodiment of the present application.
  • Figure 15 is a two-dimensional side view of another capacitor in the embodiment of the present application.
  • 16 is a two-dimensional side view of a capacitor arranged in a vertical direction in an embodiment of the present application.
  • Figure 17 is a two dimensional side view of the distribution of capacitors in different layers in an embodiment of the present application.
  • FIG. 1 is a schematic diagram of a capacitor 10 built in a semiconductor chip 01 in the embodiment of the present application.
  • the semiconductor chip 01 may also be simply referred to as a chip, which may be a collection of integrated circuits formed on a substrate of an integrated circuit by an integrated circuit process, typically a semiconductor material such as silicon.
  • the exterior of the substrate after the formation of the integrated circuit is typically encapsulated by a semiconductor package material.
  • the integrated circuit may include various functional devices, each of which includes a transistor such as a logic gate circuit, a MOS transistor, a bipolar transistor, or a diode, and may also include other components such as a capacitor, a resistor, or an inductor.
  • Functional devices can work independently or with the necessary driver software to implement various functions such as communication, computing, or storage.
  • the semiconductor chip 01 may include an application processor chip, a video processor chip, a communication chip, a control chip, an artificial intelligence chip, a radio frequency chip, or a system on chip (SoC, System on Chip) that integrates any of the above functions. ), this embodiment does not limit this.
  • a semiconductor chip 01 includes a capacitor 10 including a first capacitor 12 and a second capacitor 11.
  • One end of the first capacitor 12 is electrically coupled to one end of the second capacitor 11 and is electrically coupled to the first end of the capacitor 10.
  • the other end of the first capacitor 12 is electrically coupled to the other end of the second capacitor 11 and electrically coupled to the second end of the capacitor 10.
  • the two capacitors 11 and 12 are arranged in different directions on the three-dimensional structure. For example, one of the capacitors is arranged in one direction, such as a vertical direction, and the other capacitor is arranged in the other direction, such as a horizontal direction. This design is resistant to semiconductors.
  • the capacitance value deviation of the capacitor 10 caused by the non-ideality of the fabrication process.
  • the thickness of the dielectric of the capacitors arranged in the vertical direction changes to some extent, and this change usually causes the plate length or area of another capacitor arranged in the horizontal direction to change correspondingly, so that the capacitance value of the two capacitors changes.
  • this change usually causes the plate length or area of another capacitor arranged in the horizontal direction to change correspondingly, so that the capacitance value of the two capacitors changes.
  • This embodiment is described by taking the capacitor 10 as being built in the semiconductor chip 01. It can be understood that the capacitor 10 can also be placed in devices formed by other fabrication processes, such as PCBs or other discrete devices.
  • the capacitor of the present embodiment can be applied to a product formed by the specific fabrication process as long as it can be used to overcome the capacitance value deviation of the capacitor caused by fluctuations in a particular fabrication process.
  • FIG. 2 provides a three-dimensional structure diagram of a capacitor 10 in the embodiment of the present application.
  • the x-axis represents the length direction or the horizontal direction
  • the z-axis represents the width direction or the depth direction
  • the y-axis represents the height direction or the vertical direction.
  • the z-axis and the x-axis are used to form a horizontal plane
  • the y-axis is perpendicular to a horizontal plane.
  • the capacitor 10 is an MOM capacitor including a first capacitor 12 arranged in the vertical direction on the right side and a second capacitor 11 arranged in the horizontal direction on the left side.
  • the first capacitor 12 includes a plurality of first electrical conductors 121 arranged in a vertical direction. Each of the two adjacent first electrical conductors 121 is separated by the first medium 122 to form a plurality of vertical capacitors arranged in a vertical direction, for example, specifically including a plurality of metal plate capacitors C_MP .
  • the first capacitor 12 includes a plurality of vertical capacitors.
  • the second capacitor 11 includes a plurality of second electric conductors 111 arranged in a horizontal direction.
  • Each of the two adjacent second electrical conductors 111 is separated by the second medium 112 to form a plurality of horizontal capacitors arranged in a horizontal direction, for example, specifically including a plurality of horizontal inter-metal capacitors (C _HM ) Capacitor formed between horizontal slot VIA C _HSV .
  • the second capacitor 11 includes a plurality of horizontal capacitors.
  • each of the first electrical conductors 121 is a plate of a vertical capacitor and is located on a conductive layer.
  • the metal layer is a typical conductive layer.
  • any of the first electrical conductors 121 may be a metal plate and is located on one of the plurality of layers in the semiconductor chip 01.
  • the first medium 122 located between any two adjacent first conductors 121 or metal layers is located on a dielectric layer, as specifically referred to the two-dimensional side view of FIG.
  • the plurality of first electrical conductors 121 electrically coupled to the first end and the plurality of first electrical conductors 121 electrically coupled to the second end may form an interdigitated structure, or two of the first plurality of metal plate capacitors C_MP An electrical conductor 121 is electrically coupled to the first end and the second end, respectively, and a plurality of metal plate capacitors C_MP are used to form the first capacitor 12.
  • each of the second electrical conductors 111 penetrates at least a portion of the plurality of layers in the semiconductor chip 01 through one or more via slots 113.
  • each of the second electrical conductors 111 includes a plurality of metal electrical conductors 115 on the plurality of metal layers and a corresponding plurality of through-hole grooves 113, each of the second electrical conductors 111 forming the first One plate of the two capacitors 11.
  • the via trenches 113 can include a conductive material, such as a metal, to electrically connect the different metal conductors 115 on the different conductive layers.
  • the via trenches 113 can be formed using conventional via trench fabrication methods in semiconductor fabrication processes.
  • each metal conductor 115 is located on the same metal layer as a metal plate of the corresponding first conductor 121, as shown in FIG. Any of the through-holes 113 may be located in the same dielectric layer, and may be located on the same dielectric layer as the corresponding first medium 122. See also the two-dimensional side view of FIG.
  • the metal plate 121 or the metal conductor 115 may include various metals such as aluminum, copper or tin.
  • the dielectric or dielectric layer can include various insulator materials, such as silicon dioxide, for effecting the function of the capacitor dielectric.
  • the second dielectric 112 between the two adjacent metal conductors 115 on the same metal layer and the adjacent metal conductor 115 forms a horizontal inter-metal capacitor.
  • C _HM The second dielectric 112 between the adjacent apertures 113 on the same dielectric layer and the adjacent apertures 113 forms a horizontal via-to-slot capacitor C_HSV .
  • the second capacitor 11 includes a plurality of horizontal capacitors, each of which includes a plurality of horizontal inter-metal capacitors C_HM and a plurality of horizontal via-hole capacitors C_HSV .
  • a second electrical conductor 111, which is a plate of each horizontal capacitor, is electrically coupled to the first end, and another second electrical conductor 111, which is the other of the plates, is electrically coupled to the second end.
  • FIG. 17 is a two-dimensional side view of the simplified structure of FIG. 2, which includes a plurality of layers of the semiconductor chip 01, specifically including a plurality of metal layers and a dielectric layer between adjacent metal layers.
  • the plurality of first electrical conductors 121 on the different metal layers form the first capacitor 12, and the plurality of second electrical conductors 111 penetrating the plurality of layers form the first capacitor 11.
  • the capacitance value of the vertical capacitor will change according to a certain trend, and the capacitance value of the horizontal capacitor is pressed.
  • the momentum of the same trend will be curbed, helping to reduce the capacitance value deviation of the entire capacitor 10 caused by the non-ideality of the manufacturing process.
  • the dielectric of the vertical capacitor is thickened to cause a decrease in the capacitance value, but such an increase in thickness causes an increase in the capacitance of the capacitor between the horizontal via holes to cause a level.
  • the increase in the capacitance of the capacitor is equivalent to increasing the length or area of the plate of the horizontal capacitor. This effect resists the influence of the reduction of the capacitance of the vertical capacitor to a certain extent, thereby helping to suppress the capacitance value deviation of the entire capacitor 10 and reducing the influence of the process angle. Further, considering the resistance of the present embodiment to the manufacturing process deviation, the design flexibility between the gaps between the different metal layers in the interdigitated structure, that is, the thickness of the dielectric layer is also improved. In particular, the thickness of the dielectric layer can be designed to be small, thereby contributing to reducing the volume of the capacitor 10.
  • FIG. 3 is a schematic diagram showing the three-dimensional structure of another capacitor 10 in the embodiment of the present application.
  • the difference from FIG. 2 is that the via grooves 113 for penetrating the plurality of layers in the semiconductor chip 01 can be replaced by the via holes 114.
  • the horizontal via-hole capacitor C_HSV is replaced by the horizontal via-hole capacitor C_HV .
  • Figure 4 a two-dimensional top view of the via and via trenches used to form the capacitor is shown, with the x-axis still showing the horizontal direction and the z-axis still showing the depth direction.
  • the through hole groove 113 on the left side is a complete groove in the depth direction, and the right side shows a plurality of independently existing through holes 114 in the depth direction, that is, the plurality of through holes 114 are in the depth direction. It does not connect as a whole, but it achieves an effect similar to the through-hole 114 as a whole.
  • via trenches 113 or vias 114 may be used to electrically connect different metal conductors 115 on different conductive layers and to form horizontal via inter-cavity capacitor C_HSV or horizontal inter-cell capacitor C_HV .
  • Either of the via grooves 113 or the through holes 114 may optionally include a metal material to achieve electrical connectivity.
  • vias 113 or vias 114 may also be replaced by other connections that are capable of penetrating through the dielectric layer and for electrically connecting different metal conductors 115 on different conductive layers.
  • a similar advantageous effect in the previous embodiment can be achieved as long as the connecting portion can form capacitors arranged in the horizontal direction to be distinguished from a plurality of vertical capacitors arranged in the vertical direction.
  • the length of the plate of the horizontal capacitor generally increases as the thickness increases, that is, increases the plate area of the horizontal capacitor, thereby Conducive to the increase in the capacitance of the horizontal capacitor.
  • the variation of the capacitance values of different capacitors according to different trends helps to offset the adverse effects caused by the non-ideality of the manufacturing process.
  • the three-dimensional coordinate axes x, y, and z are perpendicular to each other, and the first direction (vertical) in which the first capacitor 12 is arranged and the second direction (horizontal) in which the second capacitor 1 is arranged are perpendicular to each other of.
  • the second direction and the first direction may not be strictly perpendicular, that is, there is a certain angular deviation.
  • the beneficial effects of the embodiment can be effectively achieved.
  • the substantially vertical is that the angle between the second direction and the first direction is approximately ninety degrees.
  • the difference between the angle between the second direction and the first direction and ninety degrees is less than a preset threshold.
  • How to set the threshold or how to set the angle to be close to ninety degrees which may be calculated according to historical experience values, experimental data or theoretical calculations according to different manufacturing processes, which is not specifically limited in this embodiment.
  • the adjacent plurality of second electric conductors 111 are not arranged strictly in the horizontal direction of the x-axis, that is, each of the second electric conductors 111. It is not a strict vertical structure extending in the y-axis direction.
  • the extending direction y' of the second electric conductor 111 is not perpendicular to the x-axis, and thus the horizontal capacitor formed is not a horizontal capacitor in a strict sense, but since it is described according to the above embodiment, it can still resist the fluctuation of the manufacturing process to some extent. The effect of achieving a more accurate capacitance value.
  • FIG. 5 is a schematic diagram of a three-dimensional structure of another capacitor 10 in the embodiment of the present application.
  • the first electrical conductor 121 for forming the metal plate capacitor C_MP on any one or more of the metal layers is not a continuous length of metal body but a plurality of metals separated from each other. body.
  • the first electrical conductor 121 is a plurality of discontinuous metal electrical conductors in an extending direction along the x-axis, that is, in the horizontal direction.
  • FIG. 6 is a schematic diagram of a three-dimensional structure of another capacitor 10 in the embodiment of the present application.
  • the difference from FIG. 5 is that the via hole 113 is replaced by the via hole 114, and other designs are similar.
  • FIG. 7 is a schematic diagram of a three-dimensional structure of another capacitor 10 in the embodiment of the present application.
  • the difference from FIG. 2 is that the first electric conductor 121 in the first capacitor 12 in FIG. 7 shares a part of the electric conductor in the second electric conductor 111 in the second capacitor 11.
  • a plurality of first electrical conductors 121 electrically coupled to the first end are coupled to a portion of a second electrical conductor 111 electrically coupled to the first end, Thereby a fusion portion is formed, but this does not affect the technical effect achieved by the embodiment.
  • FIG. 8 is another modified embodiment which differs from FIG. 7 in that the via hole 114 replaces the via groove 113.
  • the boundary between the first capacitor 12 and the second capacitor 11 is no longer clear, although functionally, the two have different alignment directions and are capable of resisting the manufacturing process fluctuations of the integral capacitor 10 The capacitance value deviation, but the two are physically coupled tightly.
  • FIG. 9 is a schematic diagram of a three-dimensional structure of another capacitor 10 in the embodiment of the present application.
  • the difference from FIG. 2 is that the corresponding second conductor 111 is not present on the left side of the first conductor 121 on the lowermost metal layer forming the first capacitor 12.
  • the corresponding first electric conductor 121 does not exist on the right side of the uppermost metal layer of the second electric conductor 111. That is to say, the plurality of layers corresponding to the first capacitor 12 and the plurality of layers corresponding to the second capacitor 11 are not perfectly aligned.
  • FIG. 10 shows another embodiment in which, unlike FIG. 9, the number of layers for forming the first capacitor 12 is smaller than the number of layers for forming the second capacitor 11. As can be seen from the embodiment corresponding to FIG.
  • the plurality of layers in which the first capacitor 12 is located and the plurality of layers through which the second capacitor 11 is inserted may be partially different.
  • the plurality of layers in which the first capacitor 12 is located and the plurality of layers through which the second capacitor 11 is inserted may be completely different. The figure is not shown in this case, but this does not affect the present invention. The implementation of the embodiments can still achieve beneficial effects.
  • the positions of the first capacitor 12 and the second capacitor 11 are adjacent, but in actual implementation, the distance between the two may be further apart, as shown in FIG.
  • the first capacitor 12 and the second capacitor 11 may be isolated by other third party devices, which is not shown in FIG. That is to say, the difference from FIG. 2 is that the two capacitors in FIG. 11 may not be directly adjacent, but are separated by other one or more devices, which does not affect the implementation of the present technical solution.
  • the third party device can make a radio frequency device.
  • any one or more of the second electrical conductors 111 may not be a complete electrical conductor in the depth direction along the z-axis. It is a plurality of electrical conductors including separate from each other. That is, for any one or more of the metal conductors 115, the metal conductors 115 may form a plurality of discrete independent metal bodies in the depth direction along the z-axis.
  • Figure 13 shows another alternative embodiment. In FIG.
  • any one or more of the first electrical conductors 121 may not be one complete electrical conductor, but may include a plurality of metal bodies separated from each other and discontinuous. Therefore, the present embodiment may have many different forms in physical structure, but the advantageous effects achieved are similar to those of the previous embodiments.
  • Figure 15 is a two-dimensional side view of another capacitor 10 in an embodiment of the present application.
  • the structure corresponding to Fig. 15 is a further modification based on the previous embodiment.
  • the first electrical conductor 121 and the second electrical conductor 111 are shared, and for the same metal electrical conductor 115, it is used to form the first electrical conductor 121 in the first capacitor 12, and in the second
  • the capacitor 11 is used to form the second electrical conductor 111. Therefore, it can be considered that the metal conductor 115 is used to form the second conductor 111 in the horizontal direction, and the same one of the metal conductors 115 is used to form the first conductor 121 in the vertical direction. Therefore, this sharing enables the first capacitor 12 and the second capacitor 11 to achieve better fusion.
  • the two capacitors are respectively arranged in different directions, and the existence of the two different capacitors is beneficial to resist the adverse effects of the manufacturing process fluctuations, The two capacitors form a whole in physical structure and there is no obvious physical boundary.
  • the electrical conductor for connecting to the first end and the electrical conductor for connecting to the second end may be formed. Interdigitated structure.
  • the interdigital structure is more efficient, and the preset capacitance value can be achieved by occupying only a small volume.
  • at least one of the first capacitor 12 and the second capacitor 11 may not employ an interdigitated structure.
  • neither the first capacitor 12 nor the second capacitor 11 adopts an interdigital structure, that is, any adjacent two electric conductors are not necessarily connected to different ones of the first end and the second end, respectively.
  • At least one of the one or more first electrical conductors 121 and the one or more second electrical conductors 111 may comprise at least one material: a metallic material or a semiconductor material.
  • the conductors of the previous embodiments are all described using a metal material as an example, but this description is not intended to be limiting.
  • the first conductor of the lowermost layer of the plurality of first conductors 121 includes a semiconductor material
  • the first conductor 121 of the other layers includes a metal material
  • the substrate in the semiconductor chip 01 that is, the semiconductor portion can be directly used to form the lower plate of the lowermost vertical capacitor in place of the embodiment of FIG.
  • the middlemost metal plate The other at least one of the plates on the substrate for forming the vertical capacitor is still a metal plate, using a metallic material and located in the metal layer.
  • the plurality of metal layers can be formed on the substrate directly by an integrated circuit fabrication process, and the substrate itself can be fully utilized to form a capacitor.
  • the first medium 122 and the second medium 112 in the above embodiments may include one or more dielectric materials, and illustratively, the same dielectric material may be used, such as silicon dioxide. Of course, the silica can be replaced by one or more other dielectric materials.
  • the dielectric material used to make the medium typically has a lower electrical conductivity than the electrical conductor.
  • the capacitor 10 described in the above embodiment is integrated in an integrated circuit such as the semiconductor chip 01.
  • This application can achieve good effects and can better resist the capacitance value deviation of the capacitor caused by the non-ideality of the semiconductor fabrication process.
  • the solution of the present embodiment is well suited for the radio frequency field.
  • the semiconductor chip 10 includes a radio frequency chip, a better effect than the field of low frequency signal processing can be achieved.
  • an MOM capacitor is used as an example.
  • at least one of the first capacitor 12 and the second capacitor 11 may also include a MIM capacitor, a MOS capacitor, or may include a MIM capacitor, MOS.
  • the combination of any of the capacitors and the MOM capacitors is not limited in this embodiment.

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Abstract

一种电容器，包括第一端、第二端、第一电容器和第二电容器。所述第一电容器包括按第一方向排列的至少两个第一导电体，所述至少两个第一导电体中每两个相邻的第一导电体被第一介质所分隔，所述至少两个第一导电体中的一部分与所述第一端电耦合，所述至少两个第一导电体中的其他部分与所述第二端电耦合。所述第二电容器包括按第二方向排列的至少两个第二导电体，所述至少两个第二导电体中每两个相邻的第二导电体被所述第二介质所分隔，所述至少两个第二导电体中的一部分与所述第一端电耦合，所述至少两个第二导电体中的其他部分与所述第二端电耦合。所述第一电容器和第二电容器均具有叉指结构。

Description

电容器 技术领域
本申请涉及电子技术领域，尤其涉及一种电容器。
背景技术
随着集成电路制作工艺的演进，各类器件的制作工艺尺寸不断减小，其中金属-氧化物-金属(MOM，Metal-Oxide-Metal)电容器因面积较小而被广泛使用。相对金属-绝缘体-金属(MIM，Metal-Insulator-Metal)电容器，MOM电容器不仅节省面积，还不需要额外的光罩(mask)，可以降低制作成本。MOM电容器包括多个极板以及位于极板之间的介质。极板可以位于金属层，介质可以位于不同金属层之间的介质层。随着技术的演进，由先进制作工艺形成的MOM电容器的金属层或介质层的厚度越来越小，在制作工艺上精确控制各层的厚度变得越来越困难，这导致MOM电容器的工艺角(process corner)越来越大并形成工艺波动或偏差，这种工艺波动或偏差，也叫做制作工艺非理想性。在现有的MOM电容器结构中，MOM电容器按水平方向或垂直方向排列，一旦制作工艺的非理想性导致的MOM电容器的介质厚度出现偏差，会导致电容值不准确，如大于或小于预设电容值，从而影响系统性能。因此，如何减少制作工艺波动引起的电容值的偏差成为一个难题。
发明内容
本申请的实施例提供一种电容器，以减小制作工艺波动引起的电容值的偏差。
有鉴于此，本申请第一方面提供了一种电容器，包括第一端、第二端、第一电容器和第二电容器。所述第一电容器包括至少两个第一导电体和第一介质，所述至少两个第一导电体按第一方向排列，所述至少两个第一导电体中每两个相邻的第一导电体被所述第一介质所分隔，所述至少两个第一导电体中的一部分与所述第一端电耦合，所述至少两个第一导电体中的其他部分与所述第二端电耦合。所述第二电容器包括至少两个第二导电体和第二介质，所述至少两个第二导电体按不同于所述第一方向的第二方向排列，所述至少两个第二导电体中每两个相邻的第二导电体被所述第二介质所分隔，所述至少两个第二导电体中的一部分与所述第一端电耦合，所述至少两个第二导电体中的其他部分与所述第二端电耦合。
根据以上技术方案，一旦制作工艺的非理想性导致某一个方向的工艺参数，如第一介质的厚度出现某种变化，将导致按该方向排列的第一电容器的电容值按某种趋势变化。由于第一电容器和第二电容器排列方向不同，按另一方向排列的第二电容器的至少两个第二导电体长度也会随着第一介质的厚度变化发生对应变化，从而导致此第二电容器的电容值的变化趋势与第一电容器的电容值不同，这有助于减小制作工艺非理想性造成的整个电容器的电容值偏差。
在一种可能的实现方案中，所述每两个相邻的第一导电体包括第三导电体和第四导电体，所述第三导电体与所述第一端电耦合，所述第四导电体与所述第二端电耦合。 在本方案中，与所述第一端电耦合的多个第一导电体和与所述第二端电耦合的多个第一导电体可以形成第一叉指结构，以优化第一电容器的体积。
在另一种可能的实现方案中，所述每两个相邻的第二导电体包括第五导电体和第六导电体，所述第五导电体与所述第一端电耦合，所述第六导电体与所述第二端电耦合。在本方案中，与所述第一端电耦合的多个第二导电体和与所述第二端电耦合的多个第二导电体形成第二叉指结构，以优化第二电容器的体积。
在另一种可能的实现方案中，所述至少两个第一导电体分别位于多个层中的至少两个导电层上，所述多个层按所述第一方向排列。可选地，所述第一方向可以是垂直方向。此时，所述第一电容器是垂直电容器，例如可以包括金属板电容器。
进一步地，在另一种可能的实现方案中，所述第一介质位于所述多个层中的至少一个介质层上。可选地，所述第二电容器贯穿所述至少两个导电层和至少一个介质层。
在另一种可能的实现方案中，所述至少两个第二导电体贯穿所述多个层的至少部分层。可选地，所述至少两个第二导电体通过至少一个通孔(VIA)或通孔槽(Slot VIA)贯穿所述至少部分层。所述第二电容器贯穿全部或部分的所述多个层，形成水平电容器。例如水平电容器可包括水平金属间电容器，还可进一步选择性包括水平通孔间电容器或水平通孔槽间电容器。进一步地，在一种可能的示例中，所述至少一个通孔或通孔槽位于并贯穿所述至少部分层中的至少一个介质层。
在另一种可能的实现方案中，所述第二方向与所述第一方向大致垂直。例如，所述大致垂直是所述第二方向与所述第一方向的夹角接近九十度。或者，所述第二方向与所述第一方向的夹角与九十度之差小于预设阈值。
在另一种可能的实现方案中，所述至少两个第一导电体中的至少部分与所述至少两个第二导电体中的至少部分是共享的。在本方案中，所述第一电容器的至少一部分和所述第二电容器的至少一部分是共享。也即是说，所述第一电容器和所述第二电容器存在融合的部分。这种设计有利于减小电容器的体积。
在另一种可能的实现方案中，所述至少两个第一导电体与所述至少两个第二导电体是彼此独立的，即不存在融合。进一步地，所述第一电容器和所述第二电容器可以被第三方器件所隔离。也即是说，所述第一电容器和所述第二电容器之间可以包括一个或多个其他器件。即便这两个电容器不是直接相邻，而是被其他器件间隔，也不影响本技术方案的实施。
在另一种可能的实现方案中，所述至少两个第一导电体和所述至少两个第二导电体中的至少一个包括如下至少一种材料：金属材料或半导体材料。例如，当所述第一方向是垂直方向，所述至少两个第一导电体中最下层的第一导电体包括半导体材料，而其他第一导电体包括金属材料，以这种设计实现的第一电容器较为易于工艺实现。
在另一种可能的实现方案中，所述至少两个第一导电体和所述至少两个第二导电体包括相同的材料，例如，均为金属材料。
在另一种可能的实现方案中，所述第一介质和所述第二介质包括相同的介质材料，例如均为二氧化硅。
在另一种可能的实现方案中，所述电容器被集成在半导体芯片上。以上技术方案应用于半导体芯片一类的集成电路时，能达到很好的效果，可以较好的抵御半导体制 作工艺的非理想性导致的电容器的电容值偏差。进一步地，所述半导体芯片可以包括射频芯片，当以上技术方案应用于射频领域的时候，可达到比低频信号处理领域更好的效果。
在另一种可能的实现方案中，所述第一电容器和第二电容器的至少一个包括金属-氧化物-金属MOM电容器。可替换地，所述第一电容器和第二电容器的至少一个也可以包括MIM电容器。可替换地，所述第一电容器和第二电容器的至少一个也可以包括MOM电容器和金属-氧化物-半导体(MOS，Metal–Oxide–Semiconductor)电容器。可替换地，所述第一电容器和第二电容器的至少一个也可以包括MIM电容器和MOS电容器。
本申请第二方面提供了一种芯片，包括以上第一方面或其中任一可能的实现方案中提到的电容器。可选地，该芯片是射频芯片。
本申请第三方面提供了一种电路板，包括以上第一方面或其中任一可能的实现方案中提到的电容器。
本申请的以上方面或可能的实现方案在以下实施例的描述中会更加清楚易懂。
附图说明
图1为本申请实施例中一种内置于半导体芯片的电容器的示意图；
图2为本申请实施例中一种电容器的三维结构示意图；
图3为本申请实施例中另一种电容器的三维结构示意图；
图4为本申请实施例中一种用于形成电容器的通孔和通孔槽的二维俯视图；
图5为本申请实施例中另一种电容器的三维结构示意图；
图6为本申请实施例中另一种电容器的三维结构示意图；
图7为本申请实施例中另一种电容器的三维结构示意图；
图8为本申请实施例中另一种电容器的三维结构示意图；
图9为本申请实施例中另一种电容器的三维结构示意图；
图10为本申请实施例中另一种电容器的三维结构示意图；
图11为本申请实施例中另一种电容器的三维结构示意图；
图12为本申请实施例中一种电容器的二维俯视图；
图13为本申请实施例中另一种电容器的二维俯视图；
图14为本申请实施例中一种电容器的二维侧视图；
图15为本申请实施例中另一种电容器的二维侧视图；
图16为本申请实施例中一种按垂直方向排列的电容器的二维侧视图；
图17为本申请实施例中电容器在不同层中分布的二维侧视图。
具体实施方式
为了使本技术领域的人员更好地理解本申请实施例方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚地描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。本申请的说明书实施例和权利要求书及上述 附图中的术语“第一”、“第二”、和“第三”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。此外，术语“包括”以及其任何变形，意图在于覆盖不排他的包含，例如，包含了一系列模块或单元。本实施例所描述的电耦合，包括了任意电连接形式，如直接接触，通过导线、通孔、通孔槽、或其他器件连接等方式，以实现电连通。
在现代通信或电子系统中，电容器被越来越广泛地应用，例如应用在半导体芯片中或其他类型的电路，如印制电路板(PCB，Printed Circuit Board)中。图1为本申请实施例中一种内置于半导体芯片01的电容器10的示意图。该半导体芯片01也可以简称为芯片，其可以是利用集成电路工艺制作在集成电路的衬底上形成的集成电路的集合，衬底通常是例如硅一类的半导体材料。形成集成电路后的衬底的外部通常被半导体封装材料封装。所述集成电路可以包括各类功能器件，每一类功能器件包括逻辑门电路、MOS晶体管、双极晶体管或二极管等晶体管，也可包括电容器、电阻或电感等其他部件。功能器件可以独立工作或者在必要的驱动软件的作用下工作，可以实现通信、运算、或存储等各类功能。例如，半导体芯片01可以包括应用处理器芯片、视频处理器芯片、通信芯片、控制芯片、人工智能芯片、射频芯片、或集成了以上各芯片中任意多个功能的片上系统(SoC，System on Chip)，本实施例对此不作限制。
在图1中，半导体芯片01包括电容器10，该电容器10包括第一电容器12和第二电容器11。第一电容器12的一端与第二电容器11的一端电耦合并电耦合于电容器10的第一端。第一电容器12的另一端与第二电容器11的另一端电耦合并电耦合于电容器10的第二端。这两个电容器11和12在三维结构上按不同的方向排列，例如，其中一个电容器按一个方向，如垂直方向排列，另一个电容器按另一方向，如水平方向排列，这种设计可抵御半导体制作工艺的非理想性导致的电容器10的电容值偏差。例如，按垂直方向排列的电容器的介质厚度发生某种变化，这种变化通常使得按水平方向排列的另一个电容器的极板长度或面积发生对应变化，而使得两个电容器的电容值的变化趋势不同以抵御所述制作工艺非理想性的影响，后续实施例对此有更详细描述。
本实施例以电容器10被内置于半导体芯片01为例进行描述，可以理解，电容器10也可以被置于其他制作工艺形成的器件中，例如被用于PCB或其他分立器件。只要能够用于克服特定制作工艺波动导致的电容器的电容值偏差，那么本实施例的电容器均可以应用在该特定制作工艺形成的产品中。
为了更清晰的理解电容器10的结构，图2提供了本申请实施例中一种电容器10的三维结构示意图。在该三维示意图中，存在x、y和z三个坐标轴，x轴代表长度方向或水平方向，z轴代表宽度方向或深度方向，y轴代表高度方向或垂直方向。其中，z轴和x轴用于形成水平面，y轴则垂直于水平面。在该三维结构中，电容器10是MOM电容器，其包括右侧的按垂直方向排列的第一电容器12和左侧的按水平方向排列的第二电容器11。所述第一电容器12包括多个按垂直方向排列的第一导电体121。每两个相邻的第一导电体121被第一介质122所分隔，从而形成按垂直方向排列的多个垂直电容器，例如具体包括多个金属板电容器(metal plate capacitor)C _MP。第一电容器12包括多个垂直电容器。所述第二电容器11包括多个按水平方向排列的第二导电体111。每两个相邻的第二导电体111被第二介质112所分隔，从而形成按水平方向排列的多个水平电容器，例如具体包括多个水平金属间电容器(capacitor formed between horizontal metal)C _HM和多个水平通孔槽间电 容器(capacitor formed between horizontal slot VIA)C _HSV。第二电容器11包括多个水平电容器。
在图2的第一电容器12中，每个第一导电体121是一垂直电容器的极板，并位于一个导电层上。金属层则是一种典型的导电层。例如，任一第一导电体121可以是一个金属板，并位于半导体芯片01中多个层中的一个金属层上。位于任意两个相邻第一导电体121或金属层之间的第一介质122位于一个介质层上，具体可参照图17的二维侧视图。电耦合于第一端的多个第一导电体121与电耦合于第二端的多个第一导电体121可以形成叉指结构，或者说，任一金属板电容器C _MP所包括的两个第一导电体121分别电耦合至第一端和第二端，多个金属板电容器C _MP用于形成第一电容器12。
在图2的第二电容器11中，每个第二导电体111通过一个或多个通孔槽113贯穿半导体芯片01中的所述多个层的至少部分层。例如，在垂直方向上，每个第二导电体111包括了位于多个金属层上的多个金属导电体115和对应的多个通孔槽113，每个第二导电体111形成所述第二电容器11的一个极板。通孔槽113可包括导电材料，如金属，以电连通不同导电层上的不同金属导电体115，该通孔槽113可以采用半导体制作工艺中常规的通孔槽制作方法生成。在水平方向上，每个金属导电体115与对应的第一导电体121的一个金属板位于同一个金属层上，具体如图2所示。任一通孔槽113可以位于并贯穿一个介质层，具体地可以与对应的第一介质122位于同一个介质层上，具体也可参照图17的二维侧视图。所述金属板121或金属导电体115可以包括铝、铜或锡等各类金属。所述介质或介质层可包括各种用于实现电容器介质功能的绝缘体材料，例如二氧化硅。
在图2中，对于第二导电体111而言，位于同一个金属层上的两个相邻金属导电体115与该相邻金属导电体115之间的第二介质112形成一水平金属间电容器C _HM。位于同一个介质层上的相邻孔槽113与该相邻孔槽113之间的第二介质112形成一水平通孔槽间电容器C _HSV。第二电容器11包括多个水平电容器，每个水平电容器包括多个水平金属间电容器C _HM和多个水平通孔槽间电容器C _HSV。作为每个水平电容器的极板的一个第二导电体111与第一端电耦合，而作为另一极板的另一第二导电体111则与第二端电耦合。
在图2中，电耦合至第一端的导电体以阴影表示，而电耦合至第二端的导电体以无色表示。可以看到，无论是在第一电容器12和第二电容器11中，电耦合至第一端的导电体和电耦合至第二端的导电体彼此之间间隔排列，即相邻的两个导电体不会电耦合至电容器10的同一端，这种交叉排列设计形成叉指结构。具体请参考图17，为图2的简化结构的二维侧视图，该图17中包括半导体芯片01的多个层，具体包括多个金属层和位于相邻金属层之间的介质层。不同金属层上的多个第一导电体121形成第一电容器12，贯穿多个层的多个第二导电体111形成第一电容器11。
通过以上技术方案，即便制作工艺的非理想性导致某一个方向的工艺参数，如一个或多个介质层的厚度出现偏差，垂直电容器的电容值将按某种趋势变化，水平电容器的电容值按相同趋势的势头会得到遏制，有助于减小制作工艺非理想性造成的整个电容器10的电容值偏差。例如，当一个或多个介质层的厚度增大，则导致垂直电容器的介质变厚从而导致电容值减小，但这种厚度增加会导致水平通孔槽间电容器的电容值增大进而导致水平电容器的电容值增加，相当于增加了水平电容器的极板长度或面积。这种效果在一定程度上抵御垂直电容器的电容值减小带来的影响，从而有助于抑制整个电容器10的电容值偏 差，减少工艺角影响。进一步地，考虑到本实施例对于制作工艺偏差的抵御效果，叉指结构中的不同金属层之间的间隙，即介质层的厚度的设计灵活性也提高了。具体地，介质层的厚度可以被设计的很小，从而有利于减小电容器10的体积。
图3提供了本申请实施例中另一种电容器10的三维结构示意图。与图2的区别在于，用于贯穿半导体芯片01中的所述多个层的通孔槽113，可以被通孔114所代替。此时在图3中，水平通孔槽间电容器C _HSV则被水平通孔间电容器C _HV所代替。为了便于理解，请参照图4，给出了用于形成电容器的通孔和通孔槽的二维俯视图，x轴依然展示了水平方向，而z轴依然展示了深度方向。左侧的通孔槽113在深度方向上是一个完整的槽，而右侧则示出了在深度方向上多个独立存在的通孔114，也即是说多个通孔114在深度方向上不会连接成一个整体，但是其实现的效果与作为一个整体的通孔槽114类似。
在本发明各实施例中，通孔槽113或通孔114可以用于电连通不同导电层上的不同金属导电体115并用于形成水平通孔槽间电容器C _HSV或水平通孔间电容器C _HV。通孔槽113或通孔114中任一可选择性包括金属材料以实现电连通性。在可替换的实施例中，通孔槽113或通孔114也可以被其他能够贯穿介质层、并用于电连通不同导电层上的不同金属导电体115的连接部所代替。只要该连接部能够形成按水平方向排列的电容器以区别于按垂直方向排列的多个垂直电容器，即可达到之前实施例中类似的有益效果。例如，当垂直电容器的介质厚度增大，导致垂直电容器的电容值减小，此时水平电容器的极板长度通常会随着厚度增大相应增大，即增大水平电容器的极板面积，从而有利于水平电容器的电容值增大。不同电容器的电容值按不同趋势变化有助于抵消制作工艺非理想性造成的不良影响。
在以上实施例中，三维坐标轴x，y和z彼此之间垂直，且第一电容器12所排列的第一方向(垂直)和第二电容器1所排列的第二方向(水平)是互相垂直的。通常情况下，可以理解，在实际工程实现的时候，所述第二方向与所述第一方向可以不是严格垂直的，也即存在一定角度偏差。只要所述第二方向与所述第一方向大致垂直，即可有效达到本实施例的有益效果。例如，所述大致垂直是所述第二方向与所述第一方向的夹角接近九十度。或者说，所述第二方向与所述第一方向的夹角与九十度之差小于预设阈值。如何设置所述阈值或如何通过设置使得所述夹角达到接近九十度，可以是根据制作工艺的不同，依照历史经验值、实验数据或理论计算得到，本实施例对此不作具体限制。具体可参照图14，从该图14的二维侧视图中看起来，相邻的多个第二导电体111之间不是严格按照按x轴的水平方向排列，即每个第二导电体111不是严格的沿y轴方向延伸的垂直结构。第二导电体111的延伸方向y’与x轴不是垂直的，因此形成的水平电容器不是严格意义上的水平电容器，但是由于其根据以上实施例的描述，依然可以在一定程度上抵御制作工艺波动的影响，实现更准确的电容值。
图5是本申请实施例中另一种电容器10的三维结构示意图。与图2不同之处在于，在图5中，在任一个或多个金属层上用于形成金属板电容器C _MP的第一导电体121不是连续的一段金属体，而是彼此分离的多个金属体。例如，在一个金属层中，在沿x轴，即水平方向的延伸方向上，所述第一导电体121是多个不连续的金属导电体。图6则是本申请实施例中另一种电容器10的三维结构示意图。与图5不同之处在于，以通孔代114替通孔槽113，其他设计则类似。
图7是本申请实施例中另一种电容器10的三维结构示意图。与图2的不同之处在于，图7中的第一电容器12中第一导电体121与第二电容器11中的第二导电体111共享了一部分导电体。例如，在第一电容器12与第二电容器11靠近的部分，电耦合至第一端的多个第一导电体121与电耦合至第一端的一个第二导电体111的一部分偶合在一起，从而形成了融合部分，但这不影响该实施例达到的技术效果。图8则是另一种变形的实施例，其与图7的不同之处在于通孔代114替通孔槽113。在所述具有融合部分的方案中，第一电容器12与第二电容器11的分界线不再鲜明，虽然从功能上来看，二者具有不同的排列方向并能够抵御制作工艺波动导致的整体电容器10的电容值偏差，但二者在物理结构上是紧密耦合的。
图9是本申请实施例中另一种电容器10的三维结构示意图。与图2的不同之处在于，形成第一电容器12的最下金属层上的第一导电体121左侧不存在对应的第二导电体111。相反，第二导电体111最上金属层的右侧则不存在对应的第一导电体121。也即是说，第一电容器12对应的多个层与第二电容器11对应的多个层不是完全对齐的。图10则展示了另一个实施例，其中与图9不同，用于形成第一电容器12的多个层的数量少于用于形成第二电容器11的多个层的数量。从图9或10对应的实施例可以看到，第一电容器12所位于的多个层与第二电容器11贯穿的多个层可以部分不同。在另一种可替换的实现方案中，第一电容器12所位于的多个层与第二电容器11贯穿的多个层可以完全不同，附图对此种情况未示出，但这不影响本实施例的实施，并依然可以达到有益效果。
在之前的各实施例中，第一电容器12与第二电容器11的位置相邻，但在实际上实现中，二者之间可相距较远，如图11所示。例如，第一电容器12与第二电容器11可以被其他第三方方器件所隔离，图11对此未示出。也即是说，与图2不同之处在于，图11中的两个电容器可以不是直接相邻，而是被有其他一个或多个器件所间隔，这并不影响本技术方案的实施。例如，所述第三方器件可以使射频器件。
本申请实施例的电容器10还可以存在其他变形方式。例如，如图12的二维俯视图所示，在一种可替换的实施例中，在沿z轴的深度方向上，任意一个或多个第二导电体111可以不是一个完整的导电体，而是包括彼此分离的多个导电体。即对于任意一个或多个金属导电体115而言，该金属导电体115可以在沿z轴的深度方向上形成不连续的多个独立金属体。图13则展示了另一种可替换的实施例。在图13中，在沿z轴的深度方向上，任意一个或多个第一导电体121也可以不是一个完整的导电体，而是包括彼此分离且不连续的多个金属体。因此，本实施例在物理结构上可能存在多种不同的形式，但是达到的有益效果与之前的实施例类似。
图15是本申请实施例中另一种电容器10的二维侧视图。图15对应的结构是在之前实施例基础上的进一步变形。在图15中，第一导电体121与第二导电体111是共享的，对于同一个金属导电体115而言，其在第一电容器12中用于形成第一导电体121，并在第二电容器11中用于形成第二导电体111。因此，可以认为，在水平方向上，金属导电体115用于形成第二导电体111；而在垂直方向上，同样的一个金属导电体115用于形成第一导电体121。因此，这种共享使得第一电容器12与第二电容器11实现较好的融合，两个电容器虽然分别按不同方向排列，并且这两种不同电容器的存在有利于抵御制作工艺波动的不良影响，但两个电容器在物理结构上形成一个整体，且没有明显的物理分界线。
需要说明的是，在之前各实施例中，无论是在第一电容器12中还是在第二电容器11中，用于连接至第一端的导电体和用于连接至第二端的导电体可形成叉指结构。这种叉指结构效率较高，仅占用较小的体积即可实现预设的电容值。作为一种可替换的实现方案，第一电容器12和第二电容器11中的至少一个可以不采用叉指结构。具体可以参照图16，第一电容器12和第二电容器11均没有采用叉指结构，也就是说，任意相邻的两个导电体不一定会分别连接至第一端和第二端中的不同端，可能存在两个相邻的导电体连接至同一端，如第二端的情况，这种情况可以作为之前实施例的有效扩展，但是依然可以达到抵御制作工艺偏差的影响。
在另一种可能的实现方案中，一个或多个第一导电体121和一个或多个第二导电体111中的至少一个可包括如下至少一种材料：金属材料或半导体材料。之前的实施例的导电体均使用金属材料作为示例来说明，但是这种说明不用于限定。例如，在垂直方向上，多个第一导电体121中最下层的第一导电体包括半导体材料，而其他层上的第一导电体121则包括金属材料，以这种设计实现的第一电容器较为易于工艺实现。也即是说，当在垂直方向上形成多个垂直电容器时，半导体芯片01中的衬底，即半导体部分可直接用于形成最下一层的垂直电容器的下极板以代替图2实施例中最下层的金属板。衬底之上的其它用于形成垂直电容器的至少一个极板依然是金属板，使用金属材料并位于金属层之中。具体地，可以直接通过集成电路制作工艺在衬底上形成所述多个金属层，并充分利用了衬底本身来形成电容器。
以上实施例中的所述第一介质122和所述第二介质112可以包括一种或多种介质材料，示例性地，可使用相同的介质材料，如为二氧化硅。当然，二氧化硅可以被其他一种或多种介质材料所代替。用于制作介质的介质材料的导电率通常会低于导电体的导电率。
以上实施例中所述电容器10被集成在半导体芯片01一类的集成电路，这种应用能达到很好的效果，可以较好的抵御半导体制作工艺的非理想性导致的电容器的电容值偏差。特别地，本实施例的所述方案能很好地适合射频领域。例如，当所述半导体芯片10包括射频芯片时，可达到比低频信号处理领域更好的效果。
在本申请以上实施例中以MOM电容器来举例进行介绍，可扩展地，所述第一电容器12和第二电容器11的至少一个可以也可以包括MIM电容器、MOS电容器，或者可以包括MIM电容器、MOS电容器和MOM电容器中任意多种的结合，本实施例对此不做限制。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。例如，装置实施例中的一些具体操作可以参考之前的方法实施例。

Claims (15)

  1. 一种电容器，其特征在于，包括第一端、第二端、第一电容器和第二电容器；
    所述第一电容器包括至少两个第一导电体和第一介质，所述至少两个第一导电体按第一方向排列，所述至少两个第一导电体中每两个相邻的第一导电体被所述第一介质所分隔，所述至少两个第一导电体中的一部分与所述第一端电耦合，所述至少两个第一导电体中的其他部分与所述第二端电耦合；
    所述第二电容器包括至少两个第二导电体和第二介质，所述至少两个第二导电体按不同于所述第一方向的第二方向排列，所述至少两个第二导电体中每两个相邻的第二导电体被所述第二介质所分隔，所述至少两个第二导电体中的一部分与所述第一端电耦合，所述至少两个第二导电体中的其他部分与所述第二端电耦合。
  2. 根据权利要求1所述电容器，其特征在于，所述每两个相邻的第一导电体包括第三导电体和第四导电体，所述第三导电体与所述第一端电耦合，所述第四导电体与所述第二端电耦合。
  3. 根据权利要求1或2所述电容器，其特征在于，所述每两个相邻的第二导电体包括第五导电体和第六导电体，所述第五导电体与所述第一端电耦合，所述第六导电体与所述第二端电耦合。
  4. 根据权利要求1至3中任一项所述电容器，其特征在于，所述至少两个第一导电体分别位于多个层中的至少两个导电层上，所述多个层按所述第一方向排列。
  5. 根据权利要求4所述电容器，其特征在于，所述至少两个第二导电体贯穿所述多个层的至少部分层。
  6. 根据权利要求5所述电容器，其特征在于，所述至少两个第二导电体通过至少一个通孔或通孔槽贯穿所述至少部分层。
  7. 根据权利要求6所述电容器，其特征在于，所述至少一个通孔或通孔槽位于并贯穿所述至少部分层中的至少一个介质层。
  8. 根据权利要求1至7中任一项所述电容器，其特征在于，所述第二方向与所述第一方向大致垂直。
  9. 根据权利要求1至8中任一项所述电容器，其特征在于，所述至少两个第一导电体中的至少部分与所述至少两个第二导电体中的至少部分是共享的。
  10. 根据权利要求1至9中任一项所述电容器，其特征在于，所述至少两个第一导电体和所述至少两个第二导电体中的至少一个包括如下至少一种材料：金属材料或半导体材料。
  11. 根据权利要求1至10中任一项所述电容器，其特征在于，所述至少两个第一导电体和所述至少两个第二导电体包括相同的材料。
  12. 根据权利要求1至11中任一项所述电容器，其特征在于，所述第一介质和所述第二介质包括相同的介质材料。
  13. 根据权利要求1至12中任一项所述电容器，其特征在于，所述电容器被集成在半导体芯片上。
  14. 根据权利要求1至13中任一项所述电容器，其特征在于，所述第一电容器和第二电容器的至少一个包括金属-氧化物-金属MOM电容。
  15. 根据权利要求1至14中任一项所述电容器，其特征在于，所述第一电容器和所述第二电容器被第三方器件所隔离。
PCT/CN2017/120203 2017-12-29 2017-12-29 电容器 WO2019127489A1 (zh)

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CN201780096679.0A CN111357103A (zh) 2017-12-29 2017-12-29 电容器
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