WO2019114054A1 - 一种用于检测显示面板中像素电位的电路及方法、显示面板 - Google Patents

一种用于检测显示面板中像素电位的电路及方法、显示面板 Download PDF

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Publication number
WO2019114054A1
WO2019114054A1 PCT/CN2018/071259 CN2018071259W WO2019114054A1 WO 2019114054 A1 WO2019114054 A1 WO 2019114054A1 CN 2018071259 W CN2018071259 W CN 2018071259W WO 2019114054 A1 WO2019114054 A1 WO 2019114054A1
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Prior art keywords
thin film
pixel
film transistor
display panel
signal
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PCT/CN2018/071259
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English (en)
French (fr)
Inventor
洪光辉
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武汉华星光电技术有限公司
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Priority to US15/749,422 priority Critical patent/US10741111B2/en
Publication of WO2019114054A1 publication Critical patent/WO2019114054A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a circuit and method for detecting pixel potential in a display panel, and a display panel.
  • the AA area (ie, effective display area) design and the pixel driving circuit (shown in FIG. 1) of the commonly used display panel include a Gate trace (ie, a gate line), a Data trace (ie, a first data line), and a sub-pixel. Unit and demultiplexer circuit.
  • the Gate trace is used to realize the progressive scan of the panel AA sub-pixel unit
  • the Data trace is used to charge the sub-pixel unit of the panel AA area
  • the sub-pixel unit is used to display the image in the panel
  • the demultiplexer circuit is used for realizing Multi-output selection of the Data trace in the display panel.
  • the display panel drives the liquid crystal rotation through the potential in the sub-pixel unit to achieve different degrees of transmittance required by the display panel under different screens.
  • the true potential state in the display panel sub-pixel unit is an important indicator.
  • the real potential in the sub-pixel unit of the display panel cannot be truly measured. Therefore, in the process of problem analysis, the design cannot obtain the real potential in the sub-pixel unit through the existing device. situation. Since the current design does not design a structure for detecting the true potential in the sub-pixel unit, the true potential of the sub-pixel unit in the display panel, that is, the true pixel potential, cannot be accurately obtained.
  • the present invention provides a circuit and method for detecting a pixel potential in a display panel, and a display panel, which can measure a true pixel potential in the display panel.
  • the detecting circuit includes a first thin film transistor, a first end of the first thin film transistor is connected to the test signal, a second end is connected to the signal amplifier, and a third end is connected to the multiple output selector;
  • the multi-output selector is connected to the first data line of the display panel and the detecting circuit, and is configured to select, according to the reverse clock signal, the first data line connecting the sub-pixel unit to be detected and the first thin film transistor Turning on to transmit the pixel potential signal of the sub-pixel unit to be detected to the first thin film transistor, and controlling the first thin film transistor to send the test signal to the signal amplifier;
  • the first end of the thin film transistor in the circuit for detecting the pixel potential in the display panel is one of a source and a drain, the second end is the other of the source and the drain, and the third end is a gate.
  • the multiple output selector comprises N sets of inverted clock signal lines and a plurality of second thin film transistors respectively connected to the first data lines of the display panel, each set of reverse clock signal lines comprising Three reverse clock signal lines;
  • Each adjacent 3*N second thin film transistors in the display panel are respectively connected to different reverse clock signal lines in the N sets of inverted clock signal lines;
  • the first thin film transistor and the second thin film transistor are both N-channel thin film transistors.
  • the signal analysis module is connected to the signal amplifier for receiving the received signal output by the signal amplifier, and determining the potential of the pixel to be detected according to the intensity of the received signal.
  • the present invention also provides a display panel including a pixel driving circuit and a circuit for detecting a pixel potential in the display panel;
  • the circuit for detecting a pixel potential in a display panel includes a multiple output selector, at least one detection circuit, and at least one signal amplifier;
  • the detecting circuit includes a first thin film transistor, a first end of the first thin film transistor is connected to the test signal, a second end is connected to the signal amplifier, and a third end is connected to the multiple output selector;
  • the multi-output selector is connected to the first data line of the display panel and the detecting circuit, and is configured to select, according to the reverse clock signal, the first data line connecting the sub-pixel unit to be detected and the first thin film transistor Turning on to transmit the pixel potential signal of the sub-pixel unit to be detected to the first thin film transistor, and controlling the first thin film transistor to send the test signal to the signal amplifier;
  • the signal amplifier is configured to receive the test signal, and amplify the test signal into a received signal output;
  • the pixel driving circuit includes a plurality of first data lines, a plurality of gate lines, and three sub-pixels a switch control signal line, the plurality of first data lines intersecting the plurality of gate lines to form an array structure;
  • the rectangular regions formed by the adjacent two first data lines and the adjacent two gate lines are sub-pixel units, each of the sub-pixel units
  • the pixel unit includes a pixel thin film transistor, the first end of the pixel thin film transistor is connected to an adjacent first data line, the third end is connected to an adjacent gate line, and the first data line and the gate intersecting each other Connect up to one pixel thin film transistor on the line;
  • Each of the first data lines is connected to the sub-pixel switch control signal line through a third thin film transistor, and each of the three adjacent first data lines is respectively connected to three different sub-pixel switch control signal lines;
  • all of the thin film transistors in the pixel driving circuit are N-channel thin film transistors.
  • the multiple output selector comprises N sets of inverted clock signal lines and a plurality of second thin film transistors respectively connected to the first data lines of the display panel, each set of reverse clock signal lines comprising Three reverse clock signal lines;
  • Each adjacent 3*N second thin film transistors in the display panel are respectively connected to different reverse clock signal lines in the N sets of inverted clock signal lines;
  • the first end of the second thin film transistor is connected to the third end of the first thin film transistor, and the second end of the second thin film transistor is connected to the first data line of the display panel, and the third end is opposite Connect to the clock signal line.
  • the total number of the first data lines in the display panel is set to M, and the number of the detection circuit and the signal amplifier are both the smallest integer greater than or equal to M/(3*N), and the The first thin film transistor is connected to the signal amplifier in a one-to-one correspondence.
  • the first thin film transistor and the second thin film transistor are both N-channel thin film transistors.
  • a signal analysis module is further included;
  • the signal analysis module is connected to the signal amplifier for receiving the received signal output by the signal amplifier, and determining the potential of the pixel to be detected according to the intensity of the received signal.
  • the present invention also provides a method for detecting a pixel potential in a display panel, which is applied to a display panel, the display panel comprising a pixel driving circuit and a circuit for detecting a pixel potential in the display panel;
  • the circuit for detecting a pixel potential in a display panel includes a multiple output selector, at least one detection circuit, and at least one signal amplifier;
  • the detecting circuit includes a first thin film transistor, a first end of the first thin film transistor is connected to the test signal, a second end is connected to the signal amplifier, and a third end is connected to the multiple output selector;
  • the multi-output selector is connected to the first data line of the display panel and the detecting circuit, and is configured to select, according to the reverse clock signal, the first data line connecting the sub-pixel unit to be detected and the first thin film transistor Turning on to transmit the pixel potential signal of the sub-pixel unit to be detected to the first thin film transistor, and controlling the first thin film transistor to send the test signal to the signal amplifier;
  • the signal amplifier is configured to receive the test signal, and amplify the test signal into a received signal output;
  • the pixel driving circuit includes a plurality of first data lines, a plurality of gate lines, and three sub-pixels a switch control signal line, the plurality of first data lines intersecting the plurality of gate lines to form an array structure;
  • the rectangular regions formed by the adjacent two first data lines and the adjacent two gate lines are sub-pixel units, each of the sub-pixel units
  • the pixel unit includes a pixel thin film transistor, the first end of the pixel thin film transistor is connected to an adjacent first data line, the third end is connected to an adjacent gate line, and the first data line and the gate intersecting each other Connect up to one pixel thin film transistor on the line;
  • Each of the first data lines is connected to the sub-pixel switch control signal line through a third thin film transistor, and each of the three adjacent first data lines is respectively connected to three different sub-pixel switch control signal lines;
  • the pixel potential signal to be detected controls the first thin film transistor to send a test signal to a signal amplifier
  • the pixel potential to be detected is determined according to the intensity of the received signal.
  • the display panel includes the circuit for detecting a pixel potential in the display panel according to claim 4,
  • a reverse clock signal line connected to the pixel thin film transistor of the sub-pixel unit to be detected is at a high potential, and a reverse clock signal line not connected to the pixel thin film transistor of the sub-pixel unit to be detected is at a low potential;
  • the invention has the following beneficial effects: the first data line connecting the sub-pixel unit to be detected is connected to the first thin film transistor by the multi-output selector, and the pixel potential signal of the sub-pixel unit to be detected is sent to the first a thin film transistor that controls the first thin film transistor to send the test signal to a signal amplifier, the signal amplifier amplifies the test signal into a received signal, and can inversely measure the true potential state of the sub-pixel unit in the display panel according to the intensity of the received signal .
  • FIG. 1 is a schematic diagram of a pixel driving circuit of AA area in the background art provided by the present invention.
  • FIG. 2 is a schematic diagram of a circuit for detecting a pixel potential in a display panel in the first embodiment provided by the present invention.
  • FIG. 3 is a schematic diagram of a circuit for detecting a pixel potential in a display panel in a second embodiment provided by the present invention.
  • Fig. 4 is a schematic diagram of a circuit for detecting a pixel potential in a display panel in a third embodiment provided by the present invention.
  • FIG. 6 is a timing diagram of signals corresponding to the normal operation of the display panel in the first embodiment provided by the present invention.
  • FIG. 7 is a signal timing diagram of a display panel corresponding to the pixel potential of the pixel thin film transistor NT201 in the first embodiment of the present invention.
  • FIG. 8 is a timing chart of signals of a display panel corresponding to the pixel potential of the pixel thin film transistor NT202 in the first embodiment of the present invention.
  • FIG. 9 is a signal timing diagram of a display panel corresponding to the pixel potential of the detection pixel thin film transistor NT203 in the first embodiment of the present invention.
  • FIG. 10 is a timing diagram of signals corresponding to a normal operation of the display panel in the second embodiment of the present invention.
  • the detecting circuit 120 includes a first thin film transistor NT1.
  • the first end of the first thin film transistor NT1 is connected to the test signal, and the second end of the first thin film transistor NT1 is connected to the signal amplifier 130.
  • the third end of the first thin film transistor NT1 is The multiple output selectors 110 are connected.
  • the signal amplifier 130 is configured to receive the test signal and amplify the test signal into a received signal output.
  • the first end of the second thin film transistor NT2 is connected to the third end of the first thin film transistor NT1
  • the second end of the second thin film transistor NT2 is connected to the first data line of the display panel, and the third end is connected with The reverse clock signal line is connected.
  • the total number of the first data lines in the display panel is set to M, and M is a positive integer, and the number of the detection circuit 120 and the signal amplifier 130 are both the smallest integer greater than or equal to M/(3*N), and the number A thin film transistor NT1 and a signal amplifier 130 are connected in one-to-one correspondence.
  • first thin film transistor NT1 and the second thin film transistor NT2 are both N-channel thin film transistors.
  • the circuit for detecting the pixel potential in the display panel further includes a signal analysis module 140; the signal analysis module 140 is connected to the signal amplifier 130 for receiving the received signal output by the signal amplifier 130, and receiving according to The strength of the signal determines the potential of the pixel to be detected.
  • the present invention also provides a display panel, as shown in Figs. 5a and 5b, the display panel 10 includes a pixel driving circuit 200 and the above-described circuit 100 for detecting a pixel potential in the display panel.
  • the pixel driving circuit 200 is located in the AA area 20 of the display panel 10.
  • the circuit 100 for detecting the pixel potential in the display panel may be located in the AA area 20, as shown in FIG. 5b, for detecting the display.
  • the circuit 100 of the pixel potential in the panel may not be located in the AA area 20.
  • the pixel driving circuit 200 includes a plurality of first data lines, a plurality of gate lines, and three sub-pixel switching control signal lines, wherein the plurality of first data lines and the plurality of gate lines intersect to form an array structure; adjacent two first data
  • the rectangular region formed by the line and the adjacent two gate lines is a sub-pixel unit, and each of the sub-pixel units includes a pixel thin film transistor, and the first end of the pixel thin film transistor is connected to the adjacent first data line, and the pixel thin film transistor is The third end is connected to the adjacent gate line, and the first data line and the gate line intersecting each other are connected with a maximum of one pixel thin film transistor, that is, two different pixel thin film transistors cannot be connected at the same time in the first group of intersecting first Data lines and gate lines.
  • Each of the first data lines is connected to the sub-pixel switch control signal line through a third thin film transistor NT3, and each of the three adjacent first data lines is respectively connected to three different sub-pixel switch control signal lines.
  • the three different sub-pixel switch control signal lines are a red sub-pixel switch control signal line, a green sub-pixel switch control signal line, and a blue sub-pixel switch control signal line.
  • the third end of the third thin film transistor NT3 is connected to the sub-pixel switch control signal line, the first data line is connected to the first end of the third thin film transistor NT3, and the second end of the adjacent three third thin film transistors NT3 Access to the same second data line (the second data line is Data1, Data2, Data3 as shown in Figures 2 and 3).
  • the first end of the thin film transistor in the pixel driving circuit 200 is one of a source and a drain, the second end is the other of the source and the drain, and the third end is a gate.
  • the reverse clock signals in the circuit 100 for detecting the pixel potential in the display panel when the display panel is in operation are all low potential VGL.
  • the present invention also provides a method for detecting a pixel potential in a display panel, which is applied to the above display panel, the method comprising the following steps:
  • the pixel potential signal to be detected is also the potential signal of the sub-pixel unit to be detected;
  • the pixel potential signal to be detected controls the first thin film transistor NT1 to send a test signal to the signal amplifier 130;
  • the signal amplifier 130 amplifies the test signal to obtain a received signal
  • the pixel potential to be detected is judged based on the intensity of the received signal.
  • the pixel potential to be detected is also the potential of the sub-pixel unit to be detected.
  • the pixel thin film transistor other than the pixel thin film transistor of the display sub-pixel unit in the display panel is turned off by the gate line and the sub-pixel control signal, and the multi-output selector 110 is controlled by the reverse clock signal, and is to be
  • the detection pixel potential signal is sent to the first thin film transistor NT1, specifically:
  • a gate line connected to the pixel thin film transistor of the sub-pixel unit to be detected is a high potential VGH, and a gate line not connected to the pixel thin film transistor of the sub-pixel unit to be detected is a low potential VGL;
  • the three sub-pixel control signals are controlled to be low potential VGL.
  • the multiple output selector 110 includes three reverse clock signal lines TCK1, TCK2, TCK3, and the reverse clock signals in TCK1, TCK2, and TCK3.
  • TCK1, TCK2, TCK3, TCK3 To control the on and off of the second thin film transistor NT2, and control the gate lines Gate1, Gate2, Gate3, Gate4 through a GOA (Gate Driver on Array) circuit, and also control signals through the red sub-pixel switch
  • the line MUXR, the green sub-pixel switch control signal line MUXG, and the blue sub-pixel switch control signal line MUXB control the turn-on and turn-off of the third thin film transistor NT3 to display a potential signal (ie, a pixel potential signal) in the panel sub-pixel unit.
  • a potential signal ie, a pixel potential signal
  • FIG. 6 shows a signal timing diagram when the display panel is in normal operation, specifically, a timing chart of the pixel driving circuit 200 of the display panel AA area.
  • the inverted clock signals in the added reverse clock signal lines TCK1, TCK2, TCK3 are maintained at a low potential VGL, and the multi-output selector 110 is added. The circuit does not work and the display panel is driving normally.
  • the sub-pixel unit corresponding to the pixel thin film transistor NT201 in FIG. The potential will be turned on to the pixel potential signal 1 to drive the detection circuit 120 to operate, and the received test signal is converted into a received signal by the action of the signal amplifier 130, and the true state in the sub-pixel unit in the display panel is determined according to the intensity of the received signal. Potential condition.
  • FIG. 8 shows a signal timing chart of the display panel corresponding to the pixel potential of the detection pixel thin film transistor NT202 in the first embodiment.
  • Gate1, Gate2, Gate4, and MUXR, MUXG, and MUXB to the low potential VGL, respectively, and turn Gate3 separately, and it is necessary to ensure the increase.
  • TCK2 is a high potential VGH
  • TCK1 and TCK3 are a low potential VGL.
  • the potential in the sub-pixel unit corresponding to the pixel thin film transistor NT202 in FIG. 2 is turned on to the pixel potential signal.
  • the drive detection circuit 120 is operated, and the received test signal is converted into a received signal by the action of the signal amplifier 130, and the true potential condition in the sub-pixel unit in the display panel is reversed according to the intensity of the received signal.
  • the on and off of the second thin film transistor NT2 are controlled by the inverted clock signals in TCK1, TCK2, TCK3, TCK4, TCK5, TCK6.
  • FIG. 10 is a timing chart corresponding to a signal when the display panel is normally operated in the second embodiment.
  • the signals on the TCK1, TCK2, TCK3, TCK4, TCK5, and TCK6 signal lines are maintained at a low potential VGL.
  • the increased multi-output selector 110 circuit does not work and the display panel is normally driven.
  • the pixel potential signal 2 drives the detection circuit 120 to operate, and converts the test signal into a received signal by the amplification of the signal amplifier 130, and inversely displays the true potential condition in the panel sub-pixel unit according to the intensity of the received signal.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
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Abstract

一种用于检测显示面板中像素电位的电路及方法、显示面板，电路包括多路输出选择器（110）、至少一个检测电路（120）以及至少一个信号放大器（130）；检测电路（120）包括一个第一薄膜晶体管（NT1），第一薄膜晶体管（NT1）接入测试信号并与多路输出选择器（110）连接；多路输出选择器（110）根据反向时钟信号选择将待检测子像素单元连接的第一数据线与第一薄膜晶体管（NT1）接通，以将待检测子像素单元的像素电位信号输送至第一薄膜晶体管（NT1），控制第一薄膜晶体管（NT1）将测试信号输送至信号放大器（130）；信号放大器（130）将所述测试信号进行放大，转化为接收信号输出。可以测量显示面板中的真实像素电位。

Description

一种用于检测显示面板中像素电位的电路及方法、显示面板
本申请要求于2017年12月12日提交中国专利局、申请号为201711322422.0、发明名称为“一种用于检测显示面板中像素电位的电路及方法、显示面板”的中国专利申请的优先权，上述专利的全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示技术领域，尤其涉及一种用于检测显示面板中像素电位的电路及方法、显示面板。
背景技术
现在常用的显示面板中AA区(即有效显示区)设计以及像素驱动电路(如图1所示)包括Gate走线(即栅极线)、Data走线(即第一数据线)、子像素单元以及多路分配器电路。Gate走线用来实现面板AA区子像素单元逐行扫描，Data走线用来给面板AA区的子像素单元充电，子像素单元用来显示面板中的图像、多路分配器电路用于实现显示面板中Data走线的多路输出选择。显示面板通过子像素单元中的电位来驱动液晶转动，以实现显示面板在显示不同画面下，所要求的不同程度的透过率，因此显示面板子像素单元中的真实电位状况是一个重要指标。但是在现在的面板设计方案中无法真实量测到显示面板子像素单元中的真实电位，因此，在问题解析等过程中，这种设计方案无法通过现有的设备获取子像素单元中的真实电位状况。由于现在的设计方案中没有设计探测子像素单元中真实电位的结构，因此无法准确获得显示面板中子像素单元的真实电位，也即是真实的像素电位。
发明内容
为解决上述技术问题，本发明提供一种用于检测显示面板中像素电位的电路及方法、显示面板，可以测量显示面板中的真实像素电位。
本发明提供的一种用于检测显示面板中像素电位的电路，包括多路输出选择器、至少一个检测电路以及至少一个信号放大器；
所述检测电路包括一个第一薄膜晶体管，所述第一薄膜晶体管的第一端接入测试信号，第二端与所述信号放大器连接，第三端与所述多路输出选择器连接；
所述多路输出选择器，与显示面板的第一数据线以及所述检测电路连接，用于根据反向时钟信号选择将待检测子像素单元连接的第一数据线与所述第一薄膜晶体管接通，以将所述待检测子像素单元的像素电位信号输送至所述第一薄膜晶体管，控制所述第一薄膜晶体管将所述测试信号输送至所述信号放大器；
所述信号放大器，用于接收所述测试信号，并将所述测试信号进行放大，转化为接收信号输出；
用于检测显示面板中像素电位的电路中薄膜晶体管的第一端为源极和漏极中的一个，第二端为源极和漏极中的另一个，第三端为栅极。
优选地，所述多路输出选择器包括N组反向时钟信号线以及多个与所述显示面板中的第一数据线分别对应连接的第二薄膜晶体管，每一组反向时钟信号线包括三条反向时钟信号线；
所述显示面板中每相邻的3*N个第二薄膜晶体管分别与N组反向时钟信号线中不同的反向时钟信号线连接；
每一个第一薄膜晶体管对应连接相邻的3*N个第二薄膜晶体管；
其中，N≥1，第二薄膜晶体管的第一端与第一薄膜晶体管的第三端连接，第二薄膜晶体管的第二端与所述显示面板的第一数据线连接，第三端与反向时钟信号线连接。
优选地，所述显示面板中的第一数据线总数量设为M，则所述检测电路和所述信号放大器的数量均为大于或等于M/(3*N)的最小整数，且所述第一薄膜晶体管与所述信号放大器之间一一对应连接。
优选地，所述第一薄膜晶体管和所述第二薄膜晶体管均为N沟道薄膜晶体管。
优选地，还包括信号分析模块；
所述信号分析模块，与所述信号放大器连接，用于接收所述信号放大器输出的所述接收信号，并根据所述接收信号的强度判断所述待检测像素电位。
本发明还提供一种显示面板，包括像素驱动电路和用于检测显示面板中像素电位的电路；
所述用于检测显示面板中像素电位的电路包括多路输出选择器、至少一个检测电路以及至少一个信号放大器；
所述检测电路包括一个第一薄膜晶体管，所述第一薄膜晶体管的第一端接入测试信号，第二端与所述信号放大器连接，第三端与所述多路输出选择器连接；
所述多路输出选择器，与显示面板的第一数据线以及所述检测电路连接，用于根据反向时钟信号选择将待检测子像素单元连接的第一数据线与所述第一薄膜晶体管接通，以将所述待检测子像素单元的像素电位信号输送至所述第一薄膜晶体管，控制所述第一薄膜晶体管将所述测试信号输送至所述信号放大器；
所述信号放大器，用于接收所述测试信号，并将所述测试信号进行放大，转化为接收信号输出；所述像素驱动电路包括多条第一数据线、多条栅极线和三条子像素开关控制信号线，多条第一数据线与多条栅极线交叉形成阵列结构；相邻两条第一数据线与相邻两条栅极线形成的矩形区域为子像素单元，每一个子像素单元包括一个像素薄膜晶体管，所述像素薄膜晶体管的第一端与相邻的第一数据线连接，第三端与相邻的栅极线连接，且相互交叉的第一数据线和栅极线上最多连接一个像素薄膜晶体管；
每一条第一数据线均通过一个第三薄膜晶体管与子像素开关控制信号线连接，且每相邻的三条第一数据线分别接入三条不同的子像素开关控制信号线；
其中，所述第三薄膜晶体管的第三端与子像素开关控制信号线连接，第一数据线与第三薄膜晶体管的第一端连接，相邻的三个第三薄膜晶体管的第二端接入同一条第二数据线；用于检测显示面板中像素电位的电路以及像素驱动电路中薄膜晶体管的第一端为源极和漏极中的一个，第二端为源极和漏 极中的另一个，第三端为栅极。
优选地，所述像素驱动电路中所有的薄膜晶体管均为N沟道的薄膜晶体管。
优选地，在显示面板工作时，用于检测显示面板中像素电位的电路中的反向时钟信号均为低电位。
优选地，所述多路输出选择器包括N组反向时钟信号线以及多个与所述显示面板中的第一数据线分别对应连接的第二薄膜晶体管，每一组反向时钟信号线包括三条反向时钟信号线；
所述显示面板中每相邻的3*N个第二薄膜晶体管分别与N组反向时钟信号线中不同的反向时钟信号线连接；
每一个第一薄膜晶体管对应连接相邻的3*N个第二薄膜晶体管；
其中，N≥1，第二薄膜晶体管的第一端与第一薄膜晶体管的第三端连接，第二薄膜晶体管的第二端与所述显示面板的第一数据线连接，第三端与反向时钟信号线连接。
优选地，所述显示面板中的第一数据线总数量设为M，则所述检测电路和所述信号放大器的数量均为大于或等于M/(3*N)的最小整数，且所述第一薄膜晶体管与所述信号放大器之间一一对应连接。
优选地，所述第一薄膜晶体管和所述第二薄膜晶体管均为N沟道薄膜晶体管。
优选地，还包括信号分析模块；
所述信号分析模块，与所述信号放大器连接，用于接收所述信号放大器输出的所述接收信号，并根据所述接收信号的强度判断所述待检测像素电位。
本发明还提供一种用于检测显示面板中像素电位的方法，应用于显示面板中，所述显示面板包括像素驱动电路和用于检测显示面板中像素电位的电路；
所述用于检测显示面板中像素电位的电路包括多路输出选择器、至少一个检测电路以及至少一个信号放大器；
所述检测电路包括一个第一薄膜晶体管，所述第一薄膜晶体管的第一端 接入测试信号，第二端与所述信号放大器连接，第三端与所述多路输出选择器连接；
所述多路输出选择器，与显示面板的第一数据线以及所述检测电路连接，用于根据反向时钟信号选择将待检测子像素单元连接的第一数据线与所述第一薄膜晶体管接通，以将所述待检测子像素单元的像素电位信号输送至所述第一薄膜晶体管，控制所述第一薄膜晶体管将所述测试信号输送至所述信号放大器；
所述信号放大器，用于接收所述测试信号，并将所述测试信号进行放大，转化为接收信号输出；所述像素驱动电路包括多条第一数据线、多条栅极线和三条子像素开关控制信号线，多条第一数据线与多条栅极线交叉形成阵列结构；相邻两条第一数据线与相邻两条栅极线形成的矩形区域为子像素单元，每一个子像素单元包括一个像素薄膜晶体管，所述像素薄膜晶体管的第一端与相邻的第一数据线连接，第三端与相邻的栅极线连接，且相互交叉的第一数据线和栅极线上最多连接一个像素薄膜晶体管；
每一条第一数据线均通过一个第三薄膜晶体管与子像素开关控制信号线连接，且每相邻的三条第一数据线分别接入三条不同的子像素开关控制信号线；
其中，所述第三薄膜晶体管的第三端与子像素开关控制信号线连接，第一数据线与第三薄膜晶体管的第一端连接，相邻的三个第三薄膜晶体管的第二端接入同一条第二数据线；用于检测显示面板中像素电位的电路以及像素驱动电路中薄膜晶体管的第一端为源极和漏极中的一个，第二端为源极和漏极中的另一个，第三端为栅极。
用于检测显示面板中像素电位的方法包括下述步骤：
通过栅极线和子像素控制信号将显示面板中除待检测子像素单元的像素薄膜晶体管之外的其他像素薄膜晶体管关断，通过反向时钟信号控制多路输出选择器，将待检测像素电位信号输送至第一薄膜晶体管；
所述待检测像素电位信号控制所述第一薄膜晶体管将测试信号输送至信号放大器；
所述信号放大器将所述测试信号进行放大，得到接收信号；
根据所述接收信号的强度判断待检测的像素电位。
优选地，当所述显示面板包含权利要求4所述的用于检测显示面板中像素电位的电路时，
通过栅极线和子像素控制信号将显示面板中除待检测子像素单元的像素薄膜晶体管之外的其他像素薄膜晶体管关断，通过反向时钟信号控制多路输出选择器，将待检测像素电位信号输送至第一薄膜晶体管，具体为：
控制与所述待检测子像素单元的像素薄膜晶体管连接的栅极线为高电位，不与所述待检测子像素单元的像素薄膜晶体管连接的栅极线均为低电位；
控制与所述待检测子像素单元的像素薄膜晶体管连接的反向时钟信号线为高电位，不与所述待检测子像素单元的像素薄膜晶体管连接的反向时钟信号线为低电位；
控制三条子像素控制信号均为低电位。实施本发明，具有如下有益效果：通过多路输出选择器选择将待检测子像素单元连接的第一数据线与第一薄膜晶体管接通，将待检测子像素单元的像素电位信号输送至第一薄膜晶体管，控制第一薄膜晶体管将所述测试信号输送至信号放大器，信号放大器将测试信号进行放大转化为接收信号，可以根据接收信号的强度来反推测量显示面板中子像素单元的真实电位状况。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明提供的背景技术中AA区像素驱动电路的示意图。
图2是本发明提供的第一实施例中用于检测显示面板中像素电位的电路的示意图。
图3是本发明提供的第二实施例中用于检测显示面板中像素电位的电路的示意图。
图4是本发明提供的第三实施例中用于检测显示面板中像素电位的电路 的示意图。
图5a是本发明提供的一个实施例中显示面板的示意图。
图5b是本发明提供的另一个实施例中显示面板的示意图。
图6是本发明提供的第一实施例中显示面板正常工作时对应的信号时序图。
图7是本发明提供的第一实施例中检测像素薄膜晶体管NT201的像素电位对应的显示面板的信号时序图。
图8是本发明提供的第一实施例中检测像素薄膜晶体管NT202的像素电位对应的显示面板的信号时序图。
图9是本发明提供的第一实施例中检测像素薄膜晶体管NT203的像素电位对应的显示面板的信号时序图。
图10是本发明提供的第二实施例中显示面板正常工作时对应的信号时序图。
图11是本发明提供的第二实施例中检测像素薄膜晶体管NT210的像素电位对应的显示面板的信号时序图。
具体实施方式
本发明提供一种用于检测显示面板中像素电位的电路，如图2所示，用于检测显示面板中像素电位的电路包括多路输出选择器110、至少一个检测电路120以及至少一个信号放大器130。
检测电路120包括一个第一薄膜晶体管NT1，第一薄膜晶体管NT1的第一端接入测试信号，第一薄膜晶体管NT1的第二端与信号放大器130连接，第一薄膜晶体管NT1的第三端与多路输出选择器110连接。
多路输出选择器110与显示面板的第一数据线(第一数据线为子像素单元的数据线，如图2和图3中所示的DataR、DataG、DataB)以及检测电路120连接，用于根据反向时钟信号选择将待检测子像素单元连接的第一数据线与第一薄膜晶体管NT1接通，以将待检测子像素单元的像素电位信号输送至第一薄膜晶体管NT1，控制第一薄膜晶体管NT1将测试信号输送至信号放大器130。
信号放大器130用于接收测试信号，并将测试信号进行放大，转化为接 收信号输出。
用于检测显示面板中像素电位的电路中薄膜晶体管的第一端为源极和漏极中的一个，第二端为源极和漏极中的另一个，第三端为栅极。
进一步地，多路输出选择器110包括N组反向时钟信号线以及多个与显示面板中的第一数据线分别对应连接的第二薄膜晶体管NT2，每一组反向时钟信号线包括三条反向时钟信号线。一般而言，第二薄膜晶体管NT2的数量与显示面板AA区(即有效显示区)的第一数据线对应相等。如图2所示，在第一实施例中，多路输出选择器110包括一组反向时钟信号线，即共有三条反向时钟信号线，分别为TCK1、TCK2、TCK3；如图3所示，在第二实施例中，多路输出选择器110包括两组反向时钟信号线，即共有六条反向时钟信号线，分别为TCK1、TCK2、TCK3、TCK4、TCK5、TCK6。
显示面板中每相邻的3*N个第二薄膜晶体管NT2分别与N组反向时钟信号线中不同的反向时钟信号线连接。例如，多路输出选择器110有三条反向时钟信号线，AA区的第一条第一数据线与第一条反向时钟信号线TCK1连接，第二条第一数据线与第二条反向时钟信号线TCK2连接，第三条第一数据线与第三条反向时钟信号线TCK3连接，第四条第一数据线与第一条反向时钟信号线TCK1连接，第五条第一数据线与第二条反向时钟信号线TCK2连接，第六条第一数据线与第三条反向时钟信号线TCK3连接。
每一个第一薄膜晶体管NT1对应连接相邻的3*N个第二薄膜晶体管NT2。例如当N＝1时，从图2中左侧或右侧开始数，第1个第一薄膜晶体管NT1与第1～3个第二薄膜晶体管NT2连接，第2个第一薄膜晶体管NT1与第4～6个第二薄膜晶体管NT2连接，第k个第一薄膜晶体管NT1与第3k-2～3k个第二薄膜晶体管NT2连接。当N＝2时，从图3中左侧或右侧开始数，第1个第一薄膜晶体管NT1与第1～6个第二薄膜晶体管NT2连接，第2个第一薄膜晶体管NT1与第7～12个第二薄膜晶体管NT2连接。
其中，N≥1，第二薄膜晶体管NT2的第一端与第一薄膜晶体管NT1的第三端连接，第二薄膜晶体管NT2的第二端与显示面板的第一数据线连接，第三端与反向时钟信号线连接。
进一步地，显示面板中的第一数据线总数量设为M，M为正整数，则检 测电路120和信号放大器130的数量均为大于或等于M/(3*N)的最小整数，且第一薄膜晶体管NT1与信号放大器130之间一一对应连接。例如，M＝1980，N＝1，那么大于或等于M/(3*N)的最小整数为660。
进一步地，第一薄膜晶体管NT1和第二薄膜晶体管NT2均为N沟道薄膜晶体管。
进一步地，如图4所示，用于检测显示面板中像素电位的电路还包括信号分析模块140；信号分析模块140与信号放大器130连接，用于接收信号放大器130输出的接收信号，并根据接收信号的强度判断待检测像素电位。
本发明还提供一种显示面板，如图5a和5b所示，显示面板10包括像素驱动电路200和上述的用于检测显示面板中像素电位的电路100。优选地，像素驱动电路200位于显示面板10的AA区20，如图5a所示，用于检测显示面板中像素电位的电路100可以位于AA区20中，如图5b所示，用于检测显示面板中像素电位的电路100可以不位于AA区20中。
像素驱动电路200包括多条第一数据线、多条栅极线和三条子像素开关控制信号线，多条第一数据线与多条栅极线交叉形成阵列结构；相邻两条第一数据线与相邻两条栅极线形成的矩形区域为子像素单元，每一个子像素单元包括一个像素薄膜晶体管，像素薄膜晶体管的第一端与相邻的第一数据线连接，像素薄膜晶体管的第三端与相邻的栅极线连接，且相互交叉的第一数据线和栅极线上最多连接一个像素薄膜晶体管，即两个不同的像素薄膜晶体管不能同时连接在同一组交叉的第一数据线和栅极线上。
每一条第一数据线均通过一个第三薄膜晶体管NT3与子像素开关控制信号线连接，且每相邻的三条第一数据线分别接入三条不同的子像素开关控制信号线。三条不同的子像素开关控制信号线分别为红色子像素开关控制信号线、绿色子像素开关控制信号线、蓝色子像素开关控制信号线。
其中，第三薄膜晶体管NT3的第三端与子像素开关控制信号线连接，第一数据线与第三薄膜晶体管NT3的第一端连接，相邻的三个第三薄膜晶体管NT3的第二端接入同一条第二数据线(第二数据线如图2和图3中所示的Data1、Data2、Data3)。像素驱动电路200中薄膜晶体管的第一端为源极和漏极中的一个，第二端为源极和漏极中的另一个，第三端为栅极。
进一步地，像素驱动电路200中所有的薄膜晶体管均为N沟道的薄膜晶体管。
进一步地，在显示面板工作时用于检测显示面板中像素电位的电路100中的反向时钟信号均为低电位VGL。
本发明还提供一种用于检测显示面板中像素电位的方法，应用于上述的显示面板中，该方法包括下述步骤：
通过栅极线和子像素控制信号将显示面板中除待检测子像素单元的像素薄膜晶体管之外的其他像素薄膜晶体管关断，通过反向时钟信号控制多路输出选择器110，将待检测像素电位信号输送至第一薄膜晶体管NT1；这里，待检测像素电位信号也即是待检测子像素单元的电位信号；
待检测像素电位信号控制第一薄膜晶体管NT1将测试信号输送至信号放大器130；
信号放大器130将测试信号进行放大，得到接收信号；
根据接收信号的强度判断待检测的像素电位。待检测的像素电位也即是待检测子像素单元的电位。
进一步地，通过栅极线和子像素控制信号将显示面板中除待检测子像素单元的像素薄膜晶体管之外的其他像素薄膜晶体管关断，通过反向时钟信号控制多路输出选择器110，将待检测像素电位信号输送至第一薄膜晶体管NT1，具体为：
控制与待检测子像素单元的像素薄膜晶体管连接的栅极线为高电位VGH，不与待检测子像素单元的像素薄膜晶体管连接的栅极线均为低电位VGL；
控制与待检测子像素单元的像素薄膜晶体管连接的反向时钟信号线为高电位VGH，不与待检测子像素单元的像素薄膜晶体管连接的反向时钟信号线为低电位VGL；
控制三条子像素控制信号均为低电位VGL。
在本发明提供的第一实施例中，如图2所示，多路输出选择器110中包含有三条反向时钟信号线TCK1、TCK2、TCK3，通过TCK1、TCK2、TCK3中的反向时钟信号来控制第二薄膜晶体管NT2的导通与关断，以及通过 GOA(Gate Driver on Array，阵列基板行驱动技术)电路控制栅极线Gate1、Gate2、Gate3、Gate4，还通过红色子像素开关控制信号线MUXR、绿色子像素开关控制信号线MUXG、蓝色子像素开关控制信号线MUXB，控制第三薄膜晶体管NT3的导通与关断，将显示面板子像素单元中的电位信号(即像素电位信号)输送至检测电路120中，也即是将像素电位信号输送至对应的第一薄膜晶体管NT1，驱动第一薄膜晶体管NT1将测试信号输送至信号放大器130，并通过信号放大器130的放大作用将测试信号转变成接收信号，根据接收信号的强度来反推显示面板子像素单元中的真实电位状况。
如图6所示，图6示出了显示面板正常工作时的信号时序图，具体为显示面板AA区的像素驱动电路200的时序图。为了保证多路输出选择器110电路不影响显示面板的正常工作，将增加的反向时钟信号线TCK1、TCK2、TCK3中的反向时钟信号均维持低电位VGL，增加的多路输出选择器110电路不工作，而显示面板正常驱动。同时，栅极线Gate1、Gate2、Gate3、Gate4中的电位依次变为高电位VGH，将子像素单元逐行打开，并且MUXR、MUXG、MUXB依次为高电位VGH，分别给第一数据线DataR、DataG、DataB提供电位进而给显示面板中的子像素单元充电来驱动液晶转动。
如图7所示，图7示出了第一实施例中检测像素薄膜晶体管NT202的像素电位对应的显示面板的信号时序图。为了了解图2中像素薄膜晶体管NT201所在子像素单元的真实电位状况，首先我们将Gate2、Gate3、Gate4以及MUXR、MUXG、MUXB分别给低电位VGL，而将Gate1单独打开(即给高电位VGH)，这时要保证增加的多路输出选择器110电路中TCK1为高电位VGH，TCK2和TCK3为低电位VGL，这样的驱动时序条件下，图2中像素薄膜晶体管NT201对应的子像素单元中的电位将导通到像素电位信号1上来驱动检测电路120工作，并通过信号放大器130的作用将所接收的测试信号转变成接收信号，根据接收信号的强度来判断显示面板中子像素单元中的真实电位状况。
如图8所示，图8示出了第一实施例中检测像素薄膜晶体管NT202的像素电位对应的显示面板的信号时序图。为了了解图2中像素薄膜晶体管NT202对应子像素单元的真实电位状况，首先我们将Gate1、Gate2、Gate4 以及MUXR、MUXG、MUXB分别给低电位VGL，而将Gate3单独打开，这时要保证增加的多路输出选择器110电路中TCK2为高电位VGH，TCK1和TCK3为低电位VGL，这样的驱动时序条件下，图2中像素薄膜晶体管NT202对应子像素单元中的电位将导通到像素电位信号2上来驱动检测电路120工作，并通过信号放大器130的作用将所接收的测试信号转变成接收信号，根据接收信号的强度来反推显示面板中子像素单元中的真实电位状况。
如图9所示，图9示出了第一实施例中检测像素薄膜晶体管NT203的像素电位对应的显示面板的信号时序图。为了了解图2中像素薄膜晶体管NT203处子像素单元的真实电位状况，首先我们将Gate1、Gate2、Gate3以及MUXR、MUXG、MUXB分别给低电位VGL，而将Gate4单独打开，这时要保证增加的多路输出选择器110电路中TCK3为高电位VGH，TCK1和TCK2为低电位VGL，这样的驱动时序条件下，图2中像素薄膜晶体管NT203处子像素单元中的电位将导通到像素电位信号3上来驱动检测电路120工作，并通过信号放大器130的作用将测试信号转变成接收信号，根据接收信号的强度来反推显示面板子像素单元中的真实电位状况。
在本发明提供的第二实施例中，如图3所示，通过TCK1、TCK2、TCK3、TCK4、TCK5、TCK6中的反向时钟信号来控制第二薄膜晶体管NT2的导通与关断。
如图10所示，图10示出了第二实施例中显示面板正常工作时对应的信号时序图。在显示面板正常工作时，为了保证增加的多路输出选择器110电路不影响显示面板的正常工作，将增加的TCK1、TCK2、TCK3、TCK4、TCK5、TCK6信号线上的信号维持低电位VGL，增加的多路输出选择器110电路不工作，而显示面板正常驱动。
如图11所示，图11示出了第二实施例中检测像素薄膜晶体管NT210的像素电位对应的显示面板的信号时序图。为了了解图3中像素薄膜晶体管NT210处子像素单元的真实电位状况，首先将Gate1、Gate2、Gate3以及MUXR、MUXG、MUXB分别给低电位VGL，而将Gate4单独打开，这时要保证增加的多路输出选择器110电路中TCK3为高电位VGH，TCK1、TCK2、TCK4、TCK5、TCK6为低电位VGL，这样的驱动时序条件下，图 3中像素薄膜晶体管NT210处子像素单元中的电位将导通到像素电位信号2上来驱动检测电路120工作，并通过信号放大器130的放大作用将测试信号转变成接收信号，根据接收信号的强度来反推显示面板子像素单元中的真实电位状况。
因此，本发明通过增加至少一组反向时钟信号线控制的多路输出选择器110、检测电路120以及信号放大器130并搭配显示面板电路的驱动来实现准确量测显示面板中子像素单元的真实电位，为问题解析、产品设计等提供便利。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (14)

  1. 一种用于检测显示面板中像素电位的电路，其中，包括多路输出选择器、至少一个检测电路以及至少一个信号放大器；
    所述检测电路包括一个第一薄膜晶体管，所述第一薄膜晶体管的第一端接入测试信号，第二端与所述信号放大器连接，第三端与所述多路输出选择器连接；
    所述多路输出选择器，与显示面板的第一数据线以及所述检测电路连接，用于根据反向时钟信号选择将待检测子像素单元连接的第一数据线与所述第一薄膜晶体管接通，以将所述待检测子像素单元的像素电位信号输送至所述第一薄膜晶体管，控制所述第一薄膜晶体管将所述测试信号输送至所述信号放大器；
    所述信号放大器，用于接收所述测试信号，并将所述测试信号进行放大，转化为接收信号输出；
    用于检测显示面板中像素电位的电路中薄膜晶体管的第一端为源极和漏极中的一个，第二端为源极和漏极中的另一个，第三端为栅极。
  2. 根据权利要求1所述的用于检测显示面板中像素电位的电路，其中，所述多路输出选择器包括N组反向时钟信号线以及多个与所述显示面板中的第一数据线分别对应连接的第二薄膜晶体管，每一组反向时钟信号线包括三条反向时钟信号线；
    所述显示面板中每相邻的3*N个第二薄膜晶体管分别与N组反向时钟信号线中不同的反向时钟信号线连接；
    每一个第一薄膜晶体管对应连接相邻的3*N个第二薄膜晶体管；
    其中，N≥1，第二薄膜晶体管的第一端与第一薄膜晶体管的第三端连接，第二薄膜晶体管的第二端与所述显示面板的第一数据线连接，第三端与反向时钟信号线连接。
  3. 根据权利要求2所述的用于检测显示面板中像素电位的电路，其中，所述显示面板中的第一数据线总数量设为M，则所述检测电路和所述信号放大器的数量均为大于或等于M/(3*N)的最小整数，且所述第一薄膜晶体管与 所述信号放大器之间一一对应连接。
  4. 根据权利要求2所述的用于检测显示面板中像素电位的电路，其中，所述第一薄膜晶体管和所述第二薄膜晶体管均为N沟道薄膜晶体管。
  5. 根据权利要求1所述的用于检测显示面板中像素电位的电路，其中，还包括信号分析模块；
    所述信号分析模块，与所述信号放大器连接，用于接收所述信号放大器输出的所述接收信号，并根据所述接收信号的强度判断所述待检测像素电位。
  6. 一种显示面板，其中，包括像素驱动电路和用于检测显示面板中像素电位的电路；
    所述用于检测显示面板中像素电位的电路包括多路输出选择器、至少一个检测电路以及至少一个信号放大器；
    所述检测电路包括一个第一薄膜晶体管，所述第一薄膜晶体管的第一端接入测试信号，第二端与所述信号放大器连接，第三端与所述多路输出选择器连接；
    所述多路输出选择器，与显示面板的第一数据线以及所述检测电路连接，用于根据反向时钟信号选择将待检测子像素单元连接的第一数据线与所述第一薄膜晶体管接通，以将所述待检测子像素单元的像素电位信号输送至所述第一薄膜晶体管，控制所述第一薄膜晶体管将所述测试信号输送至所述信号放大器；
    所述信号放大器，用于接收所述测试信号，并将所述测试信号进行放大，转化为接收信号输出；所述像素驱动电路包括多条第一数据线、多条栅极线和三条子像素开关控制信号线，多条第一数据线与多条栅极线交叉形成阵列结构；相邻两条第一数据线与相邻两条栅极线形成的矩形区域为子像素单元，每一个子像素单元包括一个像素薄膜晶体管，所述像素薄膜晶体管的第一端与相邻的第一数据线连接，第三端与相邻的栅极线连接，且相互交叉的第一数据线和栅极线上最多连接一个像素薄膜晶体管；
    每一条第一数据线均通过一个第三薄膜晶体管与子像素开关控制信号线连接，且每相邻的三条第一数据线分别接入三条不同的子像素开关控制信 号线；
    其中，所述第三薄膜晶体管的第三端与子像素开关控制信号线连接，第一数据线与第三薄膜晶体管的第一端连接，相邻的三个第三薄膜晶体管的第二端接入同一条第二数据线；用于检测显示面板中像素电位的电路以及像素驱动电路中薄膜晶体管的第一端为源极和漏极中的一个，第二端为源极和漏极中的另一个，第三端为栅极。
  7. 根据权利要求1所述的显示面板，其中，所述像素驱动电路中所有的薄膜晶体管均为N沟道的薄膜晶体管。
  8. 根据权利要求7所述的显示面板，其中，在显示面板工作时，用于检测显示面板中像素电位的电路中的反向时钟信号均为低电位。
  9. 根据权利要求6所述的显示面板，其中，所述多路输出选择器包括N组反向时钟信号线以及多个与所述显示面板中的第一数据线分别对应连接的第二薄膜晶体管，每一组反向时钟信号线包括三条反向时钟信号线；
    所述显示面板中每相邻的3*N个第二薄膜晶体管分别与N组反向时钟信号线中不同的反向时钟信号线连接；
    每一个第一薄膜晶体管对应连接相邻的3*N个第二薄膜晶体管；
    其中，N≥1，第二薄膜晶体管的第一端与第一薄膜晶体管的第三端连接，第二薄膜晶体管的第二端与所述显示面板的第一数据线连接，第三端与反向时钟信号线连接。
  10. 根据权利要求9所述的显示面板，其中，所述显示面板中的第一数据线总数量设为M，则所述检测电路和所述信号放大器的数量均为大于或等于M/(3*N)的最小整数，且所述第一薄膜晶体管与所述信号放大器之间一一对应连接。
  11. 根据权利要求9所述的显示面板，其中，所述第一薄膜晶体管和所述第二薄膜晶体管均为N沟道薄膜晶体管。
  12. 根据权利要求6所述的显示面板，其中，还包括信号分析模块；
    所述信号分析模块，与所述信号放大器连接，用于接收所述信号放大器输出的所述接收信号，并根据所述接收信号的强度判断所述待检测像素电位。
  13. 一种用于检测显示面板中像素电位的方法，应用于显示面板中，其中，所述显示面板包括像素驱动电路和用于检测显示面板中像素电位的电路；
    所述用于检测显示面板中像素电位的电路包括多路输出选择器、至少一个检测电路以及至少一个信号放大器；
    所述检测电路包括一个第一薄膜晶体管，所述第一薄膜晶体管的第一端接入测试信号，第二端与所述信号放大器连接，第三端与所述多路输出选择器连接；
    所述多路输出选择器，与显示面板的第一数据线以及所述检测电路连接，用于根据反向时钟信号选择将待检测子像素单元连接的第一数据线与所述第一薄膜晶体管接通，以将所述待检测子像素单元的像素电位信号输送至所述第一薄膜晶体管，控制所述第一薄膜晶体管将所述测试信号输送至所述信号放大器；
    所述信号放大器，用于接收所述测试信号，并将所述测试信号进行放大，转化为接收信号输出；所述像素驱动电路包括多条第一数据线、多条栅极线和三条子像素开关控制信号线，多条第一数据线与多条栅极线交叉形成阵列结构；相邻两条第一数据线与相邻两条栅极线形成的矩形区域为子像素单元，每一个子像素单元包括一个像素薄膜晶体管，所述像素薄膜晶体管的第一端与相邻的第一数据线连接，第三端与相邻的栅极线连接，且相互交叉的第一数据线和栅极线上最多连接一个像素薄膜晶体管；
    每一条第一数据线均通过一个第三薄膜晶体管与子像素开关控制信号线连接，且每相邻的三条第一数据线分别接入三条不同的子像素开关控制信号线；
    其中，所述第三薄膜晶体管的第三端与子像素开关控制信号线连接，第一数据线与第三薄膜晶体管的第一端连接，相邻的三个第三薄膜晶体管的第二端接入同一条第二数据线；用于检测显示面板中像素电位的电路以及像素驱动电路中薄膜晶体管的第一端为源极和漏极中的一个，第二端为源极和漏极中的另一个，第三端为栅极。
    用于检测显示面板中像素电位的方法包括下述步骤：
    通过栅极线和子像素控制信号将显示面板中除待检测子像素单元的像素薄膜晶体管之外的其他像素薄膜晶体管关断，通过反向时钟信号控制多路输出选择器，将待检测像素电位信号输送至第一薄膜晶体管；
    所述待检测像素电位信号控制所述第一薄膜晶体管将测试信号输送至信号放大器；
    所述信号放大器将所述测试信号进行放大，得到接收信号；
    根据所述接收信号的强度判断待检测的像素电位。
  14. 根据权利要求13所述的用于检测显示面板中像素电位的方法，其中，当所述显示面板包含权利要求4所述的用于检测显示面板中像素电位的电路时，
    通过栅极线和子像素控制信号将显示面板中除待检测子像素单元的像素薄膜晶体管之外的其他像素薄膜晶体管关断，通过反向时钟信号控制多路输出选择器，将待检测像素电位信号输送至第一薄膜晶体管，具体为：
    控制与所述待检测子像素单元的像素薄膜晶体管连接的栅极线为高电位，不与所述待检测子像素单元的像素薄膜晶体管连接的栅极线均为低电位；
    控制与所述待检测子像素单元的像素薄膜晶体管连接的反向时钟信号线为高电位，不与所述待检测子像素单元的像素薄膜晶体管连接的反向时钟信号线为低电位；
    控制三条子像素控制信号均为低电位。
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