WO2017035854A1 - 液晶显示面板驱动方法及液晶显示装置 - Google Patents

液晶显示面板驱动方法及液晶显示装置 Download PDF

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WO2017035854A1
WO2017035854A1 PCT/CN2015/089272 CN2015089272W WO2017035854A1 WO 2017035854 A1 WO2017035854 A1 WO 2017035854A1 CN 2015089272 W CN2015089272 W CN 2015089272W WO 2017035854 A1 WO2017035854 A1 WO 2017035854A1
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Prior art keywords
transistor
pixel
voltage
sub
pixel unit
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PCT/CN2015/089272
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English (en)
French (fr)
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国春朋
秦杰辉
谭小平
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深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Priority to US14/907,524 priority Critical patent/US9978334B2/en
Publication of WO2017035854A1 publication Critical patent/WO2017035854A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/0646—Modulation of illumination source brightness and image signal correlated to each other
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0666—Adjustment of display parameters for control of colour parameters, e.g. colour temperature

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a liquid crystal display panel driving method and a liquid crystal display device.
  • the liquid crystal display panel in order to extend the life of the liquid crystal, the liquid crystal display panel is usually driven in such a manner that the polarity is reversed.
  • the control chip In the liquid crystal display panel driving circuit using the polarity inversion method described above, the control chip needs to control the source voltage of each data line to frequently switch between the positive polarity voltage and the negative polarity voltage, which causes a large charging voltage difference. It is not conducive to reducing the power consumption of the liquid crystal display panel.
  • the TFTs corresponding to the R, G, and B sub-pixel electrodes are simultaneously turned on, and each sub-pixel electrode is charged to a GND voltage, that is, 0V, so that the potentials of all R, G, and B sub-pixel electrodes in the row become simultaneously GND voltage, and then sequentially control the strobe signals SELR, SELG, and SELB to a high level, and sequentially turn on the TFTs corresponding to the R, G, and B sub-pixel electrodes to charge the sub-pixel electrodes one by one with corresponding polarities. Voltage.
  • the negative polarity pixel voltage is uniformly charged to 0V, and then charged by 0V one by one to the positive polarity pixel voltage, so that the charging pressure difference is not too large, so that Reduce the power consumption of the liquid crystal display panel.
  • GND is not the intermediate value of the positive and negative polarity pixel voltage switching.
  • the common voltage is 1.2V
  • the positive and negative pixel voltages corresponding to the source voltage of the 128 grayscale luminance are 6V and -3.6, respectively.
  • V if the method of charging each pixel electrode to the GND voltage first, then When charging from the GND voltage to the positive pixel voltage, the charging voltage difference reaches 6V, and the charging voltage is still relatively large, resulting in a longer charging time and higher power consumption.
  • the present invention provides a liquid crystal display panel driving method, which first charges each sub-pixel unit of the liquid crystal display panel to a pre-charge voltage, and then sequentially sequentially sets each sub-pixel unit from the pre-charged unit.
  • the charging voltage is charged to the corresponding pixel voltage to reduce the charging voltage difference when the liquid crystal display panel is driven by the polarity inversion, shorten the charging time, and further reduce the power consumption of the liquid crystal display device.
  • the present invention also provides a liquid crystal display device to which the liquid crystal display panel driving method is applied.
  • a liquid crystal display panel driving method comprising:
  • the control chip synchronously outputs a first strobe signal of a first level, a second strobe signal of a first level, and a third strobe signal of a first level, and controls connection between the buffer and each pixel column
  • the first transistor, the second transistor, and the third transistor are both turned on;
  • the buffer outputs a precharge voltage signal to charge the sub-pixel units in each of the pixel columns to the pre-charge voltage.
  • the pre-charge voltage is any voltage value within a preset floating range centered on the mean value of the positive-polarity pixel voltage and the negative polarity voltage corresponding to the same gray-scale luminance of the sub-pixel unit.
  • the pre-charge voltage is any voltage value within a preset floating range centered on the mean value of the positive-polarity pixel voltage and the negative polarity voltage corresponding to the highest gray-scale luminance of the sub-pixel unit.
  • the precharge voltage is an average value of a positive polarity pixel voltage and a negative polarity voltage corresponding to a highest gray scale luminance of the sub-pixel unit.
  • the method further includes: after charging the sub-pixel unit in each of the pixel columns to the pre-charge voltage, the method further includes:
  • the control chip outputs a first strobe signal of a first level, a second strobe signal of a second level, and a third strobe signal of a second level, and controls the first transistor to be turned on, the second transistor And the third transistor is turned off, the buffer outputs a data signal for driving the red sub-pixel unit, and the red sub-pixel unit is charged from the pre-charge voltage to a corresponding pixel voltage.
  • the method After the charging the red sub-pixel unit to a corresponding pixel voltage, the method also includes:
  • the control chip outputs a first strobe signal of a second level, a second strobe signal of a first level, and a third strobe signal of a second level, and controls the second transistor to be turned on, the first transistor And a third transistor, the buffer outputting a data signal for driving the green sub-pixel unit, and charging the green sub-pixel unit from the pre-charge voltage to a corresponding pixel voltage.
  • the method further includes:
  • the control chip outputs a first strobe signal of a second level, a second strobe signal of a second level, and a third strobe signal of a first level, and controls the third transistor to be turned on, the first transistor And the second transistor is turned off, the buffer outputs a data signal for driving the blue sub-pixel unit, and the blue sub-pixel unit is charged from the pre-charge voltage to a corresponding pixel voltage.
  • a liquid crystal display device includes a liquid crystal display panel and a driving circuit for driving the liquid crystal display panel, the liquid crystal display panel includes a plurality of pixel columns, each pixel column includes a plurality of sub-pixel units, and the driving circuit includes a control chip, a plurality of buffers, and a plurality of gate circuits, wherein the control chip is configured to output a first gate signal, a second gate signal, and a third gate signal, wherein the buffer is configured to output a precharge voltage signal,
  • Each of the gate circuits includes a first transistor, a second transistor, and a third transistor, each of the buffers passing through the first, second, and third transistors and a sub-pixel unit in the pixel column Connected, the control chip controls the first transistor, the second transistor, and the third transistor to be turned on by the first strobe signal, the second strobe signal, and the third strobe signal, respectively, to pass through the buffer
  • the output pre-charge voltage signal charges the sub-pixel cells within each of the pixel
  • the pre-charge voltage is any voltage value within a preset floating range centered on the mean value of the positive-polarity pixel voltage and the negative polarity voltage corresponding to the same gray-scale luminance of the sub-pixel unit.
  • the pre-charge voltage is any voltage value within a preset floating range centered on the mean value of the positive-polarity pixel voltage and the negative polarity voltage corresponding to the highest gray-scale luminance of the sub-pixel unit.
  • the precharge voltage is an average value of a positive polarity pixel voltage and a negative polarity voltage corresponding to a highest gray scale luminance of the sub-pixel unit.
  • each pixel unit in each pixel column are arranged in columns, each pixel unit includes a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit, and the red sub-pixel unit
  • the first transistor corresponds to the connection between the buffer and the red sub-pixel unit located in a column
  • the second transistor corresponds to the conduction center.
  • the connection between the buffer and the green sub-pixel unit located in a column corresponding to the connection between the buffer and the blue sub-pixel unit located in a column.
  • the control chip includes a first port, a second port, and a third port, the first port is configured to output a first strobe signal, and the second port is configured to output a second strobe signal, where the a three port for outputting a third strobe signal, the transistors each including a gate, a source and a drain, the first port being connected to a gate of each of the first transistors, the second port and each A gate of the second transistor is connected, and the third port is connected to a gate of each of the third transistors.
  • the buffer is further configured to buffer data signals, each of the buffers includes an output end, and the output terminal and the first transistor, the second transistor, and the first of each of the gate circuits corresponding thereto
  • the source of the three transistors is connected, and the drains of the first transistor, the second transistor and the third transistor of each of the gate circuits are respectively connected to each column of sub-pixel units in each of the pixel columns.
  • the first strobe signal, the second strobe signal, and the third strobe signal are each composed of a first level and a second level, when the first strobe signal is at a first level, the first When the second strobe signal and the third strobe signal are both at the second level, the first transistor is turned on, the second transistor and the third transistor are turned off, and the data signal buffered in the buffer passes the first The transistor is transferred to a red sub-pixel unit located in a column to charge the red sub-pixel unit from the pre-charge voltage to a corresponding pixel voltage.
  • the second transistor when the second strobe signal is at a first level, the first strobe signal, and the third strobe signal are both at a second level, the second transistor is turned on, the first transistor and The third transistors are all turned off, and the data signal buffered in the buffer is transmitted to the green sub-pixel unit located in one column through the second transistor to charge the green sub-pixel unit from the pre-charge voltage to the corresponding pixel Voltage.
  • the third transistor when the third strobe signal is at a first level, the first strobe signal and the second strobe signal are both at a second level, the third transistor is turned on, the first transistor and The second transistors are all turned off, and the data signal buffered in the buffer is transmitted to the blue sub-pixel unit located in a column through the third transistor to charge the blue sub-pixel unit from the pre-charge voltage to corresponding The pixel voltage.
  • the liquid crystal display panel driving method first charges the sub-pixel unit to the pre-charge voltage by controlling the first transistor, the second transistor, and the third transistor to be simultaneously turned on, so that the liquid crystal display panel is When the frame image is switched, the maximum voltage difference when the pixel voltage polarity of the sub-pixel units of the adjacent two pixel columns is reversed is reduced, thereby reducing the charging time of the sub-pixel unit when the liquid crystal display panel switches the frame image, thereby reducing The power consumption of the liquid crystal display device.
  • FIG. 1 is a timing chart of a charge strobe signal of a liquid crystal display device in the prior art.
  • FIG. 2 is a schematic structural diagram of a liquid crystal display device according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of polarity inversion of a pixel unit of a liquid crystal display device according to an embodiment of the present invention.
  • FIG. 4 is a timing chart of operation of a liquid crystal display device according to an embodiment of the present invention.
  • FIG. 5 is a voltage curve diagram of a gray scale of a liquid crystal display device according to an embodiment of the present invention.
  • FIG. 6 is a flowchart of a method for driving a liquid crystal display panel according to an embodiment of the present invention.
  • a first embodiment of the present invention provides a liquid crystal display device 100 including a liquid crystal display panel 110 and a driving circuit 120 for driving the liquid crystal display panel.
  • the liquid crystal display panel 110 includes a plurality of data lines 111, a plurality of scan lines 113, and a plurality of pixel units 115.
  • the plurality of data lines 111 are arranged in parallel in the vertical direction, and the plurality of scanning lines 113 are arranged in parallel in the horizontal direction.
  • the plurality of pixel units 115 are arranged in a matrix, wherein each of the pixel units 115 includes three sub-pixel units 1151 for displaying three primary colors of red, green, and blue.
  • the three sub-pixel units 1151 of each of the pixel units 115 are spaced apart from each other in the horizontal direction, and are respectively recorded as a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit, and all the sub-pixel units 1151 Arranged in a matrix, each of the sub-pixel units 1151 is driven by a Thin Film Transistor (TFT).
  • TFT Thin Film Transistor
  • Each of the data lines 111 is connected to the sub-pixel unit 1151 located in a column, and the data signal provided by the driving circuit 120 is transmitted to the sub-pixel unit 1151.
  • Each of the scan lines 113 is respectively connected to the sub-pixel unit 1151 located in a row for transmitting a scan signal provided by the drive circuit 120 to the sub-pixel unit 1151.
  • the liquid crystal display panel 110 is driven by a column inversion driving method in units of pixels. Specifically, the liquid crystal display panel 110 is divided into a plurality of pixel columns 1101 in units of pixel units 115 located in the same column, and the driving circuit 120 passes through the data lines 111. Providing a source voltage of opposite polarity for the pixel unit 115 between any two adjacent pixel columns 1101, thereby controlling the pixel unit 115 between any adjacent two pixel columns 1101 to exhibit pixel voltages of opposite polarities, and When the liquid crystal display panel 110 switches the frame image, the polarity of the pixel voltage of the pixel unit 115 of the adjacent two pixel columns 1101 is controlled by the driving circuit 120 (refer to FIG. 3 in detail).
  • each of the pixel columns 1101 includes a plurality of pixel units 115, the plurality of pixel units 115 are arranged in columns, and each of the pixel units 115 includes a red sub-pixel unit, a green sub-pixel unit, and a blue
  • the sub-pixel unit, the red sub-pixel unit, the green sub-pixel unit, and the blue sub-pixel unit are arranged in a row.
  • the first transistor T1 corresponds to a connection between the turn-on buffer 123 and a red sub-pixel unit located in a column
  • the second transistor T2 corresponds to a connection between the turn-on buffer 123 and a green sub-pixel unit located in a column.
  • the third transistor T3 corresponds to a connection between the turn-on buffer 123 and a blue sub-pixel unit located in a column.
  • the source voltage is a source driving voltage provided by the driving circuit 120 for driving the TFT corresponding to the sub-pixel unit 1151 to charge the corresponding sub-pixel unit 1151 to correspond to the source voltage. Pixel voltage.
  • the sub-pixel unit 1151 in each of the pixel columns 1101 has the same pixel voltage polarity, and the sub-pixel units 1151 in the adjacent two pixel columns 1101 The opposite is always the opposite pixel voltage polarity.
  • the pixel voltage polarity of the sub-pixel unit 1151 in the pixel column 1101 in FIG. 3 is "+" when the image of the Nth frame is displayed, that is, corresponding to the sub-pixel units R11, G11, and B11 in FIG.
  • the pixel voltage polarity of the sub-pixel unit in the pixel column in which R21, B21, and G21 are located is “+”, and the pixel voltage of the sub-pixel unit 1151 in the pixel column adjacent to the pixel column 1101 in FIG.
  • the polarity is "-", that is, the pixel voltage polarity of the sub-pixel unit in the pixel column corresponding to the sub-pixel unit R12, G12, B12, R22, B22, G22 in FIG. 2 is "-"; when switching to In the case of the N+1th frame image, the pixel voltage polarities of the sub-pixel units 1151 in the pixel column 1101 in FIG.
  • the pixel voltage polarities of the sub-pixel units in the pixel column in which R21, B21, and G21 are located are all inverted to "-", and at the same time, the pixels of the sub-pixel unit 1151 in the pixel column adjacent to the pixel column 1101 in FIG.
  • the voltage polarities are all inverted to "+", which corresponds to the sub-pixel units R12, G12, B12, R22, B22, G22 in FIG.
  • the pixel voltage polarity of sub-pixel units in the pixel columns are inverted to "+.”
  • the driving circuit 120 includes a control chip 121, a plurality of buffers 123, and a plurality of gate circuits 125.
  • the control chip 121 includes a first port 1211 for outputting a first strobe signal SELR, and a third port 1212 for outputting a second selective communication. No. SELG, the third port 1213 is for outputting the third strobe signal SELB.
  • the buffer 123 is configured to buffer the data signal and the pre-charge voltage signal, and each of the buffers 123 includes an output terminal 1231 for outputting the data signal and the pre-charge voltage signal.
  • Each of the buffers 123 is connected to a gate circuit 125, and each of the gate circuits 125 is connected to a pixel column 1101.
  • Each of the gate circuits 125 includes a first transistor T1, a second transistor T2, and a third transistor T3, and the first transistor T1, the second transistor T2, and the third transistor T3 each include a gate g, a source s, and Drain d.
  • the first port 1211 is connected to the gate g of each of the first transistors T1
  • the second port 1212 is connected to the gate g of each of the second transistors T2, and the third port 1213 and each A gate g of the third transistor T3 is connected.
  • the output terminal 1231 of each of the buffers 123 is connected to the source s of the first transistor T1, the second transistor T2, and the third transistor T3 of each of the gate circuits 125 corresponding thereto.
  • the drains d of the first transistor T1, the second transistor T2, and the third transistor T3 of each of the gate circuits 125 pass through one of the data lines 111 and each of the pixels corresponding to the gate circuit 125, respectively.
  • Each column of sub-pixel units 1151 in column 1101 is connected.
  • the first strobe signal SELR, the second strobe signal SELG, and the third strobe signal SELB are each composed of a first level and a second level, and the first transistor T1, the second transistor T2, and the third transistor T3
  • the control chip 121 controls the first strobe signal SELR, the second strobe signal SELG, and the third strobe signal SELB according to the operation timing of the liquid crystal device 100. Switching between the first level and the second level to control the first transistor T1, the second transistor T2, and the third transistor T3 to be turned on or off.
  • the first transistor T1 of each of the strobe circuits 125 is turned on, and the data signal buffered in each of the buffers 123 passes the a transistor T1 and a data line 111 connected to the first transistor T1 are transferred to the red sub-pixel unit in a column; when the first strobe signal SELR is at a second level, each of the strobe circuits The first transistor T1 of 125 is turned off.
  • the second strobe signal SELG is at the first level
  • the second transistor T2 of each of the strobe circuits 125 is turned on, and the data signal buffered in each of the buffers 123 passes through the second crystal.
  • the tube T2 and the data line 111 connected to the second transistor T2 are transferred to the green sub-pixel unit located in a column; when the second strobe signal SELR is at the second level, each of the strobe circuits 125 The second transistor T2 is turned off.
  • the third strobe signal SELB is at the first level, the third transistor T3 of each of the strobe circuits 125 is turned on, and the data signal buffered in each of the buffers 123 passes through the third transistor T3.
  • the data line 111 connected to the third transistor T3 is transferred to the blue sub-pixel unit located in a column; when the third strobe signal SELR is at a second level, each of the strobe circuits 125 The third transistor T3 is turned off.
  • FIG. 4 is a timing chart of the operation of the liquid crystal display device 100.
  • the timing diagram includes a plurality of timing periods, each of the timing periods including a first timing, a second timing, a third timing, a fourth timing, and a fifth timing that are sequentially connected.
  • GATE is a scan signal on the scan line 113;
  • SELR, SELG and SELB are respectively a first strobe signal, a second strobe signal and a third strobe signal provided by the control chip 121;
  • DATA is the The data signal provided by the buffer 123.
  • Each of the scan lines 113 sequentially supplies the scan signal according to the timing cycle.
  • the first row scan line G1 provides a scan signal to turn on the sub-pixel unit 1151 located in the first row.
  • the TFTs of the second row scan line G2 provide a scan signal to turn on the TFTs in the sub-pixel unit 1151 of the second row.
  • the GATE shown in FIG. 3 is a timing chart corresponding to when the scanning signals are supplied to the Nth scanning line and the N+1th scanning line.
  • the working principle of the liquid crystal display device 100 at each timing in one timing cycle is:
  • the control chip 121 controls the first port 1211, the second port 1212, and the third port 1213 to output a first level first strobe signal SELR, a first level second selection, respectively.
  • the signal SELG and the third strobe signal SELB of the first level at the same time, the output 1231 of each of the buffers 123 outputs a precharge voltage, due to the first transistor T1, the second transistor T2 and the third Transistor T3 is both turned on and all sub-pixel units 1151 are charged to the pre-charge voltage.
  • FIG. 5 is a voltage curve corresponding to different gray scale luminances of a sub-pixel unit 1151 of the liquid crystal display device 100 during polarity inversion.
  • the position indicated by V+ corresponds to the positive pixel voltage of the highest gray level brightness
  • the position indicated by V- corresponds to the negative polarity pixel voltage of the highest gray level brightness
  • the position indicated by GND corresponds to the ground voltage, as indicated by VCOM
  • the position corresponds to the common voltage.
  • the common voltage VCOM is located on the symmetry axis of the voltage curve, that is, the common voltage VCOM is the average of the positive polarity pixel voltage V+ and the negative polarity pixel voltage V-, and the GND voltage is not the positive polarity pixel voltage V+ and the negative polarity pixel.
  • the average value of the voltage V- Therefore, in the process of polarity inversion of the sub-pixel unit 1151, the pixel voltage of the sub-pixel unit 1151 is first charged to the GND voltage, and then charged to the positive electrode by the GND voltage.
  • the pixel voltages of the sub-pixel unit 1151 are first charged to the common voltage VCOM, and then the common voltage VCOM is respectively used by the common pixel voltage V+. Charging to the positive polarity pixel voltage V+ or the negative polarity pixel voltage V- can effectively reduce the voltage difference for charging the pixel electrode of the sub-pixel unit 1151 during polarity inversion, shorten the charging time, and reduce the liquid crystal display.
  • the power consumption of device 100 is not limited to the common voltage VCOM, and then the common voltage VCOM is respectively used by the common pixel voltage V+.
  • the common voltage VCOM is 1.2V
  • the positive and negative pixel voltages V+ and V ⁇ of the 128 gray scale luminance are 6V and ⁇ 3.6V, respectively, by first charging the sub-pixel unit 1151 to the
  • the common voltage VCOM is 1.2 V
  • the pixel circuit 115 of the adjacent two pixel columns 1101 is controlled to have the maximum polarity of the pixel voltage inversion by the driving circuit 120.
  • the voltage difference is 4.8 V, which is reduced by 1.2 V as compared with the maximum voltage difference of 6 V when the sub-pixel unit 1151 is charged to the GND voltage, that is, 0 V, thereby reducing the power consumption of the liquid crystal display device 100.
  • the common voltage VCOM is also a precharge voltage.
  • the precharge voltage value refers to a positive pixel voltage value and a negative polarity pixel voltage value corresponding to the same gray scale luminance of the sub pixel unit 1151.
  • the center fluctuation value also known as the mean value, and the precharge voltage value is often not 0V, which is different from the GND voltage. Therefore, at the first timing, a precharge voltage signal is output through each of the buffers 123 to charge each of the sub-pixel units 1151 to the precharge voltage.
  • the precharge voltage may be set to any voltage value within a preset floating range centered on the mean value of the positive polarity pixel voltage V+ and the negative polarity voltage V ⁇ corresponding to the highest gray level luminance of the sub-pixel unit 1151.
  • the preset floating range is 20%
  • the pre-charge voltage may be set to the mean value of the positive polarity pixel voltage V+ and the negative polarity voltage V- corresponding to the highest gray-scale luminance of the sub-pixel unit 1151 ⁇ (1 ⁇ Any voltage value within 20%).
  • the preset floating range is not limited to 20%, and may also be 5%, 10%, 25%, and the like.
  • the precharge voltage is not limited to any one of preset floating ranges set to be centered on the mean value of the positive polarity pixel voltage V+ and the negative polarity voltage V ⁇ corresponding to the highest gray scale luminance of the sub pixel unit 1151.
  • Voltage value can also be set Any voltage value within a preset floating range centered on the positive polarity pixel voltage value and the negative polarity pixel voltage value corresponding to the other gray scale luminances of the sub-pixel unit 1151.
  • the precharge voltage it is preferable to set the precharge voltage to be the average value of the positive polarity pixel voltage V+ and the negative polarity voltage V ⁇ corresponding to the highest gray scale luminance of the sub-pixel unit 1151, that is, the common voltage VCOM.
  • the control chip 121 controls the first port 1211 to output a first level of the first strobe signal SELR, and controls the second port 1212 and the third port 1213 to output a second level, respectively.
  • the second strobe signal SELG and the second strobe signal SELB of the second level at the same time, the output 1231 of each of the buffers 123 outputs a data signal RED for driving the red sub-pixel unit,
  • the first transistor T1 is turned on, and the second transistor T2 and the third transistor T3 are both turned off, so that the data signal RED is only transmitted to the red sub-pixel unit located in a column, and the red sub-pixel is further
  • the cell is charged from the precharge voltage to a corresponding pixel voltage.
  • the control chip 121 controls the first port 1211 to output a second level of the first strobe signal SELR, and controls the second port 1212 to output a first level second strobe signal SELG. And controlling the third port 1213 to output a third level of the third strobe signal SELB, and at the same time, the output end 1231 of each of the buffers 123 outputs a data signal GREEN for driving the green sub-pixel unit Since the second transistor T2 is turned on, the first transistor T1 and the third transistor T3 are both turned off, and thus the data signal GREEN is only transmitted to the green sub-pixel unit located in a column, and then the green The sub-pixel unit is charged from the pre-charge voltage to a corresponding pixel voltage.
  • the control chip 121 controls the first port 1211 and the second port 1212 to output a second level first strobe signal SELR and a second level second strobe signal SELG, respectively.
  • the control chip 121 controls the first port 1211, the second port 1212, and the third port 1213 to output a second level first strobe signal SELR and a second level second, respectively.
  • the strobe signal SELG and the third level strobe signal SELB, the first transistor T1, the second transistor T2 and the third transistor T3 are both turned off, so the output 1231 of each of the buffers 123 is presented High resistance HiZ state.
  • the scan line 113 located in the Nth row provides the scan signal GATE, turns on the TFTs in all the sub-pixel units 1151 of the Nth row, and then passes The first to fifth timings complete the scanning process of the Nth row of pixel units; after the scanning of the Nth row of pixel cells is completed, the scan line 113 located in the Nth row stops providing the scan signal, and is located at the N+th
  • the scan line 113 of one row starts to provide the scan signal, turns on the TFTs in all the sub-pixel units 1151 of the (N+1)th row, and repeats the first to fifth timing completion to the N+1th row of pixel units.
  • the scanning process is described in the process of scanning the pixel unit of the Nth row.
  • a second embodiment of the present invention provides a liquid crystal display panel driving method.
  • the method is applied to the liquid crystal display device 100 of the embodiment shown in FIG. 2, and includes at least the following steps:
  • Step S201 The control chip 121 synchronously outputs a first strobe signal SELR of a first level, a second strobe signal SELG of a first level, and a third strobe signal SELB of a first level, and is controlled to be connected to the buffer 123.
  • the first transistor T1, the second transistor T2, and the third transistor T3 are electrically connected to each pixel column 1101;
  • the pixel column 1101 includes a plurality of pixel units 115, and the plurality of pixel units 115 are arranged in columns.
  • Each of the pixel units 115 includes a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel.
  • the unit, the red sub-pixel unit, the green sub-pixel unit, and the blue sub-pixel unit are arranged in a row.
  • the first transistor T1 corresponds to a connection between the turn-on buffer 123 and a red sub-pixel unit located in a column
  • the second transistor T2 corresponds to a connection between the turn-on buffer 123 and a green sub-pixel unit located in a column.
  • the third transistor T3 corresponds to a connection between the turn-on buffer 123 and a blue sub-pixel unit located in a column.
  • Step S202 The buffer 123 outputs a precharge voltage signal, and the sub-pixel unit 1151 in each pixel column 1101 is charged to the pre-charge voltage; wherein the pre-charge voltage is in the sub-pixel
  • the average value of the positive polarity pixel voltage V+ and the negative polarity voltage V ⁇ corresponding to the gray level brightness of the unit 1151 is any voltage value within a preset floating range of the center;
  • Step S203 The control chip 121 outputs a first level first strobe signal SELR, a second level second strobe signal SELG, and a second level third strobe signal SELB to control the first
  • the transistor T1 is turned on, the second transistor T2 and the third transistor T3 are turned off, the buffer 121 outputs a data signal RED for driving the red sub-pixel unit, and the red sub-pixel unit is charged from the precharge voltage to the corresponding Pixel voltage
  • Step S204 The control chip 121 outputs a second level first strobe signal SELR, a first level second strobe signal SELG, and a second level third strobe signal SELB to control the second
  • the transistor T2 is turned on, the first transistor T1 and the third transistor T3 are turned off, the buffer 121 outputs a data signal GREEN for driving the green sub-pixel unit, and the green sub-pixel unit is charged from the precharge voltage to the corresponding Pixel voltage
  • Step S205 The control chip 121 outputs a second level first strobe signal SELR, a second level second strobe signal SELG, and a first level third strobe signal SELB to control the third
  • the transistor T3 is turned on, the first transistor T1 and the second transistor T2 are turned off, the buffer 121 outputs a data signal BLUE for driving the blue sub-pixel unit, and the blue sub-pixel unit is charged from the precharge voltage. To the corresponding pixel voltage.
  • the precharge voltage is preferably set to an average value of the positive polarity pixel voltage V+ and the negative polarity voltage V ⁇ corresponding to the highest gray level luminance of the sub-pixel unit 1151, that is, the common voltage VCOM.
  • the first transistor T1 and the second transistor are controlled by the control chip 121 in a charging phase before data is written to each pixel unit through a data line.
  • the transistor T2 and the third transistor T3 are simultaneously turned on to charge the sub-pixel unit 1151 to the common voltage VCOM, so that when the liquid crystal display panel 110 switches the frame image, the pixel unit 115 of the adjacent two pixel columns 1101 When the pixel voltage polarity is reversed, the maximum differential voltage is reduced, thereby reducing the charging time of the sub-pixel unit 1151 when the liquid crystal display panel 110 switches the frame image, and reducing the power consumption of the liquid crystal display device 100.

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Abstract

提供了一种液晶显示面板驱动方法，该方法包括：控制芯片(121)同步输出第一电平的第一选通信号(STLR)、第一电平的第二选通信号(STLG)和第一电平的第三选通信号(STLB)，控制连接于缓存器(123)与每一像素列(1101)之间的第一晶体管(T1)、第二晶体管(T2)和第三晶体管(T3)均导通；缓存器(123)输出预充电电压信号，将每一像素列(1101)内的子像素单元(1151)均充电至预充电电压。还提供了一种液晶显示装置。该液晶显示面板驱动方法可以有效降低液晶显示装置的功耗。

Description

液晶显示面板驱动方法及液晶显示装置
本发明要求2015年8月28日递交的发明名称为“液晶显示面板驱动方法及液晶显示装置”的申请号(201510541803.2)的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种液晶显示面板驱动方法及液晶显示装置。
背景技术
目前，在薄膜晶体管(Thin Film Transistor，TFT)液晶显示装置中，为了延长液晶的使用寿命，通常对液晶显示面板采用极性反转的方式进行驱动。在采用上述极性反转方式的液晶显示面板驱动电路中，控制芯片需要控制每条数据线的源电压在正极性电压和负极性电压之间频繁切换，这样便会导致充电压差较大，不利于降低液晶显示面板的功耗。
如图1所示，为解决上述问题，在现有液晶显示装置中，通常在充电时序开始时首先通过控制选通信号SELR、SELG和SELB为高电平，使得逐行扫描时每一行内所有的R、G、B子像素电极所对应的TFT均同时导通，并将各个子像素电极均充电至GND电压，即0V，从而使得该行内所有R、G、B子像素电极的电位同时成为GND电压，然后再依次控制选通信号SELR、SELG和SELB为高电平，进而依次打开R、G、B子像素电极对应的TFT，以对所述子像素电极逐一充入对应极性的像素电压。
如此便可在极性反转方式驱动的液晶显示面板电路中，先由负极性像素电压统一充电至0V，然后再由0V逐一充电至正极性像素电压，使得充电压差不至于太大，以降低液晶显示面板的功耗。
然而，一般情况下GND并不是正负极性像素电压切换的中间值，例如，假设公共电压为1.2V，则128灰阶亮度的源电压对应的正负极性像素电压分别为6V和-3.6V，如果按照先将各个像素电极均充电至GND电压的方式，则 在由GND电压充电至正极性像素电压时，充电压差达到6V，该充电电压依然相对较大，从而导致充电时间较长，功耗较高。
发明内容
鉴于现有技术中存在的上述问题，本发明提供一种液晶显示面板驱动方法，首先将液晶显示面板的各个子像素单元均充电至预充电电压，然后再依次将各个子像素单元从所述预充电电压充电至对应的像素电压，以降低采用极性反转的方式进行驱动液晶显示面板时的充电压差，缩短充电时间，进而降低液晶显示装置的功耗。
另，本发明还提供一种应用所述液晶显示面板驱动方法的液晶显示装置。
一种液晶显示面板驱动方法，包括：
控制芯片同步输出第一电平的第一选通信号、第一电平的第二选通信号和第一电平的第三选通信号，控制连接于缓存器与每一像素列之间的第一晶体管、第二晶体管和第三晶体管均导通；
所述缓存器输出预充电电压信号，将所述每一像素列内的子像素单元均充电至所述预充电电压。
其中，所述预充电电压为以所述子像素单元同一灰阶亮度对应的正极性像素电压与负极性电压的均值为中心的预设浮动范围内的任一电压值。
其中，所述预充电电压为以所述子像素单元最高灰阶亮度对应的正极性像素电压与负极性电压的均值为中心的预设浮动范围内的任一电压值。
其中，所述预充电电压为所述子像素单元最高灰阶亮度对应的正极性像素电压与负极性电压的均值。
其中，所述将所述每一像素列内的子像素单元均充电至所述预充电电压之后，所述方法还包括：
所述控制芯片输出第一电平的第一选通信号、第二电平的第二选通信号及第二电平的第三选通信号，控制所述第一晶体管导通、第二晶体管及第三晶体管截止，所述缓存器输出用于驱动红色子像素单元的数据信号，将所述红色子像素单元从所述预充电电压充电至对应的像素电压。
其中，所述将所述红色子像素单元充电至对应的像素电压之后，所述方法 还包括：
所述控制芯片输出第二电平的第一选通信号、第一电平的第二选通信号及第二电平的第三选通信号，控制所述第二晶体管导通、第一晶体管及第三晶体管，所述缓存器输出用于驱动绿色子像素单元的数据信号，将所述绿色子像素单元从所述预充电电压充电至对应的像素电压。
其中，所述将所述绿色子像素单元充电至对应的像素电压之后，所述方法还包括：
所述控制芯片输出第二电平的第一选通信号、第二电平的第二选通信号及第一电平的第三选通信号，控制所述第三晶体管导通、第一晶体管及第二晶体管截止，所述缓存器输出用于驱动蓝色子像素单元的数据信号，将所述蓝色子像素单元从所述预充电电压充电至对应的像素电压。
一种液晶显示装置，包括液晶显示面板和用于驱动所述液晶显示面板的驱动电路，所述液晶显示面板包括多个像素列，每一像素列内包括多个子像素单元，所述驱动电路包括控制芯片、多个缓存器和多个选通电路，所述控制芯片用于输出第一选通信号、第二选通信号和第三选通信号，所述缓存器用于输出预充电电压信号，每一所述选通电路包括第一晶体管、第二晶体管和第三晶体管，每一所述缓存器通过所述第一晶体管、第二晶体管和第三晶体管与所述像素列内的子像素单元连接，所述控制芯片通过所述第一选通信号、第二选通信号和第三选通信号分别控制所述第一晶体管、第二晶体管和第三晶体管导通，以通过所述缓存器输出的预充电电压信号将所述每一像素列内的子像素单元均充电至所述预充电电压。
其中，所述预充电电压为以所述子像素单元同一灰阶亮度对应的正极性像素电压与负极性电压的均值为中心的预设浮动范围内的任一电压值。
其中，所述预充电电压为以所述子像素单元最高灰阶亮度对应的正极性像素电压与负极性电压的均值为中心的预设浮动范围内的任一电压值。
其中，所述预充电电压为所述子像素单元最高灰阶亮度对应的正极性像素电压与负极性电压的均值。
其中，所述每一像素列内的多个像素单元呈列设置，每一像素单元包括一红色子像素单元、一绿色子像素单元和一蓝色子像素单元，所述红色子像素单 元、绿色子像素单元和蓝色子像素单元呈行设置，所述第一晶体管对应导通所述缓存器与位于一列的红色子像素单元之间的连接，所述第二晶体管对应导通所述缓存器与位于一列的绿色子像素单元之间的连接，所述第三晶体管对应导通所述缓存器与位于一列的蓝色子像素单元之间的连接。
其中，所述控制芯片包括第一端口、第二端口和第三端口，所述第一端口用于输出第一选通信号，所述第二端口用于输出第二选通信号，所述第三端口用于输出第三选通信号，所述晶体管均包括栅极、源极和漏极，所述第一端口与每一所述第一晶体管的栅极连接，所述第二端口与每一所述第二晶体管的栅极连接，所述第三端口与每一所述第三晶体管的栅极连接。
其中，所述缓存器还用于缓存数据信号，每一所述缓存器包括一输出端，所述输出端和与之对应的每一所述选通电路的第一晶体管、第二晶体管和第三晶体管的源极连接，每一所述选通电路的第一晶体管、第二晶体管和第三晶体管的漏极分别和每一所述像素列内的每一列子像素单元连接。
其中，所述第一选通信号、第二选通信号和第三选通信号均由第一电平和第二电平组成，当所述第一选通信号为第一电平、所述第二选通信号及第三选通信号均为第二电平时，所述第一晶体管导通，所述第二晶体管及第三晶体管截止，所述缓存器内缓存的数据信号通过所述第一晶体管传送给位于一列的红色子像素单元，以将所述红色子像素单元从所述预充电电压充电至对应的像素电压。
其中，当所述第二选通信号为第一电平、所述第一选通信号及第三选通信号均为第二电平时，所述第二晶体管导通，所述第一晶体管及第三晶体管均截止，所述缓存器内缓存的数据信号通过所述第二晶体管传送给位于一列的绿色子像素单元，以将所述绿色子像素单元从所述预充电电压充电至对应的像素电压。
其中，当所述第三选通信号为第一电平、所述第一选通信号及第二选通信号均为第二电平时，所述第三晶体管导通，所述第一晶体管及第二晶体管均截止，所述缓存器内缓存的数据信号通过所述第三晶体管传送给位于一列的蓝色子像素单元，以将所述蓝色子像素单元从所述预充电电压充电至对应的像素电压。
所述液晶显示面板驱动方法，首先通过控制所述第一晶体管、第二晶体管及第三晶体管同时导通，将所述子像素单元均充电至所述预充电电压，使得所述液晶显示面板在切换帧图像时，相邻的两个像素列的子像素单元的像素电压极性反转时的最大压差缩小，从而缩减所述液晶显示面板在切换帧图像时的子像素单元充电时间，降低所述液晶显示装置的功耗。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中液晶显示装置的充电选通信号的时序图。
图2为本发明实施例提供的液晶显示装置的结构示意图。
图3为本发明实施例提供的液晶显示装置的像素单元的极性反转示意图。
图4为本发明实施例提供的液晶显示装置的工作时序图。
图5为本发明实施例提供的液晶显示装置的灰阶的电压曲线图。
图6为本发明实施例提供的液晶显示面板驱动方法的流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
为便于描述，这里可以使用诸如“在…之下”、“在…下面”、“下”、“在…之上”、“上”等空间相对性术语来描述如图中所示的一个元件或特征与另一个(些)元件或特征的关系。可以理解，当一个元件或层被称为在另一元件或层“上”、“连接到”或“耦接到”另一元件或层时，它可以直接在另一元件或层上、直接连接到或耦接到另一元件或层，或者可以存在居间元件或层。相反，当一个元件被称为“直接在”另一元件或层上、“直接连接到”或“直接耦接 到”另一元件或层时，不存在居间元件或层。
可以理解，这里所用的术语仅是为了描述特定实施例，并非要限制本发明。在这里使用时，除非上下文另有明确表述，否则单数形式“一”和“该”也旨在包括复数形式。进一步地，当在本说明书中使用时，术语“包括”和/或“包含”表明所述特征、整体、步骤、操作、元件和/或组件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、组件和/或其组合的存在或增加。
除非另行定义，这里使用的所有术语(包括技术术语和科学术语)都具有本发明所属领域内的普通技术人员所通常理解的相同含义。将进一步理解，诸如通用词典中所定义的术语，否则应当被解释为具有与它们在相关领域的语境中的含义相一致的含义，而不应被解释为理想化或过度形式化的意义，除非在此明确地如此定义。
请参阅图2，本发明第一实施例提供一种液晶显示装置100，包括液晶显示面板110和用于驱动所述液晶显示面板的驱动电路120。所述液晶显示面板110包括多条数据线111、多条扫描线113和多个像素单元115。所述多条数据线111沿垂直方向平行间隔设置，所述多条扫描线113沿水平方向平行间隔设置。所述多个像素单元115呈矩阵排列，其中，每一个所述像素单元115包括三个子像素单元1151，分别用于显示红、绿、蓝三原色。
在本实施例中，每一个所述像素单元115的三个子像素单元1151沿水平方向相互间隔设置，分别记为红色子像素单元、绿色子像素单元和蓝色子像素单元，所有子像素单元1151呈矩阵排列，每一个所述子像素单元1151由薄膜晶体管(Thin Film Transistor，TFT)驱动。每一条所述数据线111分别与位于一列的所述子像素单元1151连接，用于降所述驱动电路120提供的数据信号传送给所述子像素单元1151。每一条所述扫描线113分别与位于一行的所述子像素单元1151连接，用于将所述驱动电路120提供的扫描信号传送给所述子像素单元1151。
在本实施例中，所述液晶显示面板110采用以像素为单位的列反转驱动方式进行驱动。具体地，将所述液晶显示面板110以位于同一列的像素单元115为单位，划分为多个像素列1101，由所述驱动电路120通过所述数据线111 为任意相邻的两个像素列1101之间的像素单元115提供极性相反的源电压，从而控制任意相邻的两个像素列1101之间的像素单元115呈现极性相反的像素电压，且在所述液晶显示面板110切换帧图像时，通过所述驱动电路120控制所述相邻的两个像素列1101的像素单元115的像素电压极性反转(具体参考图3)。
图2中，所述每一像素列1101包括多个像素单元115，所述多个像素单元115呈列设置，每一像素单元115包括一红色子像素单元、一绿色子像素单元和一蓝色子像素单元，所述红色子像素单元、绿色子像素单元和蓝色子像素单元呈行设置。所述第一晶体管T1对应导通缓存器123与位于一列的红色子像素单元之间的连接，所述第二晶体管T2对应导通缓存器123与位于一列的绿色子像素单元之间的连接，所述第三晶体管T3对应导通缓存器123与位于一列的蓝色子像素单元之间的连接。其中，所述源电压为由所述驱动电路120提供的用于驱动所述子像素单元1151对应的TFT的源极驱动电压，以将对应的子像素单元1151充电至与所述源电压对应的像素电压。
具体地，请一并参阅图2和图3，每一所述像素列1101内的子像素单元1151具有相同的像素电压极性，而相邻的两个像素列1101内的子像素单元1151之间则始终呈现相反的像素电压极性。例如，假设在显示第N帧图像时，图3中的像素列1101内的子像素单元1151的像素电压极性均为“+”，即对应于图2中的子像素单元R11、G11、B11、R21、B21、G21所在像素列内的子像素单元的像素电压极性均为“+”，则图3中与所述像素列1101相邻的像素列内的子像素单元1151的像素电压极性均为“-”，即对应于图2中的子像素单元R12、G12、B12、R22、B22、G22所在像素列内的子像素单元的像素电压极性均为“-”；当切换到第N+1帧图像时，图3中的像素列1101内的子像素单元1151的像素电压极性均反转为“-”，即对应于图2中的子像素单元R11、G11、B11、R21、B21、G21所在像素列内的子像素单元的像素电压极性均反转为“-”，同时，图3中与所述像素列1101相邻的像素列内的子像素单元1151的像素电压极性则均反转为“+”，即对应于图2中的子像素单元R12、G12、B12、R22、B22、G22所在像素列内的子像素单元的像素电压极性均反转为“+”。
所述驱动电路120包括控制芯片121、多个缓存器123和多个选通电路 125。所述控制芯片121包括第一端口1211、第二端口1212和第三端口1213，所述第一端口1211用于输出第一选通信号SELR，所述第二端口1212用于输出第二选通信号SELG，所述第三端口1213用于输出第三选通信号SELB。所述缓存器123用于缓存数据信号及预充电电压信号，每一所述缓存器123包括一输出端1231，用于输出所述数据信号及预充电电压信号。其中，每一所述缓存器123对应与一所述选通电路125连接，每一所述选通电路125对应与一所述像素列1101连接。每一所述选通电路125包括第一晶体管T1、第二晶体管T2和第三晶体管T3，所述第一晶体管T1、第二晶体管T2和第三晶体管T3均包括栅极g、源极s和漏极d。所述第一端口1211与每一所述第一晶体管T1的栅极g连接，所述第二端口1212与每一所述第二晶体管T2的栅极g连接，所述第三端口1213与每一所述第三晶体管T3的栅极g连接。每一所述缓存器123的输出端1231和与之对应的每一所述选通电路125的第一晶体管T1、第二晶体管T2和第三晶体管T3的源极s连接。每一所述选通电路125的第一晶体管T1、第二晶体管T2和第三晶体管T3的漏极d分别通过一条所述数据线111和与所述选通电路125对应的每一所述像素列1101内的每一列子像素单元1151连接。
下面进一步说明所述液晶装置100的工作原理:
所述第一选通信号SELR、第二选通信号SELG和第三选通信号SELB均由第一电平和第二电平组成，所述第一晶体管T1、第二晶体管T2和第三晶体管T3均具有导通和截止两种工作状态，所述控制芯片121根据所述液晶装置100的工作时序控制所述第一选通信号SELR、第二选通信号SELG和第三选通信号SELB在所述第一电平和第二电平之间切换，以控制所述第一晶体管T1、第二晶体管T2和第三晶体管T3导通或者截止。具体地，当所述第一选通信号SELR为第一电平时，每一所述选通电路125的第一晶体管T1导通，每一所述缓存器123内缓存的数据信号通过所述第一晶体管T1及与所述第一晶体管T1连接的数据线111传送给位于一列的所述红色子像素单元；当所述第一选通信号SELR为第二电平时，每一所述选通电路125的第一晶体管T1截止。当所述第二选通信号SELG为第一电平时，每一所述选通电路125的第二晶体管T2导通，每一所述缓存器123内缓存的数据信号通过所述第二晶体 管T2及与所述第二晶体管T2连接的数据线111传送给位于一列的所述绿色子像素单元；当所述第二选通信号SELR为第二电平时，每一所述选通电路125的第二晶体管T2截止。当所述第三选通信号SELB为第一电平时，每一所述选通电路125的第三晶体管T3导通，每一所述缓存器123内缓存的数据信号通过所述第三晶体管T3及与所述第三晶体管T3连接的数据线111传送给位于一列的所述蓝色子像素单元；当所述第三选通信号SELR为第二电平时，每一所述选通电路125的第三晶体管T3截止。
请参阅图4，图4为所述液晶显示装置100的工作时序图。所述时序图包括多个时序周期，每一所述时序周期分别包括依次相连的第一时序、第二时序、第三时序、第四时序和第五时序。其中，GATE为所述扫描线113上的扫描信号；SELR、SELG和SELB分别为所述控制芯片121提供的第一选通信号、第二选通信号和第三选通信号；DATA为所述缓存器123提供的数据信号。所述每一条扫描线113按照所述时序周期依次提供所述扫描信号，如第一时序周期时，所述第一行扫描线G1提供扫描信号，以开启位于第一行的子像素单元1151中的TFT，在第二时序周期时，所述第二行扫描线G2提供扫描信号，以开启位于第二行的子像素单元1151中的TFT。图3中所示GATE为第N行扫描线和第N+1行扫描线提供扫描信号时对应的时序图。所述液晶显示装置100在一个时序周期内的每一时序下的工作原理为：
在第一时序下，所述控制芯片121控制所述第一端口1211、第二端口1212和第三端口1213分别输出第一电平的第一选通信号SELR、第一电平的第二选通信号SELG和第一电平的第三选通信号SELB，同时，每一所述缓存器123的输出端1231均输出预充电电压，由于所述第一晶体管T1、第二晶体管T2和第三晶体管T3均导通，所有子像素单元1151均被充电至所述预充电电压。
请参阅图5，图5所示为所述液晶显示装置100的一个子像素单元1151在极性反转过程中的对应于不同灰阶亮度的电压曲线。其中，V+所指示的位置对应于最高灰阶亮度的正极性像素电压，V-所指示的位置对应于最高灰阶亮度的负极性像素电压，GND所指示的位置对应于接地电压，VCOM所指示的位置对应于公共电压。
从图5可以看出，在所述子像素单元1151极性反转过程中，公共电压 VCOM位于所述电压曲线的对称轴上，即公共电压VCOM为所述正极性像素电压V+与负极性像素电压V-的均值，而GND电压则并非为所述正极性像素电压V+与负极性像素电压V-的均值。因此，在所述子像素单元1151极性反转的过程中，相对于首先将所述子像素单元1151的像素电压均充电至所述GND电压，再由所述GND电压分别充电至所述正极性像素电压V+或者负极性像素电压V-的技术方案，在本发明实施例中，首先将所述子像素单元1151的像素电压均充电至所述公共电压VCOM，再由所述公共电压VCOM分别充电至所述正极性像素电压V+或者负极性像素电压V-，可以有效降低极性反转过程中对所述子像素单元1151的像素电极充电的压差，缩短充电时间，降低所述液晶显示装置100的功耗。例如，假设所述公共电压VCOM为1.2V，则128灰阶亮度的正负极性像素电压V+和V-分别为6V和-3.6V，通过先将所述子像素单元1151均充电至所述公共电压VCOM即1.2V，则在所述液晶显示面板110切换帧图像时，通过所述驱动电路120控制所述相邻的两个像素列1101的像素单元115的像素电压极性反转的最大压差为4.8V，相较于将所述子像素单元1151均充电至GND电压即0V时的最大压差6V减少了1.2V，从而降低所述液晶显示装置100的功耗。
即在本实施例中，公共电压VCOM亦即预充电电压，值得说明的是，该预充电电压值是指与子像素单元1151同一灰阶亮度对应的正极性像素电压值和负极性像素电压值的中心波动值，也称为均值，且该预充电电压值常常并不是0V，与GND电压不同。因此，在所述第一时序下，通过每一所述缓存器123输出一预充电电压信号，以将所述每一子像素单元1151均充电至所述预充电电压。例如，所述预充电电压可设置为以所述子像素单元1151最高灰阶亮度对应的正极性像素电压V+与负极性电压V-的均值为中心的预设浮动范围内的任一电压值。例如，所述预设浮动范围为20％时，所述预充电电压可设置为所述子像素单元1151最高灰阶亮度对应的正极性像素电压V+与负极性电压V-的均值×(1±20％)内的任一电压值。可以理解，所述预设浮动范围并不限于20％，还可以为5％、10％、25％等。可以理解，所述预充电电压并不限于设置为以所述子像素单元1151最高灰阶亮度对应的正极性像素电压V+与负极性电压V-的均值为中心的预设浮动范围内的任一电压值，还可以设置 为以所述子像素单元1151其他灰阶亮度对应的正极性像素电压值和负极性像素电压值为中心的预设浮动范围内的任一电压值。
在本实施例中，优选设置所述预充电电压为所述子像素单元1151最高灰阶亮度对应的正极性像素电压V+与负极性电压V-的均值，即所述公共电压VCOM。
在第二时序下，所述控制芯片121控制所述第一端口1211输出第一电平的第一选通信号SELR，并控制所述第二端口1212和第三端口1213分别输出第二电平的第二选通信号SELG和第二电平的第三选通信号SELB，同时，每一所述缓存器123的输出端1231均输出用于驱动所述红色子像素单元的数据信号RED，由于所述第一晶体管T1导通，所述第二晶体管T2和第三晶体管T3均截止，因而所述数据信号RED仅被传送至位于一列的所述红色子像素单元，进而将所述红色子像素单元从所述预充电电压充电至对应的像素电压。
在第三时序下，所述控制芯片121控制所述第一端口1211输出第二电平的第一选通信号SELR，控制所述第二端口1212输出第一电平的第二选通信号SELG，并控制所述第三端口1213输出第二电平的第三选通信号SELB，同时，每一所述缓存器123的输出端1231均输出用于驱动所述绿色子像素单元的数据信号GREEN，由于所述第二晶体管T2导通，所述第一晶体管T1和第三晶体管T3均截止，因而所述数据信号GREEN仅被传送至位于一列的所述绿色子像素单元，进而将所述绿色子像素单元从所述预充电电压充电至对应的像素电压。
在第四时序下，所述控制芯片121控制所述第一端口1211和第二端口1212分别输出第二电平的第一选通信号SELR和第二电平的第二选通信号SELG，并控制所述第三端口1213输出第一电平的第三选通信号SELB，同时，每一所述缓存器123的输出端1231均输出用于驱动所述蓝色子像素单元的数据信号BLUE，由于所述第一晶体管T1和第二晶体管T2均截止，所述第三晶体管T3导通，因而所述数据信号BLUE仅被传送至位于一列的所述蓝色子像素单元，进而将所述蓝色子像素单元从所述预充电电压充电至对应的像素电压。
在第五时序下，所述控制芯片121控制所述第一端口1211、第二端口1212和第三端口1213分别输出第二电平的第一选通信号SELR、第二电平的第二 选通信号SELG和第二电平的第三选通信号SELB，所述第一晶体管T1、第二晶体管T2和第三晶体管T3均截止，因此每一所述缓存器123的输出端1231均呈现出高阻HiZ状态。
可以理解，在对第N行像素单元进行扫描的过程中，位于第N行的所述扫描线113提供所述扫描信号GATE，开启位于第N行的所有子像素单元1151中的TFT，进而通过上述第一至第五时序完成对所述第N行像素单元的扫描过程；当第N行像素单元扫描完成后，所述位于第N行的扫描线113停止提供扫描信号，同时位于第N+1行的所述扫描线113开始提供所述扫描信号，开启位于第N+1行的所有子像素单元1151中的TFT，进而重复上述第一至第五时序完成对第N+1行像素单元的扫描过程。
请参阅图6，本发明第二实施例提供一种液晶显示面板驱动方法，所述方法应用于图2所示实施例的液晶显示装置100中，至少包括如下步骤：
步骤S201：控制芯片121同步输出第一电平的第一选通信号SELR、第一电平的第二选通信号SELG和第一电平的第三选通信号SELB，控制连接于缓存器123与每一像素列1101之间的第一晶体管T1、第二晶体管T2和第三晶体管T3均导通；
其中，所述每一像素列1101包括多个像素单元115，所述多个像素单元115呈列设置，每一像素单元115包括一红色子像素单元、一绿色子像素单元和一蓝色子像素单元，所述红色子像素单元、绿色子像素单元和蓝色子像素单元呈行设置。所述第一晶体管T1对应导通缓存器123与位于一列的红色子像素单元之间的连接，所述第二晶体管T2对应导通缓存器123与位于一列的绿色子像素单元之间的连接，所述第三晶体管T3对应导通缓存器123与位于一列的蓝色子像素单元之间的连接。
步骤S202：所述缓存器123输出预充电电压信号，将所述每一像素列1101内的子像素单元1151均充电至所述预充电电压；其中，所述预充电电压为以所述子像素单元1151同一灰阶亮度对应的正极性像素电压V+与负极性电压V-的均值为中心的预设浮动范围内的任一电压值；
步骤S203：所述控制芯片121输出第一电平的第一选通信号SELR、第二电平的第二选通信号SELG及第二电平的第三选通信号SELB，控制所述第一 晶体管T1导通、第二晶体管T2及第三晶体管T3截止，所述缓存器121输出用于驱动红色子像素单元的数据信号RED，将所述红色子像素单元从所述预充电电压充电至对应的像素电压；
步骤S204：所述控制芯片121输出第二电平的第一选通信号SELR、第一电平的第二选通信号SELG及第二电平的第三选通信号SELB，控制所述第二晶体管T2导通、第一晶体管T1及第三晶体管T3截止，所述缓存器121输出用于驱动绿色子像素单元的数据信号GREEN，将所述绿色子像素单元从所述预充电电压充电至对应的像素电压；
步骤S205：所述控制芯片121输出第二电平的第一选通信号SELR、第二电平的第二选通信号SELG及第一电平的第三选通信号SELB，控制所述第三晶体管T3导通、第一晶体管T1及第二晶体管T2截止，所述缓存器121输出用于驱动蓝色子像素单元的数据信号BLUE，将所述蓝色子像素单元从所述预充电电压充电至对应的像素电压。
在本实施例中，所述预充电电压优选设置为所述子像素单元1151最高灰阶亮度对应的正极性像素电压V+与负极性电压V-的均值，即所述公共电压VCOM。
可以理解，本实施例所述液晶显示面板驱动方法的各步骤的实施还可以参照图2至图5所示装置实施例中的描述，此处不再赘述。
本发明所述的液晶显示装置100及液晶显示面板驱动方法，首先，在通过数据线向各像素单元写入数据之前的充电阶段，通过所述控制芯片121控制所述第一晶体管T1、第二晶体管T2及第三晶体管T3同时导通，将所述子像素单元1151均充电至公共电压VCOM，使得所述液晶显示面板110在切换帧图像时，相邻的两个像素列1101的像素单元115的像素电压极性反转时的最大压差缩小，从而缩减所述液晶显示面板110在切换帧图像时的子像素单元1151充电时间，降低所述液晶显示装置100的功耗。
以上所揭露的仅为本发明的较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (17)

  1. 一种液晶显示面板驱动方法，其中，所述方法包括：
    控制芯片同步输出第一电平的第一选通信号、第一电平的第二选通信号和第一电平的第三选通信号，控制连接于缓存器与每一像素列之间的第一晶体管、第二晶体管和第三晶体管均导通；
    所述缓存器输出预充电电压信号，将所述每一像素列内的子像素单元均充电至所述预充电电压。
  2. 如权利要求1所述的液晶显示面板驱动方法，其中，所述预充电电压为以所述子像素单元同一灰阶亮度对应的正极性像素电压与负极性电压的均值为中心的预设浮动范围内的任一电压值。
  3. 如权利要求2所述的液晶显示面板驱动方法，其中，所述预充电电压为以所述子像素单元最高灰阶亮度对应的正极性像素电压与负极性电压的均值为中心的预设浮动范围内的任一电压值。
  4. 如权利要求3所述的液晶显示面板驱动方法，其中，所述预充电电压为所述子像素单元最高灰阶亮度对应的正极性像素电压与负极性电压的均值。
  5. 如权利要求2所述的液晶显示面板驱动方法，其中，所述将所述每一像素列内的子像素单元均充电至所述预充电电压之后，所述方法还包括：
    所述控制芯片输出第一电平的第一选通信号、第二电平的第二选通信号及第二电平的第三选通信号，控制所述第一晶体管导通、第二晶体管及第三晶体管截止，所述缓存器输出用于驱动红色子像素单元的数据信号，将所述红色子像素单元从所述预充电电压充电至对应的像素电压。
  6. 如权利要求5所述的液晶显示面板驱动方法，其中，所述将所述红色子像素单元充电至对应的像素电压之后，所述方法还包括：
    所述控制芯片输出第二电平的第一选通信号、第一电平的第二选通信号及第二电平的第三选通信号，控制所述第二晶体管导通、第一晶体管及第三晶体管，所述缓存器输出用于驱动绿色子像素单元的数据信号，将所述绿色子像素单元从所述预充电电压充电至对应的像素电压。
  7. 如权利要求6所述的液晶显示面板驱动方法，其中，所述将所述绿色 子像素单元充电至对应的像素电压之后，所述方法还包括：
    所述控制芯片输出第二电平的第一选通信号、第二电平的第二选通信号及第一电平的第三选通信号，控制所述第三晶体管导通、第一晶体管及第二晶体管截止，所述缓存器输出用于驱动蓝色子像素单元的数据信号，将所述蓝色子像素单元从所述预充电电压充电至对应的像素电压。
  8. 一种液晶显示装置，其中，所述液晶显示装置包括液晶显示面板和用于驱动所述液晶显示面板的驱动电路，所述液晶显示面板包括多个像素列，每一像素列内包括多个子像素单元，所述驱动电路包括控制芯片、多个缓存器和多个选通电路，所述控制芯片用于输出第一选通信号、第二选通信号和第三选通信号，所述缓存器用于输出预充电电压信号，每一所述选通电路包括第一晶体管、第二晶体管和第三晶体管，每一所述缓存器通过所述第一晶体管、第二晶体管和第三晶体管与所述像素列内的子像素单元连接，所述控制芯片通过所述第一选通信号、第二选通信号和第三选通信号分别控制所述第一晶体管、第二晶体管和第三晶体管导通，以通过所述缓存器输出的预充电电压信号将所述每一像素列内的子像素单元均充电至所述预充电电压。
  9. 如权利要求8所述的液晶显示装置，其中，所述预充电电压为以所述子像素单元同一灰阶亮度对应的正极性像素电压与负极性电压的均值为中心的预设浮动范围内的任一电压值。
  10. 如权利要求9所述的液晶显示装置，其中，所述预充电电压为以所述子像素单元最高灰阶亮度对应的正极性像素电压与负极性电压的均值为中心的预设浮动范围内的任一电压值。
  11. 如权利要求10所述的液晶显示装置，其中，所述预充电电压为所述子像素单元最高灰阶亮度对应的正极性像素电压与负极性电压的均值。
  12. 如权利要求9所述的液晶显示装置，其中，所述每一像素列内的多个像素单元呈列设置，每一像素单元包括一红色子像素单元、一绿色子像素单元和一蓝色子像素单元，所述红色子像素单元、绿色子像素单元和蓝色子像素单元呈行设置，所述第一晶体管对应导通所述缓存器与位于一列的红色子像素单元之间的连接，所述第二晶体管对应导通所述缓存器与位于一列的绿色子像素单元之间的连接，所述第三晶体管对应导通所述缓存器与位于一列的蓝色子像 素单元之间的连接。
  13. 如权利要求12所述的液晶显示装置，其中，所述控制芯片包括第一端口、第二端口和第三端口，所述第一端口用于输出第一选通信号，所述第二端口用于输出第二选通信号，所述第三端口用于输出第三选通信号，所述晶体管均包括栅极、源极和漏极，所述第一端口与每一所述第一晶体管的栅极连接，所述第二端口与每一所述第二晶体管的栅极连接，所述第三端口与每一所述第三晶体管的栅极连接。
  14. 如权利要求13所述的液晶显示装置，其中，所述缓存器还用于缓存数据信号，每一所述缓存器包括一输出端，所述输出端和与之对应的每一所述选通电路的第一晶体管、第二晶体管和第三晶体管的源极连接，每一所述选通电路的第一晶体管、第二晶体管和第三晶体管的漏极分别和每一所述像素列内的每一列子像素单元连接。
  15. 如权利要求14所述的液晶显示装置，其中，所述第一选通信号、第二选通信号和第三选通信号均由第一电平和第二电平组成，当所述第一选通信号为第一电平、所述第二选通信号及第三选通信号均为第二电平时，所述第一晶体管导通，所述第二晶体管及第三晶体管截止，所述缓存器内缓存的数据信号通过所述第一晶体管传送给位于一列的红色子像素单元，以将所述红色子像素单元从所述预充电电压充电至对应的像素电压。
  16. 如权利要求15所述的液晶显示装置，其中，当所述第二选通信号为第一电平、所述第一选通信号及第三选通信号均为第二电平时，所述第二晶体管导通，所述第一晶体管及第三晶体管均截止，所述缓存器内缓存的数据信号通过所述第二晶体管传送给位于一列的绿色子像素单元，以将所述绿色子像素单元从所述预充电电压充电至对应的像素电压。
  17. 如权利要求15所述的液晶显示装置，其中，当所述第三选通信号为第一电平、所述第一选通信号及第二选通信号均为第二电平时，所述第三晶体管导通，所述第一晶体管及第二晶体管均截止，所述缓存器内缓存的数据信号通过所述第三晶体管传送给位于一列的蓝色子像素单元，以将所述蓝色子像素单元从所述预充电电压充电至对应的像素电压。
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