WO2019104807A1 - 一种增强型场效应晶体管 - Google Patents

一种增强型场效应晶体管 Download PDF

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Publication number
WO2019104807A1
WO2019104807A1 PCT/CN2017/118837 CN2017118837W WO2019104807A1 WO 2019104807 A1 WO2019104807 A1 WO 2019104807A1 CN 2017118837 W CN2017118837 W CN 2017118837W WO 2019104807 A1 WO2019104807 A1 WO 2019104807A1
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Prior art keywords
channel layer
carrier
region
field effect
effect transistor
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PCT/CN2017/118837
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English (en)
French (fr)
Inventor
吕元杰
王元刚
宋旭波
谭鑫
周幸叶
冯志红
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中国电子科技集团公司第十三研究所
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Priority to EP17933333.1A priority Critical patent/EP3690953A4/en
Priority to US16/759,518 priority patent/US11127849B2/en
Publication of WO2019104807A1 publication Critical patent/WO2019104807A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Definitions

  • This solution belongs to the field of semiconductor technology, and in particular relates to an enhanced field effect transistor.
  • FETs Field effect transistors
  • FETs are voltage-controlled semiconductor devices with high input resistance, low noise, low power consumption, large dynamic range, easy integration, no secondary breakdown, and a wide safe working area. Divided into conductive ways, FETs are divided into enhancement FETs and depletion FETs.
  • semiconductor-based enhancement FETs usually use an isoplanar channel layer, which is enhanced by a gate under etched trench, ion implantation or capping, but the enhanced FET has a damage to the gate interface. Big.
  • the embodiment of the present invention provides an enhanced field effect transistor to solve the problem that the enhanced FET in the prior art has a large damage to the gate interface.
  • the source electrode and the drain electrode are respectively formed on an upper surface of the channel layer and on opposite sides of the channel layer;
  • a gate electrode formed on an upper surface of the channel layer and located between the source electrode and the drain electrode;
  • the region outside the corresponding region of the gate electrode in the channel layer is provided with a carrier-free region; the carrier-free region has no carriers, and the remaining portion of the channel layer has carriers.
  • the carrier-free region implants dopant ions opposite to a doping type of the channel layer in a channel layer in which the carrier-free region is located, and the dopant ions are neutralized. Carriers in the channel layer where the carrier-free region is located are formed.
  • the no-carrier region is formed by etching a groove in the channel layer.
  • the no-carrier region is provided with a cap layer opposite to a doping type of the channel layer on an upper surface of the channel layer where the carrier-free region is located, the cap layer is doped
  • the impurity concentration is greater than the doping concentration of the channel layer, and carriers in the cap layer and carriers in the channel layer in which the carrier-free region is located are formed.
  • the number of the no-carrier regions is 1 or more.
  • the number of the gate electrodes is one or more.
  • a dielectric layer is disposed between the gate electrode and the channel layer.
  • a region other than the source electrode, the gate electrode, and the drain electrode on the upper surface of the channel layer is provided with a passivation layer.
  • the carrier-free region has a width of 1 nm to 10 ⁇ m.
  • an intrinsic layer is disposed between the substrate and the channel layer.
  • the embodiment of the present embodiment has the beneficial effects that the enhanced field effect transistor provided by the embodiment of the present invention has no carrier region disposed under the gate electrode but is disposed in the channel layer.
  • the region other than the corresponding region does not cause damage to the lower surface of the gate electrode when the carrier-free region is formed.
  • the remaining part of the carrier-free region in the channel layer always has carriers.
  • the enhanced FET provided by the embodiment of the present invention can control the threshold voltage of the device by regulating the width and the number of the carrier-free region, and the opening and closing of the device only needs to control the presence or absence of a small number of carriers in the no-carrier region. The switching speed is fast.
  • FIG. 1 is a schematic structural diagram of an enhanced field effect transistor according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of an enhanced field effect transistor according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of an enhanced field effect transistor according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of an enhanced field effect transistor according to an embodiment of the present disclosure.
  • the enhancement type field effect transistor includes a substrate 101, and a channel layer 102 formed on an upper surface of the substrate 101.
  • the source electrode 103 and the drain electrode 104 are respectively formed on the upper surface of the channel layer 102 and on opposite sides of the channel layer 102.
  • the gate electrode 105 is formed on the upper surface of the channel layer 102. And located between the source electrode 103 and the drain electrode 104.
  • a region other than the corresponding region of the gate electrode 105 in the channel layer 102 is provided with a carrier-free region 106, the carrier-free region 106 has no carriers, and the remaining portion of the channel layer 102 has a current carrying current. child
  • the carrier-free region 106 is not disposed under the gate electrode 105, but is disposed outside the corresponding region of the gate electrode 105 in the channel layer 102 to form no carriers. At the time of the region 106, damage to the lower surface of the gate electrode 105 is not caused. Carriers are not present in the carrierless region 106, and carriers are present in the remaining portion of the channel layer 102.
  • the gate voltage is less than the threshold voltage of the device, the channel layer 102 is non-conductive.
  • the conduction band of the carrier-free region 106 decreases.
  • the conduction band is lowered to Fermi.
  • the carrier-free region 106 forms carriers, the channel layer 102 is turned on, and the device is turned on.
  • the enhancement type FET provided by the embodiment of the present invention can control the threshold voltage of the device by regulating the width and number of the carrier-free region 106, and the device needs to control a small number of carriers in the carrier-free region 106 by turning on and off the device. The presence or absence of the switch is fast.
  • the carrier-free region 106 injects dopant ions opposite to the doping type of the channel layer 102 in the channel layer 102 where the carrier-free region 106 is located.
  • the dopants neutralize the formation of carriers in the channel layer 102 in which the carrier-free region 106 is located.
  • doping ions opposite to the doping type in the channel layer 102 are implanted in the channel layer 102 in which the carrier-free region 106 is located by ion implantation, for example, doping of the channel layer 102.
  • the impurity type is n-type
  • p-type dopant ions are implanted in the channel layer 102 where the carrier-free region 106 is located, so that the implanted dopant ions neutralize the channel layer 102 in which the carrier-free region 106 is located.
  • the carriers are such that carriers are not present in the carrier-free region 106, and carriers are present in the remaining portion of the channel layer 102.
  • the carrier-free region 106 is formed by etching a groove in the channel layer 102.
  • the non-carrier region 106 is formed by etching a recess in the channel layer 102 by a photolithography and etching process.
  • an intrinsic layer 107 is disposed between the substrate 101 and the channel layer 102.
  • the gate voltage is greater than the threshold voltage, carriers are formed in the intrinsic layer 107 corresponding to the region where the carrier-free region 106 is located, thereby turning on the channel layer 102.
  • the carrier-free region 106 is disposed opposite to the doping type of the channel layer 102 by the upper surface of the channel layer 102 where the carrier-free region 106 is located.
  • Cap layer 108, the doping concentration of the cap layer 108 is greater than the doping concentration of the channel layer 102, and the carrier in the cap layer 108 and the channel in which the carrierless region 106 is located Carriers in layer 102 are formed.
  • the upper surface of the channel layer 102 where the carrier-free region 106 is located is provided with a cap layer 108 of a type opposite to that of the channel layer 102.
  • the doping type of the channel layer 102 is n-type.
  • the doping type of the cap layer 108 is p-type, and the doping concentration of the cap layer 108 is greater than the doping concentration of the channel layer 102, thereby enabling holes in the cap layer 108 to completely neutralize the no-carrier region 106.
  • the electrons in the channel layer 102 are such that no carriers are present in the carrier-free region 106, and carriers are present in the remaining portion of the channel layer 102.
  • the number of the no-carrier regions is 1 or more.
  • the number of the no-carrier regions may be one or more, and when there is one no-carrier region, the carrier-free region 106 may be formed by using any of the above methods.
  • the carrier-free region 106 can be formed using any one of the above methods or a combination of a plurality of methods. For example, as shown in FIG. 4, two carrier-free regions 106 are provided in the channel layer, and one carrier-free region 106 is formed by etching a recess in the channel layer 102, and the other carrier-free region 106 is formed.
  • a cap layer 108 opposite to the doping type of the channel layer 102 is formed on the upper surface of the channel layer 102 where the carrier-free region 106 is located.
  • Dielectric layer 109 is disposed between the gate electrode 105 and the channel layer 102.
  • Dielectric layer 109 includes, but is not limited to, an oxide layer, a nitride layer, or a composite layer of oxide and nitride.
  • the upper surface of the channel layer 102 is provided with a passivation layer 110.
  • the channel layer 102 is protected by the passivation layer 110.
  • the gate electrode 105 is one or more.
  • the gate electrode 105 may be one or more, and the gate electrode 105 may adopt various shapes, including but not limited to a straight gate, a T gate, a Y gate, a TT grid, and a V shape. Gate and U-gate.
  • the carrier-free region 106 has a width of 1 nm to 10 ⁇ m.
  • the carrier free region 106 has a width of from 50 nanometers to 800 microns.
  • the threshold voltage of the device can be regulated by adjusting the width and number of carrierless regions 106.
  • the material of the channel layer 102 includes but is not limited to GaN, SiC, GaAs, Si, ZnO, graphene, diamond or Ga 2 O 3
  • the material of the substrate 101 includes but is not limited to SiC, Si, diamond, sapphire.
  • the GaN, the substrate 101 may also be a multilayer composite substrate.

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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

提供一种增强型场效应晶体管，包括：衬底（101）；沟道层（102），形成于衬底（101）的上表面；源电极（103）和漏电极（104），分别形成于沟道层（102）的两侧；栅电极（105），形成于沟道层（102）的上表面；沟道层（102）中栅电极（105）对应区域之外的区域设有无载流子区（106）；无载流子区（106）不存在载流子，沟道层（102）的其余部分存在载流子。无载流子区（106）不是设置在于栅电极（105）下，而是设置在沟道层（102）中栅电极（105）对应区域之外的区域，在形成无载流子区（106）时，不会对栅电极（105）的下表面造成损伤，并且，可以通过调控无载流子区（106）的宽度和数量调控器件的阈值电压，器件开关速度快。

Description

一种增强型场效应晶体管 技术领域
本方案属于半导体技术领域，尤其涉及一种增强型场效应晶体管。
 背景技术
场效应晶体管（FET）属于电压控制型半导体器件，具有输入电阻高、噪声小、功耗低、动态范围大、易于集成、没有二次击穿现象、安全工作区域宽等优点。按照导电方式划分，FET分为增强型FET和耗尽型FET。
目前，基于半导体的增强型FET通常采用等平面沟道层，通过栅极下刻蚀槽、离子注入或设置帽层等方法实现增强型，但是这种增强型FET对栅极界面处的损伤较大。
 技术问题
有鉴于此，本方案实施例提供了一种增强型场效应晶体管，以解决现有技术中增强型FET对栅极界面处的损伤较大的问题。
 技术解决方案
本方案实施例的增强型场效应晶体管，包括：
衬底；
沟道层，形成于所述衬底的上表面；
源电极和漏电极，分别形成于所述沟道层的上表面，且位于所述沟道层的相对两侧；
栅电极，形成于所述沟道层的上表面，且位于所述源电极和所述漏电极之间；
所述沟道层中栅电极对应区域的之外的区域设有无载流子区；所述无载流子区不存在载流子，所述沟道层的其余部分存在载流子。
可选的，所述无载流子区通过在所述无载流子区所在的沟道层中注入与所述沟道层的掺杂类型相反的掺杂离子，所述掺杂离子中和所述无载流子区所在的沟道层中的载流子形成。
可选的，所述无载流子区通过在所述沟道层中刻蚀凹槽形成。
可选的，所述无载流子区通过在所述无载流子区所在的沟道层的上表面设置与所述沟道层的掺杂类型相反的帽层，所述帽层的掺杂浓度大于所述沟道层的掺杂浓度，所述帽层中的载流子中和所述无载流子区所在的沟道层中的载流子形成。
可选的，所述无载流子区的数量为1以上。
可选的，所述栅电极的数量为1个以上。
可选的，所述栅电极与所述沟道层之间设有介质层。
可选的，所述沟道层上表面的所述源电极、所述栅电极和所述漏电极以外的区域设有钝化层。
可选的，所述无载流子区的宽度为1纳米至10微米。
可选的，所述衬底与所述沟道层之间设有本征层。
 有益效果
本方案实施例与现有技术相比存在的有益效果是：本方案实施例提供的增强型场效应晶体管，无载流子区不是设置在栅电极下，而是设置在沟道层中栅电极对应区域的之外的区域，在形成无载流子区时，不会对栅电极的下表面造成损伤。沟道层中的无载流子区的其余部分一直存在载流子，当栅压小于器件的阈值电压时，无载流子区不存在载流子，沟道层不导电，随着栅压正向增加，无载流子区的导带降低，当栅压大于阈值电压时，导带降低至费米能级之下，无载流子区形成载流子，沟道层导通，器件开启。本方案实施例提供的增强型FET，可以通过调控无载流子区的宽度和数量调控器件的阈值电压，并且器件的开启和关断只需控制无载流子区少量载流子的有无，开关速度快。
 附图说明
为了更清楚地说明本方案实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本方案的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本方案实施例提供的增强型场效应晶体管的结构示意图；
图2是本方案实施例提供的增强型场效应晶体管的结构示意图；
图3是本方案实施例提供的增强型场效应晶体管的结构示意图；
图4是本方案实施例提供的增强型场效应晶体管的结构示意图。
 本发明的实施方式
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、技术之类的具体细节，以便透彻理解本方案实施例。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本方案。在其它情况中，省略对众所周知的系统、装置、电路以及方法的详细说明，以免不必要的细节妨碍本方案的描述。
为了说明本方案所述的技术方案，下面通过具体实施例来进行说明。
请参考图1，增强型场效应晶体管包括：衬底101；沟道层102，形成于所述衬底101的上表面。源电极103和漏电极104，分别形成于所述沟道层102的上表面，且位于所述沟道层102的相对两侧；栅电极105，形成于所述沟道层102的上表面，且位于所述源电极103和所述漏电极104之间。所述沟道层102中栅电极105对应区域的之外的区域设有无载流子区106，所述无载流子区106不存在载流子，沟道层102的其余部分存在载流子
本方案实施例提供的增强型FET，无载流子区106不是设置在于栅电极105下，而是设置在沟道层102中栅电极105对应区域的之外的区域，在形成无载流子区106时，不会对栅电极105的下表面造成损伤。无载流子区106中不存在载流子，沟道层102中的其余部分存在载流子。当栅压小于器件的阈值电压时，沟道层102不导电，随着栅压正向增加，无载流子区106的导带降低，当栅压大于阈值电压时，导带降低至费米能级之下，无载流子区106形成载流子，沟道层102导通，器件开启。本方案实施例提供的增强型FET，可以通过调控无载流子区106的宽度和数量调控器件的阈值电压，并且器件的开启和关断只需控制无载流子区106中少量载流子的有无，开关速度快。
可选的，所述无载流子区106通过在所述无载流子区106所在的沟道层102中注入与所述沟道层102的掺杂类型相反的掺杂离子，所述掺杂离子中和所述无载流子区106所在的沟道层102中的载流子形成。
在本方案实施例中，通过离子注入法在无载流子区106所在的沟道层102中注入与沟道层102中的掺杂类型相反的掺杂离子，例如，沟道层102的掺杂类型为n型，则在无载流子区106所在的沟道层102中注入p型掺杂离子，使注入的掺杂离子中和无载流子区106所在的沟道层102中的载流子，从而使无载流子区106不存在载流子，而沟道层102的其余部分存在载流子。
如图2所示，可选的，所述无载流子区106通过在所述沟道层102中刻蚀凹槽形成。
在本方案实施例中，通过光刻和刻蚀工艺在沟道层102中刻蚀凹槽形成无载流子区106。
可选的，衬底101与沟道层102之间设有一层本征层107。当在栅压大于阈值电压使，无载流子区106所在区域对应的的本征层107中形成载流子，从而使沟道层102导通。
如图3所示，可选的，所述无载流子区106通过在所述无载流子区106所在的沟道层102的上表面设置与所述沟道层102的掺杂类型相反的帽层108，所述帽层108的掺杂浓度大于所述沟道层102的掺杂浓度，所述帽层108中的载流子中和所述无载流子区106所在的沟道层102中的载流子形成。
在本方案实施例中，无载流子区106所在的沟道层102的上表面设置与沟道层102掺杂类型相反的帽层108，例如，沟道层102的掺杂类型为n型，则帽层108的掺杂类型为p型，并且帽层108的掺杂浓度大于沟道层102的掺杂浓度，从而使帽层108中的空穴能够完全中和无载流子区106所在的沟道层102中的电子，使无载流子区106不存在载流子，沟道层102的其余部分存在载流子。
可选的，所述无载流子区的数量为1以上。
在本方案实施例中，无载流子区的数量可以为1个也可以为多个，当无载流子区为1个时，可以使用上述任意一种方法形成无载流子区106，当无载流子区106为多个时，可以使用上述任意一种方法或者多种方法的组合形成无载流子区106。例如，如图4所示，沟道层中设有2个无载流子区106，一个无载流子区106通过在沟道层102刻蚀凹槽形成，另一个无载流子区106通过在无载流子区106所在的沟道层102的上表面设置与沟道层102掺杂类型相反的帽层108形成。
可选的所述栅电极105与所述沟道层102之间设有介质层109。介质层109包括但不限于氧化物层、氮化物层或者氧化物和氮化物的复合层。
可选的，所述沟道层102的上表面设有钝化层110。通过钝化层110保护沟道层102。
可选的，所述栅电极105为1个以上。
在本方案实施例中，栅电极105可以为一个也可以为多个，栅电极105可以采用多种形貌，包括但不限于直栅、T型栅、Y型栅、TT型栅、V型栅和U型栅。
可选的，所述无载流子区106的宽度为1纳米至10微米。优选的，无载流子区106的宽度为50纳米至800微米。通过调节无载流子区106的宽度和数量可以调控器件的阈值电压。
可选的，沟道层102的材料包括但不限于GaN、SiC、GaAs、Si、ZnO、石墨烯、金刚石或Ga 2O 3，衬底101的材料包括但不限于SiC、Si、金刚石、蓝宝石、GaN，衬底101还可以为多层复合衬底。
应理解，上述实施例中各步骤的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本方案实施例的实施过程构成任何限定。
以上所述实施例仅用以说明本方案的技术方案，而非对其限制；尽管参照前述实施例对本方案进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本方案各实施例技术方案的精神和范围，均应包含在本方案的保护范围之内。

Claims (10)

  1. 一种增强型场效应晶体管，其特征在于，包括：
    衬底；
    沟道层，形成于所述衬底的上表面；
    源电极和漏电极，分别形成于所述沟道层的上表面，且位于所述沟道层的相对两侧；
    栅电极，形成于所述沟道层的上表面，且位于所述源电极和所述漏电极之间；
    所述沟道层中栅电极对应区域的之外的区域设有无载流子区；所述无载流子区不存在载流子，所述沟道层的其余部分存在载流子。
  2. 如权利要求1所述的增强型场效应晶体管，其特征在于，所述无载流子区通过在所述无载流子区所在的沟道层中注入与所述沟道层的掺杂类型相反的掺杂离子，所述掺杂离子中和所述无载流子区所在的沟道层中的载流子形成。
  3. 如权利要求1所述的增强型场效应晶体管，其特征在于，所述无载流子区通过在所述沟道层中刻蚀凹槽形成。
  4. 如权利要求1所述的增强型场效应晶体管，其特征在于，所述无载流子区通过在所述无载流子区所在的沟道层的上表面设置与所述沟道层的掺杂类型相反的帽层，所述帽层的掺杂浓度大于所述沟道层的掺杂浓度，所述帽层中的载流子中和所述无载流子区所在的沟道层中的载流子形成。
  5. 如权利要求1所述的增强型场效应晶体管，其特征在于，所述无载流子区的数量为1以上。
  6. 如权利要求1所述的增强型场效应晶体管，其特征在于，所述栅电极的数量为1个以上。
  7. 如权利要求1所述的增强型场效应晶体管，其特征在于，所述栅电极与所述沟道层之间设有介质层。
  8. 如权利要求1所述的增强型场效应晶体管，其特征在于，所述沟道层上表面的所述源电极、所述栅电极和所述漏电极以外的区域设有钝化层。
  9. 如权利要求1所述的增强型场效应晶体管，其特征在于，所述无载流子区的宽度为1纳米至10微米。
  10. 如权利要求1至9任一项所述的增强型场效应晶体管，其特征在于，所述衬底与所述沟道层之间设有本征层。
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