WO2019100381A1 - 一种nmos型goa电路及显示面板 - Google Patents

一种nmos型goa电路及显示面板 Download PDF

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Publication number
WO2019100381A1
WO2019100381A1 PCT/CN2017/113107 CN2017113107W WO2019100381A1 WO 2019100381 A1 WO2019100381 A1 WO 2019100381A1 CN 2017113107 W CN2017113107 W CN 2017113107W WO 2019100381 A1 WO2019100381 A1 WO 2019100381A1
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Prior art keywords
thin film
film transistor
signal
circuit
goa
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PCT/CN2017/113107
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English (en)
French (fr)
Inventor
洪光辉
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武汉华星光电技术有限公司
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Priority to US15/745,109 priority Critical patent/US10672356B2/en
Publication of WO2019100381A1 publication Critical patent/WO2019100381A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an NMOS type GOA circuit and a display panel.
  • the GOA (Gate Driver on Array) circuit is a circuit for realizing the progressive scanning of the display panel.
  • the driving circuit commonly used in the display panel includes a CMOS type GOA circuit and an NMOS type GOA circuit, and the CMOS type GOA circuit includes NTFT (N-channel thin film transistor) device and PTFT (P-channel thin film transistor) device; and NMOS type GOA circuit includes only NTFT device.
  • the GOA control signal line in the NMOS display panel is directly connected to the first-stage GOA unit through the WOA trace, and the GOA control signal line needs to pass through a large RC circuit (Resistance-Capacitance Circuits, or phase shift circuit, or RC filter).
  • RC circuit Resistance-Capacitance Circuits, or phase shift circuit, or RC filter
  • the control signal on the GOA control signal line will have a delay condition, especially an AC signal such as a CK signal (clock signal), so the control of the last stage GOA unit is accessed.
  • the signal has a certain degree of delay compared to the access to the first stage GOA unit, including the CK signal, the GAS signal (global control signal), and the like.
  • FIG. 1 shows a GOA unit in the conventional NMOS type GOA circuit, which is controlled by the Q point potential control thin film transistor NT1, thereby outputting a CK signal to a Gate signal (gate control signal).
  • the output waveform delay state of the first-stage GOA unit on the same side and the last-stage GOA unit connected to the first-stage GOA unit are inconsistent. That is, the output signal of the first stage GOA unit has a small degree of delay, and the output signal of the last stage GOA unit has a large degree of delay.
  • CK_1 is a clock signal waveform diagram of the first-stage GOA unit
  • CK_3 is a clock signal waveform diagram of the next-stage GOA unit cascaded with the first-stage GOA unit, and it can be seen that the adjacent The clock signal between the two cascaded GOA units is delayed
  • Gate_1 is the gate control signal waveform output of the first-stage GOA unit
  • Gate_M-1 is the last-level GOA unit connected to the first-stage GOA unit. It can be seen that there is a delay in the gate control signal output by the last stage GOA unit.
  • ⁇ Va is lower panel AA display region (effective display area) (i.e., Level 1 GOA units corresponding portion) of the feedthrough voltage, ⁇ Vb region AA of the display panel (i.e., the first-stage unit 1 GOA
  • the feed-through voltage of the upper part of the corresponding part of the last stage GOA unit is connected. It can be seen from Fig. 3 that the feed-through voltages at the upper and lower ends of the AA area are significantly inconsistent. The feedthrough voltages of the upper and lower parts of the NMOS display panel are inconsistent, resulting in poor uniformity of the upper and lower parts of the NMOS display panel.
  • the present invention provides an NMOS type GOA circuit and a display panel, which can ensure that the feedthrough voltage of the AA area of the display panel is uniform, thereby ensuring good scintillation uniformity of the NMOS display panel.
  • the invention provides an NMOS type GOA circuit for use in a liquid crystal display panel, comprising M cascaded GOA units, and the Nth stage GOA unit comprises: a forward and reverse scan control circuit, a node signal control circuit, and a node signal output circuit. , pull-down circuit, output circuit;
  • the forward/reverse scan control circuit is configured to control the GOA circuit to perform forward scan or reverse scan according to a forward scan control signal or a reverse scan control signal;
  • the output circuit includes a first thin film transistor and a second thin film transistor, the node signal output circuit includes a third thin film transistor, and the pull-down circuit includes a fourth thin film transistor;
  • the first end of the second thin film transistor is connected to a high potential signal or connected to the third end of the first thin film transistor, and the second end of the second thin film transistor and the first end of the first thin film transistor Connecting, the third end of the second thin film transistor is connected to the Nth clock signal;
  • a third end of the first thin film transistor is connected to an output end of the forward-reverse scan control circuit, and a low-potential signal is input through a first stabilizing capacitor, and a second end of the first thin film transistor Connected to the first end of the fourth thin film transistor and used as an output end of the Nth stage gate driving signal, and the second end of the fourth thin film transistor is connected to a low potential signal;
  • the node signal control circuit is connected to the third end of the third thin film transistor for outputting a clock signal to the third thin film transistor, and controlling turning on and off of the third thin film transistor;
  • the first end of the third thin film transistor is connected to the high potential signal, and the second end is connected to the third end of the fourth thin film transistor;
  • the high potential signal is a DC signal
  • the first end of the thin film transistor is one of the source and the drain
  • the second end is the other of the source and the drain
  • the third end is Gate.
  • the forward and reverse scan control circuit includes a fifth thin film transistor and a sixth thin film transistor, and the GOA unit further includes a seventh thin film transistor;
  • the first end and the third end of the fifth thin film transistor respectively connect a forward scan control signal and an N-2th gate drive signal, and the second end is connected to the first end of the seventh thin film transistor;
  • the third end of the seventh thin film transistor is connected to the high potential signal, and the second end is connected to the third end of the first thin film transistor;
  • the first end and the third end of the sixth thin film transistor respectively connect a reverse scan control signal and an N+2th gate drive signal, and the second end is connected to the second end of the fifth thin film transistor.
  • the GOA unit further includes a pull-up circuit
  • the pull-up circuit includes an eighth thin film transistor and a ninth thin film transistor, and the pull-down circuit further includes a tenth thin film transistor;
  • the first end of the eighth thin film transistor is connected to the third end of the fourth thin film transistor, and the second end and the third end of the eighth thin film transistor respectively input a low potential signal and a first global control signal;
  • the first end of the ninth thin film transistor is connected to the third end and both are connected to the first global control signal, and the second end is connected to the second end of the first thin film transistor;
  • the first end of the tenth thin film transistor is connected to the second end of the first thin film transistor, and the second end and the third end of the tenth thin film transistor respectively input a low potential signal and a second global control signal.
  • the node signal control circuit comprises an eleventh thin film transistor and a twelfth thin film crystal Body tube
  • the first end of the eleventh thin film transistor and the first end of the twelfth thin film transistor respectively input an N+1th clock signal and an N-1th clock signal, and the eleventh thin film transistor
  • the second end is connected to the second end of the twelfth thin film transistor and the third end of the third thin film transistor, the third end of the eleventh thin film transistor and the third end of the twelfth thin film transistor
  • the terminals respectively access the forward scan control signal and the reverse scan control signal.
  • the GOA unit further includes a reset circuit
  • the reset circuit includes a thirteenth thin film transistor, and a first end of the thirteenth thin film transistor is connected to a third end of the fourth thin film transistor, the The second end of the thirteen thin film transistor is connected to the third end and is connected to the reset signal.
  • the GOA unit further includes a fourteenth thin film transistor and a fifteenth thin film transistor;
  • the first end and the third end of the fourteenth thin film transistor are respectively connected to the first end of the seventh thin film transistor and the second end of the third thin film transistor, and the second end of the fourteenth thin film transistor
  • the terminal is connected to a low potential signal
  • the first end and the third end of the fifteenth thin film transistor are respectively connected to the third end of the fourth thin film transistor and the second end of the sixth thin film transistor, and the second end of the fifteenth thin film transistor
  • the terminal is connected to a low potential signal.
  • the GOA unit further includes a second voltage stabilizing capacitor
  • Both ends of the second voltage stabilizing capacitor are respectively connected to the first end and the second end of the eighth thin film transistor.
  • an RC circuit is connected in series between GOA units of adjacent odd-numbered stages and GOA units of adjacent even-numbered stages.
  • a source of the second thin film transistor is connected to a high potential signal, and a drain is connected to a source of the first thin film transistor.
  • the present invention also provides an NMOS type GOA circuit for use in a liquid crystal display panel comprising M cascaded GOA units, the Nth stage GOA unit comprising: a forward and reverse scan control circuit, a node signal control circuit, and a node signal output circuit , pull-down circuit, output circuit;
  • the forward/reverse scan control circuit is configured to control the GOA circuit to perform forward scan or reverse scan according to a forward scan control signal or a reverse scan control signal;
  • the output circuit includes a first thin film transistor and a second thin film transistor, and the node signal is input
  • the output circuit includes a third thin film transistor, and the pull-down circuit includes a fourth thin film transistor;
  • the first end of the second thin film transistor is connected to a high potential signal or connected to the third end of the first thin film transistor, and the second end of the second thin film transistor and the first end of the first thin film transistor Connecting, the third end of the second thin film transistor is connected to the Nth clock signal;
  • a third end of the first thin film transistor is connected to an output end of the forward and reverse scan control circuit, and a low potential signal is input through a first voltage stabilizing capacitor, and a second end of the first thin film transistor is The first end of the fourth thin film transistor is connected and serves as an output end of the Nth stage gate driving signal, and the second end of the fourth thin film transistor is connected to the low potential signal;
  • the node signal control circuit is connected to the third end of the third thin film transistor for outputting a clock signal to the third thin film transistor, and controlling turning on and off of the third thin film transistor;
  • the first end of the third thin film transistor is connected to the high potential signal, and the second end is connected to the third end of the fourth thin film transistor;
  • the forward and reverse scan control circuit includes a fifth thin film transistor and a sixth thin film transistor, and the GOA unit further includes a seventh thin film transistor;
  • the first end and the third end of the fifth thin film transistor respectively connect a forward scan control signal and an N-2th gate drive signal, and the second end is connected to the first end of the seventh thin film transistor;
  • the third end of the seventh thin film transistor is connected to the high potential signal, and the second end is connected to the third end of the first thin film transistor;
  • the first end and the third end of the sixth thin film transistor respectively input a reverse scan control signal and an N+2th gate drive signal, and the second end is connected to the second end of the fifth thin film transistor;
  • the high potential signal is a DC signal
  • the first end of the thin film transistor is one of the source and the drain
  • the second end is the other of the source and the drain
  • the third end is Gate.
  • the GOA unit further includes a pull-up circuit
  • the pull-up circuit includes an eighth thin film transistor and a ninth thin film transistor, and the pull-down circuit further includes a tenth thin film transistor;
  • the first end of the eighth thin film transistor is connected to the third end of the fourth thin film transistor, and the second end and the third end of the eighth thin film transistor respectively input a low potential signal and a first global control signal;
  • the first end of the ninth thin film transistor is connected to the third end and both are connected to the first global control signal, and the second end is connected to the second end of the first thin film transistor;
  • the first end of the tenth thin film transistor is connected to the second end of the first thin film transistor, and the second end and the third end of the tenth thin film transistor respectively input a low potential signal and a second global control signal.
  • the node signal control circuit comprises an eleventh thin film transistor and a twelfth thin film transistor;
  • the first end of the eleventh thin film transistor and the first end of the twelfth thin film transistor respectively input an N+1th clock signal and an N-1th clock signal, and the eleventh thin film transistor
  • the second end is connected to the second end of the twelfth thin film transistor and the third end of the third thin film transistor, the third end of the eleventh thin film transistor and the third end of the twelfth thin film transistor
  • the terminals respectively access the forward scan control signal and the reverse scan control signal.
  • the GOA unit further includes a reset circuit
  • the reset circuit includes a thirteenth thin film transistor, and a first end of the thirteenth thin film transistor is connected to a third end of the fourth thin film transistor, the The second end of the thirteen thin film transistor is connected to the third end and is connected to the reset signal.
  • the GOA unit further includes a fourteenth thin film transistor and a fifteenth thin film transistor;
  • the first end and the third end of the fourteenth thin film transistor are respectively connected to the first end of the seventh thin film transistor and the second end of the third thin film transistor, and the second end of the fourteenth thin film transistor
  • the terminal is connected to a low potential signal
  • the first end and the third end of the fifteenth thin film transistor are respectively connected to the third end of the fourth thin film transistor and the second end of the sixth thin film transistor, and the second end of the fifteenth thin film transistor
  • the terminal is connected to a low potential signal.
  • the GOA unit further includes a second voltage stabilizing capacitor
  • Both ends of the second voltage stabilizing capacitor are respectively connected to the first end and the second end of the eighth thin film transistor.
  • an RC circuit is connected in series between GOA units of adjacent odd-numbered stages and GOA units of adjacent even-numbered stages.
  • a source of the second thin film transistor is connected to a high potential signal, and a drain is connected to a source of the first thin film transistor.
  • the present invention also provides a display panel comprising an NMOS type GOA circuit, the NMOS type GOA circuit comprising M cascaded GOA units, the Nth stage GOA unit comprising: a forward and reverse scan control circuit, a node signal control circuit, a node Signal output circuit, pull-down circuit, output circuit;
  • the forward/reverse scan control circuit is configured to control the GOA circuit to perform forward scan or reverse scan according to a forward scan control signal or a reverse scan control signal;
  • the output circuit includes a first thin film transistor and a second thin film transistor, the node signal output circuit includes a third thin film transistor, and the pull-down circuit includes a fourth thin film transistor;
  • the first end of the second thin film transistor is connected to a high potential signal or connected to the third end of the first thin film transistor, and the second end of the second thin film transistor and the first end of the first thin film transistor Connecting, the third end of the second thin film transistor is connected to the Nth clock signal;
  • a third end of the first thin film transistor is connected to an output end of the forward and reverse scan control circuit, and a low potential signal is input through a first voltage stabilizing capacitor, and a second end of the first thin film transistor is The first end of the fourth thin film transistor is connected and serves as an output end of the Nth stage gate driving signal, and the second end of the fourth thin film transistor is connected to the low potential signal;
  • the node signal control circuit is connected to the third end of the third thin film transistor for outputting a clock signal to the third thin film transistor, and controlling turning on and off of the third thin film transistor;
  • the first end of the third thin film transistor is connected to the high potential signal, and the second end is connected to the third end of the fourth thin film transistor;
  • the high potential signal is a DC signal
  • the first end of the thin film transistor is one of the source and the drain
  • the second end is the other of the source and the drain
  • the third end is Gate.
  • the forward and reverse scan control circuit includes a fifth thin film transistor and a sixth thin film transistor, and the GOA unit further includes a seventh thin film transistor;
  • the first end and the third end of the fifth thin film transistor respectively connect a forward scan control signal and an N-2th gate drive signal, and the second end is connected to the first end of the seventh thin film transistor;
  • the third end of the seventh thin film transistor is connected to the high potential signal, and the second end is connected to the third end of the first thin film transistor;
  • the first end and the third end of the sixth thin film transistor respectively receive a reverse scan control signal and The N+2th gate drive signal is coupled to the second end of the fifth thin film transistor.
  • the GOA unit further includes a pull-up circuit
  • the pull-up circuit includes an eighth thin film transistor and a ninth thin film transistor, and the pull-down circuit further includes a tenth thin film transistor;
  • the first end of the eighth thin film transistor is connected to the third end of the fourth thin film transistor, and the second end and the third end of the eighth thin film transistor respectively input a low potential signal and a first global control signal;
  • the first end of the ninth thin film transistor is connected to the third end and both are connected to the first global control signal, and the second end is connected to the second end of the first thin film transistor;
  • the first end of the tenth thin film transistor is connected to the second end of the first thin film transistor, and the second end and the third end of the tenth thin film transistor respectively input a low potential signal and a second global control signal.
  • the present invention has the following beneficial effects: the first thin film transistor is turned on by the Q point potential by adding the second thin film transistor controlled by the Nth clock signal, and the high potential signal is turned on when the first thin film transistor and the second thin film transistor are turned on.
  • the Nth stage gate drive signal is output.
  • the high potential signal is a DC signal, and after the high potential signal passes through the RC circuit between adjacent cascaded GOA units, the delay condition is small, thereby ensuring the output of the upper and lower parts of the NMOS display panel.
  • the delay conditions of the gate drive signals are substantially the same.
  • the first thin film transistor may be turned on by the Q point potential, and the Q point signal may be output to the Nth stage gate drive signal.
  • the Q point signal is a signal directly generated by each stage of the GOA unit, and the Q point is also connected with the first voltage stabilizing capacitor. Therefore, the Q point potential is relatively stable when operating in each level of the GOA unit. The potential, substantially no delay occurs, thereby ensuring that the delay of the gate drive signal outputted by the upper and lower portions of the NMOS display panel is uniform. Therefore, the feedthrough voltage of the AA area of the display panel is consistent, and the NMOS display panel has good flicker uniformity.
  • Figure 1 is a circuit diagram of a GOA unit in the background art provided by the present invention.
  • FIG. 2 is a schematic diagram of signal delay and GOA unit output delay conditions in a display panel based on an NMOS type GOA circuit in the background art provided by the present invention.
  • FIG. 3 is a schematic diagram showing the state of the feedthrough voltage of the upper and lower ends of the AA area in the display panel based on the NMOS type GOA circuit provided by the present invention.
  • FIG. 4 is a circuit diagram of a GOA unit in the first embodiment provided by the present invention.
  • Figure 5 is a circuit diagram of a GOA unit in a second embodiment provided by the present invention.
  • FIG. 6 is a schematic diagram of the arrangement of an NMOS type GOA circuit provided by the present invention in a display panel.
  • FIG. 7 is a schematic diagram showing the unipolar operation timing of the NMOS type GOA circuit provided by the present invention.
  • FIG. 8a is a schematic diagram of signal delay and GOA unit output delay status in a display panel corresponding to an odd-numbered GOA unit in the first embodiment provided by the present invention.
  • FIG. 8b is a schematic diagram of signal delay and GOA unit output delay status in a display panel corresponding to an even-numbered GOA unit in the first embodiment provided by the present invention.
  • FIG. 9a is a schematic diagram of signal delay and GOA unit output delay status in a display panel corresponding to an odd-numbered GOA unit in a second embodiment provided by the present invention.
  • FIG. 9b is a schematic diagram of signal delay and GOA unit output delay status in a display panel corresponding to an even-numbered GOA unit in the second embodiment provided by the present invention.
  • FIG. 10a is a schematic diagram showing the state of the feedthrough voltage of the upper and lower portions of the AA area in the display panel corresponding to the odd-numbered GOA unit according to the present invention.
  • FIG. 10b is a schematic diagram showing the state of the feedthrough voltage of the upper and lower portions of the AA area in the display panel corresponding to the even-numbered GOA unit according to the present invention.
  • FIG. 11 is a schematic view of a display panel provided by the present invention.
  • the present invention provides an NMOS type GOA circuit for use in a liquid crystal display panel.
  • the NMOS type GOA circuit includes M cascaded GOA units, and the Nth stage GOA unit includes The forward/reverse scan control circuit 200, the node signal control circuit 300, the node signal output circuit 400, the pull-down circuit 500, and the output circuit 100.
  • the forward/reverse scan control circuit 200 is configured to control the GOA circuit to perform forward scan or reverse scan according to the forward scan control signal U2D or the reverse scan control signal D2U.
  • the output circuit 100 includes a first thin film transistor NT1 and a second thin film transistor NT2, the node signal output circuit 400 includes a third thin film transistor NT3, and the pull-down circuit 500 includes a fourth thin film transistor NT4.
  • the first end of the second thin film transistor NT2 is connected to the high potential signal VGH, the second end of the second thin film transistor NT2 is connected to the first end of the first thin film transistor NT1, and the third end of the second thin film transistor NT2 is connected to the Nth Strip clock signal CK[N].
  • the third end of the first thin film transistor NT1 is connected to the output end of the forward and reverse scan control circuit 200, and the low voltage signal VGL is connected through the first voltage stabilizing capacitor C1, and the second end and the fourth film of the first thin film transistor NT1 are connected.
  • the first end of the transistor NT4 is connected and serves as an output terminal of the Nth stage gate driving signal G[N], and the second end of the fourth thin film transistor NT4 is connected to the low potential signal VGL.
  • the node signal control circuit 300 is connected to the third terminal of the third thin film transistor NT3 for outputting a clock signal to the third thin film transistor NT3 to control the on and off of the third thin film transistor NT3.
  • the first end of the third thin film transistor NT3 is connected to the high potential signal VGH, and the second end is connected to the third end of the fourth thin film transistor NT4.
  • the high potential signal VGH is a direct current signal
  • the first end of the thin film transistor is one of the source and the drain, and the second end is the other of the source and the drain, the third end Is the gate.
  • the low potential signal VGL is also a direct current signal. All of the thin film transistors in the NMOS type GOA circuit are N-channel thin film transistors.
  • the Q point in FIG. 3 or FIG. 4 is connected to the third end of the first thin film transistor NT1, and the P point is connected to the third end of the fourth thin film transistor NT4.
  • the first end of the second thin film transistor NT2 is connected to the third end of the first thin film transistor NT1.
  • an RC circuit is connected in series between GOA units of adjacent odd-numbered stages and GOA units of adjacent even-numbered stages.
  • the number M of GOA units in an NMOS type GOA circuit is generally an even number
  • the left side of FIG. 6 is an even-numbered GOA unit (from the left side of the IC in FIG. 6 to the second level GOA unit, the fourth stage, respectively.
  • Level GOA unit ..., M-th GOA unit, etc.
  • the right side of Figure 6 is an odd-numbered GOA unit (from the right side of the IC in Figure 6 from bottom to top, respectively, level 1 GOA unit , Level 3 GOA Unit, ..., Level M-1 GOA Units, etc., in which odd-numbered GOA units are cascaded with each other, and even-level GOA units are also cascaded with each other.
  • the clock signal CK and the high potential signal VGH are output to the first-stage GOA unit and the second-stage GOA unit through the IC (i.e., integrated circuit).
  • the forward and reverse scan control circuit 200 includes a fifth thin film transistor NT5 and a sixth thin film transistor NT6, and the GOA unit further includes a seventh thin film transistor NT7.
  • the first end and the third end of the fifth thin film transistor NT5 are respectively connected to the forward scan control signal U2D and the N-2th gate drive signal G[N-2], and the second end and the seventh thin film transistor NT7 Connected at one end.
  • the third end of the seventh thin film transistor NT7 is connected to the high potential signal VGH, and the second end is connected to the third end of the first thin film transistor NT1.
  • the first end and the third end of the sixth thin film transistor NT6 are respectively connected to the reverse scan control signal D2U and the N+2th gate drive signal G[N+2], and the second end and the fifth thin film transistor NT5 Two-terminal connection.
  • the GOA unit further includes a pull-up circuit 600; the pull-up circuit 600 includes an eighth thin film transistor NT8 and a ninth thin film transistor NT9, and the pull-down circuit 500 further includes a tenth thin film transistor NT10.
  • the first end of the eighth thin film transistor NT8 is connected to the third end of the fourth thin film transistor NT4, and the second end and the third end of the eighth thin film transistor NT8 are respectively connected to the low potential signal VGL and the first global control signal GAS1.
  • the first end of the ninth thin film transistor NT9 is connected to the third end and is connected to the first global control signal GAS1, and the second end is connected to the second end of the first thin film transistor NT1.
  • the first end of the tenth thin film transistor NT10 is connected to the second end of the first thin film transistor NT1, and the second end and the third end of the tenth thin film transistor NT10 are respectively connected to the low potential signal VGL and the second global control signal GAS2.
  • the node signal control circuit 300 includes an eleventh thin film transistor NT11 and a twelfth thin film transistor NT12;
  • the first end of the eleventh thin film transistor NT11 and the first end of the twelfth thin film transistor NT12 respectively access the (N+1)th clock signal CK[N+1] and the N-1th clock signal CK[N-1 a second end of the eleventh thin film transistor NT11 and a second end of the twelfth thin film transistor NT12 and a third thin
  • the third end of the film transistor NT3 is connected, and the third end of the eleventh thin film transistor NT11 and the third end of the twelfth thin film transistor NT12 are respectively connected to the forward scan control signal U2D and the reverse scan control signal D2U.
  • the NMOS type GOA circuit has four clock signals: a first clock signal CK[1], a second clock signal CK[2], a third clock signal CK[3], and a fourth clock signal CK[ 4].
  • the Nth clock signal CK[N] is the first clock signal CK[1]
  • the N-1th clock signal CK[N-1] is the fourth clock signal CK[4]
  • the N+th One clock signal CK[N+1] is the second clock signal CK[2].
  • the Nth clock signal CK[N] is the fourth clock signal CK[4]
  • the N-1th clock signal is the third clock signal CK[3]
  • the N+1th clock signal CK[ N+1] is the first clock signal CK[1].
  • the GOA unit further includes a reset circuit 700 including a thirteenth thin film transistor NT13, the first end of the thirteenth thin film transistor NT13 is connected to the third end of the fourth thin film transistor NT4, and the thirteenth thin film transistor NT13 The second end is connected to the third end and is connected to the reset signal Reset.
  • the GOA unit further includes a fourteenth thin film transistor NT14 and a fifteenth thin film transistor NT15.
  • the first end and the third end of the fourteenth thin film transistor NT14 are respectively connected to the first end of the seventh thin film transistor NT7 and the second end of the third thin film transistor NT3, and the second end of the fourteenth thin film transistor NT14 is low. Potential signal VGL.
  • the first end and the third end of the fifteenth thin film transistor NT15 are respectively connected to the third end of the fourth thin film transistor NT4 and the second end of the sixth thin film transistor NT6, and the second end of the fifteenth thin film transistor NT15 is low. Potential signal VGL.
  • the GOA unit further includes a second voltage stabilizing capacitor C2.
  • FIG. 7 shows a timing chart of signals in the NMOS type GOA circuit.
  • the waveform diagram corresponding to Q in FIG. 7 is the waveform diagram of the Q point signal in the GOA unit
  • the waveform diagram corresponding to P is the waveform diagram of the P point signal in the GOA unit.
  • the source of the second thin film transistor NT2 is connected to the high potential signal VGH, and the drain of the second thin film transistor NT2 is connected to the source of the first thin film transistor NT1.
  • the second thin film transistor NT2 controlled by adding a CK signal (ie, the Nth clock signal CK[N]) is used to turn on the first thin film transistor NT1 through the Q point potential.
  • the high potential signal VGH is output to the Nth stage gate driving signal G[N].
  • the high potential signal VGH is a DC signal, and the high potential signal VGH passes through the RC circuit between the adjacent cascaded GOA units, and the delay condition thereof is small, thereby ensuring the gate of the upper and lower portions of the NMOS display panel.
  • the delay conditions of the pole drive signals are basically the same.
  • FIG. 8a shows a signal delay corresponding to the odd-numbered GOA unit of the first embodiment and a GOA unit output delay condition, and the last-level GOA unit connected to the first stage (the last odd-numbered GOA)
  • the gate drive signal Gate_M-1 outputted by the cell has no delay with respect to the gate drive signal Gate_1 outputted by the first-stage GOA cell.
  • FIG. 8b shows a signal delay corresponding to the odd-numbered GOA unit of the first embodiment and a GOA unit output delay condition, and the last-level GOA unit connected to the first stage (the last odd-numbered GOA)
  • the gate drive signal Gate_M-1 outputted by the cell has no delay with respect to the gate drive signal Gate_1 outputted by the first-stage GOA cell.
  • FIG. 8b FIG.
  • FIG. 8b shows a signal delay corresponding to the even-numbered GOA unit of the first embodiment and a GOA unit output delay condition, and the last-stage GOA unit connected to the second stage (the last even-order GOA) The output of the gate drive signal of the cell) is also delayed relative to the gate drive signal output by the second stage GOA cell.
  • the first thin film transistor NT1 can be turned on by the Q point potential, and the Q point signal can be output to the Nth stage gate drive signal G[N].
  • the Q point signal is a signal directly generated by each stage of the GOA unit, and the Q point is also connected with the first voltage stabilizing capacitor C1. Therefore, the Q point potential is stable when operating in each level of the GOA unit. The potential is substantially undelayed, thereby ensuring that the delay of the gate drive signal outputted by the upper and lower portions of the NMOS display panel is uniform.
  • FIG. 9a shows a signal delay corresponding to the odd-numbered GOA unit and a GOA unit output delay condition in the second embodiment, and the last-level GOA unit connected to the first stage (the last odd-numbered stage)
  • the gate drive signal Gate_M-1 outputted by the GOA unit has no delay with respect to the gate drive signal Gate_1 outputted by the first stage GOA unit.
  • FIG. 9b shows a signal delay corresponding to the odd-numbered GOA unit and a GOA unit output delay condition in the second embodiment, and the last-level GOA unit connected to the first stage (the last odd-numbered stage)
  • the gate drive signal Gate_M-1 outputted by the GOA unit has no delay with respect to the gate drive signal Gate_1 outputted by the first stage GOA unit.
  • FIG. 9b shows a signal delay corresponding to the even-numbered GOA unit in the second embodiment and a GOA unit output delay condition, and the last-stage GOA unit of the second-level connection (the last even-numbered stage) The gate drive signal output by the GOA unit) is also delayed with respect to the gate drive signal output from the second stage GOA unit.
  • the delay conditions of the gate driving signals outputted from the upper and lower portions of the NMOS display panel are substantially the same, and the uniformity of the feedthrough voltage of the upper and lower portions of the NMOS display panel can be ensured.
  • the display panel of the NMOS type GOA circuit provided by the present invention is provided.
  • Vpixel in Figures 10a and 10b is the pixel voltage in the upper or lower portion of the AA region.
  • the present invention also provides a display panel, as shown in FIG. 11, which includes the above-described NMOS type GOA circuit.

Abstract

一种NMOS型GOA电路，用于液晶显示面板中，包括M个级联的GOA单元，第N级GOA单元包括：正反向扫描控制电路（200）、节点信号控制电路（300）、节点信号输出电路（400）、下拉电路（500）、输出电路（100）。输出电路（100）包括第一薄膜晶体管（NT1）和第二薄膜晶体管（NT2），第二薄膜晶体管（NT2）的第一端接入高电位信号（VGH）或者与第一薄膜晶体管（NT1）的第三端连接，第二薄膜晶体管（NT2）的第二端与第一薄膜晶体管（NT1）的第一端连接，第二薄膜晶体管（NT2）的第三端接入第N条时钟信号（CK[N]）。可以保证显示面板AA区的馈穿电压一致，从而保证NMOS显示面板具有良好的闪烁均一性。

Description

一种NMOS型GOA电路及显示面板
本申请要求于2017年11月22日提交中国专利局、申请号为201711176115.6、发明名称为“一种NMOS型GOA电路及显示面板”的中国专利申请的优先权，上述专利的全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示技术领域，尤其涉及一种NMOS型GOA电路及显示面板。
背景技术
GOA(Gate Driver on Array，阵列基板行驱动技术)电路，是实现显示面板逐行扫描的电路，现在显示面板中常用的驱动电路包括CMOS型GOA电路和NMOS型GOA电路，CMOS型GOA电路中包括NTFT(N沟道薄膜晶体管)器件和PTFT(P沟道薄膜晶体管)器件；而NMOS型GOA电路中只包括NTFT器件。现在NMOS显示面板中GOA控制信号线通过WOA走线直接接入第一级GOA单元，而GOA控制信号线需要经过很大的RC电路(Resistance-Capacitance Circuits，即相移电路，或称RC滤波器、RC网络)后才能接入最后一级GOA单元。这种情况下，由于要经过很大的RC电路，GOA控制信号线上的控制信号会出现延迟状况，特别是像CK信号(时钟信号)等交流信号，因此接入最后一级GOA单元的控制信号相比于接入第一级GOA单元时会有一定程度的延迟，包括CK信号、GAS信号(全局控制信号)等。此外如图1所示，图1所示的为现有的NMOS型GOA电路中的GOA单元，其是靠Q点电位控制薄膜晶体管NT1打开，从而将CK信号输出Gate信号(栅极控制信号)，即Gate输出的为CK信号的波形，由于存在以上情况下的信号延迟，会造成同侧的第一级GOA单元和与第一级GOA单元连接的最后一级GOA单元输出波形延迟状况不一致，即第一级GOA单元输出信号延迟程度较小，而最后一级GOA单元输出信号延迟程度较大。如图 2所示，CK_1为第一级GOA单元所接入的时钟信号波形图，CK_3为与第一级GOA单元级联的下一级GOA单元所接入的时钟信号波形图，可以看出相邻级联的两个GOA单元之间的时钟信号出现延迟；Gate_1为第一级GOA单元输出的栅极控制信号波形图，Gate_M-1为与第一级GOA单元连接的最后一级GOA单元，可以看出该最后一级GOA单元输出的栅极控制信号出现延迟。
出现这种状况会造成NMOS显示面板(即包含NMOS型GOA电路的显示面板)上下部分馈穿电压不一致。如图3所示，ΔVa为显示面板AA区(有效显示区)下部(即第1级GOA单元对应的部分)的馈穿电压，ΔVb为显示面板AA区(即与第1级GOA单元连接的最后一级GOA单元对应的部分)上部的馈穿电压，从图3中可以看出AA区上下两端的馈穿电压明显不一致。NMOS显示面板上下部分的馈穿电压不一致，最终导致NMOS显示面板上下部分闪烁均一性较差。
发明内容
为解决上述技术问题，本发明提供一种NMOS型GOA电路及显示面板，可以保证显示面板AA区的馈穿电压一致，从而保证NMOS显示面板具有良好的闪烁均一性。
本发明提供的一种NMOS型GOA电路，用于液晶显示面板中，包括M个级联的GOA单元，第N级GOA单元包括：正反向扫描控制电路、节点信号控制电路、节点信号输出电路、下拉电路、输出电路；
所述正反向扫描控制电路，用于根据正向扫描控制信号或反向扫描控制信号控制GOA电路进行正向扫描或反向扫描；
所述输出电路包括第一薄膜晶体管和第二薄膜晶体管，所述节点信号输出电路包括第三薄膜晶体管，所述下拉电路包括第四薄膜晶体管；
所述第二薄膜晶体管的第一端接入高电位信号或者与所述第一薄膜晶体管的第三端连接，所述第二薄膜晶体管的第二端与所述第一薄膜晶体管的第一端连接，所述第二薄膜晶体管的第三端接入第N条时钟信号；
所述第一薄膜晶体管的第三端与所述正反向扫描控制电路的输出端连接以及通过第一稳压电容接入低电位信号，且所述第一薄膜晶体管的第二端 与所述第四薄膜晶体管的第一端连接并作为第N级栅极驱动信号的输出端，所述第四薄膜晶体管的第二端接入低电位信号；
所述节点信号控制电路，与所述第三薄膜晶体管的第三端连接，用于输出时钟信号至所述第三薄膜晶体管，控制所述第三薄膜晶体管的导通与关断；
所述第三薄膜晶体管的第一端接入高电位信号，第二端与所述第四薄膜晶体管的第三端连接；
其中，M≥N≥1，高电位信号为直流信号，且薄膜晶体管的第一端为源极和漏极中的一个，第二端为源极和漏极中的另一个，第三端为栅极。
优选地，所述正反向扫描控制电路包括第五薄膜晶体管和第六薄膜晶体管，所述GOA单元还包括第七薄膜晶体管；
所述第五薄膜晶体管的第一端和第三端分别接入正向扫描控制信号和第N-2级栅极驱动信号，第二端与所述第七薄膜晶体管的第一端连接；
所述第七薄膜晶体管的第三端接入高电位信号，第二端与所述第一薄膜晶体管的第三端连接；
所述第六薄膜晶体管的第一端和第三端分别接入反向扫描控制信号和第N+2级栅极驱动信号，第二端与所述第五薄膜晶体管的第二端连接。
优选地，所述GOA单元还包括上拉电路；
所述上拉电路包括第八薄膜晶体管和第九薄膜晶体管，所述下拉电路还包括第十薄膜晶体管；
所述第八薄膜晶体管的第一端与所述第四薄膜晶体管的第三端连接，所述第八薄膜晶体管的第二端和第三端分别接入低电位信号和第一全局控制信号；
所述第九薄膜晶体管的第一端与第三端连接且均接入第一全局控制信号，第二端与所述第一薄膜晶体管的第二端连接；
所述第十薄膜晶体管的第一端与所述第一薄膜晶体管的第二端连接，所述第十薄膜晶体管的第二端和第三端分别接入低电位信号和第二全局控制信号。
优选地，所述节点信号控制电路包括第十一薄膜晶体管和第十二薄膜晶 体管；
所述第十一薄膜晶体管的第一端和所述第十二薄膜晶体管的第一端分别接入第N+1条时钟信号和第N-1条时钟信号，所述第十一薄膜晶体管的第二端与所述第十二薄膜晶体管的第二端以及所述第三薄膜晶体管的第三端连接，所述第十一薄膜晶体管的第三端和所述第十二薄膜晶体管的第三端分别接入正向扫描控制信号和反向扫描控制信号。
优选地，所述GOA单元还包括复位电路，所述复位电路包括第十三薄膜晶体管，所述第十三薄膜晶体管的第一端与所述第四薄膜晶体管的第三端连接，所述第十三薄膜晶体管的第二端与第三端连接且接入复位信号。
优选地，所述GOA单元还包括第十四薄膜晶体管和第十五薄膜晶体管；
所述第十四薄膜晶体管的第一端和第三端分别与所述第七薄膜晶体管的第一端以及所述第三薄膜晶体管的第二端连接，所述第十四薄膜晶体管的第二端接入低电位信号；
所述第十五薄膜晶体管的第一端和第三端分别与所述第四薄膜晶体管的第三端以及所述第六薄膜晶体管的第二端连接，所述第十五薄膜晶体管的第二端接入低电位信号。
优选地，所述GOA单元还包括第二稳压电容；
所述第二稳压电容的两端分别与所述第八薄膜晶体管的第一端和第二端连接。
优选地，相邻奇数级的GOA单元之间以及相邻偶数级的GOA单元之间串联有RC电路。
优选地，所述第二薄膜晶体管的源极接入高电位信号，漏极与所述第一薄膜晶体管的源极连接。
本发明还提供一种NMOS型GOA电路，用于液晶显示面板中，包括M个级联的GOA单元，第N级GOA单元包括：正反向扫描控制电路、节点信号控制电路、节点信号输出电路、下拉电路、输出电路；
所述正反向扫描控制电路，用于根据正向扫描控制信号或反向扫描控制信号控制GOA电路进行正向扫描或反向扫描；
所述输出电路包括第一薄膜晶体管和第二薄膜晶体管，所述节点信号输 出电路包括第三薄膜晶体管，所述下拉电路包括第四薄膜晶体管；
所述第二薄膜晶体管的第一端接入高电位信号或者与所述第一薄膜晶体管的第三端连接，所述第二薄膜晶体管的第二端与所述第一薄膜晶体管的第一端连接，所述第二薄膜晶体管的第三端接入第N条时钟信号；
所述第一薄膜晶体管的第三端与所述正反向扫描控制电路的输出端连接以及通过第一稳压电容接入低电位信号，且所述第一薄膜晶体管的第二端与所述第四薄膜晶体管的第一端连接并作为第N级栅极驱动信号的输出端，所述第四薄膜晶体管的第二端接入低电位信号；
所述节点信号控制电路，与所述第三薄膜晶体管的第三端连接，用于输出时钟信号至所述第三薄膜晶体管，控制所述第三薄膜晶体管的导通与关断；
所述第三薄膜晶体管的第一端接入高电位信号，第二端与所述第四薄膜晶体管的第三端连接；
所述正反向扫描控制电路包括第五薄膜晶体管和第六薄膜晶体管，所述GOA单元还包括第七薄膜晶体管；
所述第五薄膜晶体管的第一端和第三端分别接入正向扫描控制信号和第N-2级栅极驱动信号，第二端与所述第七薄膜晶体管的第一端连接；
所述第七薄膜晶体管的第三端接入高电位信号，第二端与所述第一薄膜晶体管的第三端连接；
所述第六薄膜晶体管的第一端和第三端分别接入反向扫描控制信号和第N+2级栅极驱动信号，第二端与所述第五薄膜晶体管的第二端连接；
其中，M≥N≥1，高电位信号为直流信号，且薄膜晶体管的第一端为源极和漏极中的一个，第二端为源极和漏极中的另一个，第三端为栅极。
优选地，所述GOA单元还包括上拉电路；
所述上拉电路包括第八薄膜晶体管和第九薄膜晶体管，所述下拉电路还包括第十薄膜晶体管；
所述第八薄膜晶体管的第一端与所述第四薄膜晶体管的第三端连接，所述第八薄膜晶体管的第二端和第三端分别接入低电位信号和第一全局控制信号；
所述第九薄膜晶体管的第一端与第三端连接且均接入第一全局控制信号，第二端与所述第一薄膜晶体管的第二端连接；
所述第十薄膜晶体管的第一端与所述第一薄膜晶体管的第二端连接，所述第十薄膜晶体管的第二端和第三端分别接入低电位信号和第二全局控制信号。
优选地，所述节点信号控制电路包括第十一薄膜晶体管和第十二薄膜晶体管；
所述第十一薄膜晶体管的第一端和所述第十二薄膜晶体管的第一端分别接入第N+1条时钟信号和第N-1条时钟信号，所述第十一薄膜晶体管的第二端与所述第十二薄膜晶体管的第二端以及所述第三薄膜晶体管的第三端连接，所述第十一薄膜晶体管的第三端和所述第十二薄膜晶体管的第三端分别接入正向扫描控制信号和反向扫描控制信号。
优选地，所述GOA单元还包括复位电路，所述复位电路包括第十三薄膜晶体管，所述第十三薄膜晶体管的第一端与所述第四薄膜晶体管的第三端连接，所述第十三薄膜晶体管的第二端与第三端连接且接入复位信号。
优选地，所述GOA单元还包括第十四薄膜晶体管和第十五薄膜晶体管；
所述第十四薄膜晶体管的第一端和第三端分别与所述第七薄膜晶体管的第一端以及所述第三薄膜晶体管的第二端连接，所述第十四薄膜晶体管的第二端接入低电位信号；
所述第十五薄膜晶体管的第一端和第三端分别与所述第四薄膜晶体管的第三端以及所述第六薄膜晶体管的第二端连接，所述第十五薄膜晶体管的第二端接入低电位信号。
优选地，所述GOA单元还包括第二稳压电容；
所述第二稳压电容的两端分别与所述第八薄膜晶体管的第一端和第二端连接。
优选地，相邻奇数级的GOA单元之间以及相邻偶数级的GOA单元之间串联有RC电路。
优选地，所述第二薄膜晶体管的源极接入高电位信号，漏极与所述第一薄膜晶体管的源极连接。
本发明还提供一种显示面板，包括NMOS型GOA电路，所述NMOS型GOA电路包括M个级联的GOA单元，第N级GOA单元包括：正反向扫描控制电路、节点信号控制电路、节点信号输出电路、下拉电路、输出电路；
所述正反向扫描控制电路，用于根据正向扫描控制信号或反向扫描控制信号控制GOA电路进行正向扫描或反向扫描；
所述输出电路包括第一薄膜晶体管和第二薄膜晶体管，所述节点信号输出电路包括第三薄膜晶体管，所述下拉电路包括第四薄膜晶体管；
所述第二薄膜晶体管的第一端接入高电位信号或者与所述第一薄膜晶体管的第三端连接，所述第二薄膜晶体管的第二端与所述第一薄膜晶体管的第一端连接，所述第二薄膜晶体管的第三端接入第N条时钟信号；
所述第一薄膜晶体管的第三端与所述正反向扫描控制电路的输出端连接以及通过第一稳压电容接入低电位信号，且所述第一薄膜晶体管的第二端与所述第四薄膜晶体管的第一端连接并作为第N级栅极驱动信号的输出端，所述第四薄膜晶体管的第二端接入低电位信号；
所述节点信号控制电路，与所述第三薄膜晶体管的第三端连接，用于输出时钟信号至所述第三薄膜晶体管，控制所述第三薄膜晶体管的导通与关断；
所述第三薄膜晶体管的第一端接入高电位信号，第二端与所述第四薄膜晶体管的第三端连接；
其中，M≥N≥1，高电位信号为直流信号，且薄膜晶体管的第一端为源极和漏极中的一个，第二端为源极和漏极中的另一个，第三端为栅极。
优选地，所述正反向扫描控制电路包括第五薄膜晶体管和第六薄膜晶体管，所述GOA单元还包括第七薄膜晶体管；
所述第五薄膜晶体管的第一端和第三端分别接入正向扫描控制信号和第N-2级栅极驱动信号，第二端与所述第七薄膜晶体管的第一端连接；
所述第七薄膜晶体管的第三端接入高电位信号，第二端与所述第一薄膜晶体管的第三端连接；
所述第六薄膜晶体管的第一端和第三端分别接入反向扫描控制信号和 第N+2级栅极驱动信号，第二端与所述第五薄膜晶体管的第二端连接。
优选地，所述GOA单元还包括上拉电路；
所述上拉电路包括第八薄膜晶体管和第九薄膜晶体管，所述下拉电路还包括第十薄膜晶体管；
所述第八薄膜晶体管的第一端与所述第四薄膜晶体管的第三端连接，所述第八薄膜晶体管的第二端和第三端分别接入低电位信号和第一全局控制信号；
所述第九薄膜晶体管的第一端与第三端连接且均接入第一全局控制信号，第二端与所述第一薄膜晶体管的第二端连接；
所述第十薄膜晶体管的第一端与所述第一薄膜晶体管的第二端连接，所述第十薄膜晶体管的第二端和第三端分别接入低电位信号和第二全局控制信号。
实施本发明，具有如下有益效果：通过增加第N条时钟信号控制的第二薄膜晶体管，通过Q点电位打开第一薄膜晶体管，当第一薄膜晶体管和第二薄膜晶体管打开时，将高电位信号输出第N级栅极驱动信号。相对于第N条时钟信号而言，高电位信号是直流信号，高电位信号经过相邻级联的GOA单元之间的RC电路后，其延迟状况较小，从而保证NMOS显示面板上下部分输出的栅极驱动信号的延迟状况基本一致。或者，可以通过Q点电位打开第一薄膜晶体管，并将Q点信号输出第N级栅极驱动信号。相对于CK信号而言，Q点信号是每级GOA单元直接产生的信号，且Q点还连接有第一稳压电容，因此，Q点电位在每级GOA单元工作时，是一个比较稳定的电位，基本上没有延迟的状况发生，从而保证NMOS显示面板上下部分输出的栅极驱动信号的延迟状况基板一致。从而可以保证显示面板AA区的馈穿电压一致，保证了NMOS显示面板具有良好的闪烁均一性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明提供的背景技术中GOA单元的电路图。
图2是本发明提供的背景技术中基于NMOS型GOA电路的显示面板中信号延迟以及GOA单元输出延迟状况示意图。
图3是本发明提供的基于NMOS型GOA电路的显示面板中AA区上下两端馈穿电压状况示意图。
图4是本发明提供的第一实施例中GOA单元的电路图。
图5是本发明提供的第二实施例中GOA单元的电路图。
图6是本发明提供的NMOS型GOA电路在显示面板中的排布示意图。
图7是本发明提供的NMOS型GOA电路单极工作时序示意图。
图8a是本发明提供的第一实施例中奇数级GOA单元对应的显示面板中信号延迟以及GOA单元输出延迟状况示意图。
图8b是本发明提供的第一实施例中偶数级GOA单元对应的显示面板中信号延迟以及GOA单元输出延迟状况示意图。
图9a是本发明提供的第二实施例中奇数级GOA单元对应的显示面板中信号延迟以及GOA单元输出延迟状况示意图。
图9b是本发明提供的第二实施例中偶数级GOA单元对应的显示面板中信号延迟以及GOA单元输出延迟状况示意图。
图10a是本发明提供奇数级GOA单元对应的显示面板中AA区上下部分的馈穿电压状况示意图。
图10b是本发明提供偶数级GOA单元对应的显示面板中AA区上下部分的馈穿电压状况示意图。
图11是本发明提供的显示面板的示意图。
具体实施方式
本发明提供一种NMOS型GOA电路，用于液晶显示面板中，如图4所示，在第一实施例中，该NMOS型GOA电路包括M个级联的GOA单元，第N级GOA单元包括：正反向扫描控制电路200、节点信号控制电路300、节点信号输出电路400、下拉电路500、输出电路100。
正反向扫描控制电路200，用于根据正向扫描控制信号U2D或反向扫描控制信号D2U控制GOA电路进行正向扫描或反向扫描。
输出电路100包括第一薄膜晶体管NT1和第二薄膜晶体管NT2，节点信号输出电路400包括第三薄膜晶体管NT3，下拉电路500包括第四薄膜晶体管NT4。
第二薄膜晶体管NT2的第一端接入高电位信号VGH，第二薄膜晶体管NT2的第二端与第一薄膜晶体管NT1的第一端连接，第二薄膜晶体管NT2的第三端接入第N条时钟信号CK[N]。
第一薄膜晶体管NT1的第三端与正反向扫描控制电路200的输出端连接以及通过第一稳压电容C1接入低电位信号VGL，且第一薄膜晶体管NT1的第二端与第四薄膜晶体管NT4的第一端连接并作为第N级栅极驱动信号G[N]的输出端，第四薄膜晶体管NT4的第二端接入低电位信号VGL。
节点信号控制电路300，与第三薄膜晶体管NT3的第三端连接，用于输出时钟信号至第三薄膜晶体管NT3，控制第三薄膜晶体管NT3的导通与关断。
第三薄膜晶体管NT3的第一端接入高电位信号VGH，第二端与第四薄膜晶体管NT4的第三端连接。
其中，M≥N≥1，高电位信号VGH为直流信号，且薄膜晶体管的第一端为源极和漏极中的一个，第二端为源极和漏极中的另一个，第三端为栅极。优选地，低电位信号VGL也为直流信号。NMOS型GOA电路中所有的薄膜晶体管均为N沟道薄膜晶体管。
图3或图4中的Q点与第一薄膜晶体管NT1的第三端连接，P点与第四薄膜晶体管NT4的第三端连接。
如图5所示，在第二实施例中，上述第二薄膜晶体管NT2的第一端与第一薄膜晶体管NT1的第三端连接。
进一步地于，如图6所示，相邻奇数级的GOA单元之间以及相邻偶数级的GOA单元之间串联有RC电路。例如，NMOS型GOA电路中GOA单元的数量M一般为偶数，图6中的左侧为偶数级的GOA单元(从图6中IC的左侧由下至上分别为第2级GOA单元、第4级GOA单元、......、第M级GOA单元等)，图6中的右侧为奇数级的GOA单元(从图6中IC的右侧由下至上分别为第1级GOA单元、第3级GOA单元、......、第M-1级GOA 单元等)，其中，奇数级的GOA单元相互级联，偶数级的GOA单元也相互级联。从图6中还可以看出，通过IC(即集成电路)输出时钟信号CK和高电位信号VGH至第1级GOA单元和第2级GOA单元。
进一步地，正反向扫描控制电路200包括第五薄膜晶体管NT5和第六薄膜晶体管NT6，GOA单元还包括第七薄膜晶体管NT7。
第五薄膜晶体管NT5的第一端和第三端分别接入正向扫描控制信号U2D和第N-2级栅极驱动信号G[N-2]，第二端与第七薄膜晶体管NT7的第一端连接。
第七薄膜晶体管NT7的第三端接入高电位信号VGH，第二端与第一薄膜晶体管NT1的第三端连接。
第六薄膜晶体管NT6的第一端和第三端分别接入反向扫描控制信号D2U和第N+2级栅极驱动信号G[N+2]，第二端与第五薄膜晶体管NT5的第二端连接。
进一步地，GOA单元还包括上拉电路600；上拉电路600包括第八薄膜晶体管NT8和第九薄膜晶体管NT9，下拉电路500还包括第十薄膜晶体管NT10。
第八薄膜晶体管NT8的第一端与第四薄膜晶体管NT4的第三端连接，第八薄膜晶体管NT8的第二端和第三端分别接入低电位信号VGL和第一全局控制信号GAS1。
第九薄膜晶体管NT9的第一端与第三端连接且均接入第一全局控制信号GAS1，第二端与第一薄膜晶体管NT1的第二端连接。
第十薄膜晶体管NT10的第一端与第一薄膜晶体管NT1的第二端连接，第十薄膜晶体管NT10的第二端和第三端分别接入低电位信号VGL和第二全局控制信号GAS2。
进一步地，节点信号控制电路300包括第十一薄膜晶体管NT11和第十二薄膜晶体管NT12；
第十一薄膜晶体管NT11的第一端和第十二薄膜晶体管NT12的第一端分别接入第N+1条时钟信号CK[N+1]和第N-1条时钟信号CK[N-1]，第十一薄膜晶体管NT11的第二端与第十二薄膜晶体管NT12的第二端以及第三薄 膜晶体管NT3的第三端连接，第十一薄膜晶体管NT11的第三端和第十二薄膜晶体管NT12的第三端分别接入正向扫描控制信号U2D和反向扫描控制信号D2U。
优选地，NMOS型GOA电路中有四条时钟信号：第一条时钟信号CK[1]、第二条时钟信号CK[2]、第三条时钟信号CK[3]、第四条时钟信号CK[4]。当第N条时钟信号CK[N]为第一条时钟信号CK[1]时，则第N-1条时钟信号CK[N-1]为第四条时钟信号CK[4]，第N+1条时钟信号CK[N+1]为第二条时钟信号CK[2]。当第N条时钟信号CK[N]为第四条时钟信号CK[4]时，则第N-1条时钟信号为第三条时钟信号CK[3]，第N+1条时钟信号CK[N+1]为第一条时钟信号CK[1]。
进一步地，GOA单元还包括复位电路700，复位电路700包括第十三薄膜晶体管NT13，第十三薄膜晶体管NT13的第一端与第四薄膜晶体管NT4的第三端连接，第十三薄膜晶体管NT13的第二端与第三端连接且接入复位信号Reset。
进一步地，GOA单元还包括第十四薄膜晶体管NT14和第十五薄膜晶体管NT15。
第十四薄膜晶体管NT14的第一端和第三端分别与第七薄膜晶体管NT7的第一端以及第三薄膜晶体管NT3的第二端连接，第十四薄膜晶体管NT14的第二端接入低电位信号VGL。
第十五薄膜晶体管NT15的第一端和第三端分别与第四薄膜晶体管NT4的第三端以及第六薄膜晶体管NT6的第二端连接，第十五薄膜晶体管NT15的第二端接入低电位信号VGL。
进一步地，GOA单元还包括第二稳压电容C2。
第二稳压电容C2的两端分别与第八薄膜晶体管NT8的第一端和第二端连接。如图7所示，图7示出了NMOS型GOA电路中各信号的时序图。图7中Q对应的波形图即为GOA单元中Q点信号的波形图，P对应的波形图即为GOA单元中P点信号的波形图。
进一步地，第二薄膜晶体管NT2的源极接入高电位信号VGH，第二薄膜晶体管NT2的漏极与第一薄膜晶体管NT1的源极连接。
本发明提供的NMOS GOA电路，在第一实施例中，通过增加一个CK信号(即第N条时钟信号CK[N])控制的第二薄膜晶体管NT2，通过Q点电位打开第一薄膜晶体管NT1，当第一薄膜晶体管NT1和第二薄膜晶体管NT2打开时，将高电位信号VGH输出第N级栅极驱动信号G[N]。相对于CK信号而言，高电位信号VGH是直流信号，高电位信号VGH经过相邻级联的GOA单元之间的RC电路后，其延迟状况较小，从而保证NMOS显示面板上下部分输出的栅极驱动信号的延迟状况基本一致。
如图8a所示，图8a示出了第一实施例的奇数级GOA单元对应的信号延迟以及GOA单元输出延迟状况示意图，与第一级连接的最后一级GOA单元(最后一个奇数级的GOA单元)输出的栅极驱动信号Gate_M-1相对于第一级GOA单元输出的栅极驱动信号Gate_1而言，没有出现延迟。如图8b所示，图8b示出了第一实施例的偶数级GOA单元对应的信号延迟以及GOA单元输出延迟状况示意图，与第二级连接的最后一级GOA单元(最后一个偶数级的GOA单元)输出的栅极驱动信号相对于第二级GOA单元输出的栅极驱动信号而言，也不会出现延迟。
同样，本发明提供的NMOS型GOA电路，在第二实施例中，可以通过Q点电位打开第一薄膜晶体管NT1，并将Q点信号输出第N级栅极驱动信号G[N]。相对于CK信号而言，Q点信号是每级GOA单元直接产生的信号，且Q点还连接有第一稳压电容C1，因此，Q点电位在每级GOA单元工作时，是一个比较稳定的电位，基本上没有延迟的状况发生，从而保证NMOS显示面板上下部分输出的栅极驱动信号的延迟状况基板一致。
如图9a所示，图9a示出了第二实施例中的奇数级GOA单元对应的信号延迟以及GOA单元输出延迟状况示意图，与第一级连接的最后一级GOA单元(最后一个奇数级的GOA单元)输出的栅极驱动信号Gate_M-1相对于第一级GOA单元输出的栅极驱动信号Gate_1而言，没有出现延迟。同样，如图9b所示，图9b示出了第二实施例中的偶数级GOA单元对应的信号延迟以及GOA单元输出延迟状况示意图，第二级连接的最后一级GOA单元(最后一个偶数级的GOA单元)输出的栅极驱动信号相对于第二级GOA单元输出的栅极驱动信号而言，也不会出现延迟。
NMOS显示面板上下部分输出的栅极驱动信号的延迟状况基本一致，可以保证NMOS显示面板上下部分的馈穿电压的一致性，如图10a所示，基于本发明提供的NMOS型GOA电路的显示面板的AA区中，奇数级GOA单元对应的AA区下部馈穿电压ΔVa，与奇数级GOA单元对应AA区的上部馈穿电压ΔVb基本相等，偶数级GOA单元对应的AA区下部馈穿电压ΔVa’，与偶数级GOA单元对应AA区的上部馈穿电压ΔVb’基本相等，最终确保NMOS显示面板上下部分的闪烁均一性较好。图10a和10b中的Vpixel为AA区中上部或下部的像素电压。
本发明还提供一种显示面板，如图11所示，该显示面板包括上述的NMOS型GOA电路。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (20)

  1. 一种NMOS型GOA电路，用于液晶显示面板中，其中，包括M个级联的GOA单元，第N级GOA单元包括：正反向扫描控制电路、节点信号控制电路、节点信号输出电路、下拉电路、输出电路；
    所述正反向扫描控制电路，用于根据正向扫描控制信号或反向扫描控制信号控制GOA电路进行正向扫描或反向扫描；
    所述输出电路包括第一薄膜晶体管和第二薄膜晶体管，所述节点信号输出电路包括第三薄膜晶体管，所述下拉电路包括第四薄膜晶体管；
    所述第二薄膜晶体管的第一端接入高电位信号或者与所述第一薄膜晶体管的第三端连接，所述第二薄膜晶体管的第二端与所述第一薄膜晶体管的第一端连接，所述第二薄膜晶体管的第三端接入第N条时钟信号；
    所述第一薄膜晶体管的第三端与所述正反向扫描控制电路的输出端连接以及通过第一稳压电容接入低电位信号，且所述第一薄膜晶体管的第二端与所述第四薄膜晶体管的第一端连接并作为第N级栅极驱动信号的输出端，所述第四薄膜晶体管的第二端接入低电位信号；
    所述节点信号控制电路，与所述第三薄膜晶体管的第三端连接，用于输出时钟信号至所述第三薄膜晶体管，控制所述第三薄膜晶体管的导通与关断；
    所述第三薄膜晶体管的第一端接入高电位信号，第二端与所述第四薄膜晶体管的第三端连接；
    其中，M≥N≥1，高电位信号为直流信号，且薄膜晶体管的第一端为源极和漏极中的一个，第二端为源极和漏极中的另一个，第三端为栅极。
  2. 根据权利要求1所述的NMOS型GOA电路，其中，所述正反向扫描控制电路包括第五薄膜晶体管和第六薄膜晶体管，所述GOA单元还包括第七薄膜晶体管；
    所述第五薄膜晶体管的第一端和第三端分别接入正向扫描控制信号和第N-2级栅极驱动信号，第二端与所述第七薄膜晶体管的第一端连接；
    所述第七薄膜晶体管的第三端接入高电位信号，第二端与所述第一薄膜 晶体管的第三端连接；
    所述第六薄膜晶体管的第一端和第三端分别接入反向扫描控制信号和第N+2级栅极驱动信号，第二端与所述第五薄膜晶体管的第二端连接。
  3. 根据权利要求1所述的NMOS型GOA电路，其中，所述GOA单元还包括上拉电路；
    所述上拉电路包括第八薄膜晶体管和第九薄膜晶体管，所述下拉电路还包括第十薄膜晶体管；
    所述第八薄膜晶体管的第一端与所述第四薄膜晶体管的第三端连接，所述第八薄膜晶体管的第二端和第三端分别接入低电位信号和第一全局控制信号；
    所述第九薄膜晶体管的第一端与第三端连接且均接入第一全局控制信号，第二端与所述第一薄膜晶体管的第二端连接；
    所述第十薄膜晶体管的第一端与所述第一薄膜晶体管的第二端连接，所述第十薄膜晶体管的第二端和第三端分别接入低电位信号和第二全局控制信号。
  4. 根据权利要求1所述的NMOS型GOA电路，其中，所述节点信号控制电路包括第十一薄膜晶体管和第十二薄膜晶体管；
    所述第十一薄膜晶体管的第一端和所述第十二薄膜晶体管的第一端分别接入第N+1条时钟信号和第N-1条时钟信号，所述第十一薄膜晶体管的第二端与所述第十二薄膜晶体管的第二端以及所述第三薄膜晶体管的第三端连接，所述第十一薄膜晶体管的第三端和所述第十二薄膜晶体管的第三端分别接入正向扫描控制信号和反向扫描控制信号。
  5. 根据权利要求1所述的NMOS型GOA电路，其中，所述GOA单元还包括复位电路，所述复位电路包括第十三薄膜晶体管，所述第十三薄膜晶体管的第一端与所述第四薄膜晶体管的第三端连接，所述第十三薄膜晶体管的第二端与第三端连接且接入复位信号。
  6. 根据权利要求2所述的NMOS型GOA电路，其中，所述GOA单元还包括第十四薄膜晶体管和第十五薄膜晶体管；
    所述第十四薄膜晶体管的第一端和第三端分别与所述第七薄膜晶体管 的第一端以及所述第三薄膜晶体管的第二端连接，所述第十四薄膜晶体管的第二端接入低电位信号；
    所述第十五薄膜晶体管的第一端和第三端分别与所述第四薄膜晶体管的第三端以及所述第六薄膜晶体管的第二端连接，所述第十五薄膜晶体管的第二端接入低电位信号。
  7. 根据权利要求3所述的NMOS型GOA电路，其中，所述GOA单元还包括第二稳压电容；
    所述第二稳压电容的两端分别与所述第八薄膜晶体管的第一端和第二端连接。
  8. 根据权利要求1所述的NMOS型GOA电路，其中，相邻奇数级的GOA单元之间以及相邻偶数级的GOA单元之间串联有RC电路。
  9. 根据权利要求1所述的NMOS型GOA电路，其中，所述第二薄膜晶体管的源极接入高电位信号，漏极与所述第一薄膜晶体管的源极连接。
  10. 一种NMOS型GOA电路，用于液晶显示面板中，其中，包括M个级联的GOA单元，第N级GOA单元包括：正反向扫描控制电路、节点信号控制电路、节点信号输出电路、下拉电路、输出电路；
    所述正反向扫描控制电路，用于根据正向扫描控制信号或反向扫描控制信号控制GOA电路进行正向扫描或反向扫描；
    所述输出电路包括第一薄膜晶体管和第二薄膜晶体管，所述节点信号输出电路包括第三薄膜晶体管，所述下拉电路包括第四薄膜晶体管；
    所述第二薄膜晶体管的第一端接入高电位信号或者与所述第一薄膜晶体管的第三端连接，所述第二薄膜晶体管的第二端与所述第一薄膜晶体管的第一端连接，所述第二薄膜晶体管的第三端接入第N条时钟信号；
    所述第一薄膜晶体管的第三端与所述正反向扫描控制电路的输出端连接以及通过第一稳压电容接入低电位信号，且所述第一薄膜晶体管的第二端与所述第四薄膜晶体管的第一端连接并作为第N级栅极驱动信号的输出端，所述第四薄膜晶体管的第二端接入低电位信号；
    所述节点信号控制电路，与所述第三薄膜晶体管的第三端连接，用于输出时钟信号至所述第三薄膜晶体管，控制所述第三薄膜晶体管的导通与关 断；
    所述第三薄膜晶体管的第一端接入高电位信号，第二端与所述第四薄膜晶体管的第三端连接；
    所述正反向扫描控制电路包括第五薄膜晶体管和第六薄膜晶体管，所述GOA单元还包括第七薄膜晶体管；
    所述第五薄膜晶体管的第一端和第三端分别接入正向扫描控制信号和第N-2级栅极驱动信号，第二端与所述第七薄膜晶体管的第一端连接；
    所述第七薄膜晶体管的第三端接入高电位信号，第二端与所述第一薄膜晶体管的第三端连接；
    所述第六薄膜晶体管的第一端和第三端分别接入反向扫描控制信号和第N+2级栅极驱动信号，第二端与所述第五薄膜晶体管的第二端连接；
    其中，M≥N≥1，高电位信号为直流信号，且薄膜晶体管的第一端为源极和漏极中的一个，第二端为源极和漏极中的另一个，第三端为栅极。
  11. 根据权利要求10所述的NMOS型GOA电路，其中，所述GOA单元还包括上拉电路；
    所述上拉电路包括第八薄膜晶体管和第九薄膜晶体管，所述下拉电路还包括第十薄膜晶体管；
    所述第八薄膜晶体管的第一端与所述第四薄膜晶体管的第三端连接，所述第八薄膜晶体管的第二端和第三端分别接入低电位信号和第一全局控制信号；
    所述第九薄膜晶体管的第一端与第三端连接且均接入第一全局控制信号，第二端与所述第一薄膜晶体管的第二端连接；
    所述第十薄膜晶体管的第一端与所述第一薄膜晶体管的第二端连接，所述第十薄膜晶体管的第二端和第三端分别接入低电位信号和第二全局控制信号。
  12. 根据权利要求10所述的NMOS型GOA电路，其中，所述节点信号控制电路包括第十一薄膜晶体管和第十二薄膜晶体管；
    所述第十一薄膜晶体管的第一端和所述第十二薄膜晶体管的第一端分别接入第N+1条时钟信号和第N-1条时钟信号，所述第十一薄膜晶体管的 第二端与所述第十二薄膜晶体管的第二端以及所述第三薄膜晶体管的第三端连接，所述第十一薄膜晶体管的第三端和所述第十二薄膜晶体管的第三端分别接入正向扫描控制信号和反向扫描控制信号。
  13. 根据权利要求10所述的NMOS型GOA电路，其中，所述GOA单元还包括复位电路，所述复位电路包括第十三薄膜晶体管，所述第十三薄膜晶体管的第一端与所述第四薄膜晶体管的第三端连接，所述第十三薄膜晶体管的第二端与第三端连接且接入复位信号。
  14. 根据权利要求10所述的NMOS型GOA电路，其中，所述GOA单元还包括第十四薄膜晶体管和第十五薄膜晶体管；
    所述第十四薄膜晶体管的第一端和第三端分别与所述第七薄膜晶体管的第一端以及所述第三薄膜晶体管的第二端连接，所述第十四薄膜晶体管的第二端接入低电位信号；
    所述第十五薄膜晶体管的第一端和第三端分别与所述第四薄膜晶体管的第三端以及所述第六薄膜晶体管的第二端连接，所述第十五薄膜晶体管的第二端接入低电位信号。
  15. 根据权利要求11所述的NMOS型GOA电路，其中，所述GOA单元还包括第二稳压电容；
    所述第二稳压电容的两端分别与所述第八薄膜晶体管的第一端和第二端连接。
  16. 根据权利要求10所述的NMOS型GOA电路，其中，相邻奇数级的GOA单元之间以及相邻偶数级的GOA单元之间串联有RC电路。
  17. 根据权利要求10所述的NMOS型GOA电路，其中，所述第二薄膜晶体管的源极接入高电位信号，漏极与所述第一薄膜晶体管的源极连接。
  18. 一种显示面板，其中，包括NMOS型GOA电路，所述NMOS型GOA电路包括M个级联的GOA单元，第N级GOA单元包括：正反向扫描控制电路、节点信号控制电路、节点信号输出电路、下拉电路、输出电路；
    所述正反向扫描控制电路，用于根据正向扫描控制信号或反向扫描控制信号控制GOA电路进行正向扫描或反向扫描；
    所述输出电路包括第一薄膜晶体管和第二薄膜晶体管，所述节点信号输 出电路包括第三薄膜晶体管，所述下拉电路包括第四薄膜晶体管；
    所述第二薄膜晶体管的第一端接入高电位信号或者与所述第一薄膜晶体管的第三端连接，所述第二薄膜晶体管的第二端与所述第一薄膜晶体管的第一端连接，所述第二薄膜晶体管的第三端接入第N条时钟信号；
    所述第一薄膜晶体管的第三端与所述正反向扫描控制电路的输出端连接以及通过第一稳压电容接入低电位信号，且所述第一薄膜晶体管的第二端与所述第四薄膜晶体管的第一端连接并作为第N级栅极驱动信号的输出端，所述第四薄膜晶体管的第二端接入低电位信号；
    所述节点信号控制电路，与所述第三薄膜晶体管的第三端连接，用于输出时钟信号至所述第三薄膜晶体管，控制所述第三薄膜晶体管的导通与关断；
    所述第三薄膜晶体管的第一端接入高电位信号，第二端与所述第四薄膜晶体管的第三端连接；
    其中，M≥N≥1，高电位信号为直流信号，且薄膜晶体管的第一端为源极和漏极中的一个，第二端为源极和漏极中的另一个，第三端为栅极。
  19. 根据权利要求18所述的显示面板，其中，所述正反向扫描控制电路包括第五薄膜晶体管和第六薄膜晶体管，所述GOA单元还包括第七薄膜晶体管；
    所述第五薄膜晶体管的第一端和第三端分别接入正向扫描控制信号和第N-2级栅极驱动信号，第二端与所述第七薄膜晶体管的第一端连接；
    所述第七薄膜晶体管的第三端接入高电位信号，第二端与所述第一薄膜晶体管的第三端连接；
    所述第六薄膜晶体管的第一端和第三端分别接入反向扫描控制信号和第N+2级栅极驱动信号，第二端与所述第五薄膜晶体管的第二端连接。
  20. 根据权利要求18所述的显示面板，其中，所述GOA单元还包括上拉电路；
    所述上拉电路包括第八薄膜晶体管和第九薄膜晶体管，所述下拉电路还包括第十薄膜晶体管；
    所述第八薄膜晶体管的第一端与所述第四薄膜晶体管的第三端连接，所 述第八薄膜晶体管的第二端和第三端分别接入低电位信号和第一全局控制信号；
    所述第九薄膜晶体管的第一端与第三端连接且均接入第一全局控制信号，第二端与所述第一薄膜晶体管的第二端连接；
    所述第十薄膜晶体管的第一端与所述第一薄膜晶体管的第二端连接，所述第十薄膜晶体管的第二端和第三端分别接入低电位信号和第二全局控制信号。
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019152814A (ja) * 2018-03-06 2019-09-12 シャープ株式会社 走査信号線駆動回路、それを備えた表示装置、および、走査信号線の駆動方法
CN109036303A (zh) * 2018-07-24 2018-12-18 武汉华星光电技术有限公司 Goa电路及显示装置
US10839764B2 (en) * 2018-07-24 2020-11-17 Wuhan China Star Optoelectronics Technology Co., Ltd. GOA circuit and display device
CN108630167A (zh) * 2018-07-26 2018-10-09 武汉华星光电技术有限公司 一种goa电路、显示面板及显示装置
CN108735141A (zh) * 2018-07-27 2018-11-02 武汉华星光电技术有限公司 驱动电路
CN109300428A (zh) * 2018-11-28 2019-02-01 武汉华星光电技术有限公司 Goa电路及显示面板
CN109360533B (zh) * 2018-11-28 2020-09-01 武汉华星光电技术有限公司 液晶面板及其栅极驱动电路
CN109559697B (zh) * 2018-12-26 2021-05-07 厦门天马微电子有限公司 一种移位寄存器单元及扫描电路
CN111312177B (zh) * 2020-03-03 2021-04-02 武汉华星光电技术有限公司 Goa驱动电路、显示面板及显示装置
CN111488859B (zh) * 2020-05-06 2023-06-06 武汉华星光电技术有限公司 指纹识别驱动电路
CN111627402B (zh) * 2020-06-01 2021-09-24 武汉华星光电技术有限公司 Goa电路、显示面板以及显示装置
CN111640389B (zh) * 2020-06-09 2021-09-03 武汉华星光电技术有限公司 Goa电路及显示面板
CN111681626A (zh) * 2020-06-24 2020-09-18 武汉华星光电技术有限公司 一种集成栅极驱动电路和显示装置
CN112017584B (zh) * 2020-09-10 2022-07-12 武汉华星光电技术有限公司 移位寄存器单元、栅极驱动电路及显示面板
CN112053655B (zh) * 2020-10-10 2022-07-12 武汉华星光电技术有限公司 Goa电路及显示面板
CN113421528B (zh) * 2021-06-22 2022-08-30 京东方科技集团股份有限公司 驱动电路、驱动方法和显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120162187A1 (en) * 2010-12-24 2012-06-28 Samsung Electronics Co., Ltd. Gate drive circuit and display apparatus having the same
CN105206246A (zh) * 2015-10-31 2015-12-30 武汉华星光电技术有限公司 扫描驱动电路及具有该电路的液晶显示装置
CN105513550A (zh) * 2016-01-04 2016-04-20 武汉华星光电技术有限公司 Goa驱动电路
CN105741742A (zh) * 2016-05-09 2016-07-06 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及其驱动方法
CN106251820A (zh) * 2016-09-23 2016-12-21 南京华东电子信息科技股份有限公司 用于in‑cell触控显示屏的栅极驱动电路
CN106409243A (zh) * 2016-07-13 2017-02-15 武汉华星光电技术有限公司 一种goa驱动电路
CN107221279A (zh) * 2017-05-19 2017-09-29 南京中电熊猫平板显示科技有限公司 一种双向扫描驱动电路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102467890B (zh) * 2010-10-29 2014-05-07 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动装置及液晶显示器
CN103680386B (zh) * 2013-12-18 2016-03-09 深圳市华星光电技术有限公司 用于平板显示的goa电路及显示装置
CN103680451B (zh) * 2013-12-18 2015-12-30 深圳市华星光电技术有限公司 用于液晶显示的goa电路及显示装置
CN103714792B (zh) * 2013-12-20 2015-11-11 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
JP2015187672A (ja) * 2014-03-27 2015-10-29 ソニー株式会社 表示装置、表示装置の駆動方法、及び、電子機器
CN104966500B (zh) * 2015-07-20 2017-05-31 深圳市华星光电技术有限公司 降低功耗的goa电路
CN105405406B (zh) * 2015-12-29 2017-12-22 武汉华星光电技术有限公司 栅极驱动电路和使用栅极驱动电路的显示器
CN105469766B (zh) * 2016-01-04 2019-04-30 武汉华星光电技术有限公司 Goa电路
CN105489189B (zh) * 2016-02-01 2018-09-18 京东方科技集团股份有限公司 栅极驱动单元、栅极驱动电路及其驱动方法和显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120162187A1 (en) * 2010-12-24 2012-06-28 Samsung Electronics Co., Ltd. Gate drive circuit and display apparatus having the same
CN105206246A (zh) * 2015-10-31 2015-12-30 武汉华星光电技术有限公司 扫描驱动电路及具有该电路的液晶显示装置
CN105513550A (zh) * 2016-01-04 2016-04-20 武汉华星光电技术有限公司 Goa驱动电路
CN105741742A (zh) * 2016-05-09 2016-07-06 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及其驱动方法
CN106409243A (zh) * 2016-07-13 2017-02-15 武汉华星光电技术有限公司 一种goa驱动电路
CN106251820A (zh) * 2016-09-23 2016-12-21 南京华东电子信息科技股份有限公司 用于in‑cell触控显示屏的栅极驱动电路
CN107221279A (zh) * 2017-05-19 2017-09-29 南京中电熊猫平板显示科技有限公司 一种双向扫描驱动电路

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