WO2019095507A1 - 一种esd器件串联电阻的电阻结构 - Google Patents

一种esd器件串联电阻的电阻结构 Download PDF

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WO2019095507A1
WO2019095507A1 PCT/CN2017/118588 CN2017118588W WO2019095507A1 WO 2019095507 A1 WO2019095507 A1 WO 2019095507A1 CN 2017118588 W CN2017118588 W CN 2017118588W WO 2019095507 A1 WO2019095507 A1 WO 2019095507A1
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metal layer
resistor
esd device
upper metal
contact
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PCT/CN2017/118588
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English (en)
French (fr)
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李伊珂
李涅
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清华四川能源互联网研究院
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Priority to US16/469,135 priority Critical patent/US11127677B2/en
Publication of WO2019095507A1 publication Critical patent/WO2019095507A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/647—Resistive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H01L28/24—Resistors with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides

Definitions

  • the present invention relates to a resistor structure of an ESD device series resistor, and more particularly to a resistor structure of an ESD series resistor in a semiconductor chip circuit.
  • the main cause of damage to the resistor device is that the resistor is overheated due to excessive instantaneous power.
  • its thickness tends to be relatively thin (for example, in the .18 process, it is about 0.2um to 0.3um thick). Therefore, its heat capacity is limited under the same area. If its area is not large enough, the energy emitted by the ESD current flowing through it will cause it to heat up quickly, causing damage beyond its melting point, thus greatly limiting the layout size of the resistor circuit.
  • the technical problem to be solved by the present invention is to provide a resistor structure of a series resistor of an ESD device capable of greatly reducing the overall size of an ESD device, and to ensure that the series resistance of the ESD device is not damaged when ESD occurs.
  • a resistor structure of a series resistor of an ESD device the polysilicon resistor is divided into N small parts, each small part is connected to the upper metal layer through respective corresponding Contact and Via; each small part is The corresponding Contact and Via and the upper metal layer are connected to form a single unit; the Via and the upper metal layer are made of a metal aluminum material; the Contact is made of a metal aluminum material or an aluminum alloy material; and the N is a natural number approximately equal to 2. .
  • the polysilicon resistors are annular, and the metals on the same equipotential line are connected together for the upper metal layer of the same layer, and are spaced apart on the equipotential lines of the resistor.
  • the upper metal layer includes a first metal layer and a top metal layer, Contact is connected to Via through a first metal layer, and Via is connected to a top metal layer.
  • the edge distance between the contacts is between 4 um and 8 um.
  • the edge distance between the Contacts is 6 um.
  • the planar shape of the upper metal layer is square or rectangular.
  • the beneficial effects of the invention are: utilizing the heat capacity characteristics of the metal aluminum, cleverly utilizing the existing structure, while ensuring the occurrence of ESD, the resistance is not damaged, and the overall size of the circuit of the ESD device is greatly reduced. .
  • FIG. 1 is a schematic cross-sectional view showing a process structure of one embodiment of the present invention.
  • FIG. 2 is a plan view of a top metal plane of the embodiment shown in FIG. 1.
  • FIG. 3 is a ring-mounted polysilicon resistor structure according to an embodiment of the present invention.
  • FIG. 4 is a schematic view showing the comparison structure of the top metal layer on the basis of the polysilicon resistor on the basis of the embodiment shown in FIG. 3.
  • a resistor structure of a series resistor of an ESD device divides the polysilicon resistor 1 into N small portions, each of which is connected to the upper metal layer through respective corresponding Contact 2 and Via 3; each small portion The corresponding Contact and Via and the upper metal layer are connected to form a single unit; the Via and the upper metal layer are made of a metal aluminum material; the Contact is made of a metal aluminum material or an aluminum alloy material; and the N is greater than or equal to 2. Natural number.
  • the heat capacity of metal aluminum is 880 J/(kg ⁇ °C), which is equivalent to 700 J/(kg ⁇ °C) of polysilicon.
  • the thickness of the metal can be as thick as 3 um, and the thickness of the polysilicon is only one tenth of the thickness of the metal. Therefore, under the same area, the heat capacity of the metal is one order of magnitude larger than that of polysilicon. Using this fact, polysilicon and metal can be combined to obtain a suitable resistance and a suitable heat capacity in a relatively small area.
  • the polysilicon resistor is divided into a plurality of small portions by using the existing metal layer, and each small portion is backed by a small piece of metal, that is, an existing aluminum metal layer, through the contact and Via.
  • the polysilicon resistors are annular, and the metals on the same equipotential line are connected together at intervals on the upper metal layer of the same layer. Located on the equipotential line of the resistor.
  • the polysilicon resistor is annular, and in order to maximize the volume of metal that can be utilized, as shown in FIG. 4, the metals on the equipotential lines are connected together. And the metal on different equipotential lines is spaced apart on the equipotential lines of the resistor to form two or more annular upper metals.
  • the upper metal layer comprises a first metal layer 4 and a top metal layer 5, and Contact is connected to Via through the first metal layer. And Via is connected to the top metal layer. It can be set according to the actual situation of the process. The same applies when there are two or more layers of Via or more than three layers of metal.
  • the edge distance between the adjacent ones of the adjacent units is between 4 um and 8 um.
  • the density of the metal setting is as large as possible. However, because Contact will occupy a certain area, too dense metal will lead to larger area requirements. If the density is too sparse, it will cause the poly between the metal and the metal to dissipate heat when it is hot. After calculation, in the specific embodiment, the edge distance between the contacts is set between 4 um and 8 um.
  • the edge distance between the contacts is 6 um.
  • the planar shape of the upper metal layer is a square or a rectangle.
  • the top metal is in the positive direction, but may be arranged in a square or elongated shape.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

一种ESD器件串联电阻的电阻结构，把多晶硅电阻（1）分成N个小部分，每一小部分均通过各自对应的Contact（2）和Via（3）连接到上部金属层（4/5）；每一小部分所对应的Contact（2）和Via（3）及连接到上部金属层构成了一个独立单元；所述Via（3）和上部金属层采用金属铝材料；所述Contact（2）采用金属铝材料或铝合金材料。利用金属铝的热容特性，巧妙利用现有结构，在通过同样的ESD电流而导致发热时，不会导致电阻被损坏，同时，能大大缩小ESD器件所在电路整体尺寸。

Description

一种ESD器件串联电阻的电阻结构 技术领域
本发明涉及一种ESD器件串联电阻的电阻结构，特别是涉及一种半导体芯片电路中的ESD串联电阻的电阻结构。
背景技术
在半导体芯片电路中，有时，我们需要在ESD器件之前串一个10欧姆到200欧姆的ploy(多晶硅)电阻，这个电阻的作用是增加ESD结构对芯片外部噪声的免疫力，在接地噪声和电源噪声的环境中，更不容易使ESD被正偏。由于这个poly电阻被串联在ESD路径中，所以，当ESD发生的时候，会有安培级的电流通过它。因此，为了保证在ESD发生时，电阻不被损坏，这个poly电阻的面积通常需要被设计得相当大，来吸收掉在ESD发生时所发出的热，从而防止电阻器件的损坏。
在ESD发生时，使电阻器件损坏的主要原因是因为瞬间功率过大导致电阻过热。对于poly电阻来说，它的厚度往往比较薄(例如，在.18工艺中，大概是0.2um～0.3um厚)。因此同等面积下它的热容有限。假如它的面积不够大，ESD电流流过它的时候发出的能量会使它快速发热，超过其熔点导致损毁，因此，很大程度上制约了该电阻电路的版图尺寸。
发明内容
本发明要解决的技术问题是提供一种能大大缩小ESD器件所在电路整体尺寸的ESD器件串联电阻的电阻结构，并且能够保证在ESD发生时，ESD器件的串联电阻不被损坏。
本发明采用的技术方案如下：一种ESD器件串联电阻的电阻结构，把多晶硅电阻分成N个小部分，每一小部分均通过各自对应的Contact和Via连接到上部金属层；每一小部分所对应的Contact和Via及连接到上部金属层构成了一个独立单元；所述Via和上部金属层采用金属铝材料；所述Contact采用金属铝材料或铝合金材料；所述N为大约等于2的自然数。
所述多晶硅电阻为圆环状，对于同一层的上部金属层，将位于同一等势线上的金属连接在一起，间隔地位于电阻的等势线上。
所述上部金属层包括第一金属层和顶部金属层，Contact通过第一金属层连接到Via，且Via连接到顶层金属层。
相邻的所述独立单元之间，Contact之间的边缘距离在4um～8um之间。
所述Contact之间的边缘距离为6um。
所述上部金属层的平面形状为正方形或长方形。
与现有技术相比，本发明的有益效果是：利用金属铝的热容特性，巧妙利用现有结构，在保证ESD发生时，电阻不被损坏的同时，大大缩小了ESD器件所在电路整体尺寸。
附图说明
图1为本发明其中一实施例的工艺结构剖面示意图。
图2为图1所示实施例的顶层金属平面示意图。
图3为本发明其中一实施例的环装多晶硅电阻结构。
图4为在图3所示实施例的基础上的顶层金属层在多晶硅电阻基础上的对照结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
本说明书(包括摘要和附图)中公开的任一特征，除非特别叙述，均可被其他等效或者具有类似目的的替代特征加以替换。即，除非特别叙述，每个特征只是一系列等效或类似特征中的一个例子而已。
具体实施例1
如图1所示，一种ESD器件串联电阻的电阻结构，把多晶硅电阻1分成N个小部分，每一小部分均通过各自对应的Contact 2和Via 3连接到上部金属层；每一小部分所对应的Contact和Via及连接到上部金属层构成了一个独立单元；所述Via和上部金属层采用金属铝材料；所述Contact采用金属铝材料或铝合金材料；所述N为大于等于2的自然数。
金属铝的热容880J/(kg·℃)，与多晶硅的相当700J/(kg·℃)。而且在常见的工艺中，金属的厚度可以做到3um厚，而多晶硅厚度仅为金属厚的十分之一。因此相同的面积下，金属的热容比多晶硅大了一个量级。利用这个事实，可以把多晶硅和金属组合在一起，在比较小的面积下，得到合适的电阻和合适的热容。
在本具体实施例中，利用现有的金属层，将多晶硅电阻分为许多小的部分，每一小部分通过Contact和Via背一小块比较厚的金属，也就是现有的铝金属层，利用金属铝的热容特性，巧妙利用现有结构，在通过同样的ESD电流而导致发热时，不会导致电阻被损坏，同时，能大大缩小ESD器件所在电路整体尺寸。
具体实施例2
在具体实施例1的基础上，如图3和图4所示，所述多晶硅电阻为圆环状，对于同一层的上部金属层，将位于同一等势线上的金属连接在一起，间隔地位于电阻的等势线上。在本具体实施例中，如图3所示，多晶硅电阻为圆环状，为了最大可能地增大可以利用的金属的体积，如图4所示，把等势线上的金属连接在一起，并且使不同等势线上的金属间隔地位于电阻的等势线上，形成两个以上圆环状的上部金属。
具体实施例3
在具体实施例1或2的基础上，如图1所示，在本具体实施例中，所述上部金属层包括第一金属层4和顶部金属层5，Contact通过第一金属层连接到Via，且Via连接到顶层金属层。具体可根据实际情况工艺情况进行设置，当有两层以上Via或三层以上金属层时，同样适用。
具体实施例4
在具体实施例1到3之一的基础上，相邻的所述独立单元之间，Contact之间的边缘距离在4um～8um之间。
原则上金属设置的密度是越大越好。然而由于Contact会占据一定的面积，太密的金属会导致面积需求更大。如果密度太稀疏，又会导致金属与金属之间的poly在发热的时候热量无法散去。经过计算，在本具体实施例中，Contact之间的边缘距离设置在4um～8um之间。
具体实施例5
在具体实施例4的基础上，在本具体实施例中，所述Contact之间的边缘距离为6um。
具体实施例6
在具体实施例1或3到5之一的基础上，所述上部金属层的平面形状为正方形或长方形。在图2所示实施例中，顶层金属为正方向，然而也可以设置为正方形或长条形。

Claims (6)

  1. 一种ESD器件串联电阻的电阻结构，其特征在于：把多晶硅电阻分成N个小部分，每一小部分均通过各自对应的Contact和Via连接到上部金属层；每一小部分所对应的Contact和Via及连接到上部金属层构成了一个独立单元；所述Via和上部金属层采用金属铝材料；所述Contact采用金属铝材料或铝合金材料；所述N为大约等于2的自然数。
  2. 根据权利要求1所述的ESD器件串联电阻的电阻结构，其特征在于：所述多晶硅电阻为圆环状，对于同一层的上部金属层，将位于同一等势线上的金属连接在一起，间隔地位于电阻的等势线上。
  3. 根据权利要求1或2所述的ESD器件串联电阻的电阻结构，其特征在于：所述上部金属层包括第一金属层和顶部金属层，Contact通过第一金属层连接到Via，且Via连接到顶层金属层。
  4. 根据权利要求1或2所述的ESD器件串联电阻的电阻结构，其特征在于：相邻的所述独立单元之间，Contact之间的边缘距离在4um～8um之间。
  5. 根据权利要求4所述的ESD器件串联电阻的电阻结构，其特征在于：所述Contact之间的边缘距离为6um。
  6. 根据权利要求1所述的ESD器件串联电阻的电阻结构，其特征在于：所述上部金属层的平面形状为正方形或长方形。
PCT/CN2017/118588 2017-11-20 2017-12-26 一种esd器件串联电阻的电阻结构 WO2019095507A1 (zh)

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CN107731795A (zh) 2018-02-23
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