WO2019090894A1 - 防止面板外围走线发生静电击伤的结构 - Google Patents

防止面板外围走线发生静电击伤的结构 Download PDF

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WO2019090894A1
WO2019090894A1 PCT/CN2017/116279 CN2017116279W WO2019090894A1 WO 2019090894 A1 WO2019090894 A1 WO 2019090894A1 CN 2017116279 W CN2017116279 W CN 2017116279W WO 2019090894 A1 WO2019090894 A1 WO 2019090894A1
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metal
trace
peripheral
metal traces
electrostatic damage
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PCT/CN2017/116279
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English (en)
French (fr)
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王添鸿
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/744,808 priority Critical patent/US20200081304A1/en
Publication of WO2019090894A1 publication Critical patent/WO2019090894A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps

Definitions

  • the present invention relates to the field of liquid crystal displays, and more particularly to a structure for preventing electrostatic damage to wires on the periphery of a panel.
  • LCDs liquid crystal displays
  • LCDs liquid crystal displays
  • notebooks because of their high image quality, power saving, thin body and wide application range.
  • each sub-pixel has a thin film transistor (TFT) whose gate is connected to a horizontal scanning line, a source is connected to a vertical data line, and a drain is connected to a drain.
  • TFT thin film transistor
  • Applying a sufficient voltage on the horizontal scanning line causes all the TFTs on the horizontal scanning line to be turned on.
  • the pixel electrodes on the horizontal scanning line are connected to the data lines in the vertical direction, thereby connecting the data lines.
  • the display signal voltage is written into the pixel, and the transmittance of different liquid crystals is controlled to achieve the effect of controlling the color.
  • the product In the LCD production process, usually due to the yield factor, the product needs to be tested at a specific point in the process to find the existing problems, so as to repair the product to improve the product yield; For detection, it is necessary to energize the GOA circuit and the effective display area (AA) of the panel. It is necessary to set a signal pad around the peripheral wiring of the panel to energize the probe; however, when the panel peripheral wiring is electrostatically discharged (ESD) ), the automatic optical inspection machine (AOI) for panel scanning can not scan the peripheral traces, must use fixed-point photographs or manual inspection, because the location of ESD usually has a lot of randomness, it is difficult to effectively in a short time It is found that the ESD occurrence point or missed detection leads to loss of capacity.
  • ESD electrostatically discharged
  • FIG. 1 it is a schematic diagram of the outer wiring of the existing liquid crystal display panel.
  • a set of HVA pads 1 enters the inside of the panel 5 from the proximal peripheral trace 3
  • another set of HVA pads 2 enters the panel 5 from the lower left side around the long outer trace 4 to the upper right corner.
  • the peripheral traces 3 and 4 are usually only used as the first metal (M1) single-layer metal trace, and there is no ESD protection circuit design, so the peripheral traces 3 and 4 are easier to accumulate static electricity during the process, and then ESD damage occurred across the pad.
  • M1 first metal
  • the present invention provides a structure for preventing electrostatic damage of a peripheral trace of a panel, comprising: a first metal trace made of a first metal layer as a peripheral trace, and a second metal layer a plurality of second metal traces are formed; the plurality of second metal traces are opposite to the first metal traces and are arranged in the order of the traces of the first metal traces, the second metal traces and the first A dielectric layer is disposed between the metal traces and a second dielectric trace is connected between the two adjacent second metal traces; a plurality of capacitors are formed between the plurality of second metal traces and the first metal traces, wherein The plurality of capacitors include at least two capacitors whose capacitance values are not equal.
  • the first metal layer is a gate metal layer.
  • the second metal layer is a source/drain metal layer.
  • the width of the plurality of second metal traces is the same, and the lengths of at least two second metal traces of the plurality of second metal traces are different.
  • the lengths of the second metal traces of each segment are sequentially increased.
  • the dielectric layer is made of amorphous silicon.
  • the first metal trace is covered with an insulating layer.
  • peripheral trace is a peripheral trace of the active LCD.
  • the present invention also provides a structure for preventing electrostatic damage of a peripheral trace of a panel, comprising: a first metal trace made of a first metal layer as a peripheral trace, and a plurality of segments made of a second metal layer a second metal trace; the plurality of second metal traces are opposite to the first metal trace and arranged in a direction along a trace of the first metal trace, between the second metal trace and the first metal trace a dielectric layer is disposed, and two adjacent second metal traces are connected by a dielectric layer; a plurality of capacitors are formed between the plurality of second metal traces and the first metal trace, wherein the plurality of capacitors The capacitor includes at least two capacitors whose capacitance values are not equal;
  • the first metal layer is a gate metal layer
  • the second metal layer is a source/drain metal layer
  • the width of the plurality of second metal traces is the same, and the lengths of the at least two second metal traces of the plurality of second metal traces are different;
  • the lengths of the second metal traces of each segment are sequentially increased.
  • the structure for preventing electrostatic damage on the peripheral trace of the panel of the present invention is used as an ESD protection circuit by adding a metal wire on the current peripheral trace to achieve an antistatic effect; shortening the process detection time, reducing the production cost, and improving Yield.
  • FIG. 1 is a schematic view showing a design of a peripheral wiring of a conventional liquid crystal display panel
  • FIG. 2 is a schematic diagram showing the principle of a structure for preventing electrostatic damage on the outer circumference of the panel according to the present invention
  • FIG. 3 is a schematic diagram of the preferred embodiment of FIG. 2 after the array process is completed.
  • FIG. 2 it is a schematic diagram of a structure of a preferred embodiment of the structure for preventing electrostatic damage on the outer circumference of the panel.
  • FIG. 2 shows the structure before the passivation (PV) process. That is to say, the passivation layer and the subsequent structure are removed.
  • PV passivation
  • the structure for preventing electrostatic damage of the outer peripheral of the panel of the present invention mainly comprises: a first metal trace 10 made of a first metal layer as a peripheral trace, and a plurality of second sections made of a second metal layer Metal trace 20, in a general display panel, the first metal layer may be a gate metal layer formed of a gate metal, and the second metal layer may be a source/drain metal layer formed of a source and drain metal, that is, Both the first metal trace 10 and the second metal trace 20 can be fabricated by an existing process; the plurality of second metal traces 20 are vertically opposed to the first metal trace 10 and along the trace of the first metal trace 10 The direction is sequentially arranged, a dielectric layer 30 is disposed between the second metal trace 20 and the first metal trace 10, and a second dielectric trace 20 is connected between the two adjacent second metal traces 20 through the dielectric layer 30.
  • a metal trace 10, a dielectric layer 30 and two adjacent second metal traces 20 form a TFT structure, and the dielectric layer 30 may be made of a dielectric material such as amorphous silicon, according to a general display panel structure,
  • a metal trace 10 may be covered with an insulating layer; a plurality of second metal walks
  • a plurality of capacitors are formed between the line 20 and the first metal trace 10, wherein at least two capacitors having unequal capacitance values are included in the plurality of capacitors.
  • the two capacitors whose unequal capacitance values are unequal may or may not be adjacent.
  • the plurality of second metal traces 20 includes three segments: a second metal trace 21, a second metal trace 22, and a second metal trace 23, wherein the second metal trace 21 A capacitor C1 is formed between the first metal trace 10, a capacitor C2 is formed between the second metal trace 22 and the first metal trace 10, and a capacitor C3 is formed between the third metal trace 23 and the first metal trace 10.
  • the capacitance values of at least two of the capacitor C1, the capacitor C2, and the capacitor C3 are not equal.
  • the widths of the first metal trace 10 and the second metal trace 20 may be set unchanged, and the second metal trace 20 and the opposite first metal trace 10 are formed as opposite electrodes.
  • the plurality of capacitors C1, C2, and C3 can control the capacitance value by setting the length of each segment of the second metal trace 20. As shown in FIG. 2, the three second metal traces 20 are included, and the lengths H1, H2, and H3 of the second metal traces 20 of each segment can be set to increase sequentially.
  • the structure for preventing electrostatic damage of the peripheral wiring of the panel of the present invention is applicable to all active LCD products, and the peripheral wiring is the GOA circuit of the active LCD and the peripheral routing of the effective display area.
  • the design of the ESD damage line of the novel anti-panel peripheral trace of the present invention comprises a self-capacitance ESD.
  • H1, H2, H3, and H4 represent the length of the trace
  • C1, C2, and C3 respectively represent capacitances formed between the first metal layer and the second metal layer, because The length of the trace is different, so C1 ⁇ C2 ⁇ C3.
  • the capacitor ESD can function after the second metal layer process, that is, the source and drain processes are completed.
  • a small electrostatic voltage V1, V2, V3 accumulates on the second metal layer, and the TFT between V1 and V2 is opened and discharged, and the first metal layer
  • the upper electrostatic voltage V4 also forms a large differential pressure with V1, V2, and V3, thereby forming a static discharge path between the first metal layer, that is, the peripheral trace of the panel and the second metal layer, thereby protecting the normal HVA welding.
  • FIG. 3 it is a schematic diagram of the preferred embodiment of FIG. 2 after the array process is completed.
  • the upper and lower substrates of the display panel are generally bonded by the conductive sealant 40.
  • the second metal trace 21 at the edge and the opposite first metal trace 10 may pass through the conductive.
  • the gold ball 50 of the sealant 40 is turned on, but does not affect the antistatic function between the first metal trace 10 and the remaining second metal trace 20.
  • the principle of action is the same as that shown in FIG. 2, using different lengths H1, H2.
  • the second metal trace 20 forms different capacitors C1 and C2, thereby generating an electrostatic protection function.
  • the structure for preventing electrostatic damage on the outer wiring of the panel only adds a metal layer on the original outer trace, and no new mask is added; and an electrostatic discharge path is made by utilizing the difference in static electricity accumulation between the two metal traces.
  • a capacitor is formed by the second metal layer metal block on the first metal layer of the first metal layer, and a TFT device is combined, and a voltage difference is formed according to the amount of accumulated static electricity to turn on the TFT. Form an electrostatic consumption path to achieve electrostatic protection.
  • the structure for preventing electrostatic damage on the peripheral trace of the panel of the present invention is used as an ESD protection circuit by adding a metal wire on the current peripheral trace to achieve an antistatic effect; shortening the process detection time, reducing the production cost, and improving Yield.

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Abstract

一种防止面板外围走线发生静电击伤的结构，包括：由第一金属层制成的作为外围走线的第一金属走线（10），以及由第二金属层制成的多段第二金属走线（20）；多段第二金属走线与第一金属走线上下相对并且沿第一金属走线的走线方向顺序排列，第二金属走线与第一金属走线之间设有介电层（30）并且相邻两段第二金属走线之间通过介电层连接；对于第二金属走线和相对的第一金属走线作为相对的电极所形成的多个电容（C1、C2、C3），其中至少包括电容值不相等的两个电容。该防止面板外围走线发生静电击伤的结构在当前外围走线上通过增加一层金属线来做ESD防护电路，达到防静电效果；缩短制程检测时间，降低生产成本。

Description

防止面板外围走线发生静电击伤的结构 技术领域
本发明涉及液晶显示器领域，尤其涉及一种防止面板外围走线发生静电击伤的结构。
背景技术
液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
主动式液晶显示器中，每个子像素具有一个薄膜晶体管(TFT)，其栅极(Gate)连接至水平扫描线，源极(Source)连接至垂直方向的数据线，漏极(Drain)则连接至像素电极。在水平扫描线上施加足够的电压，会使得该条水平扫描线上的所有TFT打开，此时该条水平扫描线上的像素电极会与垂直方向上的数据线连通，从而将数据线上的显示信号电压写入像素，控制不同液晶的透光度进而达到控制色彩的效果。
在LCD生产过程中，通常因良率因素考虑，会需要在制程中的特定某个环节对该产品进行检测，找到存在的问题，以便对其进行修复来提升产品良率；若需要对产品进行检测，则需要对面板的GOA电路及有效显示区(AA)等进行通电，需要环绕面板外围走线设置信号焊垫(pad)以便探针通电；然而，当面板外围走线发生静电释放(ESD)，采用自动光学检测机台(AOI)进行面板扫描无法对外围走线进行扫描，必须采用定点拍照或者人工检查，由于ESD发生位置通常情况下存在很多随机性，因此很难有效在短时间内查出ESD发生点位或漏检导致产能损失(loss)。
如图1所示，为现有液晶显示面板外围走线设计示意图。其中，一组HVA焊垫(pad)1从近端的外围走线3进入面板5内部，而另一组HVA焊垫2则从左下侧绕长的外围走线4到右上角后进入面板5内部，从而提供面板5所需检测信号。目前该外围走线3和4通常只做第一层金属(M1)单层金属走线，且无ESD防护电路设计，因此外围走线3和4在制程过程中，较容易积累静电，而后在焊垫跨线处发生ESD击伤。
发明内容
因此，本发明的目的在于提供一种防止面板外围走线发生静电击伤的结构，提供ESD防护电路，预防面板外围走线发生ESD。
为实现上述目的，本发明提供了一种防止面板外围走线发生静电击伤的结构，包括：由第一金属层制成的作为外围走线的第一金属走线，以及由第二金属层制成的多段第二金属走线；所述多段第二金属走线与第一金属走线上下相对并且沿第一金属走线的走线方向顺序排列，所述第二金属走线与第一金属走线之间设有介电层并且相邻两段第二金属走线之间通过介电层连接；所述多段第二金属走线和第一金属走线之间形成多个电容，其中，所述多个电容中至少包括电容值不相等的两个电容。
其中，所述第一金属层为栅极金属层。
其中，所述第二金属层为源漏极金属层。
其中，所述多段第二金属走线的宽度相同，所述多段第二金属走线的至少两段第二金属走线的长度不同。
其中，各段第二金属走线的长度顺序增加。
其中，包括三段第二金属走线。
其中，所述介电层由非晶硅制成。
其中，所述第一金属走线上覆盖有绝缘层。
其中，所述外围走线为主动型LCD的外围走线。
本发明还提供一种防止面板外围走线发生静电击伤的结构，包括：由第一金属层制成的作为外围走线的第一金属走线，以及由第二金属层制成的多段第二金属走线；所述多段第二金属走线与第一金属走线上下相对并且沿第一金属走线的走线方向顺序排列，所述第二金属走线与第一金属走线之间设有介电层并且相邻两段第二金属走线之间通过介电层连接；所述多段第二金属走线和第一金属走线之间形成多个电容，其中，所述多个电容中至少包括电容值不相等的两个电容；
其中，所述第一金属层为栅极金属层；
其中，所述第二金属层为源漏极金属层；
其中，所述多段第二金属走线的宽度相同，所述多段第二金属走线的至少两段第二金属走线的长度不同；
其中，各段第二金属走线的长度顺序增加。
综上，本发明的防止面板外围走线发生静电击伤的结构在当前外围走线上通过增加一层金属线来做ESD防护电路，达到防静电效果；缩短制程检测时间，降低生产成本，提高良率。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有液晶显示面板外围走线设计示意图；
图2为本发明防止面板外围走线发生静电击伤的结构一较佳实施例的原理示意图；
图3为图2所示较佳实施例在阵列制程完成后的示意图。
具体实施方式
参见图2，其为本发明防止面板外围走线发生静电击伤的结构一较佳实施例的原理示意图，为方便显示结构，图2所示为钝化(PV)制程进行前的结构，也就是说去除了钝化层及之后的结构。本发明的防止面板外围走线发生静电击伤的结构，主要包括：由第一金属层制成的作为外围走线的第一金属走线10，以及由第二金属层制成的多段第二金属走线20，在一般的显示面板中，第一金属层可以为由栅极金属形成的栅极金属层，第二金属层可以为由源漏极金属形成的源漏极金属层，也就是第一金属走线10和第二金属走线20都可以通过现有制程制作；所述多段第二金属走线20与第一金属走线10上下相对并且沿第一金属走线10的走线方向顺序排列，所述第二金属走线20与第一金属走线10之间设有介电层30并且相邻两段第二金属走线20之间通过介电层30连接，从而利用第一金属走线10、介电层30和相邻的两段第二金属走线20形成TFT结构，介电层30可以由介电材料如非晶硅制成，根据一般的显示面板结构，第一金属走线10上可以覆盖有绝缘层；多个第二金属走线20和第一金属走线10之间形成多个电容，其中，所述多个电容中至少包括电容值不相等的两个电容。该电容值不相等的两个电容可以相邻也可以不相邻。在该较佳实施例中，所述多段第二金属走线20包括三段：第二金属走线21、第二金属走线22、第二金属走线23，其中，第二金属走线21与第一金属走线10之间形成电容C1、第二金属走线22与第一金属走线10之间形成电容C2、第三金属走线23与第一金属走线10之间形成电容C3，电容C1、电容C2和电容C3中至少有两个电容的电容值不相等。
一般为了简化设计，可以设定第一金属走线10和第二金属走线20的宽度不变，此时对于第二金属走线20和相对的第一金属走线10作为相对的电极所形成的多个电容C1、C2、C3，可以通过设定各段第二金属走线 20的长度来控制电容值。如图2所示，包括三段第二金属走线20，各段第二金属走线20的长度H1、H2、H3可以设定为顺序增加。
本发明的防止面板外围走线发生静电击伤的结构适用于所有主动型LCD的产品，外围走线为主动型LCD的GOA电路及有效显示区的外围走线。
本发明新型防面板外围走线发生ESD击伤线路的设计包含自身电容式ESD。如图2所示，其中H1、H2、H3、H4代表走线长度，H1＜H2＜H3＜H4，C1、C2、C3分别对应代表第一金属层与第二金属层间形成的电容，由于走线长度差异，所以C1<C2<C3。在第二金属层制程也就是源漏极制程完成后，该电容ESD即可起作用。当第一金属层的长走线积累了较大静电电压V4后，第二金属层上积累较小的静电电压V1、V2、V3，则V1与V2间的TFT打开放电，而第一金属层上大静电电压V4也与V1、V2、V3之间形成大压差，从而在第一金属层也就是面板外围走线与第二金属层之间形成静电泄放路径，从而可以保护正常HVA焊垫处跨线或其他位置存在跨线的区域避免发生静电击伤。
参见图3，其为图2所示较佳实施例在阵列制程完成后的示意图。当阵列(Array)段制程完成后，显示面板的上下基板一般会通过导电框胶40进行粘接，此时位于边缘的第二金属走线21和相对的第一金属走线10可能会通过导电框胶40的金球50导通，但是并不影响第一金属走线10和其余第二金属走线20之间形成防静电功能，作用原理与图2所示相同，利用不同长度H1、H2的第二金属走线20形成不同的电容C1、C2，进而产生静电防护功能。
本发明防止面板外围走线发生静电击伤的结构只在原有外围走线上增加一层金属层，且无新增光罩；利用两层金属走线间静电积累差异做一个静电放电路径。本发明中，第二金属层成膜后，通过自身第一金属层上的第二金属层金属块形成一个电容，同时结合TFT器件，则可根据聚集静电量不同形成一个压差来导通TFT，形成一个静电消耗路径，做到静电防护功能。
综上，本发明的防止面板外围走线发生静电击伤的结构在当前外围走线上通过增加一层金属线来做ESD防护电路，达到防静电效果；缩短制程检测时间，降低生产成本，提高良率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (14)

  1. 一种防止面板外围走线发生静电击伤的结构，包括：由第一金属层制成的作为外围走线的第一金属走线，以及由第二金属层制成的多段第二金属走线；所述多段第二金属走线与第一金属走线上下相对并且沿第一金属走线的走线方向顺序排列，所述第二金属走线与第一金属走线之间设有介电层并且相邻两段第二金属走线之间通过介电层连接；所述多段第二金属走线和第一金属走线之间形成多个电容，其中，所述多个电容中至少包括电容值不相等的两个电容。
  2. 如权利要求1所述的防止面板外围走线发生静电击伤的结构，其中，所述第一金属层为栅极金属层。
  3. 如权利要求1所述的防止面板外围走线发生静电击伤的结构，其中，所述第二金属层为源漏极金属层。
  4. 如权利要求1所述的防止面板外围走线发生静电击伤的结构，其中，所述多段第二金属走线的宽度相同，所述多段第二金属走线的至少两段第二金属走线的长度不同。
  5. 如权利要求4所述的防止面板外围走线发生静电击伤的结构，其中，各段第二金属走线的长度顺序增加。
  6. 如权利要求5所述的防止面板外围走线发生静电击伤的结构，其中，包括三段第二金属走线。
  7. 如权利要求1所述的防止面板外围走线发生静电击伤的结构，其中，所述介电层由非晶硅制成。
  8. 如权利要求1所述的防止面板外围走线发生静电击伤的结构，其中，所述第一金属走线上覆盖有绝缘层。
  9. 如权利要求1所述的防止面板外围走线发生静电击伤的结构，其中，所述外围走线为主动型LCD的外围走线。
  10. 一种防止面板外围走线发生静电击伤的结构，包括：由第一金属层制成的作为外围走线的第一金属走线，以及由第二金属层制成的多段第二金属走线；所述多段第二金属走线与第一金属走线上下相对并且沿第一金属走线的走线方向顺序排列，所述第二金属走线与第一金属走线之间设有介电层并且相邻两段第二金属走线之间通过介电层连接；所述多段第二金属走线和第一金属走线之间形成多个电容，其中，所述多个电容中至少包括电容值不相等的两个电容；
    其中，所述第一金属层为栅极金属层；
    其中，所述第二金属层为源漏极金属层；
    其中，所述多段第二金属走线的宽度相同，所述多段第二金属走线的至少两段第二金属走线的长度不同；
    其中，各段第二金属走线的长度顺序增加。
  11. 如权利要求10所述的防止面板外围走线发生静电击伤的结构，其中，包括三段第二金属走线。
  12. 如权利要求10所述的防止面板外围走线发生静电击伤的结构，其中，所述介电层由非晶硅制成。
  13. 如权利要求10所述的防止面板外围走线发生静电击伤的结构，其中，所述第一金属走线上覆盖有绝缘层。
  14. 如权利要求10所述的防止面板外围走线发生静电击伤的结构，其中，所述外围走线为主动型LCD的外围走线。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006350243A (ja) * 2005-06-20 2006-12-28 Fujifilm Holdings Corp 表示装置
CN101231398A (zh) * 2007-01-24 2008-07-30 胜华科技股份有限公司 具静电抑制措施的液晶面板
CN104113975A (zh) * 2013-04-19 2014-10-22 业鑫科技顾问股份有限公司 静电释放装置及其操作方法
CN104698710A (zh) * 2015-04-01 2015-06-10 上海天马微电子有限公司 一种阵列基板以及液晶显示装置
CN107145015A (zh) * 2017-06-30 2017-09-08 武汉华星光电技术有限公司 一种显示面板
CN206863403U (zh) * 2017-11-07 2018-01-09 深圳市华星光电半导体显示技术有限公司 防止面板外围走线发生静电击伤的结构

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8514200B2 (en) * 2009-12-30 2013-08-20 Au Optronics Corp. Capacitive touch display panel and capacitive touch board
TWI567450B (zh) * 2015-10-16 2017-01-21 群創光電股份有限公司 顯示裝置
KR102534053B1 (ko) * 2016-10-17 2023-05-18 삼성디스플레이 주식회사 표시 장치
CN106896609B (zh) * 2017-04-28 2019-11-19 厦门天马微电子有限公司 一种阵列基板及包括其的显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006350243A (ja) * 2005-06-20 2006-12-28 Fujifilm Holdings Corp 表示装置
CN101231398A (zh) * 2007-01-24 2008-07-30 胜华科技股份有限公司 具静电抑制措施的液晶面板
CN104113975A (zh) * 2013-04-19 2014-10-22 业鑫科技顾问股份有限公司 静电释放装置及其操作方法
CN104698710A (zh) * 2015-04-01 2015-06-10 上海天马微电子有限公司 一种阵列基板以及液晶显示装置
CN107145015A (zh) * 2017-06-30 2017-09-08 武汉华星光电技术有限公司 一种显示面板
CN206863403U (zh) * 2017-11-07 2018-01-09 深圳市华星光电半导体显示技术有限公司 防止面板外围走线发生静电击伤的结构

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