WO2019085512A1 - 一种像素电路及其驱动方法、显示装置 - Google Patents

一种像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2019085512A1
WO2019085512A1 PCT/CN2018/092163 CN2018092163W WO2019085512A1 WO 2019085512 A1 WO2019085512 A1 WO 2019085512A1 CN 2018092163 W CN2018092163 W CN 2018092163W WO 2019085512 A1 WO2019085512 A1 WO 2019085512A1
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Prior art keywords
thin film
film transistor
state
voltage
gate
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PCT/CN2018/092163
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English (en)
French (fr)
Inventor
籍亚男
范文志
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昆山国显光电有限公司
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Publication of WO2019085512A1 publication Critical patent/WO2019085512A1/zh
Priority to US16/441,526 priority Critical patent/US10777138B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes

Definitions

  • the present application relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display device.
  • the organic light emitting display device is a display device using an organic light emitting diode as a light emitting device, and has the characteristics of high contrast, thin thickness, wide viewing angle, fast response speed, low power consumption, etc., and is increasingly applied to various displays and illuminations. field.
  • a plurality of pixel circuits may be generally included.
  • a plurality of pixel circuits are generally supplied with a power supply voltage from the same power source, and the power supply voltage can determine a current flowing through the light-emitting diodes in the pixel circuit.
  • the main purpose of the present application is to provide a pixel circuit, a driving method thereof, and a display device, which are intended to solve the problem that the brightness of the display device is uneven due to the difference in current flowing through the LED due to the power supply voltage drop. The problem.
  • the pixel circuit proposed by the present application includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, a light emitting diode, and Storage capacitor,
  • a gate of the first thin film transistor is respectively connected to a source of the second thin film transistor and one end of the storage capacitor, and the other end of the storage capacitor is respectively connected to a drain of the third thin film transistor and the a source of the fourth thin film transistor is connected, a source of the third thin film transistor is connected to a data signal line, and a drain of the fourth thin film transistor is respectively connected to a drain of the fifth thin film transistor and a reference voltage signal line ;
  • a source of the first thin film transistor is connected to a drain of the sixth thin film transistor, and a source of the sixth thin film transistor is connected to a first power source;
  • a drain of the first thin film transistor is respectively connected to a drain of the second thin film transistor and a source of the seventh thin film transistor, and a drain of the seventh thin film transistor is respectively connected to the fifth thin film transistor
  • the source and the anode of the light emitting diode are connected, and the cathode of the light emitting diode is connected to the second power source.
  • the first power source is configured to supply a power voltage to the first thin film transistor
  • the reference voltage signal line is used to provide a reference voltage
  • the reference voltage is a negative voltage and is smaller than a voltage of the second power source
  • the reference voltage is used for a gate of the first thin film transistor
  • the data signal line is used to provide a data voltage.
  • a gate of the second thin film transistor, a gate of the fourth thin film transistor, and a gate of the fifth thin film transistor are connected to a first scan line, where the first scan line is used to provide a first a scan signal, the first scan signal is used to control the second thin film transistor, the fourth thin film transistor, and the fifth thin film transistor to be in an on state or an off state;
  • a gate of the third thin film transistor is connected to a second scan line, wherein the second scan line is used to provide a second scan signal, and the second scan signal is used to control the third thin film transistor to be in an on state or Cutoff state
  • a gate of the seventh thin film transistor is connected to the first light emission control line, the first light emission control line is configured to provide a first light emission control signal, and the first light emission control signal is used to control the seventh thin film transistor to be in On state or off state;
  • a gate of the sixth thin film transistor is connected to a second light emission control line, the second light emission control line is configured to provide a second light emission control signal, and the second light emission control signal is used to control the sixth thin film transistor to be in On or off state.
  • the first scan signal controls the second thin film transistor and the fifth thin film transistor to be in an on state
  • the first illumination control signal controls the seventh thin film transistor to be in an on state
  • the reference voltage initializes a gate of the first thin film transistor and the one end of the storage capacitor.
  • the first scan signal controls the second thin film transistor and the fifth thin film transistor to be in an on state
  • the second illumination control signal controls the sixth thin film transistor to be in an on state And compensating for a threshold voltage of the first thin film transistor.
  • the reference voltage signal line is connected to the other end of the storage capacitor, and the reference voltage is opposite to the storing The other end of the capacitor is initialized.
  • the reference voltage signal line is connected to an anode of the light emitting diode, and the reference voltage is opposite to the light emitting diode The anode is initialized.
  • the data signal line is connected to the other end of the storage capacitor, and the data voltage is applied to the storage capacitor The other end of the voltage is applied.
  • the first lighting control signal controls the seventh thin film transistor to be in an on state
  • the second lighting control signal controls the sixth thin film transistor to be in an on state
  • the first power source Connecting the gate of the first thin film transistor to the gate of the first thin film transistor, the drain of the first thin film transistor is connected to the anode of the light emitting diode through the seventh thin film transistor, and a current flows through the light a diode that is independent of a supply voltage provided by the first power source.
  • the first thin film transistor is a driving thin film transistor, and the first thin film transistor is a P-type thin film transistor;
  • the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, and the seventh thin film transistor are each independently an N-type thin film transistor or P-type thin film transistor.
  • the present application provides a driving method of a pixel circuit for driving the pixel circuit described above, the driving method including:
  • the first scan signal controls the second thin film transistor, the fourth thin film transistor, and the fifth thin film transistor to change from an off state to an on state
  • the second scan signal controls the third thin film transistor to be in a state
  • the first light emission control signal controls the seventh thin film transistor to be in an on state
  • the reference voltage initializes a gate of the first thin film transistor, both ends of the storage capacitor, and an anode of the light emitting diode
  • the second light emission control signal controls the sixth thin film transistor to change from an on state to an off state;
  • the first scan signal controls the second thin film transistor, the fourth thin film transistor, and the fifth thin film transistor to be in an on state
  • the second scan signal controls the third thin film transistor to be in a second state
  • the first light emission control signal controls the seventh thin film transistor to change from an on state to an off state
  • the second illumination control signal controls the sixth thin film transistor to change from an off state to an on state
  • the first scan signal controls the second thin film transistor, the fourth thin film transistor, and the fifth thin film transistor to change from an on state to an off state
  • the second scan signal controls the
  • the third thin film transistor is changed from an off state to an on state, a data voltage is applied to the other end of the storage capacitor, the first illumination control signal controls the seventh thin film transistor to be in an off state, and the second illumination control signal Controlling the sixth thin film transistor from an on state to an off state;
  • the first scan signal controls the second thin film transistor, the fourth thin film transistor, and the fifth thin film transistor to be in an off state
  • the second scan signal controls the third thin film transistor to be guided
  • the pass state changes to an off state
  • the first light emission control signal controls the seventh thin film transistor to change from an off state to an on state
  • the second light emission control signal controls the sixth thin film transistor to change from an off state to a state In the on state, the light emitting diode emits light.
  • the voltage across the storage capacitor and the gate voltage of the first thin film transistor are both Vref, and Vref is the reference voltage.
  • a gate of the first thin film transistor is connected to a drain, and the first power source applies a voltage to a source of the first thin film transistor, so that the first thin film transistor
  • the gate voltage is VDD-Vth, and the threshold voltage of the first thin film transistor is compensated, wherein Vth is a threshold voltage of the first thin film transistor, and VDD is the first power source.
  • the voltage of the other end of the storage capacitor is changed from Vref to Vdata, and the gate voltage of the first thin film transistor is VDD- Vth+Vdata-Vref such that in the fourth phase, the current flowing through the light emitting diode is independent of the first power source, wherein Vdata is the data voltage.
  • the embodiment of the present application further provides a display device, which includes the pixel circuit described above.
  • the pixel circuit provided by the embodiment of the present application includes seven thin film transistors, a storage capacitor, and a light emitting diode. During the light emitting phase of the light emitting diode, the pixel circuit can compensate for the power supply voltage, so that the current and the input through the light emitting diode
  • the data voltage in the pixel circuit is related to the reference voltage, and is independent of the power supply voltage, thereby effectively avoiding the problem that the display device displays unevenness due to the difference in current flowing into each of the light-emitting diodes due to the power supply voltage drop.
  • the pixel circuit provided by the embodiment of the present application can also compensate the threshold voltage of the driving thin film transistor, thereby effectively avoiding the problem that the display device is unevenly displayed due to the difference in threshold voltage of the driving thin film transistor.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present application.
  • FIG. 2 is a timing diagram of a method for driving a pixel circuit according to an embodiment of the present application.
  • the first thin film transistor is a driving thin film transistor, specifically, a P-type thin film transistor; the second thin film transistor, the third thin film transistor, and the fourth thin film transistor
  • the fifth thin film transistor, the sixth thin film transistor, and the seventh thin film transistor may all be P-type thin film transistors, or both may be N-type thin film transistors, or at least one of them may be a P-type thin film transistor.
  • the rest are N-type thin film transistors, which are not specifically limited in the embodiment of the present application.
  • different types of thin film transistors may be different in scan signals provided by different scan lines.
  • the first thin film transistor to the seventh thin film transistor are both P-type thin film transistors. Description.
  • the light emitting diode may be an LED or an OLED, and is not specifically limited herein.
  • the embodiment of the present application can be described by taking the light emitting diode as an OLED as an example.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present application.
  • the pixel circuit is as follows.
  • the pixel circuit includes a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3, a fourth thin film transistor M4, a fifth thin film transistor M5, a sixth thin film transistor M6, and a seventh thin film.
  • the first thin film transistor M1, the second thin film transistor M2, the third thin film transistor M3, the fourth thin film transistor M4, the fifth thin film transistor M5, the sixth thin film transistor M6, and the seventh thin film transistor M7 Both are P-type thin film transistors, and the light-emitting diode D1 is an OLED.
  • the circuit connection structure of the pixel circuit shown in FIG. 1 is as follows:
  • the gate of the first thin film transistor M1 is respectively connected to the source of the second thin film transistor M2 and one end of the storage capacitor C (point N1 shown in FIG. 1), the source of the first thin film transistor M1 and the sixth thin film transistor M6. a drain connection, a drain of the first thin film transistor M1 is respectively connected to a drain of the second thin film transistor M2 and a source of the seventh thin film transistor M7;
  • the source of the third thin film transistor M3 is connected to the data signal line, and the drain is connected to the source of the fourth thin film transistor M4 and the other end of the storage capacitor C (point N2 shown in FIG. 1);
  • a drain of the fourth thin film transistor M4 is respectively connected to a drain of the fifth thin film transistor M5 and a reference voltage signal line;
  • the source of the fifth thin film transistor M5 is respectively connected to the drain of the seventh thin film transistor M7 and the anode of the light emitting diode D1;
  • a source of the sixth thin film transistor M6 is connected to the first power source VDD;
  • the cathode of the light emitting diode D1 is connected to the second power source VSS.
  • the first power source VDD may be a positive voltage, and is used to supply a power voltage to the first thin film transistor M1.
  • the first thin film transistor M1 may output a current under the action of the first power source VDD, and the current flows into the light.
  • the diode D1 can cause the light emitting diode D1 to emit light.
  • the current flows into the second power source VSS, and the second power source VSS may be a negative voltage.
  • the data signal line can be used to provide a data voltage Vdata, which can be used to provide a reference voltage Vref.
  • the reference voltage Vref may be a negative voltage, and is used for the gate of the first thin film transistor M1 and the two ends of the storage capacitor C (N1 point and N2 point shown in FIG. 1 , that is, the storage capacitor C)
  • the plates and the lower plates) and the anode of the light-emitting diode D1 are initialized.
  • the reference voltage Vref may be a lower voltage than the second power source VSS, such that the reference voltage Vref may cause the LED D1 not to emit light when the anode of the LED D1 is initialized, thereby causing the pixel display Pure black, improve the contrast of the display device.
  • S1 is a first scan signal provided by a first scan line
  • S2 is a second scan signal provided by a second scan line
  • EM1 is a first illumination provided by a first illumination control line
  • EM2 is a second illumination control signal provided by the second illumination control line
  • the gate of the second thin film transistor M2, the gate of the fourth thin film transistor M4, and the gate of the fifth thin film transistor M5 are connected to the first scanning line.
  • the first scan signal S1 provided by the first scan line may control the gate of the second thin film transistor M2, the gate of the fourth thin film transistor M4, and the gate of the fifth thin film transistor M5 to be in an on state or an off state;
  • a gate of the third thin film transistor M3 is connected to the second scan line.
  • the second scan signal S2 provided by the second scan line may control the third thin film transistor M3 to be in an on state or an off state;
  • the gate of the seventh thin film transistor M7 is connected to the first light emission control line.
  • the first light emission control signal EM1 provided by the first light emission control line may control the seventh thin film transistor M7 to be in an on state or an off state;
  • a gate of the sixth thin film transistor M6 is connected to the second light emission control line.
  • the second light emission control signal EM2 provided by the second light emission control line may control the sixth thin film transistor M6 to be in an on state or an off state.
  • the first scan signal S1 can control the second thin film transistor M2, the fourth thin film transistor M4, and the fifth thin film transistor M5 to be in an on state or an off state at the same time, wherein:
  • the gate of the first thin film transistor M1 is connected to the drain, and at this time, if the seventh thin film transistor M7 is in an on state
  • the reference voltage signal line is connected to the gate and the drain of the first thin film transistor M1 and one end of the storage capacitor C (the N1 point shown in FIG. 1 , that is, the upper plate of the storage capacitor C), and the reference voltage Vref is
  • the gate and the drain of the first thin film transistor M1 and the upper plate of the storage capacitor C are initialized; if the sixth thin film transistor M6 is in an on state, the first power supply VDD can apply a voltage to the source of the first thin film transistor M1.
  • the reference voltage signal line may also be connected to the anode of the light emitting diode D1 through the fifth thin film transistor M5, and the reference voltage Vref is performed on the anode of the light emitting diode D1.
  • the reference voltage signal line may pass through the fourth thin film transistor M4 and the other end of the storage capacitor C (N2 point shown in FIG. 1, ie, a storage capacitor)
  • the lower plate of C is connected, and the reference voltage Vref initializes the lower plate of the storage capacitor C.
  • the data signal line can pass through the third thin film transistor M3 to the other end of the storage capacitor C (N2 point shown in FIG. 1, that is, the storage capacitor C
  • the lower plate is applied with a voltage such that the lower plate voltage of the storage capacitor C is Vdata.
  • the first light-emitting control signal EM1 controls the seventh thin film transistor M7 to be in an on state
  • the second light-emitting control signal EM2 controls the sixth thin film transistor M6 to be in an on state
  • the first power source VDD passes through the sixth thin film transistor M6 and the first The source of the thin film transistor M1 is connected, and a voltage is applied to the source of the first thin film transistor M1.
  • the drain of the first thin film transistor M1 is connected to the anode of the light emitting diode D1 through the seventh thin film transistor M7.
  • the first thin film transistor M1 can generate a driving current under the action of the first power source VDD, and the driving current can flow into the light emitting diode D1, so that the light emitting diode D1 emits light.
  • the pixel circuit provided by the embodiment of the present application can compensate the first power supply VDD during the operation thereof, so that the current flowing through the LED D1 is independent of the power supply voltage provided by the first power supply VDD, thereby effectively avoiding the power supply voltage.
  • the current flowing through the LED is different due to the drop, and the display device shows a problem of unevenness.
  • For a specific process of compensating the first power supply VDD reference may be made to the description of the working principle of the pixel circuit.
  • FIG. 2 is a timing diagram of another driving method of a pixel circuit according to an embodiment of the present application.
  • the timing diagram shown in FIG. 2 can be used to drive the pixel circuit shown in FIG. 1. specifically:
  • the first stage t1 The first stage t1:
  • the second scan signal S2 Since the first scan signal S1 changes from a high level to a low level, the second scan signal S2 maintains a high level, the first light emission control signal EM1 remains at a low level, and the second light emission control signal EM2 changes from a low level to a high level. Level, therefore, the second thin film transistor M2, the fourth thin film transistor M4, and the fifth thin film transistor M5 are in an on state, the third thin film transistor M3 is in an off state, and the seventh thin film transistor M7 is in an on state, the sixth thin film transistor M6 changes from the on state to the off state.
  • the reference voltage signal line is connected to the lower plate of the storage capacitor C (N2 point shown in FIG. 1) through the fourth thin film transistor M4, and the reference voltage Vref is directed to the lower plate of the storage capacitor C. Applying a voltage such that the lower plate voltage of the storage capacitor C is Vref, thereby realizing initialization of the lower plate of the storage capacitor C;
  • the reference voltage signal line is connected to the anode of the light-emitting diode D1 through the fifth thin film transistor M5, and the reference voltage Vref applies a voltage to the anode of the light-emitting diode D1 to effect initialization of the anode of the light-emitting diode D1.
  • the reference voltage Vref may be a lower negative voltage than the second power source VSS, the light emitting diode D1 does not emit light, and thus the pixel circuit can be made to display pure black, thereby improving the contrast of the display of the display device.
  • the drain of the first thin film transistor M1 is connected to the gate through the second thin film transistor M2, and the reference voltage signal line can pass through the fifth thin film transistor M5 and the seventh thin film transistor M7 and the first thin film transistor.
  • the gate and the drain of M1 are connected to the upper plate of the storage capacitor C (N1 shown in FIG. 1), and the reference voltage Vref applies a voltage to the gate and drain of the first thin film transistor M1 and the upper plate of the storage capacitor C.
  • the gate voltage of the first thin film transistor M1, the drain voltage, and the upper plate voltage of the storage capacitor C are both Vref, and the gate and the drain of the first thin film transistor M1 and the upper plate of the storage capacitor C are realized. initialization.
  • the gate voltage and the drain voltage of the first thin film transistor M1 are both Vref, the upper plate voltage of the storage capacitor C is Vref, and the lower plate voltage is Vref.
  • the second thin film transistor M2, the fourth thin film transistor M4, and the fifth thin film transistor M5 are in an on state, the third thin film transistor M3 is in an off state, and the seventh thin film transistor M7 is turned from an on state to an off state.
  • the sixth thin film transistor M6 is changed from the off state to the on state.
  • the gate and the drain of the first thin film transistor M1 are still in a connected state, and the first power supply VDD applies a voltage to the source of the first thin film transistor M1 through the sixth thin film transistor M6, and passes through the drain of the first thin film transistor M1.
  • the gate of the first thin film transistor M1 is charged, and the gate voltage and the drain voltage of the first thin film transistor M1 are both VDD-Vth, wherein Vth is the threshold voltage of the first thin film transistor M1, such that When the light emitting diode D1 emits light, the threshold voltage of the first thin film transistor M1 can be compensated.
  • the lower plate voltage of the storage capacitor C remains Vref, and the upper plate voltage is equal to the gate voltage of the first thin film transistor M1, that is, VDD-Vth.
  • the third stage t3 The third stage t3:
  • the first scan signal S1 changes from a low level to a high level
  • the second scan signal S2 changes from a high level to a low level
  • the first light emission control signal EM1 remains at a high level
  • the second light emission control signal EM2 is low.
  • the level becomes a high level. Therefore, the second thin film transistor M2, the fourth thin film transistor M4, and the fifth thin film transistor M5 are turned from the on state to the off state, and the third thin film transistor M3 is turned from the off state to the on state.
  • the seventh thin film transistor M7 is in an off state
  • the sixth thin film transistor M6 is turned from an on state to an off state.
  • the data signal line is connected to the lower plate of the storage capacitor C through the third thin film transistor M3 (point N2 shown in FIG. 1), and the data voltage Vdata is applied to the lower plate of the storage capacitor C, so that the storage capacitor C is The voltage of the lower plate is changed from Vref to Vdata. Accordingly, the voltage of the upper plate of the storage capacitor C (point N1 shown in FIG. 1) is changed from VDD-Vth to VDD-Vth+Vdata-Vref, that is, the first thin film transistor M1. The gate voltage is also changed from VDD-Vth to VDD-Vth+Vdata-Vref.
  • the second scan signal S2 changes from a low level to a high level
  • the first light emission control signal EM1 changes from a high level to a low level
  • the second light emission control signal EM2 is high.
  • the level becomes a low level. Therefore, the second thin film transistor M2, the fourth thin film transistor M4, and the fifth thin film transistor M5 are in an off state, and the third thin film transistor M3 is turned from an on state to an off state, and the seventh thin film transistor M7 From the off state to the on state, the sixth thin film transistor M6 is turned from the off state to the on state.
  • the first power source VDD applies a voltage to the source of the first thin film transistor M1 through the sixth thin film transistor M6.
  • the first thin film transistor M1 generates a driving current, and the driving current passes through the seventh film.
  • the transistor M7 flows into the light emitting diode D1, so that the light emitting diode D1 emits light.
  • the current flowing through the light emitting diode D1 can be expressed as:
  • ⁇ is the electron mobility of the first thin film transistor M1
  • C ox is the gate oxide capacitance per unit area of the first thin film transistor M1
  • W/L is the aspect ratio of the first thin film transistor M1
  • Vs is the first thin film transistor
  • the source voltage VDD, Vg of M1 is the gate voltage VDD-Vth+Vdata-Vref of the first thin film transistor M1.
  • the current flowing through the light-emitting diode D1 is related to the reference voltage Vref and the data voltage Vdata, and is independent of the power supply voltage supplied from the first power supply VDD, and is also independent of the threshold voltage Vth of the first thin film transistor M1.
  • the compensation of the first power supply VDD avoids the influence of the power supply voltage drop of the first power supply VDD on the display effect, ensures the uniformity of the display of the display device, and at the same time, compensates the threshold voltage of the first thin film transistor M1, thereby avoiding The display device exhibits a problem of unevenness due to the difference in the threshold voltage of the first thin film transistor M1.
  • the embodiment of the present application further provides a display device, and the display device may include the pixel circuit described above.

Abstract

一种像素电路及其驱动方法、显示装置，像素电路包括第一薄膜晶体管（M1）、第二薄膜晶体管（M2）、第三薄膜晶体管（M3）、第四薄膜晶体管（M4）、第五薄膜晶体管（M5）、第六薄膜晶体管（M6）、第七薄膜晶体管（M7）、发光二极管（D1）以及存储电容（C）；在发光二极管（D1）的发光阶段，可以实现对电源电压的补偿，使得流经发光二极管（D1）的电流与输入像素电路中的数据电压（Vdata）以及参考电压（Vref）有关，与电源电压无关，从而有效避免由于电源电压降导致的流入每一个发光二极管（D1）的电流不同，显示装置显示不均匀的问题。

Description

一种像素电路及其驱动方法、显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、显示装置。
背景技术
有机发光显示装置是一种应用有机发光二极管作为发光器件的显示装置，具有对比度高、厚度薄、视角广、反应速度快、低功耗等特点，被越来越多地应用到各个显示以及照明领域。
现有的有机发光显示装置中，通常可以包含多个像素电路，多个像素电路通常由同一电源提供电源电压，电源电压可以决定流经像素电路中发光二极管的电流。
然而，在实际应用中，电源电压在多个像素电路间传输时不可避免的产生电源电压降(IR drop)，导致作用在每一个像素电路的实际电源电压不同，进而导致流经每一个发光二极管的电流不同，显示装置显示的亮度不均匀。
发明内容
本申请的主要目的是提供一种像素电路及其驱动方法、显示装置，旨在解决现有的显示装置中，由于电源电压降导致的流经发光二极管的电流不同，显示装置显示的亮度不均匀的问题。
为实现上述目的，本申请提出的像素电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、发光二极管以及存储电容，
所述第一薄膜晶体管的栅极分别与所述第二薄膜晶体管的源极以及所述存储电容的一端连接，所述存储电容的另一端分别与所述第三薄膜晶体管的漏极以及所述第四薄膜晶体管的源极连接，所述第三薄膜晶体管的源极与数据信号线连接，所述第四薄膜晶体管的漏极分别与所述第五薄膜晶体管的漏极以及参考电压信号线连接；
所述第一薄膜晶体管的源极与所述第六薄膜晶体管的漏极连接，所述第 六薄膜晶体管的源极与第一电源连接；
所述第一薄膜晶体管的漏极分别与所述第二薄膜晶体管的漏极以及所述第七薄膜晶体管的源极连接，所述第七薄膜晶体管的漏极分别与所述第五薄膜晶体管的源极以及所述发光二极管的阳极连接，所述发光二极管的阴极与第二电源连接。
可选地，所述第一电源，用于为所述第一薄膜晶体管提供电源电压；
所述发光二极管发光时电流流入所述第二电源。
可选地，所述参考电压信号线用于提供参考电压，所述参考电压为负电压且小于所述第二电源的电压，所述参考电压用于对所述第一薄膜晶体管的栅极、所述存储电容的两端以及所述发光二极管的阳极进行初始化；
所述数据信号线用于提供数据电压。
可选地，所述第二薄膜晶体管的栅极、所述第四薄膜晶体管的栅极以及所述第五薄膜晶体管的栅极与第一扫描线连接，所述第一扫描线用于提供第一扫描信号，所述第一扫描信号用于控制所述第二薄膜晶体管、所述第四薄膜晶体管以及所述第五薄膜晶体管处于导通状态或截止状态；
所述第三薄膜晶体管的栅极与第二扫描线连接，所述第二扫描线用于提供第二扫描信号，所述第二扫描信号用于控制所述第三薄膜晶体管处于导通状态或截止状态；
所述第七薄膜晶体管的栅极与第一发光控制线连接，所述第一发光控制线用于提供第一发光控制信号，所述第一发光控制信号用于控制所述第七薄膜晶体管处于导通状态或截止状态；
所述第六薄膜晶体管的栅极与第二发光控制线连接，所述第二发光控制线用于提供第二发光控制信号，所述第二发光控制信号用于控制所述第六薄膜晶体管处于导通状态或截止状态。
可选地，当所述第一扫描信号控制所述第二薄膜晶体管以及所述第五薄膜晶体管处于导通状态，且所述第一发光控制信号控制所述第七薄膜晶体管处于导通状态时，所述参考电压对所述第一薄膜晶体管的栅极以及所述存储电容的所述一端进行初始化。
可选地，当所述第一扫描信号控制所述第二薄膜晶体管以及所述第五薄膜晶体管处于导通状态，且所述第二发光控制信号控制所述第六薄膜晶体管 处于导通状态时，对所述第一薄膜晶体管的阈值电压进行补偿。
可选地，当所述第一扫描信号控制所述第四薄膜晶体管处于导通状态时，所述参考电压信号线与所述存储电容的所述另一端连接，所述参考电压对所述存储电容的所述另一端进行初始化。
可选地，当所述第一扫描信号控制所述第五薄膜晶体管处于导通状态时，所述参考电压信号线与所述发光二级管的阳极连接，所述参考电压对所述发光二极管的阳极进行初始化。
可选地，当所述第二扫描信号控制所述第三薄膜晶体管处于导通状态时，所述数据信号线与所述存储电容的所述另一端连接，所述数据电压向所述存储电容的所述另一端施加电压。
可选地，当所述第一发光控制信号控制所述第七薄膜晶体管处于导通状态，且所述第二发光控制信号控制所述第六薄膜晶体管处于导通状态时，所述第一电源通过所述第六薄膜晶体管与所述第一薄膜晶体管的栅极连接，所述第一薄膜晶体管的漏极通过所述第七薄膜晶体管与所述发光二极管的阳极连接，电流流经所述发光二极管，所述电流与由所述第一电源提供的电源电压无关。
可选地，所述第一薄膜晶体管为驱动薄膜晶体管，且所述第一薄膜晶体管为P型薄膜晶体管；
所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管以及所述第七薄膜晶体管分别独立地为N型薄膜晶体管或P型薄膜晶体管。
本申请提供一种像素电路的驱动方法，所述驱动方法用于驱动上述记载的所述像素电路，所述驱动方法包括：
第一阶段，第一扫描信号控制所述第二薄膜晶体管、所述第四薄膜晶体管以及所述第五薄膜晶体管由截止状态变为导通状态，第二扫描信号控制所述第三薄膜晶体管处于截止状态，第一发光控制信号控制所述第七薄膜晶体管处于导通状态，参考电压对所述第一薄膜晶体管的栅极、所述存储电容的两端以及所述发光二极管的阳极进行初始化，第二发光控制信号控制所述第六薄膜晶体管由导通状态变为截止状态；
第二阶段，所述第一扫描信号控制所述第二薄膜晶体管、所述第四薄膜 晶体管以及所述第五薄膜晶体管处于导通状态，所述第二扫描信号控制所述第三薄膜晶体管处于截止状态，所述第一发光控制信号控制所述第七薄膜晶体管由导通状态变为截止状态，所述第二发光控制信号控制所述第六薄膜晶体管由截止状态变为导通状态，对所述第一薄膜晶体管的阈值电压进行补偿；
第三阶段，所述第一扫描信号控制所述第二薄膜晶体管、所述第四薄膜晶体管以及所述第五薄膜晶体管由导通状态变为截止状态，所述第二扫描信号控制所述第三薄膜晶体管由截止状态变为导通状态，数据电压向所述存储电容的另一端施加电压，所述第一发光控制信号控制所述第七薄膜晶体管处于截止状态，所述第二发光控制信号控制所述第六薄膜晶体管由导通状态变为截止状态；
第四阶段，所述第一扫描信号控制所述第二薄膜晶体管、所述第四薄膜晶体管以及所述第五薄膜晶体管处于截止状态，所述第二扫描信号控制所述第三薄膜晶体管由导通状态变为截止状态，所述第一发光控制信号控制所述第七薄膜晶体管由截止状态变为导通状态，所述第二发光控制信号控制所述第六薄膜晶体管由截止状态变为导通状态，所述发光二极管发光。
可选地，在所述第一阶段，所述存储电容两端的电压以及所述第一薄膜晶体管的栅极电压均为Vref，Vref为所述参考电压。
可选地，在所述第二阶段，所述第一薄膜晶体管的栅极与漏极连接，所述第一电源向所述第一薄膜晶体管的源极施加电压，使得所述第一薄膜晶体管的栅极电压为VDD-Vth，对所述第一薄膜晶体管的阈值电压进行补偿，其中，Vth为所述第一薄膜晶体管的阈值电压，VDD为所述第一电源。
可选地，在所述第三阶段，所述存储电容的所述另一端的电压由Vref变为Vdata，在所述存储电容的作用下，所述第一薄膜晶体管的栅极电压为VDD-Vth+Vdata-Vref，使得在所述第四阶段，流经所述发光二极管的电流与所述第一电源无关，其中，Vdata为所述数据电压。
本申请实施例还提供一种显示装置，该显示装置包括上述记载的所述像素电路。
本申请实施例采用的上述至少一个技术方案能够达到以下有益效果：
本申请实施例提供的像素电路，包括七个薄膜晶体管、一个存储电容以及一个发光二极管，在发光二极管的发光阶段，该像素电路可以实现对电源 电压的补偿，使得流经发光二极管的电流与输入该像素电路中的数据电压以及参考电压有关，与电源电压无关，从而有效避免由于电源电压降导致的流入每一个发光二极管的电流不同，显示装置显示不均匀的问题。
此外，本申请实施例提供的像素电路还可以对驱动薄膜晶体管阈值电压进行补偿，有效避免由于驱动薄膜晶体管阈值电压的不同导致的显示装置显示不均匀的问题。
附图说明
图1为本申请实施例提供的一种像素电路的结构示意图；
图2为本申请实施例提供的一种像素电路的驱动方法的时序图。
具体实施方式
在本申请实施例提供的像素电路中，所述第一薄膜晶体管为驱动薄膜晶体管，具体可以为P型薄膜晶体管；所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管以及所述第七薄膜晶体管可以均为P型薄膜晶体管，也可以均为N型薄膜晶体管，还可以是其中至少一者为P型薄膜晶体管，其余的为N型薄膜晶体管，本申请实施例不做具体限定。
本申请实施例中，不同类型的薄膜晶体管，不同扫描线提供的扫描信号可以不同，本申请实施例可以以所述第一薄膜晶体管至所述第七薄膜晶体管均是P型薄膜晶体管为例进行说明。
所述发光二极管可以是LED，也可以是OLED，这里也不做具体限定。本申请实施例可以以所述发光二极管是OLED为例进行说明。
以下结合附图，详细说明本申请各实施例提供的技术方案。
图1为本申请实施例提供的一种像素电路的结构示意图。所述像素电路如下所述。
如图1所示，所述像素电路包括第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第五薄膜晶体管M5、第六薄膜晶体管M6、第七薄膜晶体管M7、存储电容C以及发光二极管D1。图1所示的像素电路中，第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、 第四薄膜晶体管M4、第五薄膜晶体管M5、第六薄膜晶体管M6以及第七薄膜晶体管M7均为P型薄膜晶体管，发光二极管D1为OLED。
图1所示的像素电路的电路连接结构如下所述：
第一薄膜晶体管M1的栅极分别与第二薄膜晶体管M2的源极以及存储电容C的一端(图1所示的N1点)连接，第一薄膜晶体管M1的源极与第六薄膜晶体管M6的漏极连接，第一薄膜晶体管M1的漏极分别与第二薄膜晶体管M2的漏极以及第七薄膜晶体管M7的源极连接；
第三薄膜晶体管M3的源极与数据信号线连接，漏极分别与第四薄膜晶体管M4的源极以及存储电容C的另一端(图1所示的N2点)连接；
第四薄膜晶体管M4的漏极分别与第五薄膜晶体管M5的漏极以及参考电压信号线连接；
第五薄膜晶体管M5的源极分别与第七薄膜晶体管M7的漏极以及发光二极管D1的阳极连接；
第六薄膜晶体管M6的源极与第一电源VDD连接；
发光二极管D1的阴极与第二电源VSS连接。
本申请实施例中，所述第一电源VDD可以是正电压，并用于为第一薄膜晶体管M1提供电源电压，第一薄膜晶体管M1在第一电源VDD的作用下，可以输出电流，该电流流入发光二极管D1，可以使得发光二极管D1发光。在发光二极管D1发光时，该电流流入第二电源VSS，第二电源VSS可以是负电压。
所述数据信号线可以用于提供数据电压Vdata，所述参考电压信号线可以用于提供参考电压Vref。本申请实施例中，参考电压Vref可以为负电压，并用于对第一薄膜晶体管M1的栅极、存储电容C的两端(图1所示的N1点以及N2点，即存储电容C的上极板和下极板)以及发光二极管D1的阳极进行初始化。
需要说明的是，参考电压Vref可以是比第二电源VSS还要低的负压，这样，参考电压Vref在对发光二极管D1的阳极进行初始化时，可以使得发光二极管D1不发光，从而使得像素显示纯黑，提高显示装置显示的对比度。
图1所示的像素电路中，S1为由第一扫描线提供的第一扫描信号，S2为由第二扫描线提供的第二扫描信号，EM1为由第一发光控制线提供的第一发光控制信号，EM2为由第二发光控制线提供的第二发光控制信号，其中：
第二薄膜晶体管M2的栅极、第四薄膜晶体管M4的栅极以及第五薄膜晶体 管M5的栅极与所述第一扫描线连接。由所述第一扫描线提供的第一扫描信号S1可以控制第二薄膜晶体管M2的栅极、第四薄膜晶体管M4的栅极以及第五薄膜晶体管M5的栅极处于导通状态或截止状态；
第三薄膜晶体管M3的栅极与所述第二扫描线连接。由所述第二扫描线提供的第二扫描信号S2可以控制第三薄膜晶体管M3处于导通状态或截止状态；
第七薄膜晶体管M7的栅极与第一发光控制线连接。所述第一发光控制线提供的第一发光控制信号EM1可以控制第七薄膜晶体管M7处于导通状态或截止状态；
第六薄膜晶体管M6的栅极与所述第二发光控制线连接。由所述第二发光控制线提供的第二发光控制信号EM2可以控制第六薄膜晶体管M6处于导通状态或截止状态。
本申请实施例中，在第一扫描信号S1可以控制第二薄膜晶体管M2、第四薄膜晶体管M4以及第五薄膜晶体管M5同时处于导通状态或截止状态，其中：
当第一扫描信号S1控制第二薄膜晶体管M2、第五薄膜晶体管M5处于导通状态时，第一薄膜晶体管M1的栅极与漏极连接，此时，若第七薄膜晶体管M7处于导通状态，则所述参考电压信号线与第一薄膜晶体管M1的栅极和漏极、存储电容C的一端(图1所示的N1点，即存储电容C的上极板)连接，参考电压Vref对第一薄膜晶体管M1的栅极和漏极、存储电容C的上极板进行初始化；若第六薄膜晶体管M6处于导通状态，则第一电源VDD可以向第一薄膜晶体管M1的源极施加电压，并对第一薄膜晶体管M1的栅极充电，最终使得第一薄膜晶体管M1的栅极电压以及漏极电压变为Vdata-Vth，在发光二极管D1发光时，可以实现对第一薄膜晶体管M1阈值电压的补偿；
当第一扫描信号S1控制第五薄膜晶体管M5处于导通状态时，所述参考电压信号线还可以通过第五薄膜晶体管M5与发光二极管D1的阳极连接，参考电压Vref对发光二极管D1的阳极进行初始化；
当第一扫描信号S1控制第四薄膜晶体管M4处于导通状态时，所述参考电压信号线可以通过第四薄膜晶体管M4与存储电容C的另一端(图1所示的N2点，即存储电容C的下极板)连接，参考电压Vref对存储电容C的下极板进行初始化。
当第二扫描线S2控制第三薄膜晶体管M3处于导通状态时，所述数据信号 线可以通过第三薄膜晶体管M3向存储电容C的另一端(图1所示的N2点，即存储电容C的下极板)施加电压，使得存储电容C的下极板电压为Vdata。
当第一发光控制信号EM1控制第七薄膜晶体管M7处于导通状态，且第二发光控制信号EM2控制第六薄膜晶体管M6处于导通状态时，第一电源VDD通过第六薄膜晶体管M6与第一薄膜晶体管M1的源极连接，并向第一薄膜晶体管M1的源极施加电压，第一薄膜晶体管M1的漏极通过第七薄膜晶体管M7与发光二极管D1的阳极连接，此时，第一薄膜晶体管M1在第一电源VDD的作用下可以产生驱动电流，该驱动电流可以流入发光二极管D1，使得发光二极管D1发光。
本申请实施例提供的像素电路，在其工作过程中可以实现对第一电源VDD的补偿，使得流经发光二极管D1的电流与由第一电源VDD提供的电源电压无关，进而有效避免由于电源电压降导致的流经发光二极管的电流不同，显示装置显示不均匀的问题。其中，对第一电源VDD进行补偿的具体过程可以参见下文对所述像素电路工作原理的说明。
图2为本申请实施例提供的另一种像素电路的驱动方法的时序图。图2所示的时序图可以用于驱动图1所示的像素电路。具体地：
图2所示的时序图在驱动图1所示的像素电路时，工作周期可以分为四个阶段，即第一阶段t1、第二阶段t2、第三阶段t3以及第四阶段t4。
下面将分别针对所述像素电路的上述四个阶段进行说明：
第一阶段t1:
由于第一扫描信号S1由高电平变为低电平，第二扫描信号S2保持高电平，第一发光控制信号EM1保持低电平，第二发光控制信号EM2由低电平变为高电平，因此，第二薄膜晶体管M2、第四薄膜晶体管M4以及第五薄膜晶体管M5处于导通状态，第三薄膜晶体管M3处于截止状态，第七薄膜晶体管M7处于导通状态，第六薄膜晶体管M6由导通状态变为截止状态。
此时，针对存储电容C而言，参考电压信号线通过第四薄膜晶体管M4与存储电容C的下极板(图1所示的N2点)连接，参考电压Vref向存储电容C的下极板施加电压，使得存储电容C的下极板电压为Vref，实现对存储电容C的下极板的初始化；
针对发光二极管D1而言，参考电压信号线通过第五薄膜晶体管M5与发光 二极管D1的阳极连接，参考电压Vref向发光二极管D1的阳极施加电压，实现对发光二极管D1的阳极的初始化。此时，由于参考电压Vref可以是比第二电源VSS还要低的负压，因此，发光二极管D1不发光，这样，可以使得所述像素电路显示纯黑，从而提高显示装置显示的对比度。
针对第一薄膜晶体管M1而言，第一薄膜晶体管M1的漏极通过第二薄膜晶体管M2与栅极连接，参考电压信号线可以通过第五薄膜晶体管M5以及第七薄膜晶体管M7与第一薄膜晶体管M1的栅极和漏极、存储电容C的上极板(图1所示的N1)连接，参考电压Vref向第一薄膜晶体管M1的栅极和漏极、存储电容C的上极板施加电压，使得第一薄膜晶体管M1的栅极电压、漏极电压以及存储电容C的上极板电压均为Vref，实现对第一薄膜晶体管M1的栅极和漏极、存储电容C的上极板的初始化。
在第一阶段t1结束后，第一薄膜晶体管M1的栅极电压以及漏极电压均为Vref，存储电容C的上极板电压为Vref，下极板电压为Vref。
第二阶段t2：
由于第一扫描信号S1保持低电平，第二扫描信号S2保持高电平，第一发光控制信号EM1由低电平变为高电平，第二发光控制信号EM2由高电平变为低电平，因此，第二薄膜晶体管M2、第四薄膜晶体管M4以及第五薄膜晶体管M5处于导通状态，第三薄膜晶体管M3处于截止状态，第七薄膜晶体管M7由导通状态变为截止状态，第六薄膜晶体管M6由截止状态变为导通状态。
此时，第一薄膜晶体管M1的栅极与漏极仍处于连接状态，第一电源VDD通过第六薄膜晶体管M6向第一薄膜晶体管M1的源极施加电压，并通过第一薄膜晶体管M1的漏极对第一薄膜晶体管M1的栅极充电，电路稳定后，第一薄膜晶体管M1的栅极电压以及漏极电压均为VDD-Vth，其中，Vth为第一薄膜晶体管M1的阈值电压，这样，在发光二极管D1发光时，可以对第一薄膜晶体管M1的阈值电压进行补偿。
在第二阶段t2，存储电容C的下极板电压保持Vref不变，上极板电压等于第一薄膜晶体管M1的栅极电压，即为VDD-Vth。
第三阶段t3：
由于第一扫描信号S1由低电平变为高电平，第二扫描信号S2由高电平变为低电平，第一发光控制信号EM1保持高电平，第二发光控制信号EM2由低 电平变为高电平，因此，第二薄膜晶体管M2、第四薄膜晶体管M4以及第五薄膜晶体管M5由导通状态变为截止状态，第三薄膜晶体管M3由截止状态变为导通状态，第七薄膜晶体管M7处于截止状态，第六薄膜晶体管M6由导通状态变为截止状态。
此时，数据信号线通过第三薄膜晶体管M3与存储电容C的下极板(图1所示的N2点)连接，数据电压Vdata向存储电容C的下极板施加电压，使得存储电容C的下极板电压由Vref变为Vdata，相应地，存储电容C的上极板(图1所示的N1点)电压由VDD-Vth变为VDD-Vth+Vdata-Vref，即第一薄膜晶体管M1的栅极电压也由VDD-Vth变为VDD-Vth+Vdata-Vref。
第四阶段t4：
由于第一扫描信号S1保持高电平，第二扫描信号S2由低电平变为高电平，第一发光控制信号EM1由高电平变为低电平，第二发光控制信号EM2由高电平变为低电平，因此，第二薄膜晶体管M2、第四薄膜晶体管M4以及第五薄膜晶体管M5处于截止状态，第三薄膜晶体管M3由导通状态变为截止状态，第七薄膜晶体管M7由截止状态变为导通状态，第六薄膜晶体管M6由截止状态变为导通状态。
此时，第一电源VDD通过第六薄膜晶体管M6向第一薄膜晶体管M1的源极施加电压，在第一电源VDD的作用下，第一薄膜晶体管M1产生驱动电流，该驱动电流通过第七薄膜晶体管M7流入发光二极管D1，使得发光二极管D1发光。其中，流经发光二极管D1的电流可以表示为：
Figure PCTCN2018092163-appb-000001
其中，μ为第一薄膜晶体管M1的电子迁移率，C ox为第一薄膜晶体管M1单位面积的栅氧化层电容，W/L为第一薄膜晶体管M1的宽长比，Vs为第一薄膜晶体管M1的源极电压VDD，Vg为第一薄膜晶体管M1的栅极电压VDD-Vth+Vdata-Vref。
由上述公式可知，流经发光二极管D1的电流与参考电压Vref以及数据电压Vdata有关，与由第一电源VDD提供的电源电压无关，也与第一薄膜晶体管M1的阈值电压Vth无关，实现了对第一电源VDD的补偿，避免了第一电源VDD的电源电压降对显示效果的影响，保证了显示装置显示的均匀性，同时，实现了对第一薄膜晶体管M1的阈值电压的补偿，避免了由于第一薄膜晶体管M1 的阈值电压的不同导致的显示装置显示不均匀的问题。
本申请实施例还提供一种显示装置，所述显示装置可以包括上述记载的所述像素电路。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (16)

  1. 一种像素电路，其中，所述像素电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、发光二极管以及存储电容，
    所述第一薄膜晶体管的栅极分别与所述第二薄膜晶体管的源极以及所述存储电容的一端连接，所述存储电容的另一端分别与所述第三薄膜晶体管的漏极以及所述第四薄膜晶体管的源极连接，所述第三薄膜晶体管的源极与数据信号线连接，所述第四薄膜晶体管的漏极分别与所述第五薄膜晶体管的漏极以及参考电压信号线连接；
    所述第一薄膜晶体管的源极与所述第六薄膜晶体管的漏极连接，所述第六薄膜晶体管的源极与第一电源连接；
    所述第一薄膜晶体管的漏极分别与所述第二薄膜晶体管的漏极以及所述第七薄膜晶体管的源极连接，所述第七薄膜晶体管的漏极分别与所述第五薄膜晶体管的源极以及所述发光二极管的阳极连接，所述发光二极管的阴极与第二电源连接。
  2. 如权利要求1所述的像素电路，其中，
    所述第一电源用于为所述第一薄膜晶体管提供电源电压；
    在所述发光二极管发光时电流流入所述第二电源。
  3. 如权利要求1所述的像素电路，其中，
    所述参考电压信号线用于提供参考电压，所述参考电压为负电压且小于所述第二电源的电压，所述参考电压用于对所述第一薄膜晶体管的栅极、所述存储电容的两端以及所述发光二极管的阳极进行初始化；
    所述数据信号线用于提供数据电压。
  4. 如权利要求3所述的像素电路，其中，
    所述第二薄膜晶体管的栅极、所述第四薄膜晶体管的栅极以及所述第五薄膜晶体管的栅极与第一扫描线连接，所述第一扫描线用于提供第一扫描信号，所述第一扫描信号用于控制所述第二薄膜晶体管、所述第四薄膜晶体管 以及所述第五薄膜晶体管处于导通状态或截止状态；
    所述第三薄膜晶体管的栅极与第二扫描线连接，所述第二扫描线用于提供第二扫描信号，所述第二扫描信号用于控制所述第三薄膜晶体管处于导通状态或截止状态；
    所述第七薄膜晶体管的栅极与第一发光控制线连接，所述第一发光控制线用于提供第一发光控制信号，所述第一发光控制信号用于控制所述第七薄膜晶体管处于导通状态或截止状态；
    所述第六薄膜晶体管的栅极与第二发光控制线连接，所述第二发光控制线用于提供第二发光控制信号，所述第二发光控制信号用于控制所述第六薄膜晶体管处于导通状态或截止状态。
  5. 如权利要求4所述的像素电路，其中，
    当所述第一扫描信号控制所述第二薄膜晶体管以及所述第五薄膜晶体管处于导通状态，且所述第一发光控制信号控制所述第七薄膜晶体管处于导通状态时，所述参考电压对所述第一薄膜晶体管的栅极以及所述存储电容的所述一端进行初始化。
  6. 如权利要求4所述的像素电路，其中，
    当所述第一扫描信号控制所述第二薄膜晶体管以及所述第五薄膜晶体管处于导通状态，且所述第二发光控制信号控制所述第六薄膜晶体管处于导通状态时，对所述第一薄膜晶体管的阈值电压进行补偿。
  7. 如权利要求4所述的像素电路，其中，
    当所述第一扫描信号控制所述第四薄膜晶体管处于导通状态时，所述参考电压信号线与所述存储电容的所述另一端连接，所述参考电压对所述存储电容的所述另一端进行初始化。
  8. 如权利要求4所述的像素电路，其中，
    当所述第一扫描信号控制所述第五薄膜晶体管处于导通状态时，所述参考电压信号线与所述发光二级管的阳极连接，所述参考电压对所述发光二极管的阳极进行初始化。
  9. 如权利要求4所述的像素电路，其中，
    当所述第二扫描信号控制所述第三薄膜晶体管处于导通状态时，所述数据信号线与所述存储电容的所述另一端连接，所述数据电压向所述存储电容的所述另一端施加电压。
  10. 如权利要求4所述的像素电路，其中，
    当所述第一发光控制信号控制所述第七薄膜晶体管处于导通状态，且所述第二发光控制信号控制所述第六薄膜晶体管处于导通状态时，所述第一电源通过所述第六薄膜晶体管与所述第一薄膜晶体管的栅极连接，所述第一薄膜晶体管的漏极通过所述第七薄膜晶体管与所述发光二极管的阳极连接，电流流经所述发光二极管，所述电流与由所述第一电源提供的电源电压无关。
  11. 如权利要求1至10任一项所述的像素电路，其中，
    所述第一薄膜晶体管为驱动薄膜晶体管，且所述第一薄膜晶体管为P型薄膜晶体管；
    所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管、所述第六薄膜晶体管以及所述第七薄膜晶体管分别独立地为N型薄膜晶体管或P型薄膜晶体管。
  12. 一种如权利要求1至11任一项所述的像素电路的驱动方法，其中，包括：
    第一阶段，第一扫描信号控制所述第二薄膜晶体管、所述第四薄膜晶体管以及所述第五薄膜晶体管由截止状态变为导通状态，第二扫描信号控制所述第三薄膜晶体管处于截止状态，第一发光控制信号控制所述第七薄膜晶体管处于导通状态，参考电压对所述第一薄膜晶体管的栅极、所述存储电容的两端以及所述发光二极管的阳极进行初始化，第二发光控制信号控制所述第六薄膜晶体管由导通状态变为截止状态；
    第二阶段，所述第一扫描信号控制所述第二薄膜晶体管、所述第四薄膜晶体管以及所述第五薄膜晶体管处于导通状态，所述第二扫描信号控制所述第三薄膜晶体管处于截止状态，所述第一发光控制信号控制所述第七薄膜晶体管由导通状态变为截止状态，所述第二发光控制信号控制所述第六薄膜晶 体管由截止状态变为导通状态，对所述第一薄膜晶体管的阈值电压进行补偿；
    第三阶段，所述第一扫描信号控制所述第二薄膜晶体管、所述第四薄膜晶体管以及所述第五薄膜晶体管由导通状态变为截止状态，所述第二扫描信号控制所述第三薄膜晶体管由截止状态变为导通状态，数据电压向所述存储电容的另一端施加电压，所述第一发光控制信号控制所述第七薄膜晶体管处于截止状态，所述第二发光控制信号控制所述第六薄膜晶体管由导通状态变为截止状态；
    第四阶段，所述第一扫描信号控制所述第二薄膜晶体管、所述第四薄膜晶体管以及所述第五薄膜晶体管处于截止状态，所述第二扫描信号控制所述第三薄膜晶体管由导通状态变为截止状态，所述第一发光控制信号控制所述第七薄膜晶体管由截止状态变为导通状态，所述第二发光控制信号控制所述第六薄膜晶体管由截止状态变为导通状态，所述发光二极管发光。
  13. 如权利要求12所述的驱动方法，其中：
    在所述第一阶段，所述存储电容两端的电压以及所述第一薄膜晶体管的栅极电压均为Vref，Vref为所述参考电压。
  14. 如权利要求12所述的驱动方法，其中：
    在所述第二阶段，所述第一薄膜晶体管的栅极与漏极连接，所述第一电源向所述第一薄膜晶体管的源极施加电压，使得所述第一薄膜晶体管的栅极电压为VDD-Vth，对所述第一薄膜晶体管的阈值电压进行补偿，其中，Vth为所述第一薄膜晶体管的阈值电压，VDD为所述第一电源。
  15. 如权利要求12所述的驱动方法，其中：
    在所述第三阶段，所述存储电容的所述另一端的电压由Vref变为Vdata，在所述存储电容的作用下，所述第一薄膜晶体管的栅极电压为VDD-Vth+Vdata-Vref，使得在所述第四阶段，流经所述发光二极管的电流与所述第一电源无关，其中，Vdata为所述数据电压。
  16. 一种显示装置，其中，所述显示装置包括如权利要求1至11任一项所述的像素电路。
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