WO2019078267A1 - Transistor à couches minces organiques, son procédé de fabrication, réseau matriciel actif et dispositif d'affichage d'image - Google Patents

Transistor à couches minces organiques, son procédé de fabrication, réseau matriciel actif et dispositif d'affichage d'image Download PDF

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WO2019078267A1
WO2019078267A1 PCT/JP2018/038701 JP2018038701W WO2019078267A1 WO 2019078267 A1 WO2019078267 A1 WO 2019078267A1 JP 2018038701 W JP2018038701 W JP 2018038701W WO 2019078267 A1 WO2019078267 A1 WO 2019078267A1
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insulating layer
electrode
thin film
organic thin
film transistor
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PCT/JP2018/038701
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English (en)
Japanese (ja)
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典昭 池田
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凸版印刷株式会社
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to an organic thin film transistor, a method of manufacturing the same, an active matrix array, and an image display device.
  • Thin film transistors are widely used in active matrix display devices and sensors, such as liquid crystal display devices (LCDs), organic electroluminescence (EL) display devices, electronic paper display devices, and the like.
  • LCDs liquid crystal display devices
  • EL organic electroluminescence
  • electronic paper display devices and the like.
  • semiconductor materials used for thin film transistors those using amorphous silicon, polycrystalline silicon, oxide semiconductors, etc. are in the mainstream, and thin film transistors using these semiconductor materials use a vacuum deposition method. After film formation, patterning is generally performed by a photolithography method or the like.
  • organic thin film transistors using an organic material as a semiconductor material have attracted attention.
  • devices are formed on plastic substrates at low temperatures by using wet film formation methods such as coating and printing techniques with solutions such as semiconductor materials, conductive materials and insulating materials, and at low cost.
  • wet film formation methods such as coating and printing techniques with solutions such as semiconductor materials, conductive materials and insulating materials, and at low cost.
  • the printing method it is possible to simultaneously perform the film formation and the patterning process, and it is possible to increase the material utilization efficiency as compared with the vacuum film formation process using the conventional photolithography process.
  • the development and etching steps are not required, it is also expected that the environmental load is small (Non-Patent Document 1).
  • the bottom of a structure which forms an insulating layer on a top gate structure and a gate electrode which forms a gate electrode via an insulating layer on a semiconductor layer, and forms a semiconductor layer on it Two of the gate structures are known.
  • the insulating layer, the source electrode, and the drain electrode are formed rather than the top gate structure formed in the early stage of the thin film transistor manufacturing process. It is preferable that damage such as heat load to the semiconductor layer in the thin film transistor manufacturing process be smaller.
  • the bottom gate structure has a simpler element configuration. From such a point, it is preferable to adopt a bottom gate structure for manufacturing a thin film transistor by a printing method.
  • thin film transistors formed by the printing method are inferior in alignment accuracy and patterning accuracy as compared with the conventional photolithography process, and therefore, in consideration of the yield, the dimension of each layer of the thin film transistor is designed with allowance. It is preferable to do.
  • the area of the thin film transistor becomes large.
  • the area that can be used for the capacitor electrode functioning as a storage capacitor is limited, and it is difficult to obtain sufficient capacitance.
  • the voltage holding ratio of the image display device decreases, and rewriting of the display elements of the image display device becomes difficult. Therefore, the rewriting time increases and the power consumption increases with the decrease in display quality or the increase in the number of rewrites. A problem arises.
  • the semiconductor layer has a smaller characteristic (mobility) of the semiconductor layer compared with an oxide semiconductor or the like, in order to obtain higher element characteristic (semiconductor characteristic), a channel of a large size is obtained. Space is required.
  • a thin film transistor having an upper pixel electrode called a field shield pixel structure in order to keep the aperture ratio large. The structure is preferably used.
  • the voltage applied to the upper pixel electrode connected to the drain electrode affects the back channel portion in the channel region of the semiconductor layer, causing a change in the device characteristics of the organic thin film transistor It will In particular, when the device is used as an element operated at a large driving voltage, the influence becomes remarkable, and changes occur in the forward characteristics and the reverse characteristics of the organic thin film transistor.
  • the present invention has been made in view of the above points, and in an organic thin film transistor of a field shield pixel type bottom gate structure, it is possible to stably drive an organic thin film while maintaining semiconductor characteristics while securing a sufficient capacitance. It is an object of the present invention to provide a thin film transistor, a method of manufacturing the same, an active matrix array, and an image display device.
  • One aspect of the present invention for solving the above problems is an insulating substrate, a gate electrode formed over the substrate, a first insulating layer formed to cover the substrate and the gate electrode, and A semiconductor layer including a source electrode, a drain electrode, and an organic semiconductor material formed on the insulating layer, and a second insulating layer formed to cover at least a part of the semiconductor layer, the source electrode, and the drain electrode; A third capacitor electrode formed on the second insulating layer so as to cover at least the semiconductor layer in a plan view, a first capacitor electrode, a second insulating layer, and the first capacitor electrode It is an organic thin film transistor including a layer and an upper pixel electrode electrically connected to the drain electrode, which is formed on the third insulating layer.
  • a second capacitor electrode may be further provided in the same layer as the gate electrode over the insulating substrate.
  • the film thickness of the second insulating layer may be larger than the film thicknesses of the first insulating layer and the third insulating layer.
  • the thickness of the third insulating layer may be smaller than the thicknesses of the first insulating layer and the second insulating layer.
  • the relative dielectric constant of the third insulating layer may be larger than the relative dielectric constant of the second insulating layer.
  • the area of a region where the first capacitor electrode and the upper pixel electrode overlap in plan view may be 80% or more of the area of the upper pixel electrode.
  • the area where the first capacitor electrode and the substrate overlap in plan view may be 85% or more of the area of the substrate.
  • the first capacitor electrode may have a via hole communicating the second insulating layer with the third insulating layer, and may cover the entire top surface of the second insulating layer in a region other than the via hole in plan view.
  • another aspect of the present invention is a step of providing a gate electrode on an insulating substrate, a step of providing a first insulating layer on the gate electrode, and a source electrode and a drain electrode on the first insulating layer.
  • a semiconductor layer including an organic semiconductor material between the source electrode and the drain electrode Separately providing a semiconductor layer including an organic semiconductor material between the source electrode and the drain electrode; and forming a second insulating layer on at least a portion of the semiconductor layer, the source electrode, and the drain electrode.
  • a step of providing an upper pixel electrode electrically connected to the drain electrode on the third insulating layer is a step of providing a gate electrode on an insulating substrate, a step of providing a first insulating layer on the gate electrode, and a source electrode and a drain electrode on the first insulating layer.
  • Another aspect of the present invention is an active matrix array in which the organic thin film transistors described above are arrayed, wherein the first capacitor electrode of the organic thin film transistor in the active matrix array is the four or more neighboring organic thin film transistors It is an active matrix array connected to one capacitor electrode.
  • Another aspect of the present invention is an active matrix array in which the above-mentioned organic thin film transistors are arrayed, in the organic thin film transistors in the active matrix array, first capacitor electrodes of all adjacent organic thin film transistors are connected to each other Active matrix array.
  • Another aspect of the present invention is an image display apparatus using the above-mentioned active matrix array.
  • an organic thin film transistor of a field shield pixel type bottom gate structure an organic thin film transistor capable of stably driving while maintaining semiconductor characteristics while securing a sufficient capacitance, a manufacturing method thereof, and an active matrix array And an image display apparatus can be provided.
  • FIG. 1 is a schematic cross-sectional view of an organic thin film transistor according to a first embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of an organic thin film transistor according to a second embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional view of an organic thin film transistor according to a third embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional view of an organic thin film transistor according to a comparative example.
  • FIG. 5 is a graph of the transfer characteristics of the organic thin film transistors according to Example 1 and Comparative Example.
  • FIG. 6 is a schematic plan view of an active matrix array according to the first embodiment of the present invention.
  • FIG. 7 is a schematic plan view of an active matrix array according to a second embodiment and a third embodiment of the present invention.
  • FIG. 1 is a schematic cross-sectional view showing an organic thin film transistor 100 according to a first embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional view showing an organic thin film transistor 101 according to a second embodiment of the present invention
  • FIG. 3 is a schematic cross-sectional view showing an organic thin film transistor 102 according to a third embodiment of the present invention.
  • the organic thin film transistors 100, 101, and 102 each include a gate electrode 2 formed on an insulating substrate 1, a first insulating layer 3, a source electrode 4, a drain electrode 5, and a semiconductor layer 6 including an organic semiconductor material.
  • the second insulating layer 7, the first capacitor electrode 8, the third insulating layer 9, and the upper pixel electrode 10 at least.
  • the organic thin film transistor 102 further includes a second capacitor electrode 11 in addition to the configuration of the organic thin film transistor 100.
  • the gate electrode 2 is formed on the substrate 1, and the first insulating layer 3 is formed on the substrate 1 and the gate electrode 2.
  • the source electrode 4, the drain electrode 5, and the semiconductor layer 6 are formed on the first insulating layer 3, and the second insulation is formed on at least a part of the source electrode 4, the drain electrode 5, and the semiconductor layer 6.
  • the layer 7 is formed, the first capacitor electrode 8 is formed on the second insulating layer 7, and the third insulating layer 9 is formed on at least a part of the first capacitor electrode 8
  • the upper pixel electrode 10 electrically connected to the drain electrode 5 is formed on the third insulating layer 9.
  • the first capacitor electrode 8 overlaps at least a part of the upper pixel electrode 10 in plan view.
  • the first capacitor electrode 8 can be formed in a large area by setting the position for forming the first capacitor electrode 8 on the second insulating layer 7 on which the other electrode is not provided. Therefore, a large capacitance can be generated between the first capacitor electrode 8 and the upper pixel electrode 10.
  • the first capacitor electrode 8 is formed to overlap at least the semiconductor layer 6 in plan view. Thereby, since the influence of the voltage applied to the upper pixel electrode 10 on the back channel portion of the semiconductor layer 6 can be blocked, forward characteristics in the case where the organic thin film transistors 100, 101, 102 are operated with a large drive voltage It is possible to suppress the change with the reverse direction characteristic.
  • the drain electrode 5 and the upper pixel electrode 10 are connected via a via hole formed in the second insulating layer 7 and the third insulating layer 9. Further, as shown in FIGS. 2 and 3, in the organic thin film transistors 101 and 102, the drain electrode 5 and the upper pixel electrode 10 are the second insulating layer 7, the first capacitor electrode 8, and the third insulating layer. It is connected through the via hole formed in 9. As shown in FIGS. 2 and 3, in the organic thin film transistors 101 and 102, the first capacitor electrode 8 is formed to cover the entire upper surface of the second insulating layer 7 in a region other than the via hole in plan view. ing. Thereby, since the first capacitor electrode 8 can be formed in a wider area, the capacitance generated between the first capacitor electrode 8 and the upper pixel electrode 10 can be further increased.
  • the second capacitor electrode 11 is further formed on the substrate 1, and the second capacitor electrode 11 is a drain electrode in plan view with the first insulating layer 3 interposed therebetween. It overlaps with at least a part of 5.
  • FIG. 6 is a schematic plan view of an active matrix array 110 according to the first embodiment of the present invention.
  • the active matrix array 110 is formed by arranging the organic thin film transistors 100 in a matrix.
  • the first capacitor electrode 8 of each organic thin film transistor 100 is electrically connected to the first capacitor electrode 8 of the adjacent four organic thin film transistors 100 via a wire. It is formed.
  • FIG. 7 is a schematic plan view of active matrix arrays 111 and 112 according to the second and third embodiments of the present invention. Also in FIG. 7, the description of the third insulating layer 9 and the upper pixel electrode 10 is omitted in order to clarify the shape of the first capacitor electrode 8.
  • the active matrix arrays 111 and 112 are formed by arranging the organic thin film transistors 101 and the organic thin film transistors 102 in a matrix. As described above, in the organic thin film transistors 101 and 102, the first capacitor electrode 8 is formed to cover the second insulating layer 7 in a region other than the via hole in a plan view. Therefore, as shown in FIG. 7, in the active matrix arrays 111 and 112, the first capacitor electrodes 8 of the organic thin film transistors 101 and 102 are in contact with the first capacitor electrodes 8 of all the adjacent organic thin film transistors 100 and 101. Are electrically connected.
  • the difference between the organic thin film transistors 100 and 101 and the organic thin film transistor 102 is the presence or absence of the second capacitor electrode 11. As shown in FIG. 3, by forming the second capacitor electrode 11 in the organic thin film transistor 102, a capacitance is generated between the drain electrode 5 and the second capacitor electrode 11, so that the pixel electrode of the organic thin film transistor It is possible to further increase the capacitance.
  • an image can be obtained. It can be a display device.
  • the structure of the counter electrode and the second substrate can be appropriately changed according to the type of display element used.
  • each component of the organic thin film transistor 100, 101, 102 will be described along the manufacturing process of the organic thin film transistor 100, 101, 102.
  • the substrate 1 is prepared.
  • the material of the substrate 1 is polycarbonate, polyethylene sulfide, polyether sulfone, polyethylene terephthalate, polyethylene naphthalate, cycloolefin polymer, triacetyl cellulose, polyvinyl fluoride film, ethylene-tetrafluoroethylene copolymer resin, weather resistant polyethylene terephthalate, Although weather resistant polypropylene, glass fiber reinforced acrylic resin film, glass fiber reinforced polycarbonate, polyimide, fluorocarbon resin, cyclic polyolefin resin, glass, quartz glass and the like can be used, it is not limited thereto. These may be used alone, but can also be used as a composite substrate 1 in which two or more kinds are stacked.
  • a transparent gas barrier layer (not shown) can also be formed to improve the durability of the organic thin film transistors 100, 101, 102.
  • Materials for the gas barrier layer include aluminum oxide (Al 2 O 3 ), silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), diamond like carbon (DLC), etc. Is not limited to these.
  • these gas barrier layers can be used by laminating two or more layers.
  • the gas barrier layer may be formed only on one side of the substrate 1 using the organic film, or may be formed on both sides.
  • the gas barrier layer can be formed by vacuum deposition, ion plating, sputtering, laser ablation, plasma CVD (Chemical Vapor Deposition), hot wire CVD, sol-gel, etc. In the present invention, however, It is not limited to these.
  • an adhesion layer can be provided to improve adhesion between the substrate 1 and the gate electrode 2 and the first insulating layer 3 formed in contact with the substrate 1, or the surface treatment of the surface of the substrate 1, etc. You may
  • the gate electrode 2 is formed on the substrate 1.
  • the gate electrode 2, the source electrode 4, the drain electrode 5, the first capacitor electrode 8, and the second capacitor electrode 11 do not have to be clearly divided into an electrode portion and a wiring portion.
  • the gate electrode 2 aluminum (Al), copper (Cu), molybdenum (Mo), silver (Ag), chromium (Cr), titanium (Ti), gold (Au), platinum (Pt), tungsten (W) ,
  • Metal materials such as manganese (Mn), niobium (Nb), tantalum (Ta), indium oxide (InO), tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (indium oxide Conductive metal oxide materials such as IZO) can be used, but are not limited thereto. These materials may be used as a single layer, or may be used as a laminate and an alloy.
  • the gate electrode 2 can be formed by a vacuum deposition method such as a vacuum evaporation method or a sputtering method, a sol-gel method using a precursor of a conductive material, a method using nanoparticles, or the like, and Although the method of forming by wet film-forming methods, such as screen printing, a letterpress printing, an inkjet method, etc. can be used, it is not limited to these, A well-known general method can be used.
  • the patterning can be performed, for example, by using a photolithographic method to protect the pattern-formed portion with a resist or the like, removing unnecessary portions by etching, or directly patterning using a printing method or the like. Also, the present invention is not limited to these methods, and publicly known general patterning methods can be used.
  • the second capacitor electrode 11 is provided on the substrate 1 in order to increase the capacitance of the organic thin film transistor.
  • the second capacitor electrode 11 can be formed by the same material and method as the gate electrode 2, but may be formed using another material and method or the like.
  • the first insulating layer 3 is formed.
  • the first insulating layer 3 is provided at least on the gate electrode 2 in order to electrically insulate between the electrodes such as the gate electrode 2, the source electrode 4, and the drain electrode 5, but the outside of the gate electrode 2 It may be provided on the entire surface of the substrate 1 except for the wiring portion and the pad portion used for connection with the other electrodes.
  • oxide-based insulation such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), etc.
  • materials and organic insulating materials such as silicon nitride (SiNx), silicon oxynitride (SiON), polyacrylates such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), etc. Although it can be done, it is not limited to these.
  • a single layer or two or more layers may be laminated, or an inorganic-organic hybrid thin film may be used, or the composition may be inclined in the growth direction.
  • the first insulating layer 3 preferably has a resistivity of 10 11 ⁇ cm or more, more preferably 10 14 ⁇ cm or more, in order to suppress the leakage current in the organic thin film transistors 100, 101, 102.
  • the source electrode 4 and the drain electrode 5 are formed.
  • the source electrode 4 and the drain electrode 5 are formed separately from each other, and the source electrode 4 and the drain electrode 5 may be formed of different processes and different materials, respectively, but on the first insulating layer 3 When forming in the same layer, it is preferable to form the source electrode 4 and the drain electrode 5 simultaneously.
  • the same conductive material as the gate electrode 2 can be used for the source electrode 4 and the drain electrode 5. In addition, they may be laminated and used, or may be used as an alloy or the like.
  • the source electrode 4 and the drain electrode 5 can be formed by a vacuum deposition method such as vacuum evaporation or sputtering, a sol-gel method using a precursor of a conductive material, a method using nanoparticles, or the like.
  • a method of forming an ink and forming it by a wet film forming method such as screen printing, letterpress printing, an inkjet method, etc. can be used, but it is not limited thereto, and publicly known general methods can be used.
  • the patterning can be performed, for example, by using a photolithographic method to protect the pattern-formed portion with a resist or the like, removing unnecessary portions by etching, or directly patterning using a printing method or the like. Also, the present invention is not limited to these methods, and publicly known general patterning methods can be used.
  • the source electrode 4 and the drain electrode 5 may have a bottom contact structure in which the source electrode 4 and the drain electrode 5 are formed earlier than the semiconductor layer 6. After forming the semiconductor layer 6, the source electrode 4 and the drain electrode 5 may be used. It may be a top contact structure to be formed.
  • the source electrode 4 and the drain electrode 5 can use surface treatment or the like to reduce the contact resistance in the electrical connection with the semiconductor layer 6. Specifically, changing the work function of the electrode surface by forming a molecular film such as a self-assembled monolayer (SAM: Self-Assembled-Monolayer) on the surfaces of the source electrode 4 and the drain electrode 5 It is possible.
  • SAM Self-Assembled-Monolayer
  • the semiconductor layer 6 is formed between the source electrode 4 and the drain electrode 5 so as to connect the source electrode 4 and the drain electrode 5.
  • the source electrode 4 and the drain electrode 5 are connected by the semiconductor layer 6 and a region of the semiconductor layer 6 functioning as an organic thin film transistor is generally referred to as a channel region, and such a name is also used in the present invention. There is.
  • the semiconductor layer 6 use is made of low molecular weight organic semiconductor materials such as pentacene and derivatives thereof, high molecular organic semiconductor materials such as polythiophene, polyallylamine and fluorene bithiophene copolymer, and derivatives thereof Although it is possible, it is not limited to these.
  • the semiconductor layer 6 can also be formed by a wet film forming method such as letterpress printing, screen printing, inkjet, nozzle printing, etc. using a solution in which an organic semiconductor material is dissolved or dispersed as an ink, or a powder or crystal of an organic semiconductor material Can be formed by vapor deposition in a vacuum state.
  • the formation method of the semiconductor layer 6 is not limited to these, It is also possible to use a well-known general method.
  • wet film formation (printing) drying and baking may be performed to form the semiconductor layer 6. In the present application, it may be referred to as firing including drying.
  • a protective layer for protecting the semiconductor layer 6 may be provided on the semiconductor layer 6.
  • the second insulating layer 7 is formed to cover at least the channel region of the semiconductor layer 6.
  • the second insulating layer 7 is used to secure the insulation of each electrode in the organic thin film transistors 100, 101, 102, and also outside the channel region and the outside of the source electrode 4 and its electrodes such as wiring and drain electrode 5 and others. It can also be formed on the entire surface of the first insulating layer 3 except for the connection portion with the electrode, and the region to be formed can be appropriately adjusted.
  • oxide-based insulation such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), etc.
  • materials and organic insulating materials such as silicon nitride (SiNx), silicon oxynitride (SiON), polyacrylates such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), and fluorine resin
  • PMMA polymethyl methacrylate
  • PVA polyvinyl alcohol
  • PVP polyvinyl phenol
  • fluorine resin fluorine resin
  • the second insulating layer 7 desirably has a resistivity of 10 11 ⁇ cm or more, more preferably 10 14 ⁇ cm or more, in order to suppress the leak current in the organic thin film transistors 100, 101, 102.
  • the thickness of the second insulating layer 7 is preferably larger than that of the first insulating layer 3 and the third insulating layer 9.
  • the first capacitor electrode 8 has an effect of blocking the influence of the voltage applied to the upper pixel electrode 10 on the back channel portion of the semiconductor layer 6, and in the organic thin film transistors 100, 101, 102 of the present invention, The current applied to the semiconductor layer 6 is controlled by the voltage applied to the gate electrode 2 through the first insulating layer 3, but the film thickness of the second insulating layer 7 is thinner than that of the first insulating layer 3.
  • the capacitance generated between the semiconductor layer 6 and the first capacitor electrode 8 may be larger than the capacitance generated between the gate electrode 2 and the semiconductor layer 6, Depending on the voltage applied to the capacitor electrode 8 of the above, it may act on the back channel portion of the semiconductor layer 6, and the device characteristics of the organic thin film transistors 100, 101, 102 may be changed. Therefore, in order to control the conductivity of the semiconductor layer 6 reliably by the voltage of the gate electrode 2, it is preferable to form the second insulating layer 7 with a thickness larger than that of the first insulating layer 3. .
  • the relative dielectric constant of the second insulating layer 7 is preferably 5 or less, more preferably 4 or less.
  • the capacitance generated between the first capacitor electrode 8 and the drain electrode 5 and the upper pixel electrode 10 is used as a storage capacitance.
  • the film thickness of the second insulating layer 7 is preferably larger for the reasons described above. The capacitance generated between the capacitor electrode 8 and the drain electrode 5 is reduced. Therefore, in order to secure sufficient storage capacitance, it is necessary to increase the capacitance generated between the first capacitor electrode 8 and the upper pixel electrode 10, so It is preferable to make it thinner than the thickness of the second insulating layer 7.
  • the second insulating layer 7 may be formed by a vacuum deposition method such as a vacuum evaporation method or a sputtering method, a sol-gel method using a metal complex as a precursor, or a slit coat of an ink in which nanoparticles or the like are dispersed.
  • a vacuum deposition method such as a vacuum evaporation method or a sputtering method, a sol-gel method using a metal complex as a precursor, or a slit coat of an ink in which nanoparticles or the like are dispersed.
  • a method of forming by a wet film forming method such as spin coating, screen printing, letterpress printing, ink jet, etc. can be used, it is not limited to these, and publicly known general methods can be used.
  • the first capacitor electrode 8 is formed on the second insulating layer 7 in a region overlapping at least the channel region in plan view.
  • the first capacitor electrode 8 can be formed by the same material and method as the gate electrode 2, the source electrode 4 and the drain electrode 5 described above.
  • the first capacitor electrode 8 overlaps at least the semiconductor layer 6 in plan view for the purpose of blocking the influence of the voltage applied to the upper pixel electrodes 10 of the organic thin film transistors 100, 101, 102 on the channel region of the semiconductor 6. Thus, at least a part of the first capacitor electrode 8 is formed to cover the channel region.
  • the first capacitor electrode 8 When forming the active matrix arrays 110, 111, 112 by arranging the organic thin film transistors 100, 101, 102, the first capacitor electrode 8 is adjacent to the gate electrode 2 or the source electrode 4 by wiring or the like. It is connected to the first capacitor electrode 8 of the organic thin film transistor 100, 101, 102.
  • the first capacitor electrode 8 is preferably connected to the first capacitor electrode 8 of the surrounding adjacent four or more organic thin film transistors, and more preferably, all adjacent surrounding organic thin film transistors The first capacitor electrodes 8 are connected to each other.
  • the connection between the first capacitor electrodes 8 is not particularly required to be divided into the wiring portion, the electrode portion, and the like, and the shape can be appropriately adjusted in accordance with the structure of the organic thin film transistor.
  • the first capacitor electrodes 8 of the adjacent adjacent organic thin film transistors 100, 101, 102 By thus connecting the first capacitor electrodes 8 of the adjacent adjacent organic thin film transistors 100, 101, 102 to one another, the first capacitor electrodes 8 can be made of some of the first capacitor electrodes 8 Even when a defect occurs in the pattern, the connection between the first capacitor electrodes 8 is secured without disconnection in the active matrix arrays 110, 111, 112.
  • the first capacitor electrodes 8 are electrically connected to the first capacitor electrodes 8 of the adjacent four organic thin film transistors 100 via the wirings.
  • Each organic thin film transistor 100 formed in this manner can operate as an organic thin film transistor if at least one of four wirings is connected. Therefore, the active matrix array 110 can suppress the operation failure of the organic thin film transistor due to the disconnection of the wiring between the first capacitor electrodes 8.
  • the first capacitor electrode 8 is broken for the reasons as described above. It is possible to prevent the operation failure of the organic thin film transistor. In particular, in a method such as printing, remarkable effects can be obtained by forming the first capacitor electrode 8 as described above.
  • the first capacitor electrode 8 has an area of the substrate in order to more efficiently block the influence of the voltage applied to the upper pixel electrode 10 and to generate a larger capacitance with the upper pixel electrode 10. Preferably, it is formed to be 85% or more of the area of 1.
  • the third insulating layer 9 is formed on at least the first capacitor electrode 8.
  • the third insulating layer 9 is provided for securing the insulation between the first capacitor electrode 8 and the upper pixel electrode 10 in the organic thin film transistors 100, 101, 102, but other than on the first capacitor electrode 8.
  • the second insulating layer 7 can be formed on the second insulating layer 7 except for the connection portions with the outside and other electrodes, and the region to be formed can be appropriately adjusted.
  • the third insulating layer 9 may be an oxide insulating material such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx) or hafnium oxide (HfOx).
  • oxide insulating material such as silicon oxide (SiOx), aluminum oxide (AlOx), tantalum oxide (TaOx), yttrium oxide (YOx), zirconium oxide (ZrOx) or hafnium oxide (HfOx).
  • Uses materials and organic insulating materials such as silicon nitride (SiNx), silicon oxynitride (SiON), polyacrylates such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), and fluorine resin Although it can do, it is not limited to these.
  • a single layer or two or more layers may be laminated, or an inorganic
  • the third insulating layer 9 may be formed by a vacuum deposition method such as a vacuum evaporation method or a sputtering method, a sol-gel method using a metal complex as a precursor, a slit coating of ink in which nanoparticles are dispersed, spin
  • a vacuum deposition method such as a vacuum evaporation method or a sputtering method
  • a sol-gel method using a metal complex as a precursor a slit coating of ink in which nanoparticles are dispersed
  • spin a method of forming by wet film-forming methods, such as a coat, screen printing, relief printing, an inkjet, etc.
  • wet film-forming methods such as a coat, screen printing, relief printing, an inkjet, etc.
  • the third insulating layer 9 is formed between the first capacitor electrode 8 and the upper pixel electrode 10, and capacitance occurs in a region where the first capacitor electrode 8 and the upper pixel electrode 10 overlap in a plan view. It is formed for the purpose of In general, by using a material having a large relative dielectric constant as the material of the insulating layer, it is possible to obtain a larger capacitance even with the same film thickness. Further, as described above, in view of the influence of the voltage affecting the semiconductor layer 6 in the second insulating layer 7, it is preferable that the relative dielectric constant of the second insulating layer 7 is small, so that the third insulating layer 7 is preferable.
  • the relative dielectric constant of 9 is preferably larger than that of the second insulating layer 7.
  • the relative dielectric constant is preferably 3.0 or more, preferably 5 or more, and more preferably 20 or more, but is not limited thereto.
  • the film thickness of the third insulating layer 9 is larger than that of the first insulating layer 3 and the second insulating layer 7 in order to generate a larger capacitance between the first capacitor electrode 8 and the upper pixel electrode 10.
  • the thickness is preferably smaller than the film thickness, but the thickness can be appropriately adjusted in consideration of the insulating property of the third insulating layer 9, the reliability as the organic thin film transistors 100, 101, 102, the degree of difficulty of the manufacturing process, and the like.
  • the third insulating layer 9 is An upper pixel electrode 10 electrically connected to the drain electrode 5 is formed thereon.
  • the overlapping area of the upper pixel electrode 10 and the first capacitor electrode 8 is a capacitor area functioning as a storage capacitor of the image display device, and the larger the overlapping area, the larger the capacitor capacity, and the voltage holding ratio of the pixel voltage Can be kept high.
  • the overlapping area of the upper pixel electrode 10 and the first capacitor electrode 8 is small and the capacitance of the capacitor is small, the voltage holding ratio is small. Therefore, when the organic thin film transistors 100, 101 and 102 of the present invention are used as an image display device Since the pixel voltage applied to the display element by the upper pixel electrode is attenuated during the selection time, and the voltage applied to the image display element is reduced by the amount of reduction in the pixel voltage, the rewriting efficiency is reduced.
  • the quality is reduced. Although it is possible to take measures to increase the number of rewrites in order to maintain display quality, an increase in the number of image rewrites results in an increase in power consumption due to a decrease in image switching speed and an increase in drive time.
  • the overlapping area of the upper pixel electrode 10 and the first capacitor electrode 8 is 80% or more, preferably 85% or more. It is preferable to form so that
  • the upper pixel electrode 10 can be formed by the same material and method as the gate electrode 2, the source electrode 4, the drain electrode 5 and the first capacitor electrode 8 shown above, but the invention is not limited thereto. The method of can be used.
  • a display element (not shown), a counter electrode (not shown), and a counter substrate (not shown) are suitably provided.
  • liquid crystal, electrophoretic particles, microcapsules containing electrophoretic particles, organic electroluminescence and the like can be used.
  • the image display device it is possible to use these known general display elements without being limited to either the reflective type or the transmissive type.
  • the display element may be formed on the counter substrate on which the counter electrode is formed, and then combined with the organic thin film transistors 100, 101, and 102 provided with the pixel electrode 10 to form an image display device.
  • the counter electrode and the counter substrate may be stacked to form an image display device, and the process can be selected in accordance with the display element to be used.
  • Example 1 an active matrix array 110 composed of the organic thin film transistor 100 shown in FIG. 1 was produced.
  • An alkali-free glass 0.7 mm thick was used as the substrate 1.
  • a solution in which nanoparticles of silver (Ag) were dispersed on a substrate 1 was patterned into a desired shape using an ink jet method as an ink, and baked at 180 ° C. for 1 hour to form a gate electrode 2.
  • thermosetting resin was applied to the substrate 1 on which the gate electrode 2 was formed and fired to form a first insulating layer 3.
  • the relative dielectric constant of the first insulating layer 3 is 3.3, and the film thickness is 1.0 ⁇ m.
  • the source electrode 4 and the drain electrode 5 were formed by the ink jet method in the same manner as the gate electrode 2.
  • a mesitylene solution in which 6,13-bis (triisopropylsilylethynyl) pentacene (TIPS-pentacene) is dissolved at a concentration of 0.1% by weight as an organic semiconductor material is inkjetted
  • the semiconductor layer 6 was formed by patterning by a method and baking.
  • a fluorine resin is applied by an inkjet method and fired to form a second insulating layer 7.
  • the relative dielectric constant of the second insulating layer 7 is 2.4, and the film thickness is 3.0 ⁇ m.
  • the first capacitor electrode 8 was formed on the second insulating layer 7 by the same method as the gate electrode 2, the source electrode 4 and the drain electrode 5, using a solution in which silver nanoparticles are dispersed as an ink.
  • a photosensitive resin material was applied onto the first capacitor electrode 8, exposed to light, and developed to form a third insulating layer 9.
  • the film thickness of the third insulating layer 9 is 0.5 ⁇ m, and the relative dielectric constant is 3.5.
  • each first capacitor electrode 8 is connected to the first capacitor electrode 8 of the adjacent four organic thin film transistors 100 via a wire, and formed to be conductive.
  • the upper pixel electrode 10 was formed on the third insulating layer 9 using the screen printing method, and an active matrix array 110 composed of the organic thin film transistor 100 according to Example 1 was manufactured.
  • Example 2 an active matrix array 111 composed of the organic thin film transistor 101 shown in FIG. 2 was produced.
  • An alkali-free glass 0.7 mm thick was used as the substrate 1.
  • a solution in which nanoparticles of silver (Ag) were dispersed on a substrate 1 was patterned into a desired shape using an ink jet method as an ink, and baked at 180 ° C. for 1 hour to form a gate electrode 2.
  • thermosetting resin was applied to the substrate 1 on which the gate electrode 2 was formed and fired to form a first insulating layer 3.
  • the relative dielectric constant of the first insulating layer 3 is 3.3, and the film thickness is 1.0 ⁇ m.
  • the source electrode 4 and the drain electrode 5 were formed by the ink jet method in the same manner as the gate electrode 2.
  • a mesitylene solution in which TIPS-pentacene was dissolved at a concentration of 0.1% by weight as an organic semiconductor material was patterned by an inkjet method and baked to form a semiconductor layer 6 .
  • a fluorine resin was applied by an inkjet method to form a second insulating layer 7.
  • the relative dielectric constant of the second insulating layer 7 is 2.4, and the film thickness is 3.0 ⁇ m.
  • the first capacitor electrode 8 was formed on the second insulating layer 7 by the same method as the gate electrode 2, the source electrode 4 and the drain electrode 5, using a solution in which silver nanoparticles are dispersed as an ink.
  • each first capacitor electrode 8 is connected to the first capacitor electrode 8 of all the adjacent organic thin film transistors 101 and formed to be conductive.
  • a photosensitive resin material was applied onto the first capacitor electrode 8, exposed to light, and developed to form a third insulating layer 9.
  • the film thickness of the third insulating layer 9 is 0.5 ⁇ m, and the relative dielectric constant is 3.5.
  • the upper pixel electrode 10 was formed on the third insulating layer 9 using the screen printing method, and an active matrix array 111 composed of the organic thin film transistor 101 according to Example 2 was manufactured.
  • Example 3 an active matrix array 112 composed of the organic thin film transistor 102 shown in FIG. 3 was produced.
  • An alkali-free glass 0.7 mm thick was used as the substrate 1.
  • a solution in which nanoparticles of silver (Ag) are dispersed on a substrate 1 is patterned into a desired shape using an ink jet method as an ink, and baked at 180 ° C. for 1 hour to form gate electrode 2 and second capacitor electrode 11. Formed.
  • thermosetting resin was applied to the substrate 1 on which the gate electrode 2 and the second capacitor electrode 11 were formed and fired to form the first insulating layer 3.
  • the relative dielectric constant of the first insulating layer 3 is 3.3, and the film thickness is 1.0 ⁇ m.
  • the source electrode 4 and the drain electrode 5 are formed by the inkjet method in the same manner as the gate electrode 2 and the second capacitor electrode 11.
  • a mesitylene solution in which TIPS-pentacene was dissolved at a concentration of 0.1% by weight as an organic semiconductor material was patterned by an inkjet method and baked to form a semiconductor layer 6 .
  • a fluorine resin was applied by an inkjet method to form a second insulating layer 7.
  • the relative dielectric constant of the second insulating layer 7 is 2.4, and the film thickness is 3.0 ⁇ m.
  • the first capacitor electrode 8 was formed on the second insulating layer 7 by the same method as the gate electrode 2, the source electrode 4 and the drain electrode 5, using a solution in which silver nanoparticles are dispersed as an ink.
  • Each first capacitor electrode 8 is connected to the first capacitor electrode 8 of all the adjacent organic thin film transistors 102 as in the second embodiment, and formed to be conductive.
  • a photosensitive resin material was applied onto the first capacitor electrode 8, exposed to light, and developed to form a third insulating layer 9.
  • the film thickness of the third insulating layer 9 is 0.5 ⁇ m, and the relative dielectric constant is 3.5.
  • the upper pixel electrode 10 was formed on the third insulating layer 9 using the screen printing method, and an active matrix array 112 composed of the organic thin film transistor 102 according to Example 3 was manufactured.
  • An active matrix array (not shown) comprising the organic thin film transistor 200 shown in FIG. 4 was produced as a comparative example.
  • An alkali-free glass 0.7 mm thick was used as the substrate 21.
  • a solution in which nanoparticles of silver (Ag) are dispersed on a substrate 21 is patterned into a desired shape using an ink jet method as an ink, and baked at 180 ° C. for 1 hour to form a gate electrode 22 and a first capacitor electrode 28. Formed.
  • thermosetting resin was applied to the substrate on which the gate electrode 22 and the first capacitor electrode 28 were formed and fired to form the first insulating layer 23.
  • the relative dielectric constant of the first insulating layer 23 is 3.3, and the film thickness is 1.0 ⁇ m.
  • the source electrode 24 and the drain electrode 25 were formed by the inkjet method in the same manner as the gate electrode 22 and the first capacitor electrode 28.
  • a mesitylene solution in which poly (3-hexylthiophene) is dissolved at a concentration of 0.1 weight percent as an organic semiconductor material is patterned by an ink jet method and baked. 26 were formed.
  • a fluorine resin was applied by an inkjet method to form a second insulating layer 27.
  • the relative dielectric constant of the second insulating layer 7 is 2.4, and the film thickness is 3.0 ⁇ m.
  • the upper pixel electrode 30 was formed on the second insulating layer 27 by screen printing, and an active matrix array composed of the organic thin film transistor 200 according to the comparative example was manufactured.
  • Example 1 Active matrix arrays according to Examples 1, 2, 3 and Comparative Example were produced by the above steps.
  • Example 2 the first capacitor electrode 8 is disposed on the second insulating layer 7 so as to cover the channel regions of the organic thin film transistors 100, 101, 102 in plan view.
  • the measurement result of the transfer characteristic of the organic thin-film transistor concerning Example 1 and the comparative example which were produced in FIG. 5 is shown.
  • the rise of the on current in the transfer characteristic is on the depletion side (positive side).
  • the organic thin film transistor 100 according to the first embodiment is further on the enhancement side (negative side).
  • the difference in the rising voltage of the on current in these transfer characteristics is the difference in the effects on the semiconductor layers 6 and 26 of the voltage applied to the upper pixel electrodes 10 and 30, and the results shown in FIG.
  • the organic thin film transistor 100 according to Example 1 clearly shows that the influence of the voltage of the upper pixel electrode 10 on the semiconductor layer 6 can be effectively blocked.
  • the first capacitor electrode 8 is provided to have a sufficient capacitor electrode area, thereby securing a sufficient capacitance.
  • Table 1 shows the area of the area where the first capacitor electrode and the upper pixel electrode overlap in plan view with respect to the area of the upper pixel electrode in the active matrix array manufactured using the organic thin film transistors according to Examples 1 to 3 and the comparative example.
  • calculation of electrostatic capacitance was performed by Formula (1), and calculation of voltage retention was performed by Formula (2).
  • the difference between the active matrix array 110 composed of the organic thin film transistor 100 of Example 1 and the active matrix array 111 composed of the organic thin film transistor 101 of Example 2 is that, as shown in FIGS. 6 and 7, the first capacitor electrode 8 is An area where the number of the first capacitor electrode 8 and the upper pixel electrode 10 overlap each other with respect to the area of the upper pixel electrode 10 in each organic thin film transistor and the number connected to the first capacitor electrode 8 of the adjacent organic thin film transistor
  • the ratio of the area of The first capacitor electrode 8 is formed to be connected to more adjacent organic thin film transistors, and the area of the area where the first capacitor electrode 8 and the upper pixel electrode 10 overlap in plan view with respect to the area of the upper pixel electrode 10 By increasing the ratio, it is possible to obtain a larger capacitance, and as a result, it has been confirmed that it is possible to maintain a high voltage holding ratio.
  • Example 3 the capacitance of the organic thin film transistor 102 can be further increased by forming the second capacitor electrode 11.
  • the first capacitor electrode 8 by providing the first capacitor electrode 8, a sufficient capacitor electrode area can be provided in the field shield pixel type bottom gate organic thin film transistor, so sufficient capacitance is secured. And the influence of the upper pixel electrode voltage on the semiconductor layer can be blocked. Therefore, organic thin film transistors 100, 101, 102 that can be driven stably while maintaining semiconductor characteristics are obtained, and fabrication of an active matrix array using organic thin film transistors 100, 101, 102 and driving of an image display device are realized. It became possible.
  • the organic thin film transistors 100, 101, 102 are formed of the first capacitor electrode 8 on the second insulating layer 7 so as to overlap at least the semiconductor layer 6 in plan view. It is possible to maintain a large area and obtain sufficient capacitance. Further, since the influence of the voltage applied to the upper pixel electrode 10 on the channel region of the semiconductor layer 6 can be blocked by the first capacitor electrode 8, it is possible to suppress the characteristic change of the organic thin film transistor.
  • the organic thin film transistor of the field shield pixel type bottom gate structure it has a sufficient capacitor electrode area, can ensure a sufficient capacitance, and a channel region of a voltage applied to the upper pixel electrode. It is possible to provide an organic thin film transistor that can be stably driven while maintaining semiconductor characteristics, a method of manufacturing the same, an active matrix array, and an image display device by blocking the influence on the semiconductor layer back channel portion in the above.
  • the present invention is suitably applicable to an image display device or various sensors.

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Abstract

L'invention concerne : un transistor à couches minces organiques ayant une structure de grille inférieure de type pixel de blindage de champ, le transistor permettant une commande stable tout en maintenant des caractéristiques de semi-conducteur et assurant une capacité électrostatique suffisante ; un procédé de fabrication associé ; un réseau matriciel actif ; et un dispositif d'affichage d'image. Le transistor à couches minces organiques comprend : un substrat ; une électrode de grille sur le substrat ; une première couche isolante formée de manière à recouvrir le substrat et l'électrode de grille ; une électrode de source, une électrode de drain et une couche semi-conductrice comprenant un matériau semi-conducteur organique qui sont formées sur la première couche isolante ; une seconde couche isolante recouvrant au moins une partie de la couche semi-conductrice, l'électrode de source et l'électrode de drain ; une première électrode de condensateur formée sur la seconde couche isolante et chevauchant au moins la couche semi-conductrice dans une vue en plan ; une troisième couche isolante électroconnectée à l'électrode de drain et recouvrant la seconde couche isolante et la première électrode de condensateur ; et une électrode de pixel supérieure formée sur la troisième couche isolante.
PCT/JP2018/038701 2017-10-19 2018-10-17 Transistor à couches minces organiques, son procédé de fabrication, réseau matriciel actif et dispositif d'affichage d'image WO2019078267A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09318972A (ja) * 1996-03-05 1997-12-12 Semiconductor Energy Lab Co Ltd 液晶表示装置およびその作製方法
JPH1091099A (ja) * 1996-09-18 1998-04-10 Toshiba Corp 液晶表示装置
WO2008084697A1 (fr) * 2007-01-10 2008-07-17 Sony Corporation Dispositif semiconducteur et périphérique d'affichage
JP2008277370A (ja) * 2007-04-26 2008-11-13 Sony Corp 半導体装置およびその製造方法、ならびに表示装置およびその製造方法
WO2013099697A1 (fr) * 2011-12-28 2013-07-04 シャープ株式会社 Substrat de matrice active

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3447947B2 (ja) * 1998-03-20 2003-09-16 株式会社東芝 Ｘ線撮像装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09318972A (ja) * 1996-03-05 1997-12-12 Semiconductor Energy Lab Co Ltd 液晶表示装置およびその作製方法
JPH1091099A (ja) * 1996-09-18 1998-04-10 Toshiba Corp 液晶表示装置
WO2008084697A1 (fr) * 2007-01-10 2008-07-17 Sony Corporation Dispositif semiconducteur et périphérique d'affichage
JP2008277370A (ja) * 2007-04-26 2008-11-13 Sony Corp 半導体装置およびその製造方法、ならびに表示装置およびその製造方法
WO2013099697A1 (fr) * 2011-12-28 2013-07-04 シャープ株式会社 Substrat de matrice active

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