WO2019047467A1 - 一种数字可调的带隙基准电路 - Google Patents

一种数字可调的带隙基准电路 Download PDF

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WO2019047467A1
WO2019047467A1 PCT/CN2018/074443 CN2018074443W WO2019047467A1 WO 2019047467 A1 WO2019047467 A1 WO 2019047467A1 CN 2018074443 W CN2018074443 W CN 2018074443W WO 2019047467 A1 WO2019047467 A1 WO 2019047467A1
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pmos transistor
transistor
resistor
gate
drain
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PCT/CN2018/074443
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English (en)
French (fr)
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董海
文治平
王宗民
张铁良
彭新芒
侯贺刚
管海涛
王金豪
任艳
张雷
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北京时代民芯科技有限公司
北京微电子技术研究所
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Publication of WO2019047467A1 publication Critical patent/WO2019047467A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

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  • the invention belongs to the technical field of digital-to-analog converters, and in particular to a digitally adjustable bandgap reference circuit.
  • the conversion accuracy of digital-to-analog converters used in military equipment such as wireless communication equipment and radar is particularly important.
  • the stable reference voltage is an important factor that restricts the conversion accuracy of digital-to-analog converters.
  • the design complexity of high-precision digital-to-analog converters is becoming more and more important. The higher.
  • the output voltage of the bandgap reference circuit of the same design parameters fluctuates accordingly, which makes the digital adjustment of the output voltage necessary.
  • the traditional bandgap reference circuit often includes an operational amplifier structure, which greatly increases the design complexity of the chip and increases the instability of the circuit. As the circuit scale increases, the power consumption and area of the chip increase, and the design cost of the circuit also becomes higher. The increase in power consumption also severely limits the application range of digital-to-analog converter chips.
  • the technical problem of the present invention solves the problem: overcomes the deficiencies of the prior art, and provides a digitally adjustable bandgap reference circuit suitable for a digital-to-analog converter, which significantly improves the accuracy and flexibility of the reference voltage of the digital-to-analog converter, and further Improving the conversion accuracy of the digital-to-analog converter greatly simplifies the design complexity of the digital-to-analog converter and reduces the area and power consumption of the digital-to-analog converter.
  • the present invention discloses a digitally adjustable bandgap reference circuit, comprising: a positive temperature coefficient current generating circuit, a digital adjustable negative temperature coefficient current generating circuit and a digital adjustable resistor string circuit;
  • a positive temperature coefficient current generating circuit for generating a positive temperature coefficient current Ip and a bias voltage U1;
  • a digitally adjustable negative temperature coefficient current generating circuit for receiving a first control signal, generating a digitally adjustable negative temperature coefficient current In according to the bias voltage U1 and the first control signal; and, aligning a positive temperature coefficient Current Ip and negative temperature coefficient current In are added and processed, output current I;
  • the digital adjustable resistor string circuit is configured to receive the second control signal, and control the resistance value connected in series according to the current I and the second control signal to implement control of the output voltage Vref.
  • the positive temperature coefficient current generating circuit includes: a PMOS transistor M1, a PMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, an NPN transistor B1, an NPN transistor B2, and an NPN transistor B3. , NPN transistor B4, resistor R1, resistor R2 and resistor R3;
  • the gate of the PMOS transistor M1 is connected to the gate of the PMOS transistor M2, the source is connected to VDD, and the drain is connected to the collector of the NPN transistor B3;
  • One end of the resistor R3 is connected to the gate of the NMOS transistor M4, and the other end is connected to the GND;
  • the drain of the PMOS transistor M2 is connected to the drain and the gate of the NMOS transistor M3, and serves as an output of the bias voltage U1;
  • the source of the NMOS transistor M3 is connected to the emitter of the NPN transistor B2, the drain of the NMOS transistor M4, and is output as a positive temperature coefficient current Ip;
  • the source of the NMOS transistor M4 is connected to GND;
  • resistor R1 One end of the resistor R1 is connected to VDD, and the other end is connected to the collector of the NPN transistor B1, the base and the base of the NPN transistor B2;
  • the emitter of the NPN transistor B1 is connected to the base of the NPN transistor B3, the base of the NPN transistor B4, and the collector;
  • resistor R2 One end of the resistor R2 is connected to the emitter of the NPN transistor B3, and the other end is connected to the GND;
  • the emitter of the NPN transistor B4 is connected to GND.
  • the digitally adjustable negative temperature coefficient current generating circuit comprises: a first decoding circuit and a negative temperature coefficient current generating circuit;
  • the first decoding circuit is configured to receive the first control signal ADJ1 ⁇ 3:0> of the four-bit binary code, and decode the ADJ1 ⁇ 3:0> to obtain the control signals A0, A1, A2, A0N, A1N, A2N And A3N;
  • a negative temperature coefficient current generating circuit for generating a digitally adjustable negative temperature coefficient current In according to the bias voltage U1 and the control signals A0, A1, A2, A0N, A1N, A2N, and A3N; and, a positive temperature coefficient
  • the current Ip and the negative temperature coefficient current In are summed to output a current I.
  • the first decoding circuit includes: three identical two-input XOR gates: a first two-input XOR gate, a second two-input XOR gate, and a third a two-input exclusive OR gate; and four identical NOT gates: a first NOT gate, a second NOT gate, a third NOT gate, and a fourth NOT gate; wherein the first control signal ADJ1 ⁇ 3:0> includes : control code ADJ1 ⁇ 0>, control code ADJ1 ⁇ 1>, control code ADJ1 ⁇ 2>, and control code ADJ1 ⁇ 3>;
  • the first two input XOR gates are used to perform an exclusive OR operation on the control code ADJ1 ⁇ 0> and the control code ADJ1 ⁇ 3>, and output a control signal A0;
  • the second input XOR gate is used to perform an exclusive OR operation on the control code ADJ1 ⁇ 1> and the control code ADJ1 ⁇ 3>, and output a control signal A1;
  • the third input XOR gate is used to perform an exclusive OR operation on the control code ADJ1 ⁇ 2> and the control code ADJ1 ⁇ 3>, and output a control signal A2;
  • a first NOT gate for receiving the control signal A0 and outputting the control signal A0N;
  • a second NOT gate for receiving the control signal A1 and outputting the control signal A1N;
  • a third NOT gate for receiving the control signal A2 and outputting the control signal A2N;
  • the fourth NOT gate is configured to receive the control code ADJ1 ⁇ 3> and output the control signal A3N.
  • the negative temperature coefficient current generating circuit includes: a PMOS transistor M5, a PMOS transistor M6, a PMOS transistor M7, a PMOS transistor M8, a PMOS transistor M9, an NMOS transistor M10, and an NMOS transistor M11.
  • the sources of the PMOS transistor M5, the PMOS transistor M6, the PMOS transistor M7, and the PMOS transistor M8 are all connected to VDD, and the gates of the PMOS transistor M5, the PMOS transistor M6, and the PMOS transistor M8 are simultaneously connected to the drains of the PMOS transistor M5 and the NMOS transistor M10.
  • the gate of the NMOS transistor M10 and the gate of the NMOS transistor M11 are simultaneously connected to the bias voltage U1, the source of the NMOS transistor M10 is connected to the collector of the NPN transistor B5; the base of the NPN transistor B5 is connected to the resistor R4, and is emitted.
  • the pole is connected to the resistor R5; the other end of the resistor R4 is connected to the base of the NPN transistor B6, the drain of the PMOS transistor M9, the gate of the PMOS transistor M12, the gate of the PMOS transistor M13, the gate of the PMOS transistor M14, and the PMOS transistor M15.
  • the gate is connected and is output as In; the other end of the resistor R5 is connected to the emitter of the resistor R6 and the NPN transistor B6; the other end of the resistor R6 is connected to the resistor R7, the source of the NMOS transistor M24, and the drain of the NMOS transistor M26.
  • the other end of the resistor R7 is connected to the GND; the drain of the PMOS transistor M6 is connected to the gate of the PMOS transistor M9 and the drain of the NMOS transistor M11; the source of the NMOS transistor M11 is connected to the collector of the NPN transistor B6; the PMOS transistor M7 The gate and the drain are connected to the source of the PMOS transistor M9; the drain of the PMOS transistor M8 is simultaneously connected to the source of the PMOS transistor M12, the source of the PMOS transistor M13, and the PMOS.
  • the source of the transistor M14 and the source of the PMOS transistor M15 are connected; the drain of the PMOS transistor M13 is connected to the drain of the NMOS transistor M16 and the drain of the NMOS transistor M20; the drain of the PMOS transistor M13 and the drain of the NMOS transistor M17, The drain of the NMOS transistor M21 is connected; the drain of the PMOS transistor M14 is connected to the drain of the NMOS transistor M18 and the drain of the NMOS transistor M22; the drain of the PMOS transistor M15 and the drain of the NMOS transistor M19, and the drain of the NMOS transistor M23 Connected; the gates of the PMOS transistor M12, the PMOS transistor M13, the PMOS transistor M14, and the PMOS transistor M15 are respectively connected to A0N, A1N, A2N, and A3N; the gates of the PMOS transistor M20, the PMOS transistor M21, the PMOS transistor M22, and the PMOS transistor M23 are respectively Connected to A0, A1, A2,
  • the digitally adjustable resistor string circuit includes: a second decoding circuit and a resistor string circuit;
  • a second decoding circuit configured to receive a second control signal ADJ0 ⁇ 3:0> of the four-bit binary code, convert ADJ0 ⁇ 3:0> into sixteen-digit thermometer codes D1 to D16, and corresponding to D1 to D16 Complementary anti-signal DN1 ⁇ DN16;
  • the resistor string circuit is configured to control the resistance value connected in series according to D1 to D16, DN1 to DN16, and current I to control the output voltage Vref.
  • the resistor string circuit comprises: 16 identical resistors R8 to R23, a resistor R24, 16 identical switches S1 to S16 and a capacitor C1;
  • the first end of the resistor R8 is connected to the input end of the switch S1; the end of the resistor R8 is connected to the head end of the resistor R9 and the input end of the switch S2, and so on, the end of the resistor R22 and the head end of the resistor R23 and the input end of the switch S16 Connected; the first end of the resistor R8 is connected to the current I; the tail end of the resistor R13 is connected to the GND; the control signals A1 to A16 and AN1 to AN16 of the 16 identical switches S1 to S16 are sequentially connected to D1 to D16 and DN1 to DN16, respectively; The output terminals of the 16 identical switches S1 to S16 are connected to the resistor R24 and the capacitor C1, the other end of the capacitor C1 is connected to the GND, and the other end of the resistor R24 is used as the output port to output Vref.
  • the digitally adjustable bandgap reference circuit of the present invention controls the output reference voltage by digital code to improve the flexibility of the output voltage, so that the digital-to-analog converter can be flexibly applied to different working environments; The impact of fluctuations in process parameters during chip fabrication.
  • the digitally adjustable bandgap reference circuit of the present invention can adjust the negative temperature coefficient current through the digital code, so that the chip can realize the optimal temperature coefficient in different working environments, and greatly improve the stability of the reference voltage. Sex, which in turn improves the conversion accuracy of the digital-to-analog converter.
  • the digitally adjustable bandgap reference circuit of the present invention does not include a conventional operational amplifier structure, which greatly simplifies the design complexity of the circuit, makes the working state of the circuit more stable, and reduces power consumption and chip area.
  • FIG. 1 is a block diagram showing the structure of a digitally adjustable bandgap reference circuit in an embodiment of the present invention
  • FIG. 2 is a circuit diagram of a positive temperature coefficient current generating circuit in an embodiment of the present invention.
  • FIG. 3 is a circuit diagram of a first decoding circuit in an embodiment of the present invention.
  • FIG. 4 is a circuit diagram of a negative temperature coefficient current generating circuit in an embodiment of the present invention.
  • Figure 5 is a circuit diagram of a resistor string circuit in an embodiment of the present invention.
  • the digitally adjustable bandgap reference circuit comprises: a positive temperature coefficient current generating circuit, a digitally adjustable negative temperature coefficient current generating circuit, and a digital adjustable resistor string circuit.
  • a positive temperature coefficient current generating circuit for generating a positive temperature coefficient current Ip and a bias voltage U1.
  • a digitally adjustable negative temperature coefficient current generating circuit for receiving a first control signal, generating a digitally adjustable negative temperature coefficient current In according to the bias voltage U1 and the first control signal; and, aligning a positive temperature coefficient The current Ip and the negative temperature coefficient current In are summed to output a current I. Wherein, the In size is controlled by the input first control signal.
  • the digital adjustable resistor string circuit is configured to receive the second control signal, and control the resistance value connected in series according to the current I and the second control signal to implement control of the output voltage Vref.
  • FIG. 2 there is shown a circuit diagram of a positive temperature coefficient current generating circuit in an embodiment of the present invention.
  • the positive temperature coefficient current generating circuit may specifically include: a PMOS (P Metal-Oxide Semiconductor) tube M1, a PMOS tube M2, and an NMOS (N Metal-Oxide Semiconductor).
  • the gate of the PMOS transistor M1 is connected to the gate of the PMOS transistor M2, the source is connected to VDD (power supply voltage), the drain is connected to the collector of the NPN transistor B3, and one end of the resistor R3 is connected to the gate of the NMOS transistor M4.
  • the other end is connected to GND (power ground); the drain of the PMOS transistor M2 is connected to the drain and gate of the NMOS transistor M3, and serves as an output of the bias voltage U1; the source of the NMOS transistor M3 and the emission of the NPN transistor B2
  • the drain of the NMOS transistor M4 is connected and output as a positive temperature coefficient current Ip; the source of the NMOS transistor M4 is connected to GND; one end of the resistor R1 is connected to VDD, and the other end is connected to the collector, base and NPN transistor of the NPN transistor B1.
  • the base of B2 is connected; the emitter of NPN transistor B1 is connected to the base of NPN transistor B3, the base and collector of NPN transistor B4; one end of resistor R2 is connected to the emitter of NPN transistor B3, and the other end is connected to GND; NPN transistor The emitter of B4 is connected to GND.
  • the first control signal may specifically be: a four-bit binary control code ADJ1 ⁇ 3:0>.
  • the digitally adjustable negative temperature coefficient current generating circuit may specifically include: a first decoding circuit and a negative temperature coefficient current generating circuit.
  • the first decoding circuit is configured to receive the four-bit binary control code ADJ1 ⁇ 3:0>, decode the ADJ1 ⁇ 3:0>, and obtain the control signals A0, A1, A2, A0N, A1N, A2N and A3N; a negative temperature coefficient current generating circuit for generating a digitally adjustable negative temperature coefficient current In according to the bias voltage U1 and the control signals A0, A1, A2, A0N, A1N, A2N and A3N; The temperature coefficient current Ip and the negative temperature coefficient current In are summed to output a current I.
  • ADJ1 ⁇ 3:0> may specifically include: control code ADJ1 ⁇ 0>, control code ADJ1 ⁇ 1>, control code ADJ1 ⁇ 2>, and control code ADJ1 ⁇ 3>.
  • the first decoding circuit may specifically include: three identical two-input XOR gates: a first two-input XOR gate, a second two-input XOR gate, and a third two-input XOR gate; and four The same non-gate: first non-gate, second non-gate, third non-gate and fourth non-gate.
  • the first two-input XOR gate is used to perform an exclusive OR operation on the control code ADJ1 ⁇ 0> and the control code ADJ1 ⁇ 3>, and output a control signal A0;
  • the second two-input XOR gate is used for Performing an exclusive OR operation on the control code ADJ1 ⁇ 1> and the control code ADJ1 ⁇ 3>, outputting a control signal A1;
  • a third two-input XOR gate for differentiating the control code ADJ1 ⁇ 2> and the control code ADJ1 ⁇ 3> Or operation, output control signal A2; first NOT gate for receiving control signal A0, output control signal A0N; second NOT gate for receiving control signal A1, outputting control signal A1N; third NOT gate for receiving The control signal A2 outputs a control signal A2N;
  • the fourth NOT gate is configured to receive the control code ADJ1 ⁇ 3> and output a control signal A3N.
  • FIG. 4 there is shown a circuit diagram of a negative temperature coefficient current generating circuit in an embodiment of the present invention.
  • the negative temperature coefficient current generating circuit may specifically include: a PMOS transistor M5, a PMOS transistor M6, a PMOS transistor M7, a PMOS transistor M8, a PMOS transistor M9, an NMOS transistor M10, an NMOS transistor M11, a PMOS transistor M12, and a PMOS transistor M13.
  • PMOS transistor M14 PMOS transistor M15, NMOS transistor M16, NMOS transistor M17, NMOS transistor M18, NMOS transistor M19, NMOS transistor M20, NMOS transistor M21, NMOS transistor M22, NMOS transistor M23, NMOS transistor M24, NMOS transistor M25, NMOS Tube M26, NMOS transistor M27, NPN transistor B5, NPN transistor B6, resistor R4, resistor R5, resistor R6, and resistor R7.
  • the sources of the PMOS transistor M5, the PMOS transistor M6, the PMOS transistor M7, and the PMOS transistor M8 are all connected to VDD, and the gates of the PMOS transistor M5, the PMOS transistor M6, and the PMOS transistor M8 are simultaneously connected to the PMOS transistor M5 and the NMOS.
  • the drain of the transistor M10 is connected; the gate of the NMOS transistor M10 and the gate of the NMOS transistor M11 are simultaneously connected to the bias voltage U1, the source of the NMOS transistor M10 is connected to the collector of the NPN transistor B5; the base of the NPN transistor B5 Connected to the resistor R4, the emitter is connected to the resistor R5; the other end of the resistor R4 is connected to the base of the NPN transistor B6, the drain of the PMOS transistor M9, the gate of the PMOS transistor M12, the gate of the PMOS transistor M13, and the PMOS transistor M14.
  • the gate of the gate and the PMOS transistor M15 are connected and output as In; the other end of the resistor R5 is connected to the emitter of the resistor R6 and the NPN transistor B6; the other end of the resistor R6 is connected to the resistor R7, the source of the NMOS transistor M24, and the NMOS.
  • the drain of the transistor M26 is connected; the other end of the resistor R7 is connected to the GND; the drain of the PMOS transistor M6 is connected to the gate of the PMOS transistor M9, the drain of the NMOS transistor M11; the source of the NMOS transistor M11 and the set of the NPN transistor B6
  • the electrodes are connected; the gate and the drain of the PMOS transistor M7 are connected to the source of the PMOS transistor M9; the drain of the PMOS transistor M8 is simultaneously connected to the source of the PMOS transistor M12, and the PMOS
  • the source of the M13, the source of the PMOS transistor M14, and the source of the PMOS transistor M15 are connected; the drain of the PMOS transistor M13 is connected to the drain of the NMOS transistor M16 and the drain of the NMOS transistor M20; the drain of the PMOS transistor M13 and the NMOS
  • the drain of the transistor M17 and the drain of the NMOS transistor M21 are connected; the drain of the PMOS transistor M14 is connected to
  • the first control signal may specifically be: a four-digit binary code ADJ0 ⁇ 3:0>.
  • the digital adjustable resistor string circuit may specifically include: a second decoding circuit and a resistor string circuit.
  • the second decoding circuit is configured to receive the four-bit binary code ADJ0 ⁇ 3:0>, convert the ADJ0 ⁇ 3:0> into the sixteen-digit thermometer code D1 ⁇ D16, and the complementary inverse of the D1 ⁇ D16 Signals DN1 to DN16.
  • the resistor string circuit is configured to control the resistance value connected in series according to D1 to D16, DN1 to DN16, and current I to control the output voltage Vref.
  • FIG. 5 there is shown a circuit diagram of a resistor string circuit in an embodiment of the present invention.
  • the resistor string circuit may specifically include: 16 identical resistors R8-R23, a resistor R24, 16 identical switches S1-S16, and a capacitor C1.
  • the first end of the resistor R8 is connected to the input end of the switch S1; the end of the resistor R8 is connected to the head end of the resistor R9 and the input end of the switch S2, and so on, the end of the resistor R22 and the head end of the resistor R23 Connected to the input end of the switch S16; the first end of the resistor R8 is connected to the current I; the tail end of the resistor R13 is connected to the GND; and the control signals A1 to A16 and AN1 to AN16 of the 16 identical switches S1 to S16 are respectively connected to D1 ⁇ D16 and DN1 ⁇ DN16; 16 outputs of the same switch S1 ⁇ S16 are connected to the resistor R24, capacitor C1, the other end of the capacitor C1 is connected to GND; the other end of the resistor R24 is output Vref as an output port.
  • the digitally adjustable bandgap reference circuit of the present invention controls the output reference voltage by digital code to improve the flexibility of the output voltage, so that the digital-to-analog converter can be flexibly applied to different working environments. At the same time, the influence of fluctuations in process parameters during the chip manufacturing process is eliminated.
  • the digitally adjustable bandgap reference circuit of the present invention can adjust the negative temperature coefficient current through the digital code, so that the chip can achieve the optimal temperature coefficient in different working environments, and the reference voltage is greatly improved. Sex, which in turn improves the conversion accuracy of the digital-to-analog converter.
  • the digitally adjustable bandgap reference circuit of the present invention does not include a conventional operational amplifier structure, which greatly simplifies the design complexity of the circuit, makes the working state of the circuit more stable, and reduces power consumption and chip area.

Abstract

本发明公开了一种数字可调的带隙基准电路，包括：正温度系数电流生成电路、数字可调负温度系数电流生成电路和数字可调电阻串电路。正温度系数电流生成电路产生正温度系数电流Ip，同时产生偏置电压U1；数字可调负温度系数电流生成电路根据偏置电压U1生成数字可调的负温度系数电流In，In大小由输入第一控制信号控制；正温度系数电流Ip和负温度系数电流In经过加和后得到电流I，输入给数字可调电阻串电路，输入第二控制信号控制串联连入的电阻值，进而控制最终的输出电压Vref。本发明显著提高了带隙基准电路输出电压的精确度，大大简化了带隙基准电路的设计复杂度，降低了带隙基准电路的面积和功耗。

Description

一种数字可调的带隙基准电路
本申请要求于2017年9月5日提交中国专利局、申请号为201710790805.4、发明名称为“一种数字可调的带隙基准电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明属于数模转换器技术领域，尤其涉及一种数字可调的带隙基准电路。
背景技术
应用于无线通信设备和雷达等军用设备的数模转换器的转换精度尤为重要，稳定的参考电压成为制约着数模转换器转换精度的重要因素，高精度数模转换器的设计复杂度越来越高。
由于制作工艺和工作环境的不同，相同设计参数的带隙基准电路的输出电压也会随之波动，这使得输出电压的数字可调成为必要。传统的带隙基准电路中往往包含运算放大器结构，大大增加了芯片的设计复杂度，同时增加了电路的不稳定因素。电路规模的增大，使得芯片的功耗和面积随之增大，电路的设计成本也随之变高。功耗的增加，也严重制约着数模转换器芯片的应用范围。
发明内容
本发明的技术解决问题：克服现有技术的不足，提供一种数字可调的带隙基准电路，适用于数模转换器，显著提高了数模转换器的参考电压的精度和灵活性，进而提高数模转换器的转换精度，大大简化了数模转换器的设计复杂度，降低了数模转换器的面积和功耗。
为了解决上述技术问题，本发明公开了一种数字可调的带隙基准电路，包括：正温度系数电流生成电路、数字可调负温度系数电流生成电路和数字可调电阻串电路；
正温度系数电流生成电路，用于产生正温度系数电流Ip和偏置电压U1；
数字可调负温度系数电流生成电路，用于接收第一控制信号，根据所述偏置电压U1和所述第一控制信号，生成数字可调的负温度系数电流In；以及，对正温度系数电流Ip和负温度系数电流In进行加和处理，输出电流I；
数字可调电阻串电路，用于接收第二控制信号，根据所述电流I和所述第二控制信号，控制串联连入的电阻值，实现对输出电压Vref的控制。
在上述数字可调的带隙基准电路中，所述正温度系数电流生成电路，包括：PMOS管M1、PMOS管M2、NMOS管M3、NMOS管M4、NPN晶体管B1、NPN晶体管B2、NPN晶体管B3、NPN晶体管B4、电阻R1、电阻R2和电阻R3；
PMOS管M1的栅极和PMOS管M2的栅极相连，源极连接VDD，漏极连接NPN晶体管B3的集电极；
电阻R3的一端连接NMOS晶体管M4的栅极，另一端连接GND；
PMOS管M2的漏极和NMOS管M3的漏极、栅极相连，并作为偏置电压U1的输出；
NMOS管M3的源极和NPN晶体管B2的发射极、NMOS管M4的漏极相连，并作为正温度系数电流Ip输出；
NMOS管M4的源极连接GND；
电阻R1的一端连接VDD，另一端与NPN晶体管B1的集电极、基极和NPN晶体管B2的基极相连；
NPN晶体管B1的发射极和NPN晶体管B3的基极、NPN晶体管B4的基极和集电极相连；
电阻R2的一端连接NPN晶体管B3的发射极，另一端连接GND；
NPN晶体管B4的发射极连接GND。
在上述数字可调的带隙基准电路中，所述数字可调负温度系数电流生成电路，包括：第一译码电路和负温度系数电流生成电路；
第一译码电路，用于接收四位二进制码的第一控制信号ADJ1<3:0>，对ADJ1<3:0>进行译码，得到控制信号A0、A1、A2、A0N、A1N、A2N和A3N；
负温度系数电流生成电路，用于根据所述偏置电压U1以及控制信号A0、A1、A2、A0N、A1N、A2N和A3N，生成数字可调的负温度系数电流In；以及，对正温度系数电流Ip和负温度系数电流In进行加和处理，输出电流I。
在上述数字可调的带隙基准电路中，所述第一译码电路，包括：三个相同的二输入异或门：第一二输入异或门、第二二输入异或门和第三二输入异或门；和四个相同的非门：第一非门、第二非门、第三非门和第四非门；其中，所述第一控制信号ADJ1<3:0>，包括：控制码ADJ1<0>、控制码ADJ1<1>、控制码ADJ1<2>和控制码ADJ1<3>；
第一二输入异或门，用于对控制码ADJ1<0>和控制码ADJ1<3>进行异或运算，输出控制信号A0；
第二二输入异或门，用于对控制码ADJ1<1>和控制码ADJ1<3>进行异或运算，输出控制信号A1；
第三二输入异或门，用于对控制码ADJ1<2>和控制码ADJ1<3>进行异或运算，输出控制信号A2；
第一非门，用于接收控制信号A0，输出控制信号A0N；
第二非门，用于接收控制信号A1，输出控制信号A1N；
第三非门，用于接收控制信号A2，输出控制信号A2N；
第四非门，用于接收控制码ADJ1<3>，输出控制信号A3N。
在上述数字可调的带隙基准电路中，所述负温度系数电流生成电路，包括：PMOS管M5、PMOS管M6、PMOS管M7、PMOS管M8、PMOS管M9、NMOS管M10、NMOS管M11、PMOS管M12、PMOS管M13、PMOS管M14、PMOS管M15、NMOS管M16、NMOS管M17、NMOS管M18、NMOS管M19、NMOS管M20、NMOS管M21、NMOS管M22、NMOS管M23、NMOS管M24、NMOS管M25、NMOS管M26、NMOS管M27、NPN晶体管B5、NPN晶体管B6、电阻R4、电阻R5、电阻R6和电阻R7；
PMOS管M5、PMOS管M6、PMOS管M7、PMOS管M8的源极均与VDD相连，PMOS管M5、PMOS管M6、PMOS管M8的栅极同时与PMOS管M5、 NMOS管M10的漏极相连；NMOS管M10的栅极和NMOS管M11的栅极同时连接所述偏置电压U1，NMOS管M10的源极与NPN晶体管B5的集电极相连；NPN晶体管B5的基极与电阻R4相连，发射极与电阻R5相连；电阻R4的另一端与NPN晶体管B6的基极、PMOS管M9的漏极、PMOS管M12的栅极、PMOS管M13的栅极、PMOS管M14的栅极、PMOS管M15的栅极相连，并作为In输出；电阻R5的另一端与电阻R6、NPN晶体管B6的发射极相连；电阻R6的另一端与电阻R7、NMOS管M24的源极、NMOS管M26的漏极相连；电阻R7的另一端与GND相连；PMOS管M6的漏极与PMOS管M9的栅极、NMOS管M11的漏极相连；NMOS管M11的源极与NPN晶体管B6的集电极相连；PMOS管M7的栅极、漏极与PMOS管M9的源极相连；PMOS管M8的漏极同时与PMOS管M12的源极、PMOS管M13的源极、PMOS管M14的源极、PMOS管M15的源极相连；PMOS管M13的漏极与NMOS管M16的漏极、NMOS管M20的漏极相连；PMOS管M13的漏极与NMOS管M17的漏极、NMOS管M21的漏极相连；PMOS管M14的漏极与NMOS管M18的漏极、NMOS管M22的漏极相连；PMOS管M15的漏极与NMOS管M19的漏极、NMOS管M23的漏极相连；PMOS管M12、PMOS管M13、PMOS管M14、PMOS管M15的栅极分别与A0N、A1N、A2N和A3N相连；PMOS管M20、PMOS管M21、PMOS管M22、PMOS管M23的栅极分别与A0、A1、A2和ADJ<3>相连；PMOS管M12、PMOS管M13、PMOS管M14、PMOS管M15的源极同时与GND相连；PMOS管M20、PMOS管M21、PMOS管M22、PMOS管M23的源极同时与PMOS管M24、PMOS管M25的漏极相连；PMOS管M24的栅极连接A3N；PMOS管M25的栅极连接ADJ<3>，PMOS管M25的源极与PMOS管M26的栅极、PMOS管M27的栅极和漏极相连；PMOS管M26的源极、PMOS管M27的源极与GND相连。
在上述数字可调的带隙基准电路中，所述数字可调电阻串电路，包括：第二译码电路和电阻串电路；
第二译码电路，用于接收四位二进制码的第二控制信号ADJ0<3:0>，将 ADJ0<3:0>转成十六位温度计码D1～D16，以及，D1～D16对应的互补反信号DN1～DN16；
电阻串电路，用于根据D1～D16、DN1～DN16和电流I，控制串联连入的电阻值，实现对输出电压Vref的控制。
在上述数字可调的带隙基准电路中，所述电阻串电路，包括：16支相同的电阻R8～R23、一电阻R24、16支相同的开关S1～S16和一电容C1；
电阻R8的首端与开关S1的输入端相连；电阻R8的末端与电阻R9的首端和开关S2的输入端相连，依次类推，电阻R22的末端与电阻R23的首端和开关S16的输入端相连；电阻R8的首端连接所述电流I；电阻R13的尾端连接GND；16支相同的开关S1～S16的控制信号A1～A16和AN1～AN16分别依次连接D1～D16和DN1～DN16；16支相同的开关S1～S16的输出端与电阻R24、电容C1相连，电容C1另一端连接GND；电阻R24另一端作为输出端口输出Vref。
本发明具有以下优点：
(1)本发明中的数字可调的带隙基准电路，通过数字码控制输出的参考电压，提高了输出电压的灵活性，使得数模转换器能够灵活应用到不同的工作环境中；同时消除了芯片制作过程中的工艺参数波动带来的影响。
(2)本发明中的数字可调的带隙基准电路，可以通过数字码调节负温度系数电流，使得芯片在不同的工作环境中都能实现最佳的温度系数，大大提高了参考电压的稳定性，进而提高数模转换器的转换精度。
(3)本发明中的数字可调的带隙基准电路不包含传统的运算放大器结构，大大简化了电路的设计复杂度，使得电路的工作状态更稳定，降低了功耗和芯片面积。
附图说明
图1是本发明实施例中一种数字可调的带隙基准电路的结构框图；
图2是本发明实施例中一种正温度系数电流生成电路的电路图；
图3是本发明实施例中一种第一译码电路的电路图；
图4是本发明实施例中一种负温度系数电流生成电路的电路图；
图5是本发明实施例中一种电阻串电路的电路图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明公共的实施方式作进一步详细描述。
参照图1，示出了本发明实施例中一种数字可调的带隙基准电路的结构框图。在本实施例中，所述数字可调的带隙基准电路，包括：正温度系数电流生成电路、数字可调负温度系数电流生成电路和数字可调电阻串电路。
正温度系数电流生成电路，用于产生正温度系数电流Ip和偏置电压U1。
数字可调负温度系数电流生成电路，用于接收第一控制信号，根据所述偏置电压U1和所述第一控制信号，生成数字可调的负温度系数电流In；以及，对正温度系数电流Ip和负温度系数电流In进行加和处理，输出电流I。其中，In大小由输入的第一控制信号控制。
数字可调电阻串电路，用于接收第二控制信号，根据所述电流I和所述第二控制信号，控制串联连入的电阻值，实现对输出电压Vref的控制。
其中，
正温度系数电流生成电路
参照图2，示出了本发明实施例中一种正温度系数电流生成电路的电路图。
如图2，所述正温度系数电流生成电路，具体可以包括：PMOS(P Metal-Oxide Semiconductor，P型金属氧化物半导体)管M1、PMOS管M2、NMOS(N Metal-Oxide Semiconductor，N型金属氧化物半导体)管M3、NMOS管M4、NPN晶体管B1、NPN晶体管B2、NPN晶体管B3、NPN晶体管B4、电阻R1、电阻R2和电阻R3。
在本实施例中，PMOS管M1的栅极和PMOS管M2的栅极相连，源极连接VDD(电源电压)，漏极连接NPN晶体管B3的集电极；电阻R3的一端连接NMOS晶体管M4的栅极，另一端连接GND(电源地)；PMOS管M2的漏极和NMOS管M3的漏极、栅极相连，并作为偏置电压U1的输出；NMOS管M3的源极和NPN晶体管B2的发射极、NMOS管M4的漏极相连，并作为正 温度系数电流Ip输出；NMOS管M4的源极连接GND；电阻R1的一端连接VDD，另一端与NPN晶体管B1的集电极、基极和NPN晶体管B2的基极相连；NPN晶体管B1的发射极和NPN晶体管B3的基极、NPN晶体管B4的基极和集电极相连；电阻R2的一端连接NPN晶体管B3的发射极，另一端连接GND；NPN晶体管B4的发射极连接GND。
数字可调负温度系数电流生成电路
在本实施例中，第一控制信号具体可以为：四位二进制控制码ADJ1<3:0>。其中，数字可调负温度系数电流生成电路，具体可以包括：第一译码电路和负温度系数电流生成电路。优选的，第一译码电路，用于接收四位二进制控制码ADJ1<3:0>，对ADJ1<3:0>进行译码，得到控制信号A0、A1、A2、A0N、A1N、A2N和A3N；负温度系数电流生成电路，用于根据所述偏置电压U1以及控制信号A0、A1、A2、A0N、A1N、A2N和A3N，生成数字可调的负温度系数电流In；以及，对正温度系数电流Ip和负温度系数电流In进行加和处理，输出电流I。
参照图3，示出了本发明实施例中一种第一译码电路的电路图。在本实施例中，ADJ1<3:0>，具体可以包括：控制码ADJ1<0>、控制码ADJ1<1>、控制码ADJ1<2>和控制码ADJ1<3>。
如图3，第一译码电路，具体可以包括：三个相同的二输入异或门：第一二输入异或门、第二二输入异或门和第三二输入异或门；和四个相同的非门：第一非门、第二非门、第三非门和第四非门。
在本实施例中，第一二输入异或门，用于对控制码ADJ1<0>和控制码ADJ1<3>进行异或运算，输出控制信号A0；第二二输入异或门，用于对控制码ADJ1<1>和控制码ADJ1<3>进行异或运算，输出控制信号A1；第三二输入异或门，用于对控制码ADJ1<2>和控制码ADJ1<3>进行异或运算，输出控制信号A2；第一非门，用于接收控制信号A0，输出控制信号A0N；第二非门，用于接收控制信号A1，输出控制信号A1N；第三非门，用于接收控制信号A2，输出控制信号A2N；第四非门，用于接收控制码ADJ1<3>，输出控制信号A3N。
参照图4，示出了本发明实施例中一种负温度系数电流生成电路的电路图。
如图4，负温度系数电流生成电路，具体可以包括：PMOS管M5、PMOS管M6、PMOS管M7、PMOS管M8、PMOS管M9、NMOS管M10、NMOS管M11、PMOS管M12、PMOS管M13、PMOS管M14、PMOS管M15、NMOS管M16、NMOS管M17、NMOS管M18、NMOS管M19、NMOS管M20、NMOS管M21、NMOS管M22、NMOS管M23、NMOS管M24、NMOS管M25、NMOS管M26、NMOS管M27、NPN晶体管B5、NPN晶体管B6、电阻R4、电阻R5、电阻R6和电阻R7。
在本实施例中，PMOS管M5、PMOS管M6、PMOS管M7、PMOS管M8的源极均与VDD相连，PMOS管M5、PMOS管M6、PMOS管M8的栅极同时与PMOS管M5、NMOS管M10的漏极相连；NMOS管M10的栅极和NMOS管M11的栅极同时连接所述偏置电压U1，NMOS管M10的源极与NPN晶体管B5的集电极相连；NPN晶体管B5的基极与电阻R4相连，发射极与电阻R5相连；电阻R4的另一端与NPN晶体管B6的基极、PMOS管M9的漏极、PMOS管M12的栅极、PMOS管M13的栅极、PMOS管M14的栅极、PMOS管M15的栅极相连，并作为In输出；电阻R5的另一端与电阻R6、NPN晶体管B6的发射极相连；电阻R6的另一端与电阻R7、NMOS管M24的源极、NMOS管M26的漏极相连；电阻R7的另一端与GND相连；PMOS管M6的漏极与PMOS管M9的栅极、NMOS管M11的漏极相连；NMOS管M11的源极与NPN晶体管B6的集电极相连；PMOS管M7的栅极、漏极与PMOS管M9的源极相连；PMOS管M8的漏极同时与PMOS管M12的源极、PMOS管M13的源极、PMOS管M14的源极、PMOS管M15的源极相连；PMOS管M13的漏极与NMOS管M16的漏极、NMOS管M20的漏极相连；PMOS管M13的漏极与NMOS管M17的漏极、NMOS管M21的漏极相连；PMOS管M14的漏极与NMOS管M18的漏极、NMOS管M22的漏极相连；PMOS管M15的漏极与NMOS管M19的漏极、NMOS管M23的漏极相连；PMOS管M12、PMOS管M13、PMOS管M14、PMOS管M15的栅极分别与A0N、A1N、A2N和A3N 相连；PMOS管M20、PMOS管M21、PMOS管M22、PMOS管M23的栅极分别与A0、A1、A2和ADJ<3>相连；PMOS管M12、PMOS管M13、PMOS管M14、PMOS管M15的源极同时与GND相连；PMOS管M20、PMOS管M21、PMOS管M22、PMOS管M23的源极同时与PMOS管M24、PMOS管M25的漏极相连；PMOS管M24的栅极连接A3N；PMOS管M25的栅极连接ADJ<3>，PMOS管M25的源极与PMOS管M26的栅极、PMOS管M27的栅极和漏极相连；PMOS管M26的源极、PMOS管M27的源极与GND相连。
数字可调电阻串电路
在本实施例中，第一控制信号具体可以为：四位二进制码ADJ0<3:0>。其中，数字可调电阻串电路，具体可以包括：第二译码电路和电阻串电路。优选的，第二译码电路，用于接收四位二进制码ADJ0<3:0>，将ADJ0<3:0>转成十六位温度计码D1～D16，以及，D1～D16对应的互补反信号DN1～DN16。电阻串电路，用于根据D1～D16、DN1～DN16和电流I，控制串联连入的电阻值，实现对输出电压Vref的控制。
参照图5，示出了本发明实施例中一种电阻串电路的电路图。
如图5，电阻串电路，具体可以包括：16支相同的电阻R8～R23、一电阻R24、16支相同的开关S1～S16和一电容C1。
在本实施例中，电阻R8的首端与开关S1的输入端相连；电阻R8的末端与电阻R9的首端和开关S2的输入端相连，依次类推，电阻R22的末端与电阻R23的首端和开关S16的输入端相连；电阻R8的首端连接所述电流I；电阻R13的尾端连接GND；16支相同的开关S1～S16的控制信号A1～A16和AN1～AN16分别依次连接D1～D16和DN1～DN16；16支相同的开关S1～S16的输出端与电阻R24、电容C1相连，电容C1另一端连接GND；电阻R24另一端作为输出端口输出Vref。
在上述实施例的基础上，以ADJ0<3:0>＝1000、ADJ1<3:0>＝0000为例，数字可调的带隙基准电路的工作原理如下：ADJ1<3:0>＝0000控制调节所述负温度系数电流In的大小，使其和正温度系数电流Ip近似互补，得到近零温度系数 电流I；ADJ0<3:0>＝1000决定电阻串的分压比例，调节输出参考电压Vref至设计值，保证数模转换器的高转换精度。
综上所述，本发明所述的数字可调的带隙基准电路，通过数字码控制输出的参考电压，提高了输出电压的灵活性，使得数模转换器能够灵活应用到不同的工作环境中；同时消除了芯片制作过程中的工艺参数波动带来的影响。
其次，本发明所述的数字可调的带隙基准电路，可以通过数字码调节负温度系数电流，使得芯片在不同的工作环境中都能实现最佳的温度系数，大大提高了参考电压的稳定性，进而提高数模转换器的转换精度。
此外，本发明所述的数字可调的带隙基准电路不包含传统的运算放大器结构，大大简化了电路的设计复杂度，使得电路的工作状态更稳定，降低了功耗和芯片面积。
本说明中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
以上所述，仅为本发明最佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。
本发明说明书中未作详细描述的内容属于本领域专业技术人员的公知技术。

Claims (7)

  1. 一种数字可调的带隙基准电路，其特征在于，包括：正温度系数电流生成电路、数字可调负温度系数电流生成电路和数字可调电阻串电路；
    正温度系数电流生成电路，用于产生正温度系数电流Ip和偏置电压U1；
    数字可调负温度系数电流生成电路，用于接收第一控制信号，根据所述偏置电压U1和所述第一控制信号，生成数字可调的负温度系数电流In；以及，对正温度系数电流Ip和负温度系数电流In进行加和处理，输出电流I；
    数字可调电阻串电路，用于接收第二控制信号，根据所述电流I和所述第二控制信号，控制串联连入的电阻值，实现对输出电压Vref的控制。
  2. 根据权利要求1所述的数字可调的带隙基准电路，其特征在于，所述正温度系数电流生成电路，包括：PMOS管M1、PMOS管M2、NMOS管M3、NMOS管M4、NPN晶体管B1、NPN晶体管B2、NPN晶体管B3、NPN晶体管B4、电阻R1、电阻R2和电阻R3；
    PMOS管M1的栅极和PMOS管M2的栅极相连，源极连接VDD，漏极连接NPN晶体管B3的集电极；
    电阻R3的一端连接NMOS晶体管M4的栅极，另一端连接GND；
    PMOS管M2的漏极和NMOS管M3的漏极、栅极相连，并作为偏置电压U1的输出；
    NMOS管M3的源极和NPN晶体管B2的发射极、NMOS管M4的漏极相连，并作为正温度系数电流Ip输出；
    NMOS管M4的源极连接GND；
    电阻R1的一端连接VDD，另一端与NPN晶体管B1的集电极、基极和NPN晶体管B2的基极相连；
    NPN晶体管B1的发射极和NPN晶体管B3的基极、NPN晶体管B4的基极和集电极相连；
    电阻R2的一端连接NPN晶体管B3的发射极，另一端连接GND；
    NPN晶体管B4的发射极连接GND。
  3. 根据权利要求1所述的数字可调的带隙基准电路，其特征在于，所述数字可调负温度系数电流生成电路，包括：第一译码电路和负温度系数电流生成电路；
    第一译码电路，用于接收四位二进制码的第一控制信号ADJ1<3:0>，对ADJ1<3:0>进行译码，得到控制信号A0、A1、A2、A0N、A1N、A2N和A3N；
    负温度系数电流生成电路，用于根据所述偏置电压U1以及控制信号A0、A1、A2、A0N、A1N、A2N和A3N，生成数字可调的负温度系数电流In；以及，对正温度系数电流Ip和负温度系数电流In进行加和处理，输出电流I。
  4. 根据权利要求3所述的数字可调的带隙基准电路，其特征在于，所述第一译码电路，包括：三个相同的二输入异或门：第一二输入异或门、第二二输入异或门和第三二输入异或门；和四个相同的非门：第一非门、第二非门、第三非门和第四非门；其中，所述第一控制信号ADJ1<3:0>，包括：控制码ADJ1<0>、控制码ADJ1<1>、控制码ADJ1<2>和控制码ADJ1<3>；
    第一二输入异或门，用于对控制码ADJ1<0>和控制码ADJ1<3>进行异或运算，输出控制信号A0；
    第二二输入异或门，用于对控制码ADJ1<1>和控制码ADJ1<3>进行异或运算，输出控制信号A1；
    第三二输入异或门，用于对控制码ADJ1<2>和控制码ADJ1<3>进行异或运算，输出控制信号A2；
    第一非门，用于接收控制信号A0，输出控制信号A0N；
    第二非门，用于接收控制信号A1，输出控制信号A1N；
    第三非门，用于接收控制信号A2，输出控制信号A2N；
    第四非门，用于接收控制码ADJ1<3>，输出控制信号A3N。
  5. 根据权利要求3所述的数字可调的带隙基准电路，其特征在于，所述负温度系数电流生成电路，包括：PMOS管M5、PMOS管M6、PMOS管M7、PMOS管M8、PMOS管M9、NMOS管M10、NMOS管M11、PMOS管M12、 PMOS管M13、PMOS管M14、PMOS管M15、NMOS管M16、NMOS管M17、NMOS管M18、NMOS管M19、NMOS管M20、NMOS管M21、NMOS管M22、NMOS管M23、NMOS管M24、NMOS管M25、NMOS管M26、NMOS管M27、NPN晶体管B5、NPN晶体管B6、电阻R4、电阻R5、电阻R6和电阻R7；
    PMOS管M5、PMOS管M6、PMOS管M7、PMOS管M8的源极均与VDD相连，PMOS管M5、PMOS管M6、PMOS管M8的栅极同时与PMOS管M5、NMOS管M10的漏极相连；NMOS管M10的栅极和NMOS管M11的栅极同时连接所述偏置电压U1，NMOS管M10的源极与NPN晶体管B5的集电极相连；NPN晶体管B5的基极与电阻R4相连，发射极与电阻R5相连；电阻R4的另一端与NPN晶体管B6的基极、PMOS管M9的漏极、PMOS管M12的栅极、PMOS管M13的栅极、PMOS管M14的栅极、PMOS管M15的栅极相连，并作为In输出；电阻R5的另一端与电阻R6、NPN晶体管B6的发射极相连；电阻R6的另一端与电阻R7、NMOS管M24的源极、NMOS管M26的漏极相连；电阻R7的另一端与GND相连；PMOS管M6的漏极与PMOS管M9的栅极、NMOS管M11的漏极相连；NMOS管M11的源极与NPN晶体管B6的集电极相连；PMOS管M7的栅极、漏极与PMOS管M9的源极相连；PMOS管M8的漏极同时与PMOS管M12的源极、PMOS管M13的源极、PMOS管M14的源极、PMOS管M15的源极相连；PMOS管M13的漏极与NMOS管M16的漏极、NMOS管M20的漏极相连；PMOS管M13的漏极与NMOS管M17的漏极、NMOS管M21的漏极相连；PMOS管M14的漏极与NMOS管M18的漏极、NMOS管M22的漏极相连；PMOS管M15的漏极与NMOS管M19的漏极、NMOS管M23的漏极相连；PMOS管M12、PMOS管M13、PMOS管M14、PMOS管M15的栅极分别与A0N、A1N、A2N和A3N相连；PMOS管M20、PMOS管M21、PMOS管M22、PMOS管M23的栅极分别与A0、A1、A2和ADJ<3>相连；PMOS管M12、PMOS管M13、PMOS管M14、PMOS管M15的源极同时与GND相连；PMOS管M20、PMOS管M21、PMOS管M22、 PMOS管M23的源极同时与PMOS管M24、PMOS管M25的漏极相连；PMOS管M24的栅极连接A3N；PMOS管M25的栅极连接ADJ<3>，PMOS管M25的源极与PMOS管M26的栅极、PMOS管M27的栅极和漏极相连；PMOS管M26的源极、PMOS管M27的源极与GND相连。
  6. 根据权利要求1所述的数字可调的带隙基准电路，其特征在于，所述数字可调电阻串电路，包括：第二译码电路和电阻串电路；
    第二译码电路，用于接收四位二进制码的第二控制信号ADJ0<3:0>，将ADJ0<3:0>转成十六位温度计码D1～D16，以及，D1～D16对应的互补反信号DN1～DN16；
    电阻串电路，用于根据D1～D16、DN1～DN16和电流I，控制串联连入的电阻值，实现对输出电压Vref的控制。
  7. 根据权利要求6所述的数字可调的带隙基准电路，其特征在于，所述电阻串电路，包括：16支相同的电阻R8～R23、一电阻R24、16支相同的开关S1～S16和一电容C1；
    电阻R8的首端与开关S1的输入端相连；电阻R8的末端与电阻R9的首端和开关S2的输入端相连，依次类推，电阻R22的末端与电阻R23的首端和开关S16的输入端相连；电阻R8的首端连接所述电流I；电阻R13的尾端连接GND；16支相同的开关S1～S16的控制信号A1～A16和AN1～AN16分别依次连接D1～D16和DN1～DN16；16支相同的开关S1～S16的输出端与电阻R24、电容C1相连，电容C1另一端连接GND；电阻R24另一端作为输出端口输出Vref。
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