WO2019024803A1

WO2019024803A1 - Level shifter circuit and integrated circuit chip

Info

Publication number: WO2019024803A1
Application number: PCT/CN2018/097533
Authority: WO
Inventors: 党涛
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2017-07-31
Filing date: 2018-07-27
Publication date: 2019-02-07
Also published as: CN109327218B; CN109327218A

Abstract

Provided in the present disclosure are a level shifter circuit and an integrated circuit chip. In said level shifter circuit, access voltage division circuits are additionally arranged between the drain of a P-channel metal oxide semiconductor field effect transistor (PMOS) and the drain of an N-channel metal oxide semiconductor field effect transistor (NMOS), between the source and drain of the PMOS and between the source and drain of the NMOS respectively within a level shifter circuit composed of a first PMOS and a second PMOS that are cross-connected and a first NMOS and a second NMOS that serve as two low voltage domain inversion signal inputs.

Description

Level shift circuit and integrated circuit chip

Technical field

The present disclosure relates to the field of integrated circuits, and more particularly to a level shifting circuit and an integrated circuit chip.

Background technique

In digital-analog hybrid integrated circuit design, a level shifting circuit (Level Shifter) is usually used to convert a control signal of a digital module from a low voltage domain into a control signal of a high voltage domain for controlling an analog module in a high voltage domain. And implement different function configurations or performance adjustments. Typically, the low voltage domain portion of the level shifting circuit uses a low withstand voltage field effect transistor (MOS) and the high voltage portion uses a high withstand voltage MOS that is compatible with a high voltage source. For example, a level shift circuit that implements a control signal voltage from a low voltage of 0.9V to a high voltage of 3.3V is used, a low voltage domain uses a MOS with a withstand voltage of 0.9V, and a high voltage domain uses a MOS with a withstand voltage of 3.3V.

Different intellectual property modules (IP) are used in the system-on-chip (SOC) design, and different IPs need to be produced under a uniform selected process. For example, if a SOC chip selects a core of 0.9V (Core) and a 1.8V input-output (IO, Input-Output) device, and an IP used by the SOC chip needs to operate under 3.3V, then the slave digital core Part of the control signal sent to control the IP requires a level shift circuit to convert the signal voltage from 0.9V to 3.3V; the low-voltage part of the level shift circuit uses a device with a withstand voltage of 0.9V, but The high voltage part must use a device with a withstand voltage of 1.8V; the MOS with a withstand voltage of 1.8V operates at 3.3V and requires special design to avoid the overvoltage risk of MOS withstand voltage of 1.8V. Otherwise, Voltage can seriously affect the reliability of the device and the entire chip.

As shown in Figure 1, the conventional level shifting circuit uses an external bias BIASP/BIASN to clamp the internal node voltage to avoid overvoltage of the device; thus, it is not only necessary to rely on an external circuit to generate the BIASP/BIASN clamping voltage, and the output voltage will follow the process. The process corner changes, and the output node is in a high-impedance state; in order to avoid gate and substrate voltage (Vgb), drain (Drain), and substrate voltage (Vdb) overvoltage, each MOS The substrate and the source need to be connected, so that the MOS can not adopt the Well design, so the area is large; at the same time, the MOS overvoltage problem still exists in the power-up process of the level shift circuit.

Therefore, how to avoid the overvoltage risk of the MOS in the level shift circuit without relying on the external bias, and the output voltage is not affected by the process angle is a problem to be solved.

Summary of the invention

Embodiments of the present disclosure provide a level shift circuit including: a first P-channel field effect transistor (PMOS), a second PMOS, a first N-channel field effect transistor (NMOS), a second NMOS, and a first a voltage dividing circuit, a second voltage dividing circuit, a third voltage dividing circuit, a fourth voltage dividing circuit, a fifth voltage dividing circuit and a sixth voltage dividing circuit, wherein the source of the first PMOS and the substrate are connected to a power source, a source of the second PMOS and a substrate connected to a power source, a source of the first NMOS and a substrate being grounded, a source of the second NMOS and a substrate being grounded, and wherein the first PMOS source Connecting the first voltage dividing circuit to the drain, the second PMOS source and the drain are connected to the second voltage dividing circuit; the drain of the first PMOS is connected to the gate of the second PMOS And connecting to the drain of the first NMOS through the third voltage dividing circuit, the drain of the second PMOS is connected to the gate of the first PMOS, and passes through the fourth voltage dividing circuit and the a drain connection of the second NMOS; a connection of the first NMOS source and the drain to the fifth voltage dividing circuit, the second NMOS source and Connecting the sixth voltage dividing circuit between the poles; and setting the first voltage dividing circuit, the second voltage dividing circuit, the third voltage dividing circuit, the fourth voltage dividing circuit, the fifth voltage dividing circuit, and the sixth voltage dividing circuit The voltages for controlling the first PMOS, the second PMOS, the first NMOS, and the second NMOS do not exceed a preset value.

Embodiments of the present disclosure also provide an integrated circuit chip, the integrated circuit chip

The level shift circuit described above is included.

DRAWINGS

FIG. 1 is a schematic structural diagram of a level shift circuit.

2 is a schematic diagram showing the composition of a level shift circuit according to an embodiment of the present disclosure.

3 is a schematic diagram showing the composition of a level shifting circuit using a cascade structure of a diode-connected MOS as a voltage dividing circuit according to an embodiment of the present disclosure.

Detailed ways

In an embodiment of the present disclosure, a first P-channel field effect transistor (PMOS) and a second PMOS connected by a cross-connect and a first N-channel field effect transistor (NMOS) and a second input as an inverted signal of two low voltage domains may be used. In the existing level shifting circuit composed of two NMOSs, an access voltage dividing circuit is respectively added between the drain of the PMOS and the drain of the NMOS, between the PMOS source and the drain, and between the NMOS source and the drain, respectively. .

The present disclosure will be further described in detail below with reference to the embodiments.

The embodiment of the present disclosure provides a level shifting circuit. As shown in FIG. 2, the circuit includes: a first PMOS M14, a second PMOS M15, a first NMOS M0, a second NMOS M1, a first voltage dividing circuit, and a first a voltage divider circuit, a third voltage divider circuit, a fourth voltage divider circuit, a fifth voltage divider circuit, and a sixth voltage divider circuit, wherein the source of the first PMOS M14 and the substrate are connected to a power supply ADCC, The source and substrate of the two PMOS M15 are connected to the power supply ADCC, the source of the first NMOS M0 and the substrate are grounded, and the source of the second NMOS M1 and the substrate are grounded.

In one embodiment, the first PMOS M14 is connected between the source and the drain of the first voltage dividing circuit, and the second PMOS M15 is connected between the source and the drain.

The drain of the first PMOS M14 is connected to the gate of the second PMOS M15, and is connected to the drain of the first NMOS M0 via the third voltage dividing circuit. The drain of the second PMOS M15 is connected to the gate of the first PMOS M14, and is connected to the drain of the second NMOS M1 via the fourth voltage dividing circuit.

The fifth voltage dividing circuit is connected between the source and the drain of the first NMOS M0, and the sixth voltage dividing circuit is connected between the source and the drain of the second NMOS M1.

The gate of the first NMOS M0 is an input end of the first signal INP, the gate of the second NMOS M1 is an input end of the second signal INN, the drain of the second PMOS M15 and the second NMOS M1 The drains are respectively a shifting high level output terminal and a shifting low level output terminal corresponding to the first signal INP, and the output signals can be represented by OUTPH and OUTPL respectively; the drain and the drain of the first PMOS M14 The drains of the first NMOS MO are respectively a shift high level output terminal and a shift low level output terminal corresponding to the second signal INN, and the output signals can be represented by OUTNH and OUTNL, respectively. Here, the first signal INP and the second signal INN may be a set of inverted input signals from a low voltage domain in level shifting.

The first voltage dividing circuit, the second voltage dividing circuit, the third voltage dividing circuit, the fourth voltage dividing circuit, the fifth voltage dividing circuit and the sixth voltage dividing circuit are respectively configured to control the first PMOS M14 and the second PMOS The voltage of M15, the first NMOS M0, and the second NMOS M1 does not exceed a preset value. Specifically, when the first signal is at a high level, the first voltage dividing circuit and the third voltage dividing circuit are configured to control the voltages of the first PMOS M14 and the first NMOS M0 not to exceed a preset value, the fourth point The voltage circuit and the sixth voltage dividing circuit are configured to control the voltages of the second PMOS M15 and the second NMOS M1 not to exceed a preset value; when the first signal is low level, the third voltage dividing circuit and the fifth point The voltage circuit is configured to control the voltages of the first PMOS M14 and the first NMOS M0 not to exceed a preset value, and the second voltage dividing circuit and the fourth voltage dividing circuit are configured to control the voltages of the second PMOS M15 and the second NMOS M1 Exceeded the preset value. The voltages of the first PMOS M14, the second PMOS M15, the first NMOS M0, and the second NMOS M1 may refer to voltages that are received between the poles of the MOS; the preset value may be according to the tolerance of each MOS in the circuit. The voltage value is set to a value such that the preset value is not greater than the withstand voltage value of the MOS.

Here, the level shifting circuit may be a circuit in an integrated circuit chip, the first voltage dividing circuit, the second voltage dividing circuit, the third voltage dividing circuit, the fourth voltage dividing circuit, the fifth voltage dividing circuit, and The sixth voltage dividing circuit may be a circuit having an impedance characteristic, such as a polysilicon strip resistor used in an integrated circuit chip.

Specifically, as shown in FIG. 2, the power supply AVDD is a high voltage domain power supply, such as 3.3V. The MOS of the first NMOS M0, the second NMOS M1, the first PMOS M14, and the second PMOS M15 in the level shift circuit may be a MOS with a withstand voltage lower than a high voltage domain voltage, such as a withstand voltage of 1.8V. The first PMOS M14 and the second PMOS M15 are cross-connected PMOSs; the first signal INP and the second signal INN may be a group of mutually inverted signals, such as differential signals, etc., or may be level shifted. And a set of signals and the like which are inverted by the inverter; the first signal INP and the second signal INN may be low voltage domain signals, such as a signal level of 0.9V.

When the input first signal INP is at a high level, the second signal INN is at a low level. In this case, according to the NMOS characteristic, the first NMOS M0 is turned on, the second NMOS M1 is turned off, and the OUTNL output is about 0V. The OUTNH output is about the partial voltage of the first voltage dividing circuit and the third voltage dividing circuit. According to the PMOS characteristic, the second PMOS M15 is turned on; the OUTPH output is about the power supply voltage AVDD, the first PMOS M14 is turned off; the OUTPL output is about The partial pressure of the fourth voltage dividing circuit and the sixth voltage dividing circuit.

When the first signal INP is low, the second signal INN is at a high level. In this case, the first NMOS M0 is turned off, the second NMOS M1 is turned on; and the second signal INN is shifted by a low level. The output OUTNL output is about the partial voltage of the third voltage dividing circuit and the fifth voltage dividing circuit, and the shifting high level output terminal OUTNH corresponding to the second signal INN is about the power supply voltage AVDD, and the second PMOS M15 is turned off; The output of the low-level output terminal OUTPL corresponding to a signal INP is about 0V, and the output of the first high-level output terminal OUTPH corresponding to the first signal INP is about the partial voltage of the second voltage dividing circuit and the fourth voltage dividing circuit. The first PMOS M14 is turned on.

The level shifting circuit is followed by a high voltage domain circuit, so that the output signal can be taken out at different circuit nodes as needed, for example, the output signals OUTPH, OUTPL, OUTNH corresponding to the first signal INP and the second signal INN can be extracted. And OUTNL et al.

When the first signal INP is at a high level or a low level, the voltage difference between the respective poles of the first PMOS M14 and the second PMOS M15 is at most a voltage difference between the power supply signal AVDD and the output signal OUTPH or the power supply signal AVDD and the output signal OUTNH. Voltage; the voltage difference between the poles of the first NMOS M0 and the second NMOS M1 is at most a voltage difference between the output signal OUTPL and ground or a voltage difference between the output signal OUTNL and ground. The resistance of the voltage dividing circuit may be preset in the circuit design to adjust the voltage division, so that the first PMOS M14, the second PMOS M15, the first NMOS M0, and the second NMOS M1 are in each case between the poles. The pressure difference is less than the own withstand voltage value.

For example, when the high voltage domain voltage is 3.3V and the MOS withstand voltage is 1.8V, the impedance values of the voltage divider circuits can be set to be the same. Thus, when the first signal INP is at a high level, the output voltage OUTNL outputs a divided voltage of the third voltage dividing circuit and the fifth voltage dividing circuit, that is, about 1.65V; and the output voltage OUTNH output is about AVDD, that is, approximately 3.3V; the output voltage OUTPL output is about 0V, and the output voltage OUTPH output is about the partial voltage of the second voltage dividing circuit and the fourth voltage dividing circuit, that is, about 1.65V.

When the first signal INP is low, the second signal INN is at a high level; in this case, the output voltage OUTNL outputs a partial voltage of about the third voltage dividing circuit and the fifth voltage dividing circuit, that is, about 1.65. V; the output voltage OUTNH output is about the power supply voltage AVDD, that is, 3.3V; the output voltage OUTPL output is about 0V, and the output voltage OUTPH output is about the partial voltage of the second voltage dividing circuit and the fourth voltage dividing circuit, that is, about 1.65V. . As such, the first PMOS M14, the second PMOS M15, the first NMOS M0, and the second NMOS M1 have voltage differences between the electrodes of less than 1.8V in each case.

As such, the voltage difference between the poles of the first PMOS M14, the second PMOS M15, the first NMOS M0, and the second NMOS M1 in each case is less than 1.8V, thereby avoiding the risk of overvoltage. At the same time, each of the output voltage signals OUTPH, OUTPL, OUTNH, and OUTNL is not affected by the process, but is only related to the voltage division of each voltage dividing circuit.

Here, the impedance values of the first voltage dividing circuit, the second voltage dividing circuit, the third voltage dividing circuit, the fourth voltage dividing circuit, the fifth voltage dividing circuit, and the sixth voltage dividing circuit may be set according to a voltage requirement of the output signal; In this way, the required output signal voltage can be obtained after the voltage division.

In one embodiment, the first voltage dividing circuit, the second voltage dividing circuit, the third voltage dividing circuit, the fourth voltage dividing circuit, the fifth voltage dividing circuit, and the sixth voltage dividing circuit may be single diode connections, respectively. Cascade structure of MOS or a diode-connected MOS.

Here, the diode-connected MOS means that the gate and the drain of the MOS are connected as one end, and the MOS source is used as one end. The diode-connected MOS has characteristics similar to diode forward conduction and exhibits a small signal characteristic like a small resistance. The diode-connected MOS generates a required voltage division effect by cascading, thereby avoiding an overvoltage condition of all MOSs in the level shifting circuit. In the cascade structure of the diode-connected MOS, MOSs with a withstand voltage lower than the high voltage domain voltage can be used.

In one embodiment, the cascade structure of the diode-connected MOS is similar to a diode having a forward conducting property; in the level shifting circuit, the first voltage dividing circuit and the source of the first PMOS a connection point and a connection point of the first voltage dividing circuit and a drain of the first PMOS are respectively a current inflow end and an outflow end of the first voltage dividing circuit; a source of the second voltage dividing circuit and the second PMOS a connection point of the pole and a connection point of the second voltage dividing circuit and the drain of the second PMOS are respectively a current inflow end and an outflow end of the second voltage dividing circuit; the third voltage dividing circuit and the first PMOS a drain connection point and a connection point of the third voltage dividing circuit and the drain of the first NMOS are respectively a current inflow end and an outflow end of the third voltage dividing circuit; the fourth voltage dividing circuit and the second a drain connection point of the PMOS and a connection point of the fourth voltage dividing circuit and the drain of the second NMOS are respectively a current inflow end and an outflow end of the fourth voltage dividing circuit; the fifth voltage dividing circuit and the a drain connection point of an NMOS and a connection point of the fifth voltage dividing circuit and a source of the first NMOS respectively a current inflow end and an outflow end of the fifth voltage dividing circuit; and a drain connection point of the sixth voltage dividing circuit and the second NMOS and a connection point of the sixth voltage dividing circuit and the source of the second NMOS The current inflow end and the outflow end of the sixth voltage dividing circuit are respectively.

In one embodiment, the cascade structure of the diode-connected MOS is formed by cascading two or more diode-connected NMOSs and/or diode-connected PMOSs. The first voltage dividing circuit, the second voltage dividing circuit, the third voltage dividing circuit, the fourth voltage dividing circuit, and the fifth may be adjusted according to the difference between the used MOS and the power supply voltage AVDD and the swing range of the output signal. The voltage dividing circuit and the diode of the sixth voltage dividing circuit are connected to the cascading structure of the MOS in the cascade structure and the size of the MOS. The larger the MOS size, the stronger the current passing force. In one embodiment, the MOS in the cascade structure of the diode-connected MOS may be NMOS, PMOS or a hybrid. According to the actual subsequent circuit requirements, different circuit nodes in the cascaded MOS in the voltage dividing circuit can be taken out as an output signal.

In one embodiment, as shown in FIG. 3, the first voltage dividing circuit, the second voltage dividing circuit, the third voltage dividing circuit, the fourth voltage dividing circuit, the fifth voltage dividing circuit, and the sixth voltage dividing circuit The cascade structure of the diode-connected MOS includes a cascade structure of two diode-connected PMOSs. The cascode structure of the two diode-connected PMOSs includes: a substrate of a first cascode PMOS and a substrate connection of a second cascode PMOS, and is connected to a source of the first cascode PMOS to flow as a current a gate and a drain of the first cascode PMOS are connected and connected to a source of the second cascode PMOS; and a gate and a drain of the second cascode PMOS are connected to flow as a current end. For example, in the first voltage dividing circuit, M7 is a first cascaded PMOS, and M6 is a second cascaded PMOS.

Specifically, as shown in Figure 3, M6 and M7 form the first voltage divider circuit, M12 and M13 form the second voltage divider circuit, M4 and M5 form the third voltage divider circuit, and M10 and M11 form the fourth component. The voltage circuit, M2 and M3 form a fifth voltage dividing circuit, and M8 and M9 form a sixth voltage dividing circuit. In the level shift circuit shown in Figure 3, all MOSs can be 1.8V withstand voltage MOS, can not directly withstand AVDD 3.3V high voltage, in order to avoid 1.8V withstand voltage MOS tube overvoltage, cascode diode circuit Two-stage cascading structure eliminates the need for an external bias voltage; INP/INN is the inverting input signal from the low voltage domain, connected to the M0 and M1 gates respectively; M2 to M13 are diode-connected PMOS; M14 and M15 are cross-connected PMOS. At the same time, according to the actual subsequent circuit requirements, different circuit nodes in the cascaded PMOS in the voltage dividing circuit can be taken out as an output signal, for example, the M4 and M5 cascade nodes CN, and the M10 and M11 cascade nodes CP are taken out as output signals.

When the sizes of M2 to M13 are the same, that is, the PMOS impedance of each diode is the same, the impedance of each voltage dividing circuit is the same; when the first signal INP is input to the high level, and the second signal INN is the low level, the output signal OUTNL output is about 0V. The cascaded node CN output is approximately AVDD/4, the output signal OUTNH output is approximately AVDD/2, M15 is turned on, the output signal OUTPL output is approximately AVDD/2, and the cascade node CP output is approximately AVDD*3/4, output signal The OUTPH output is approximately AVDD and the M14 is turned off. When the input first signal INP is low and the second signal INN is high, the output signal OUTNL output is about AVDD/2, the cascade node CN output is about AVDD*3/4, and the output signal OUTNH output is about AVDD. M15 is turned off, the output signal OUTPL output is about 0V, the cascade node CP output is about AVDD/4, and the output signal OUTPH output is about AVDD/2, and M14 is turned on. In summary, the output signal OUTPH/OUTNH output range is about AVDD/2~AVDD, the output signal OUTPL/OUTNL output range is about 0~AVDD/2, and the cascade node CP/CN output range is about 1/4*AVDD. ~3/4*AVDD. Since the voltage of each node is generated by diode-connected PMOS voltage division, there will be no overvoltage problem during normal operation and power-on.

By adjusting the size of the M2 to M7 PMOS and simultaneously adjusting the size of the M8 to M13 PMOS to maintain the left and right symmetry of the level shifting circuit, different output voltage ranges can be adjusted for use by subsequent circuits. If M2 and M3 are larger than M4 and M5, and M8 and M9 are the same as M2 and M3, OUTPL and OUTNL output low voltage close to ground voltage, and output high level is lower than AVDD/2; M3 is smaller than M4 and M5, and M8 and M9 are kept the same size as M2 and M3. OUTPL and OUTNL output low voltage close to ground voltage, and output high level is higher than AVDD/2. If M6 and M7 are larger than M10 and M11, and M12 and M13 are the same size as M6 and M7, OUTPH and OUTNH output high voltage is close to the power supply voltage, and output low level is higher than AVDD/2; if M6, M7 is smaller than M10 and M11, and M12 and M13 are the same size as M6 and M7. The OUTPH and OUTNH output high voltages are close to the power supply voltage, and the output low level is lower than AVDD/2.

In one embodiment, the MOSs in the cascade structure of the diode-connected MOS are in the same well.

Specifically, in order to save the layout area, the M2 and M3 substrates can be connected to the same well, the M4 and M5 substrates are connected to the same well, the M6 and M7 substrates are connected to the same well, and the M8 and M9 substrates are connected to the same well. The M10 and M11 substrates are connected using the same well, and the M12 and M13 substrates are connected using the same well. In this way, the common-well design can save the layout area of the integrated circuit compared with the existing circuit MOS.

An integrated circuit chip provided by an embodiment of the present disclosure includes a level shift circuit. As shown in FIG. 2, the circuit includes: a first PMOS M14, a second PMOS M15, a first NMOS M0, and a second NMOS M1. a voltage circuit, a second voltage dividing circuit, a third voltage dividing circuit, a fourth voltage dividing circuit, a fifth voltage dividing circuit and a sixth voltage dividing circuit; the source of the first PMOS M14 and the substrate are connected to a power source, The source of the second PMOS M15 and the substrate are connected to a power source; the source of the first NMOS M0 and the substrate are grounded, and the source of the second NMOS M1 and the substrate are grounded.

The first voltage dividing circuit is connected between the source and the drain of the first PMOS M14, and the second voltage dividing circuit is connected between the source and the drain of the second PMOS M15.

The drain of the first PMOS M14 is connected to the gate of the second PMOS M15, and is connected to the drain of the first NMOS M0 through the third voltage dividing circuit; the drain connection of the second PMOS M15 The gate of the first PMOS M14 is connected to the drain of the second NMOS M1 via the fourth voltage dividing circuit.

The gate of the first NMOS M0 is an input end of the first signal INP, the gate of the second NMOS M1 is an input end of the second signal INN, the drain of the second PMOS M15 and the second NMOS M1 The drains are respectively a shifting high level output terminal and a shifting low level output terminal corresponding to the first signal INP, and the output signals can be represented by OUTPH and OUTPL respectively; the drain and the drain of the first PMOS M14 The drains of the first NMOS M0 are respectively a shift high level output terminal and a shift low level output terminal corresponding to the second signal INN, and the output signals can be represented by OUTNL and OUTNL, respectively. Here, the first signal INP and the second signal INN may be a set of inverted input signals in a low voltage domain from the level shift.

The first voltage dividing circuit, the second voltage dividing circuit, the third voltage dividing circuit, the fourth voltage dividing circuit, the fifth voltage dividing circuit and the sixth voltage dividing circuit are respectively configured to control the first PMOS and the second PMOS The voltages of the first NMOS and the second NMOS do not exceed a preset value. Specifically, when the first signal is at a high level, the first voltage dividing circuit and the third voltage dividing circuit are configured to control the voltages of the first PMOS and the first NMOS not to exceed a preset value, and the fourth voltage dividing circuit And a sixth voltage dividing circuit for controlling the voltages of the second PMOS and the second NMOS not exceeding a preset value; when the first signal is a low level, the third voltage dividing circuit and the fifth voltage dividing circuit are used The voltages of the first PMOS and the first NMOS are controlled not to exceed a preset value, and the second voltage dividing circuit and the fourth voltage dividing circuit are configured to control the voltages of the second PMOS and the second NMOS not to exceed a preset value. The voltages of the first PMOS, the second PMOS, the first NMOS, and the second NMOS may refer to voltages that are received between the poles of the MOS; the preset value may be set according to the withstand voltage value of each MOS in the circuit. a value such that the preset value is not greater than a withstand voltage value of the MOS; here, the level shift circuit may be a circuit in an integrated circuit chip, the first voltage dividing circuit, the second voltage dividing circuit, The third voltage dividing circuit, the fourth voltage dividing circuit, the fifth voltage dividing circuit and the sixth voltage dividing circuit may each be a circuit having an impedance characteristic, such as a polysilicon strip resistor used in an integrated circuit chip.

Specifically, as shown in FIG. 2, the power supply AVDD is a high voltage domain power supply, such as 3.3V; the MOS of the first NMOS M0, the second NMOS M1, the first PMOS M14, and the second PMOS M15 in the level shift circuit may be Is a MOS with a withstand voltage lower than a high voltage domain voltage, such as a withstand voltage of 1.8V; the first PMOS M14 and the second PMOS M15 are cross-connected PMOSs; the first signal INP and the second signal INN may be mutual A set of signals that are inverted, such as a differential signal, etc., may also be a set of signals or the like that are inverted by an inverter for level shifting; the first signal INP and the second signal INN may be low voltage The domain signal, such as the signal level is 0.9V.

When the input first signal INP is high level, the second signal INN is low level; according to the NMOS characteristic, the first NMOS M0 is turned on, the second NMOS M1 is turned off, the output signal OUTNL output is about 0V, and the output signal OUTNH is output. The output is about the partial voltage of the first voltage dividing circuit and the third voltage dividing circuit. According to the PMOS characteristic, the first PMOS M15 is turned on; the output signal OUTPH output is about the power supply voltage AVDD, the first PMOS M14 is turned off; the output signal OUTPL is output. It is about the partial pressure of the fourth voltage dividing circuit and the sixth voltage dividing circuit.

When the first signal INP is low, the second signal INN is at a high level, the first NMOS M0 is turned off, the second NMOS M1 is turned on, and the output signal OUTNL is outputted by the third voltage dividing circuit and the fifth voltage dividing circuit. The voltage is divided, the output signal OUTNH output is about the power supply voltage AVDD, the second PMOS M15 is turned off; the output signal OUTPL output is about 0V, and the output signal OUTPH output is about the partial voltage of the second voltage dividing circuit and the fourth voltage dividing circuit, A PMOS M14 is turned on.

The level transfer circuit is followed by a high voltage domain circuit, and the output signal can be extracted at different circuit nodes according to requirements. For example, the output signals OUTPH, OUTPL, OUTNH, OUTNL, etc. corresponding to the first signal INP and the second signal INN can be extracted. .

When the first signal INP is at a high level or a low level, the voltage difference between the respective poles of the first PMOS M14 and the second PMOS M15 is at most a voltage difference between the power supply signal AVDD and the output signal OUTPH or the power supply signal AVDD and the output signal OUTNH. Voltage; the voltage difference between the poles of the first NMOS M0 and the second NMOS M1 is at most a voltage difference between the output signal OUTPL and the ground or a voltage difference between the output signal OUTNL and the ground; can be preset in the circuit design The resistance of the voltage dividing circuit is used to adjust the voltage division so that the voltage difference between the first PMOS M14, the second PMOS M15, the first NMOS M0 and the second NMOS M1 in each case is smaller than the own withstand voltage value.

For example, when the high voltage domain voltage is 3.3V and the MOS withstand voltage is 1.8V, the impedance values of the voltage divider circuits can be set to be the same. Thus, when the first signal INP is at a high level, the output signal OUTNL outputs a divided voltage of the third voltage dividing circuit and the fifth voltage dividing circuit, that is, about 1.65V; and the output signal OUTNH output is about the power supply voltage AVDD, that is, It is about 3.3V; the output signal OUTPL output is about 0V, and the output signal OUTPH output is about the partial voltage of the second voltage dividing circuit and the fourth voltage dividing circuit, that is, about 1.65V.

When the first signal INP is low, the second signal INN is at a high level; in this case, the output signal OUTNL outputs a partial voltage of about the third voltage dividing circuit and the fifth voltage dividing circuit, that is, about 1.65. V; the output signal OUTNH output is about the power supply voltage AVDD, that is, 3.3V; the output signal OUTPL output is about 0V, and the output signal OUTPH output is about the partial voltage of the second voltage dividing circuit and the fourth voltage dividing circuit, that is, about 1.65V. Thus, the voltage difference between the first PMOS M14, the second PMOS M15, the first NMOS M0, and the second NMOS M1 in each case is less than 1.8V.

As such, the voltage difference between the poles of the first PMOS M14, the second PMOS M15, the first NMOS M0, and the second NMOS M1 in each case is less than 1.8V, thereby avoiding the risk of overvoltage. At the same time, OUTPH, OUTPL, OUTNH and OUTNL are not affected by the process and are only related to the voltage division of each voltage divider circuit.

Here, the diode-connected MOS means that the gate and the drain of the MOS are connected as one end, and the MOS source serves as one end. The diode-connected MOS has a characteristic similar to a diode forward conduction and exhibits a small signal characteristic like a small resistance; the diode-connected MOS generates a required voltage division effect by cascading, avoiding the level shifting circuit All MOSs have an overvoltage condition. In the cascade structure of the diode-connected MOS, MOSs with a withstand voltage lower than the high voltage domain voltage can be used. According to the actual subsequent circuit requirements, different circuit nodes in the cascaded MOS in the voltage dividing circuit can be taken out as an output signal.

In one embodiment, the cascade structure of the diode-connected MOS is similar to a diode having a forward conducting property; in the level shifting circuit, the first voltage dividing circuit and the source of the first PMOS a connection point and a connection point of the first voltage dividing circuit and a drain of the first PMOS are respectively a current inflow end and an outflow end of the first voltage dividing circuit; a source of the second voltage dividing circuit and the second PMOS a connection point of the pole and a connection point of the second voltage dividing circuit and the drain of the second PMOS are respectively a current inflow end and an outflow end of the second voltage dividing circuit; the third voltage dividing circuit and the first PMOS a drain connection point and a connection point of the third voltage dividing circuit and the drain of the first NMOS are respectively a current inflow end and an outflow end of the third voltage dividing circuit; the fourth voltage dividing circuit and the second a drain connection point of the PMOS and a connection point of the fourth voltage dividing circuit and the drain of the second NMOS are respectively a current inflow end and an outflow end of the fourth voltage dividing circuit; the fifth voltage dividing circuit and the a drain connection point of an NMOS and a connection point of the fifth voltage dividing circuit and a source of the first NMOS respectively a current inflow end and an outflow end of the fifth voltage dividing circuit; a drain connection point of the sixth voltage dividing circuit and the second NMOS; and a connection point of the sixth voltage dividing circuit and the source of the second NMOS respectively It is a current inflow end and an outflow end of the sixth voltage dividing circuit.

In one embodiment, the cascade structure of the diode-connected MOS is formed by cascading two or more diode-connected NMOSs and/or diode-connected PMOSs. Adjusting the first voltage dividing circuit, the second voltage dividing circuit, the third voltage dividing circuit, the fourth voltage dividing circuit, and the fifth partial voltage according to the difference between the MOS and AVDD voltages used and the swing range of the output signal The number of cascaded stages and the size of the MOS in the cascade structure of the diode and the MOS of the sixth voltage dividing circuit; the larger the MOS size, the stronger the current passing force; wherein the MOS in the cascade structure of the diode-connected MOS can It is NMOS, PMOS or mixed.

In one embodiment, as shown in FIG. 3, the first voltage dividing circuit, the second voltage dividing circuit, the third voltage dividing circuit, the fourth voltage dividing circuit, the fifth voltage dividing circuit, and the sixth voltage dividing circuit The cascade structure of the diode-connected MOS includes a cascade structure of two diode-connected PMOSs. The cascading structure of the two diode-connected PMOSs includes: a substrate of a first cascode PMOS and a substrate connection of a second cascode PMOS, and is connected to a source of the first cascode PMOS as a current inflow end a gate and a drain of the first cascode PMOS are connected and connected to a source of the second cascode PMOS; a gate and a drain of the second cascode PMOS are connected and serve as a current outflow terminal . For example, in the first voltage dividing circuit, M7 is a first cascaded PMOS; M6 is a second cascaded PMOS.

Specifically, as shown in Figure 3, M6 and M7 form the first voltage divider circuit, M12 and M13 form the second voltage divider circuit, M4 and M5 form the third voltage divider circuit, and M10 and M11 form the fourth component. The voltage circuit, M2 and M3 form the fifth voltage divider circuit, M8 and M9 form the sixth voltage divider circuit; in the level shift circuit shown in Figure 3, all MOS can be 1.8V withstand voltage MOS, not directly To withstand AVDD's 3.3V high voltage, in order to avoid 1.8V withstand voltage MOS overvoltage, the cascaded diode circuit uses a two-stage cascade structure, no external bias voltage is required; INP/INN is an inverting input signal from the low voltage domain. , respectively connected to the M0 and M1 gates; M2 to M13 are diode-connected PMOS; M14 and M15 are cross-connected PMOS. At the same time, according to the actual subsequent circuit requirements, different circuit nodes in the cascaded PMOS in the voltage dividing circuit can be taken out as an output signal, for example, the M4 and M5 cascade nodes CN and M10 and the M11 cascade node CP are taken out as output signals.

When the sizes of M2 to M13 are the same, that is, the PMOS impedance of each diode is the same, the impedance of each voltage dividing circuit is the same; when the first signal INP is input to the high level, and the second signal INN is the low level, the output signal OUTNL output is about 0V. The cascaded node CN output is approximately AVDD/4, the output signal OUTNH output is approximately AVDD/2, the second PMOS M15 is turned on, the output signal OUTPL output is approximately AVDD/2, and the cascaded node CP output is approximately AVDD*3/4 The output signal OUTPH output is approximately AVDD, and the first PMOS M14 is turned off. When the input first signal INP is low and the second signal INN is high, the output signal OUTNL output is about AVDD/2, the cascade node CN output is about AVDD*3/4, and the output signal OUTNH output is about AVDD. The second PMOS M15 is turned off, the output signal OUTPL output is about 0V, the cascade node CP output is about AVDD/4, the output signal OUTPH output is about AVDD/2, and the first PMOS M14 is turned on. In summary, the output signal OUTPH/OUTNH output range is about AVDD/2~AVDD, the output signal OUTPL/OUTNL output range is about 0~AVDD/2, and the cascade node CP/CN output range is about 1/4*AVDD. ~3/4*AVDD. Since the voltage of each node is generated by diode-connected PMOS voltage division, there will be no overvoltage problem during normal operation and power-on.

By adjusting the size of the M2 to M7 PMOS and simultaneously adjusting the size of the M8 to M13 PMOS to maintain the left and right symmetry of the level shifting circuit, different output voltage ranges can be adjusted for use by subsequent circuits. If M2 and M3 are larger than M4 and M5, and M8 and M9 are the same as M2 and M3, OUTPL and OUTNL output low voltage close to ground voltage, and output high level is lower than AVDD/2; M3 is smaller than M4 and M5, and M8 and M9 are kept the same size as M2 and M3. OUTPL and OUTNL output low voltage close to ground voltage, and output high level is higher than AVDD/2. If M6 and M7 are larger than M10 and M11, and M12 and M13 are the same size as M6 and M7, OUTPH and OUTNH output high voltage is close to the power supply voltage, and output low level is higher than AVDD/2; if M6, M7 is relatively smaller than M10 and M11. At the same time, M12 and M13 are kept the same size as M6 and M7. The OUTPH and OUTNH output high voltages are close to the power supply voltage, and the output low level is lower than AVDD/2.

Specifically, in order to save the layout area, the M2 and M3 substrates can be connected to the same well, the M4 and M5 substrates are connected to the same well, the M6 and M7 substrates are connected to the same well, and the M8 and M9 substrates are connected to the same well. The M10 and M11 substrates are connected to the same well, and the M12 and M13 substrates are connected to the same well; thus, compared with the existing circuit MOS, the common well design can save the layout area of the integrated circuit.

The above is only an exemplary embodiment of the present disclosure, which is not intended to limit the scope of the disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and scope of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

A level shifting circuit comprising: a first P-channel field effect transistor PMOS, a second PMOS, a first N-channel field effect transistor NMOS, a second NMOS, a first voltage dividing circuit, a second voltage dividing circuit, and a third point a voltage circuit, a fourth voltage dividing circuit, a fifth voltage dividing circuit and a sixth voltage dividing circuit, wherein a source of the first PMOS and a substrate are connected to a power source, and a source of the second PMOS and a substrate are connected to a power source The source of the first NMOS and the substrate are grounded, the source of the second NMOS and the substrate are grounded, and wherein

The first PMOS source and the drain are connected to the first voltage dividing circuit, and the second PMOS source and the drain are connected to the second voltage dividing circuit;

The drain of the first PMOS is connected to the gate of the second PMOS, and is connected to the drain of the first NMOS through the third voltage dividing circuit, and the drain of the second PMOS is connected to the first a gate of the PMOS and connected between the fourth voltage dividing circuit and the drain of the second NMOS;

Connecting a first voltage dividing circuit between the first NMOS source and the drain, and connecting the sixth voltage dividing circuit between the second NMOS source and the drain;

The first voltage dividing circuit, the second voltage dividing circuit, the third voltage dividing circuit, the fourth voltage dividing circuit, the fifth voltage dividing circuit and the sixth voltage dividing circuit are arranged to control the first PMOS, the second PMOS, The voltages of the first NMOS and the second NMOS do not exceed a preset value.
The circuit of claim 1 wherein

a gate of the first NMOS is an input end of the first signal, a gate of the second NMOS is an input end of the second signal, and a drain of the second PMOS and a drain of the second NMOS are respectively a shifting high level output end corresponding to the first signal and a shifting low level output end;

The drain of the first PMOS and the drain of the first NMOS are respectively a shift high level output end and a shift low level output end corresponding to the second signal;

The first signal is opposite in phase to the second signal.
The circuit of claim 2, wherein

When the first signal is high level, the first voltage dividing circuit and the third voltage dividing circuit are configured to control the voltages of the first PMOS and the first NMOS not to exceed a preset value;

When the first signal is high level, the fourth voltage dividing circuit and the sixth voltage dividing circuit are configured to control the voltages of the second PMOS and the second NMOS not to exceed a preset value;

The third voltage dividing circuit and the fifth voltage dividing circuit are configured to control the voltages of the first PMOS and the first NMOS not to exceed a preset value when the first signal is a low level; and when the first When the signal is low, the second voltage dividing circuit and the fourth voltage dividing circuit are configured to control the voltages of the second PMOS and the second NMOS not to exceed a preset value.
The circuit of claim 2 wherein each of the voltage dividing circuits comprises a cascade structure of a single diode-connected MOS or a diode-connected MOS.
The circuit according to claim 4, wherein

a connection point of the first voltage dividing circuit and a source of the first PMOS and a connection point of the first voltage dividing circuit and the drain of the first PMOS are current inflow and outflow of the first voltage dividing circuit, respectively end;

a connection point of the second voltage dividing circuit and a source of the second PMOS and a connection point of the second voltage dividing circuit and the drain of the second PMOS are current inflow and outflow of the second voltage dividing circuit, respectively end;

a connection point of the third voltage dividing circuit to the drain connection point of the first PMOS and the drain of the third voltage dividing circuit and the first NMOS is a current inflow end and an outflow end of the third voltage dividing circuit, respectively ;

a connection point of the drain connection point of the fourth voltage dividing circuit and the second PMOS and a connection point of the fourth voltage dividing circuit and the drain of the second NMOS are respectively a current inflow end and an outflow end of the fourth voltage dividing circuit ;

a connection point of the fifth voltage dividing circuit to the drain of the first NMOS and a source of the fifth voltage dividing circuit and the source of the first NMOS are respectively a current inflow end and an outflow end of the fifth voltage dividing circuit ;and

a connection point of the sixth voltage dividing circuit and the drain connection point of the second NMOS and a source of the sixth voltage dividing circuit and the second NMOS are respectively a current inflow end and an outflow end of the sixth voltage dividing circuit .
The circuit of claim 5 wherein the cascade structure of the diode-connected MOS is formed by cascading two or more diode-connected NMOSs and/or diode-connected PMOSs.
The circuit of claim 6 wherein the cascade structure of the diode-connected MOS comprises a cascade structure of two diode-connected PMOSs.
The circuit of claim 7 wherein

The cascode structure of the two diode-connected PMOSs includes: a substrate of a first cascode PMOS and a substrate connection of a second cascode PMOS, and is connected to a source of the first cascode PMOS to serve as a current Inflow end

a gate and a drain of the first cascode PMOS are connected and connected to a source of the second cascode PMOS;

The gate and the drain of the second cascode PMOS are connected to serve as a current outflow terminal.
The circuit according to any one of claims 4 to 8, wherein the MOSs in the cascade structure of the diode-connected MOS are in the same well.
The circuit according to any one of claims 1 to 8, wherein the first PMOS, the second PMOS, the first NMOS, and the second NMOS have a withstand voltage value that is less than a power supply voltage value.
An integrated circuit chip comprising the level shifting circuit of any one of claims 1 to 10.