WO2022116416A1

WO2022116416A1 - Schmitt trigger

Info

Publication number: WO2022116416A1
Application number: PCT/CN2021/082554
Authority: WO
Inventors: 刘炼阁; 温长清; 梁爱梅; 杨黎; 张千文
Original assignee: 深圳市紫光同创电子有限公司
Priority date: 2020-12-01
Filing date: 2021-03-24
Publication date: 2022-06-09
Also published as: CN112468121A; JP2023547187A

Abstract

Provided in the present application is a Schmitt trigger, comprising a first inverter which forms a series connection between an input node and a connection node, a second inverter which forms a series connection between the connection node and a feedback node, a third inverter which forms a series connection between the feedback node and an output node, a first adjustment branch and a third adjustment branch which are coupled between the connection node and the feedback node and which are connected to a power supply, and a second adjustment branch and a fourth adjustment branch which are coupled between the connection node and the feedback node and which are connected to a ground terminal. The second inverter, first adjustment branch and third adjustment branch constitute a first positive feedback loop, and the second inverter, second adjustment branch and fourth adjustment branch constitute a second positive feedback loop. The first positive feedback loop is connected, so that a high-to-low input voltage outputted by the output node increases, and a first flip point is shifted right; and the second positive feedback loop is connected, so that a low-to-high input voltage outputted by the output node decreases, and a second flip point is shifted left, thereby achieving a hysteresis effect.

Description

Schmitt trigger

【Technical field】

The present application relates to the technical field of integrated circuit chips, and in particular, to a Schmitt trigger.

【Background technique】

For a general inverter, due to the influence of noise, the input signal may flip back and forth near the threshold point, bringing noise to the output, thus introducing a hysteresis effect to form a Schmitt trigger.

In the prior art, in a common flip-flop circuit, a hysteresis effect is achieved by introducing positive feedback through a PMOS transistor and an NMOS transistor. However, connecting the PMOS tube to the ground and the NMOS tube to the power supply may cause ESD (Electro-Static discharge, electrostatic discharge) problems, and the hysteresis window is fixed and cannot be configured and adjusted.

【Contents of application】

The purpose of the present application is to provide a Schmitt trigger to achieve a hysteresis effect.

In order to achieve the above object, the present application provides a Schmitt trigger, comprising a first inverter connected in series between an input node and a connection node, and a second inverter connected in series between the connection node and the feedback node. an inverter, a third inverter connected in series between the feedback node and the output node, the Schmitt trigger further includes a third inverter coupled between the connection node and the feedback node and connected to a power supply The first adjustment branch and the third adjustment branch connected to the power supply, and the second adjustment branch and the fourth adjustment branch connected between the connection node and the feedback node and connected to the ground terminal, so The second inverter, the first adjustment branch and the third adjustment branch form a first positive feedback loop, and the second inverter, the second adjustment branch and the fourth adjustment branch form a second positive feedback loop.

Preferably, each of the first inverter, the second inverter and the third inverter includes a PMOS transistor and an NMOS transistor connected in series between the power supply and the ground terminal.

Preferably, the first adjustment branch, the second adjustment branch, the third adjustment branch, and the fourth adjustment branch all include a switch unit and an adjustment unit connected in series.

Preferably, the first adjustment branch includes a first switch unit and a first adjustment unit connected in series between the power supply and the connection node; the third adjustment branch includes a first adjustment unit connected in series with the power supply A third switch unit and a third adjustment unit between the power supply and the connection node.

Preferably, the first switch unit, the first adjustment unit, the third switch unit and the third adjustment unit are all PMOS transistors.

Preferably, the second adjustment branch includes a second switch unit and a second adjustment unit connected in series between the connection node and the ground terminal; the fourth adjustment branch includes a second adjustment unit connected in series between the connection node and the ground terminal. A fourth switch unit and a fourth adjustment unit between the node and the ground terminal.

Preferably, the second switch unit, the second adjustment unit, the fourth switch unit and the fourth adjustment unit are all NMOS transistors.

The beneficial effects of the present application are: a Schmitt trigger is provided, when the input node inputs a low level, the feedback node is at a low level, the output node is at a high level, the first positive feedback loop is turned on, and the output The inversion point of the node output from high to low is shifted to the right; when the input node inputs a high level, the feedback node is high, the output node is low, and the second positive feedback loop is turned on, making the output node output low and high. The flip point is shifted to the left, thus achieving a hysteresis effect.

【Description of drawings】

1 is a circuit structure diagram of a Schmitt trigger according to an embodiment of the present application;

FIG. 2 is an input and output characteristic diagram of a Schmitt trigger according to an embodiment of the present application.

【Detailed ways】

In order to make the purpose, technical solutions and advantages of this specification clearer, the technical solutions of this specification will be clearly and completely described below in conjunction with specific embodiments of this specification and the corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present specification, but not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of this specification. It should be noted that the embodiments in the present application and the features of the embodiments may be combined with each other in the case of no conflict.

The terms "first", "second" and "third" in the description and claims of the present application and the above drawings are used to distinguish different objects, rather than to describe a specific order. Furthermore, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally also includes For other steps or units inherent to these processes, methods, products or devices.

An embodiment of the present application provides a Schmitt trigger with configurable hysteresis window, including a first inverter, a second inverter, and a third inverter, wherein the first inverter is connected in series between the input node and the between connection nodes, the second inverter is connected in series between the connection node and the feedback node, and the third inverter is connected in series between the feedback node and the output node; wherein the first inverter An inverter, a second inverter, and a third inverter are the main signal paths for realizing the inversion function.

The Schmitt trigger further includes a first adjustment branch, a second adjustment branch, a third adjustment branch, and a fourth adjustment branch, and the first adjustment branch and the third adjustment branch are coupled at the same location. between the connection node and the feedback node, and connected to the power supply, the second adjustment branch and the fourth adjustment branch are coupled between the connection node and the feedback node, and connected to the ground terminal .

The power supply is 1.2V, 1.35V, 1.5V, 1.8V configurable according to circuit applications.

The second inverter, the first adjustment branch and the third adjustment branch form a first positive feedback loop. When the input node inputs a low level, the feedback node is at a low level, the output node is at a high level, and the first A positive feedback loop is turned on to move the first inversion point of the output node from high to low to the right; the second inverter, the second adjustment branch and the fourth adjustment branch form a second positive feedback loop, When the input node inputs a high level, the feedback node is at a high level, the output node is at a low level, and the second positive feedback loop is turned on, so that the second inversion point at which the output node outputs low to high is shifted to the left. The Schmitt trigger provided by the embodiments of the present application achieves a hysteresis effect through the first and second positive feedback loops.

In one embodiment, the first adjustment branch, the second adjustment branch, the third adjustment branch, and the fourth adjustment branch all include a switch unit and an adjustment unit connected in series; by controlling the above adjustment branches turn on or off, and then adjust the position of the flip point. Further, the number of the above-mentioned adjustment branches can be set according to different application occasions, so as to provide a combination of multiple turning points to meet different application requirements.

Preferably, the first adjustment branch includes a first switch unit and a first adjustment unit, and the first switch unit and the first adjustment unit are connected in series between the power supply and the connection node; the first switch unit and the first adjustment unit are connected in series between the power supply and the connection node; The three adjustment branches include a third switch unit and a third adjustment unit, and the third switch unit and the third adjustment unit are connected in series between the power supply and the connection node. Wherein, the first switch unit, the first adjustment unit, the third switch unit and the third adjustment unit are all PMOS transistors.

Specifically, the first switch unit is a second PMOS transistor, the first adjustment unit is a third PMOS transistor, the third switch unit is a fourth PMOS transistor, and the third adjustment unit is a fifth PMOS transistor.

The source of the second PMOS transistor is connected to the power supply, the gate of the second PMOS transistor is connected to the first configuration point, the drain of the second PMOS transistor is connected to the source of the third PMOS transistor, and the gate of the third PMOS transistor is connected to the feedback node, the drain of the third PMOS transistor is connected to the connection node.

The source of the fourth PMOS tube is connected to the power supply, the gate of the fourth PMOS tube is connected to the third configuration point, the drain of the fourth PMOS tube is connected to the source of the fifth PMOS tube, and the gate of the fifth PMOS tube is connected to The feedback node, the drain of the fifth PMOS transistor is connected to the connection node.

Preferably, the second adjustment branch includes a second switch unit and a second adjustment unit, and the second switch unit and the second adjustment unit are connected in series between the ground terminal and the connection node; the first switch unit and the second adjustment unit are connected in series between the ground terminal and the connection node; The four adjustment branches include a fourth switch unit and a fourth adjustment unit, and the fourth switch unit and the fourth adjustment unit are connected in series between the ground terminal and the connection node. Wherein, the second switch unit, the second adjustment unit, the fourth switch unit and the fourth adjustment unit are all NMOS transistors.

Specifically, the second switch unit is a second NMOS transistor, the second adjustment unit is a third NMOS transistor, the fourth switch unit is a fourth NMOS transistor, and the fourth adjustment unit is a fifth NMOS transistor.

The source of the second NMOS transistor is connected to the ground terminal, the gate of the second NMOS transistor is connected to the second configuration point, the drain of the second NMOS transistor is connected to the source of the third NMOS transistor, and the gate of the third NMOS transistor is connected to The feedback node, the drain of the third NMOS transistor is connected to the connection node.

The source of the fourth NMOS transistor is connected to the ground terminal, the gate of the fourth NMOS transistor is connected to the fourth configuration point, the drain of the fourth NMOS transistor is connected to the source of the fifth NMOS transistor, and the gate of the fifth NMOS transistor is connected to The feedback node, the drain of the fifth NMOS transistor is connected to the connection node.

In one of the embodiments, the first inverter, the second inverter and the third inverter all include PMOS transistors and NMOS transistors bridged between the power supply and the ground terminal, and the The first inverter, the second inverter and the third inverter are all powered by a power supply.

The first inverter consists of a first PMOS transistor and a first NMOS transistor, the second inverter consists of a sixth PMOS transistor and a sixth NMOS transistor, and the third inverter consists of a seventh PMOS transistor and the seventh NMOS transistor.

The source of the first PMOS tube is connected to the power supply, the gate of the first PMOS tube is connected to the input node, the drain of the first PMOS tube and the drain of the first NMOS tube are connected to the connection node, and the gate of the first NMOS tube is connected The input node, the source of the first NMOS transistor is connected to the ground terminal.

The source of the sixth PMOS tube is connected to the power supply, the gate of the sixth PMOS tube is connected to the connection node, the drain of the sixth PMOS tube and the drain of the sixth NMOS tube are connected to the feedback node, and the gate of the sixth NMOS tube is connected The connection node is connected, and the source of the sixth NMOS transistor is connected to the ground terminal.

The source of the seventh PMOS transistor is connected to the power supply, the gate of the seventh PMOS transistor is connected to the feedback node, the drain of the seventh PMOS transistor and the drain of the seventh NMOS transistor are connected to the output node, and the gate of the seventh NMOS transistor is connected to the output node The feedback node, the source of the seventh NMOS transistor is connected to the ground terminal.

In the Schmitt trigger of the present application, the PMOS tube is connected to the power supply, and the NMOS tube is connected to the ground terminal, thereby avoiding the ESD problem caused by the grounding of the PMOS tube and the connection of the NMOS tube to the power supply in the existing Schmitt trigger.

In one of the embodiments, as shown in FIG. 1 , a Schmitt trigger with configurable hysteresis window is provided, comprising a first inverter connected in series between the input node IN and the connection node A, connected in series at The second inverter between the connection node A and the feedback node B, the third inverter connected in series between the feedback node B and the output node OUT, the first inverter, the second inverter The phase device and the third inverter are the main signal paths to realize the inversion function.

The first inverter is composed of a first PMOS transistor MP1 and a first NMOS transistor MN1, the source of the first PMOS transistor MP1 is connected to the power supply VDD, the gate of the first PMOS transistor MP1 is connected to the input node IN, and the first PMOS transistor MP1 The drain of the first NMOS transistor MN1 is connected to the connection node A, the gate of the first NMOS transistor MN1 is connected to the input node IN, and the source of the first NMOS transistor MN1 is connected to the ground terminal GND.

The second inverter is composed of a sixth PMOS transistor MP6 and a sixth NMOS transistor MN6. The source of the sixth PMOS transistor MP6 is connected to the power supply VDD, the gate of the sixth PMOS transistor MP6 is connected to the node A, and the sixth PMOS transistor MP6 The drain of the sixth NMOS transistor MN6 is connected to the feedback node B, the gate of the sixth NMOS transistor MN6 is connected to the connection node A, and the source of the sixth NMOS transistor MN6 is connected to the ground terminal GND.

The third inverter is composed of a seventh PMOS transistor MP7 and a seventh NMOS transistor MN7. The source of the seventh PMOS transistor MP7 is connected to the power supply VDD, the gate of the seventh PMOS transistor MP7 is connected to the feedback node B, and the seventh PMOS transistor MP7 The drain of the seventh NMOS transistor MN7 is connected to the output node OUT, the gate of the seventh NMOS transistor MN7 is connected to the feedback node B, and the source of the seventh NMOS transistor MN7 is connected to the ground terminal GND.

The PMOS transistors of the first inverter, the second inverter and the third inverter are connected to the power supply, and the NMOS transistors are connected to the ground terminal, thereby avoiding that the PMOS transistor is connected to the ground and the NMOS transistor is connected to the power supply in the existing Schmitt trigger. ESD problems caused.

The Schmitt trigger further includes a first adjustment branch, a second adjustment branch, a third adjustment branch and a fourth adjustment branch, and the first adjustment branch and the third adjustment branch are coupled at the same location. Between the connection node A and the feedback node B, and connected to the power supply VDD, the second adjustment branch and the fourth adjustment branch are coupled between the connection node A and the feedback node B, And it is connected to the ground terminal GND.

The first adjustment branch includes a first switch unit and a first adjustment unit connected in series between the power supply VDD and the connection node A, the first switch unit is the second PMOS transistor MP2, and the first adjustment unit It is the third PMOS transistor MP3.

The source of the second NMOS transistor MP2 is connected to the power supply VDD, the gate of the second NMOS transistor MP2 is connected to the first configuration point S1, the drain of the second NMOS transistor MP2 is connected to the source of the third NMOS transistor MP3, and the third NMOS transistor MP2 is connected to the source of the third NMOS transistor MP3. The gate of the transistor MP3 is connected to the feedback node B, and the drain of the third NMOS transistor MP3 is connected to the connection node A.

The third adjustment branch includes a third switch unit and a third adjustment unit connected in series between the power supply VDD and the connection node A, the third switch unit is a fourth PMOS transistor MP4, and the third adjustment unit It is the fifth PMOS transistor MP5.

The source of the fourth PMOS transistor MP4 is connected to the power supply VDD, the gate of the fourth PMOS transistor MP4 is connected to the third configuration point S3, the drain of the fourth PMOS transistor MP4 is connected to the source of the fifth PMOS transistor MP5, and the fifth PMOS transistor MP4 is connected to the source of the fifth PMOS transistor MP5. The gate of the transistor MP5 is connected to the feedback node B, and the drain of the fifth PMOS transistor MP5 is connected to the connection node A.

The second adjustment branch includes a second switch unit and a second adjustment unit connected in series between the ground terminal GND and the connection node A; the second switch unit is a second NMOS transistor MN2 and a second adjustment unit It is the third NMOS transistor MN3.

The source of the second NMOS transistor MN2 is connected to the ground terminal GND, the gate of the second NMOS transistor MN2 is connected to the second configuration point S2, the drain of the second NMOS transistor MN2 is connected to the source of the third NMOS transistor MN3, and the third NMOS transistor MN2 is connected to the source of the third NMOS transistor MN3. The gate of the transistor MN3 is connected to the feedback node B, and the drain of the third NMOS transistor MN3 is connected to the connection node A.

The fourth adjustment branch includes a fourth switch unit and a fourth adjustment unit connected in series between the ground terminal GND and the connection node A; the fourth switch unit is a fourth NMOS transistor MN4 and a fourth adjustment unit It is the fifth NMOS transistor MN5.

The source of the fourth NMOS transistor MN4 is connected to the ground terminal GND, the gate of the fourth NMOS transistor MN4 is connected to the fourth configuration point S4, the drain of the fourth NMOS transistor MN4 is connected to the source of the fifth NMOS transistor MN5, and the fifth NMOS transistor MN4 is connected to the source of the fifth NMOS transistor MN5. The gate of the transistor MN5 is connected to the feedback node B, and the drain of the fifth NMOS transistor MN5 is connected to the connection node A.

The working process of the Schmitt trigger in the embodiment of the present application is as follows:

As shown in FIG. 2, when the input voltage VIN of the input node IN is at a low level, the voltage of the connection node A is pulled high, the voltage of the feedback node B is pulled down, the output node OUT is at a high level, the third PMOS transistor MP3 and the fifth PMOS transistor MP5 is turned on, the third NMOS tube MN3 and the fifth MN5 are turned off, the positive feedback loop composed of the sixth PMOS tube MP6, the third PMOS tube MP3, and the fifth PMOS tube MP5 is turned on, and the sixth NMOS tube MN6 and the third NMOS tube are turned on. The positive feedback loop composed of the transistor MN3 and the fifth NMOS transistor MN5 is disconnected, so that the first inversion point V+ is shifted to the right; when the input voltage VIN of the input node IN is at a high level, the voltage of the connection node A is pulled down, and the voltage of the feedback node B is pulled down. High, the output node OUT is at a low level, the third PMOS transistor MP3 and the fifth PMOS transistor MP5 are turned off, the third NMOS transistor MN3 and the fifth MN5 are turned on, the sixth PMOS transistor MP6, the third PMOS transistor MP3, and the fifth PMOS transistor The positive feedback loop composed of the tube MP5 is disconnected, and the positive feedback loop composed of the sixth NMOS tube MN6, the third NMOS tube MN3, and the fifth NMOS tube MN5 is turned on, so that the second inversion point V- is shifted to the left to achieve the hysteresis effect. .

At the same time, the low potential of the first configuration point S1 is active, controlling the opening and closing of the second PMOS transistor MP2, and further controlling the conduction or Disconnect; the third configuration point S3 is active at low potential, controls the opening and closing of the fourth PMOS transistor MP4, and then controls the conduction of the positive feedback loop composed of the sixth PMOS transistor MP6, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 or disconnected; the second configuration point S2 is active at high potential, controls the opening and closing of the second NMOS transistor MN2, and then controls the positive feedback loop composed of the sixth NMOS transistor MN6, the second NMOS transistor MN2, and the third NMOS transistor MN3 to be turned on or off; the fourth configuration point S4 is active at high potential, controls the opening and closing of the second NMOS transistor MN4, and then controls the positive feedback loop composed of the sixth NMOS transistor MN6, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 to conduct or closure. There are a total of 16 combinations of the first configuration point S1, the second configuration point S2, the third configuration point S3, and the fourth configuration point S4, so as to adjust the size of the hysteresis window and realize configurable hysteresis window voltage; When the third configuration point S3 is high and the second configuration point S2 and the fourth configuration point S4 are low, the circuit has no hysteresis effect; when the first configuration point S1 and the third configuration point S3 are low, the second configuration point S2 and the fourth configuration point S2 and the fourth configuration point are low. When configuration point S4 is high, the hysteresis window is at its maximum.

The above are only the embodiments of the present application. It should be pointed out that for those of ordinary skill in the art, improvements can be made without departing from the creative concept of the present application, but these belong to the present application. scope of protection.

Claims

A Schmitt trigger, characterized in that it comprises a first inverter connected in series between an input node and a connection node, a second inverter connected in series between the connection node and a feedback node, and a third inverter connected between the feedback node and the output node, the Schmitt trigger further includes a first inverter coupled between the connection node and the feedback node and connected to a power supply an adjustment branch and a third adjustment branch, and a second adjustment branch and a fourth adjustment branch coupled between the connection node and the feedback node and connected to the ground terminal, the second phase inversion The inverter, the first adjusting branch and the third adjusting branch form a first positive feedback loop, and the second inverter, the second adjusting branch and the fourth adjusting branch form a second positive feedback loop.
The Schmitt trigger according to claim 1, wherein the first inverter, the second inverter and the third inverter all comprise a series connection between the power supply and the ground terminal between the PMOS tube and the NMOS tube.
The Schmitt trigger according to claim 1, wherein the first adjustment branch, the second adjustment branch, the third adjustment branch, and the fourth adjustment branch all comprise a series-connected switch unit and Adjust the unit.
The Schmitt trigger according to claim 3, wherein the first adjustment branch comprises a first switch unit and a first adjustment unit connected in series between the power supply and the connection node; The third adjustment branch includes a third switch unit and a third adjustment unit connected in series between the power supply and the connection node.
The Schmitt trigger according to claim 4, wherein the first switch unit, the first adjustment unit, the third switch unit and the third adjustment unit are all PMOS transistors;

The first switch unit is a second PMOS tube, the first adjustment unit is a third PMOS tube, the third switch unit is a fourth PMOS tube, and the third adjustment unit is a fifth PMOS tube;

The source of the second PMOS transistor is connected to the power supply, the gate of the second PMOS transistor is connected to the first configuration point, the drain of the second PMOS transistor is connected to the source of the third PMOS transistor, and the second PMOS transistor is connected to the source of the third PMOS transistor. The gate of the three PMOS transistors is connected to the feedback node, and the drain of the third PMOS transistor is connected to the connection node;

The source of the fourth PMOS transistor is connected to the power supply, the gate of the fourth PMOS transistor is connected to the third configuration point, the drain of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor, and the fourth PMOS transistor is connected to the source of the fifth PMOS transistor. The gates of the five PMOS transistors are connected to the feedback node, and the drains of the fifth PMOS transistors are connected to the connection node.
The Schmitt trigger according to claim 3, wherein the second adjustment branch comprises a second switch unit and a second adjustment unit connected in series between the connection node and the ground terminal; The fourth adjustment branch includes a fourth switch unit and a fourth adjustment unit connected in series between the connection node and the ground terminal.
The Schmitt trigger according to claim 6, wherein the second switch unit, the second adjustment unit, the fourth switch unit and the fourth adjustment unit are all NMOS transistors;

The second switch unit is a second NMOS transistor, the second adjustment unit is a third NMOS transistor, the fourth switch unit is a fourth NMOS transistor, and the fourth adjustment unit is a fifth NMOS transistor;

The source of the second NMOS transistor is connected to the ground terminal, the gate of the second NMOS transistor is connected to the second configuration point, the drain of the second NMOS transistor is connected to the source of the third NMOS transistor, and the first NMOS transistor is connected to the source of the third NMOS transistor. The gate of the three NMOS transistors is connected to the feedback node, and the drain of the third NMOS transistor is connected to the connection node;

The source of the fourth NMOS transistor is connected to the ground terminal, the gate of the fourth NMOS transistor is connected to the fourth configuration point, the drain of the fourth NMOS transistor is connected to the source of the fifth NMOS transistor, and the fourth NMOS transistor is connected to the source of the fifth NMOS transistor. The gates of the five NMOS transistors are connected to the feedback node, and the drains of the fifth NMOS transistors are connected to the connection node.