CN113381739A - Schmitt trigger with adjustable positive and negative threshold voltages - Google Patents
Schmitt trigger with adjustable positive and negative threshold voltages Download PDFInfo
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- CN113381739A CN113381739A CN202110716046.3A CN202110716046A CN113381739A CN 113381739 A CN113381739 A CN 113381739A CN 202110716046 A CN202110716046 A CN 202110716046A CN 113381739 A CN113381739 A CN 113381739A
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- 229910044991 metal oxide Inorganic materials 0.000 abstract 2
- 150000004706 metal oxides Chemical class 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 abstract 2
- 230000006872 improvement Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
Abstract
The invention discloses a Schmitt trigger with adjustable positive and negative threshold voltages, which comprises a PMOS (P-channel metal oxide semiconductor) transistor group, an NMOS (N-channel metal oxide semiconductor) transistor group and a phase inverter, wherein input ports of a first PMOS transistor and a first NMOS transistor are an input signal IN and a positive threshold voltage adjusting signal ADP of a third PMOS transistor; the input port of the third NMOS transistor is a negative threshold voltage adjustment signal ADN, and the output ports of the second PMOS transistor and the second NMOS transistor are both output signals OUT. Grid input ends of the PMOS transistor group and the NMOS transistor group are connected with the input port, a source electrode and a body of the PMOS transistor group are connected with a power supply VDD, a source electrode and a body of the NMOS transistor group are connected with a ground GND, and a drain electrode of the PMOS transistor group, a drain electrode of the NMOS transistor group and an input end of the phase inverter are connected. The forward threshold voltage can be changed by adjusting the voltage of the forward threshold voltage adjusting signal ADP; the invention can change the negative threshold voltage by adjusting the voltage of the negative threshold voltage adjusting signal ADN.
Description
Technical Field
The invention relates to the technical field of Schmitt triggers, in particular to a Schmitt trigger with adjustable positive and negative threshold voltages.
Background
The Schmitt trigger is often placed at an input port of the integrated circuit to serve as a waveform shaping circuit, and can shape external signal waveforms with interference into standard square wave waveforms, so that the influence of the external interference on the inside of the integrated circuit is reduced, and the processing speed of the integrated circuit is increased. A conventional schmitt trigger is the structure shown in fig. 1.
Schmitt triggers have two stable states, but unlike conventional triggers, schmitt triggers use a potential-triggered approach, the state of which is maintained by the input signal potential. Referring to fig. 2, the schmitt trigger has different threshold voltages for two different changing directions of input signals, namely negative-going decreasing and positive-going increasing. That is, when the input voltage is higher than the forward threshold voltage, the output is high; when the input voltage is lower than the negative threshold voltage, the output is low; when the input is between the positive and negative threshold voltages, the output is unchanged, that is, the corresponding threshold voltage is different when the output is inverted from high level to low level or from low level to high level. The output level changes only when the input level changes sufficiently.
Some practitioners have proposed a schmitt trigger circuit (chinese patent application 201710190467.0), which includes an inverter circuit composed of MOS transistors, a first feedback circuit, and a first inverter; the inverter circuit is used for determining the negative threshold voltage of the trigger through the overturning voltage of the inverter circuit; the feedback circuit is used for changing the forward threshold voltage by changing the width-to-length ratio of the MOS tube; the first inverter is used for shaping the output signal of the inverter circuit. The Schmitt trigger circuit realizes the change of the threshold voltage of the trigger by changing the width-length ratio of the MOS tube, can only change the threshold voltage when the Schmitt trigger circuit is designed, and cannot dynamically adjust the positive or negative threshold voltage when the circuit works after being manufactured.
However, with the development of integrated circuits, application scenarios such as wide voltage control and the like desire that both the positive threshold voltage and the negative threshold voltage of the schmitt trigger at the input port of the integrated circuit can be adjusted. It is apparent that the existing schmitt trigger has not yet satisfied this requirement.
Disclosure of Invention
The schmitt trigger has the advantages of simple structure, low cost, simple and convenient manufacture and wide application range and can uniformly adjust the positive and negative threshold voltages.
In order to solve the technical problems, the invention adopts the following technical scheme:
a Schmitt trigger with adjustable positive and negative threshold voltages comprises a PMOS transistor group, an NMOS transistor group and a phase inverter, wherein input ports of a first PMOS transistor and a first NMOS transistor are respectively an input signal IN and a positive threshold voltage adjusting signal ADP of a third PMOS transistor; an input port of the third NMOS transistor is a negative threshold voltage adjusting signal ADN, and output ports of the second PMOS transistor and the second NMOS transistor are both output signals OUT; grid input ends of the PMOS transistor group and the N MOS transistor group are connected with the input port, a source electrode and a body of the PMOS transistor group are connected with a power supply VDD, a source electrode and a body of the NMOS transistor group are connected with a ground GND, and a drain electrode of the PMOS transistor group, a drain electrode of the NMOS transistor group and an input end of the phase inverter are connected.
As a further improvement of the invention: the PMOS transistor group comprises a first PMOS transistor, a second PMOS transistor and a third PMOS transistor, and the NMOS transistor group comprises a first NMOS transistor, a second NMOS transistor and a third NMOS transistor.
As a further improvement of the invention: IN the PMOS transistor group, the drain electrode of a first PMOS transistor is connected with the drain electrode of a first NMOS transistor, the drain electrode of a second PMOS transistor and the input end of an inverter, the source electrode and the body are connected with a power supply VDD, and the grid electrode is connected with an input signal IN. The drain electrode of the second PMOS transistor is connected with the drain electrode of the first PMOS transistor, the drain electrode of the first NMOS transistor, the drain electrode of the second NMOS transistor and the input end of the phase inverter, the source electrode of the second PMOS transistor is connected with the drain electrode of the third PMOS transistor, the body of the second PMOS transistor is connected with a power supply VDD, and the grid electrode of the second PMOS transistor is connected with the output end of the phase inverter. The drain electrode of the third PMOS transistor is connected with the source electrode of the second PMOS transistor, the source electrode and the body are connected with a power supply VDD, and the grid electrode of the third PMOS transistor is connected with a forward threshold voltage adjusting signal ADP.
As a further improvement of the invention: IN the NMOS transistor group, the drain electrode of a first NMOS transistor is connected with the drain electrode of a first PMOS transistor, the drain electrode of a second NMOS transistor and the input end of an inverter, the source electrode and the body are connected with the ground GND, and the grid electrode is connected with an input signal IN. The drain electrode of the second NMOS transistor is connected with the drain electrode of the first PMOS transistor, the drain electrode of the first NMOS transistor, the drain electrode of the second NMOS transistor and the input end of the phase inverter, the source electrode of the second NMOS transistor is connected with the drain electrode of the third NMOS transistor, the body of the second NMOS transistor is connected with the ground GND, and the grid electrode of the second NMOS transistor is connected with the output end of the phase inverter. The drain of the third NMOS transistor is connected to the source of the second NMOS transistor, the source and the body are connected to ground GND, and the gate is connected to the negative threshold voltage adjustment signal ADN.
As a further improvement of the invention: the input end of the phase inverter is connected with the drain electrode of the first PMOS transistor, the drain electrode of the first NMOS transistor and the drain electrode of the second PMOS transistor, and the output end of the phase inverter is connected with the output signal OUT.
As a further improvement of the invention: the phase inverter comprises a fourth PMOS transistor and a fourth NMOS transistor, wherein the source electrode and the body of the fourth PMOS transistor are connected with a power supply VDD, the drain electrode of the fourth PMOS transistor is connected with the drain electrode and the output end OUT of the fourth NMOS transistor, and the grid electrode of the fourth PMOS transistor is connected with the input end IN. The source and the bulk of the fourth NMOS transistor are connected to the GND, the drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor and the output terminal OUT, and the gate of the fourth NMOS transistor is connected to the input terminal IN.
Compared with the prior art, the invention has the advantages that:
the Schmitt trigger with the adjustable positive and negative threshold voltages has the advantages of simple structure, low cost and simple and convenient manufacture, and can provide the functions of adjusting the positive threshold voltage and the negative threshold voltage, namely the positive threshold voltage can be changed by adjusting the voltage of a positive threshold voltage adjusting signal ADP; the invention can change the negative threshold voltage by adjusting the voltage of the negative threshold voltage adjusting signal ADN. Therefore, the application range of the Schmitt trigger is greatly expanded, and the Schmitt trigger can meet different application requirements of various fields.
Drawings
Fig. 1 is a schematic diagram of a circuit structure of a conventional schmitt trigger.
Fig. 2 is a schematic diagram illustrating the operation of a conventional schmitt trigger.
Fig. 3 is a schematic diagram of a circuit structure of a schmitt trigger in a specific application example.
FIG. 4 is a schematic diagram of the circuit structure of an inverter in a specific application example of the present invention.
In fig. 3-4: 1 a first PMOS transistor, 2 a second PMOS transistor, 3 a third PMOS transistor, 4 a fourth PMOS transistor, 5 a first NMOS transistor, 6 a second NMOS transistor, 7 a third NMOS transistor, 8 a fourth NMOS transistor, and 9 an inverter.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
The invention will be described in further detail below with reference to the drawings and specific examples.
As shown in fig. 3, the schmitt trigger with adjustable positive and negative threshold voltages of the present invention includes a PMOS transistor set, an NMOS transistor set and an inverter 9; the input ports of the first PMOS transistor 1 and the first NMOS transistor 5 are an input signal IN and a forward threshold voltage adjusting signal ADP of the third PMOS transistor 3; the input port of the third NMOS transistor 7 is a negative threshold voltage adjustment signal ADN, and the output ports of the second PMOS transistor 2 and the second NMOS transistor 6 are both output signals OUT; grid input ends of the PMOS transistor group and the NMOS transistor group are connected with the input port, a source electrode and a body of the PMOS transistor group are connected with a power supply VDD, a source electrode and a body of the NMOS transistor group are connected with a ground GND, and a drain electrode of the PMOS transistor group, a drain electrode of the NMOS transistor group and an input end of the phase inverter 9 are connected.
In a specific application example, the PMOS transistor group includes a first PMOS transistor 1, a second PMOS transistor 2, and a third PMOS transistor 3, and the NMOS transistor group includes a first NMOS transistor 5, a second NMOS transistor 6, and a third NMOS transistor 7.
In a specific application example, the detailed structure of the invention comprises:
the drain of the first PMOS transistor 1 is connected to the drain of the first NMOS transistor 5, the drain of the second NMOS transistor 6, the drain of the second PMOS transistor 2, and the input terminal of the inverter 9, the source and bulk of which are connected to the power supply VDD, and the gate of which is connected to the input signal IN.
The drain of the second PMOS transistor 2 is connected to the drain of the first PMOS transistor 1, the drain of the first NMOS transistor 5, the drain of the second NMOS transistor 6, and the input terminal of the inverter 9, the source is connected to the drain of the third PMOS transistor 3, the bulk is connected to the power supply VDD, and the gate is connected to the output terminal of the inverter 9.
The drain of the third PMOS transistor 3 is connected to the source of the second PMOS transistor 2, the source and bulk are connected to the power supply VDD, and the gate is connected to the forward threshold voltage adjustment signal ADP.
The drain of the first NMOS transistor 5 is connected to the drain of the first PMOS transistor 1, the drain of the second PMOS transistor 2, the drain of the second NMOS transistor 6, and the input terminal of the inverter 9, the source and the bulk are connected to ground GND, and the gate is connected to the input signal IN.
The drain of the second NMOS transistor 6 is connected to the drain of the first PMOS transistor 1, the drain of the first NMOS transistor 5, the drain of the second NMOS transistor 6, and the input of the inverter 9, the source is connected to the drain of the third NMOS transistor 7, the bulk is connected to ground GND, and the gate is connected to the output of the inverter 9.
The third NMOS transistor 7 has a drain connected to the source of the second NMOS transistor 6, a source and a bulk connected to ground GND, and a gate connected to the negative threshold voltage adjustment signal ADN.
It is understood that the structure of the NMOS transistor group and the PMOS transistor group in other embodiments should also be within the scope of the present invention.
The input end of the inverter 9 is connected to the drain of the first PMOS transistor 1, the drain of the first NMOS transistor 5 and the drain of the second PMOS transistor 2, and the output end is connected to the output signal OUT.
Example 2
IN a preferred embodiment, as shown IN fig. 4, the inverter 9 circuit is further optimized, as shown IN fig. 4, the inverter 9 includes a fourth PMOS transistor 4 and a fourth NMOS transistor 8, wherein the source and the bulk of the fourth PMOS transistor 4 are connected to the power supply VDD, the drain of the fourth PMOS transistor 4 is connected to the drain of the fourth NMOS transistor 8 and the output OUT, and the gate of the fourth PMOS transistor 4 is connected to the input IN. The source and the bulk of the fourth NMOS transistor 8 are connected to ground GND, the drain of the fourth NMOS transistor 8 is connected to the drain of the fourth PMOS transistor 4 and to the output OUT, and the gate of the fourth NMOS transistor 8 is connected to the input IN.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (4)
1. A Schmitt trigger with adjustable positive and negative threshold voltages is characterized by comprising a PMOS transistor group, an NMOS transistor group and an inverter (9);
the PMOS transistor group comprises a first PMOS transistor (1), a second PMOS transistor (2) and a third PMOS transistor (3), and the NMOS transistor group comprises a first NMOS transistor (5), a second NMOS transistor (6) and a third NMOS transistor (7);
the input ports of the first PMOS transistor (1) and the first NMOS transistor (5) are both input signals IN, and the positive threshold voltage adjusting signal ADP of the third PMOS transistor (3) is obtained; the input port of the third NMOS transistor (7) is a negative threshold voltage adjusting signal ADN, and the output ports of the second PMOS transistor (2) and the second NMOS transistor (6) are both output signals OUT; grid input ends of the PMOS transistor group and the NMOS transistor group are connected with the input port, a source electrode and a body of the PMOS transistor group are connected with a power supply VDD, a source electrode and a body of the NMOS transistor group are connected with a ground GND, and a drain electrode of the PMOS transistor group, a drain electrode of the NMOS transistor group and an input end of the phase inverter (9) are connected.
2. The schmitt trigger according to claim 1, characterized in that: in the group of PMOS transistors, the gate of the PMOS transistor,
the drain electrode of the first PMOS transistor (1) is connected with the drain electrode (5) of the first NMOS transistor, the drain electrode of the second NMOS transistor (6), the drain electrode of the second PMOS transistor (2) and the input end of the inverter (9), the source electrode and the bulk of the first PMOS transistor (1) are connected with a power supply VDD, and the grid electrode is connected with an input signal IN;
the drain electrode of the second PMOS transistor (2) is connected with the drain electrode of the first PMOS transistor (1), the drain electrode of the first NMOS transistor (5), the drain electrode of the second NMOS transistor (6) and the input end of the inverter (9), the source electrode of the second PMOS transistor (2) is connected with the drain electrode of the third PMOS transistor (3), the body of the second PMOS transistor is connected with a power supply VDD, and the grid electrode of the second PMOS transistor (2) is connected with the output end of the inverter (9);
the drain electrode of the third PMOS transistor (3) is connected with the source electrode of the second PMOS transistor (2), the source electrode of the third PMOS transistor (3) is connected with a power supply VDD in a bulk mode, and the grid electrode of the third PMOS transistor (3) is connected with a forward threshold voltage adjusting signal ADP.
3. The schmitt trigger according to claim 2, characterized in that: the input end of the phase inverter (9) is connected with the drain electrode of the first PMOS transistor (1), the drain electrode of the first NMOS transistor (5) and the drain electrode of the second PMOS transistor (2), and the output end of the phase inverter (9) is connected with the output signal OUT.
4. The schmitt trigger according to claim 3, characterized in that: the inverter (9) comprises a fourth PMOS transistor (4) and a fourth NMOS transistor (8), wherein the source electrode of the fourth PMOS transistor (4) is connected with a power supply VDD through a bulk body, the drain electrode of the fourth PMOS transistor (4) is connected with the drain electrode of the fourth NMOS transistor (8) and an output end OUT, and the grid electrode of the fourth PMOS transistor (4) is connected with an input end IN; the source and the bulk of the fourth NMOS transistor (8) are connected to the ground GND, the drain of the fourth NMOS transistor (8) is connected to the drain of the fourth PMOS transistor (4) and the output end OUT, and the gate of the fourth NMOS transistor (8) is connected to the input end IN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110716046.3A CN113381739A (en) | 2021-06-25 | 2021-06-25 | Schmitt trigger with adjustable positive and negative threshold voltages |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110716046.3A CN113381739A (en) | 2021-06-25 | 2021-06-25 | Schmitt trigger with adjustable positive and negative threshold voltages |
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| CN113381739A true CN113381739A (en) | 2021-09-10 |
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| CN202110716046.3A Pending CN113381739A (en) | 2021-06-25 | 2021-06-25 | Schmitt trigger with adjustable positive and negative threshold voltages |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103368532A (en) * | 2013-07-09 | 2013-10-23 | 华东师范大学 | Hysteretic voltage digital adjustable Schmitt trigger |
| CN103607184A (en) * | 2013-10-23 | 2014-02-26 | 上海华力微电子有限公司 | CMOS Schmidt trigger circuit |
| CN104483611A (en) * | 2014-11-24 | 2015-04-01 | 华东师范大学 | Device and method thereof for testing bias temperature instability degrading of MOS (metal oxide semiconductor) device |
| CN105515596A (en) * | 2014-10-10 | 2016-04-20 | 三星电子株式会社 | Receiver circuit and signal receiving method thereof |
| CN106953618A (en) * | 2017-03-10 | 2017-07-14 | 上海华力微电子有限公司 | A kind of enhanced cmos schmitt circuit |
| CN108667440A (en) * | 2017-03-28 | 2018-10-16 | 峰岹科技（深圳）有限公司 | A kind of Schmitt trigger circuit |
| CN112468121A (en) * | 2020-12-01 | 2021-03-09 | 深圳市紫光同创电子有限公司 | Schmitt trigger |
-
2021
- 2021-06-25 CN CN202110716046.3A patent/CN113381739A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103368532A (en) * | 2013-07-09 | 2013-10-23 | 华东师范大学 | Hysteretic voltage digital adjustable Schmitt trigger |
| CN103607184A (en) * | 2013-10-23 | 2014-02-26 | 上海华力微电子有限公司 | CMOS Schmidt trigger circuit |
| CN105515596A (en) * | 2014-10-10 | 2016-04-20 | 三星电子株式会社 | Receiver circuit and signal receiving method thereof |
| CN104483611A (en) * | 2014-11-24 | 2015-04-01 | 华东师范大学 | Device and method thereof for testing bias temperature instability degrading of MOS (metal oxide semiconductor) device |
| CN106953618A (en) * | 2017-03-10 | 2017-07-14 | 上海华力微电子有限公司 | A kind of enhanced cmos schmitt circuit |
| CN108667440A (en) * | 2017-03-28 | 2018-10-16 | 峰岹科技（深圳）有限公司 | A kind of Schmitt trigger circuit |
| CN112468121A (en) * | 2020-12-01 | 2021-03-09 | 深圳市紫光同创电子有限公司 | Schmitt trigger |
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Application publication date: 20210910 |