CN112117992B - Delay circuit - Google Patents
Delay circuit Download PDFInfo
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- CN112117992B CN112117992B CN201910537471.9A CN201910537471A CN112117992B CN 112117992 B CN112117992 B CN 112117992B CN 201910537471 A CN201910537471 A CN 201910537471A CN 112117992 B CN112117992 B CN 112117992B
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- 238000000034 method Methods 0.000 claims abstract description 18
- 230000008569 process Effects 0.000 claims abstract description 17
- 239000003990 capacitor Substances 0.000 claims abstract description 7
- 230000005540 biological transmission Effects 0.000 claims description 11
- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
- 150000004706 metal oxides Chemical class 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000003111 delayed effect Effects 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 3
- 230000007423 decrease Effects 0.000 claims description 2
- 101100286980 Daucus carota INV2 gene Proteins 0.000 description 8
- 101100508840 Daucus carota INV3 gene Proteins 0.000 description 8
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 101100452680 Arabidopsis thaliana INVC gene Proteins 0.000 description 4
- 101150110971 CIN7 gene Proteins 0.000 description 4
- 101150110298 INV1 gene Proteins 0.000 description 4
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00078—Fixed delay
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00078—Fixed delay
- H03K2005/0013—Avoiding variations of delay due to power supply
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00078—Fixed delay
- H03K2005/00143—Avoiding variations of delay due to temperature
Abstract
The invention discloses a delay circuit which comprises an inverting receiving circuit, a reference point generating circuit, a first buffer gate and a first inverter. The inverting receiving circuit comprises a first transistor and a first switch circuit. The reference point generating circuit comprises a compensation resistor, a capacitor component and a first current source. When the input signal is at the first potential, the voltage of the output node starts to drop from the voltage reference point. The compensation resistor is used for correcting the voltage reference point when at least one of the process, the first reference voltage and the temperature changes.
Description
Technical Field
The present invention relates to a delay circuit, and more particularly, to a delay circuit having an accurate delay time without being affected by a process, a supply voltage, and a temperature.
Background
It is well known that the operating characteristics of transistors vary with temperature, with slower operating speeds at high temperatures and faster operating speeds at low temperatures. Therefore, the delay time of the delay circuit is changed with the temperature change, which is not a good phenomenon.
Likewise, the operating speed of a transistor also varies with the process or supply voltage. In other words, the rise or fall time, threshold voltage and current of the voltage at the internal node of the transistor will vary with process, supply voltage and temperature (process voltage temperature, PVT) variations, and thus the output signal will vary under different PVT conditions.
Since the performance varies greatly under different PVT conditions, it is necessary to ensure performance within a certain range at the initial stage of IC design in order to alleviate the difficulty in front-end circuit design. For example, variations in doping concentration may cause variations in performance, which increase as processing techniques expand to smaller geometries. It is known to use so-called process corners (process corners) to classify process variations. One naming convention for process corners is to use a two-letter designator, wherein the first letter represents an N-channel MOSFET (NMOS) corner and the second letter represents a P-channel MOSFET (PMOS) corner. In this naming convention, there are three corners, namely a typical (T) corner, a fast (F) corner, and a slow (S) corner. The fast and slow corners exhibit higher and lower carrier mobility than normal, respectively.
In view of the above drawbacks of the delay circuit, the present invention provides a delay circuit with a fixed delay time, which is not affected by the process, the supply voltage and the temperature, and which can improve the above drawbacks.
Disclosure of Invention
The invention aims to solve the technical problem of providing a delay circuit aiming at the defects of the prior art, and the design of a compensation resistor ensures that an output signal is not influenced by a process, a supply voltage and a temperature and has fixed delay time relative to an input signal.
In order to solve the above-mentioned problems, one of the solutions adopted by the present invention is to provide a delay circuit, which includes an inverting receiving circuit, a reference point generating circuit, a first buffer gate and a first inverter. The inverting receiving circuit comprises a first transistor and a first switch circuit. The first end of the first transistor is connected with the first node, the second end of the first transistor receives an input signal, and the third end of the first transistor is connected with the output node. The first switch circuit has a first end connected to the output node, a second end receiving the input signal, and a third end connected to the second reference voltage. The reference point generating circuit comprises a compensation resistor, a capacitor component and a first current source. The compensation resistor is connected between the first node and a first reference voltage. The capacitor element is connected between the first node and the second end of the first transistor. The first current source is connected between the first node and the second reference voltage. The input end of the first buffer gate is connected to the output node, the input end of the first inverter is connected to the output end of the first buffer gate, and the output end of the first inverter is used for outputting an output signal delayed by a delay time. When the input signal is at the first potential, the first transistor is turned off, the first switch circuit is turned on, and the voltage of the output node is reduced from the voltage reference point. The compensation resistor is used for correcting the voltage reference point when at least one of the process, the first reference voltage and the temperature changes.
The delay circuit provided by the invention has the beneficial effects that the voltage reference point following PVT variation is generated through the design of the compensation resistor, so that the output signal is not influenced by the process, the supply voltage and the temperature, and has fixed delay time relative to the input signal.
For a further understanding of the nature and the technical aspects of the present invention, reference should be made to the following detailed description of the invention and to the accompanying drawings, which are provided for purposes of reference only and are not intended to limit the invention.
Drawings
Fig. 1 is a circuit configuration diagram of a delay circuit according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of another circuit configuration of a delay circuit according to an embodiment of the present invention.
Fig. 3 is a voltage waveform diagram of an input signal, an output node voltage, and an output signal according to an embodiment of the present invention.
Detailed Description
The following specific examples are given to illustrate the embodiments of the present invention disclosed herein with respect to "delay circuits", and those skilled in the art will be able to understand the advantages and effects of the present invention from the disclosure herein. The invention is capable of other and different embodiments and its several details are capable of modification and variation in various respects, all from the point of view and application, all without departing from the spirit of the present invention. The drawings of the present invention are merely schematic illustrations, and are not intended to be drawn to actual dimensions. The following embodiments will further illustrate the related art content of the present invention in detail, but the disclosure is not intended to limit the scope of the present invention.
It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are used primarily to distinguish one element from another element or signal from another signal. In addition, the term "or" as used herein shall include any one or combination of more of the associated listed items as the case may be.
Referring to fig. 1, a block diagram of a delay circuit according to an embodiment of the invention is shown. As shown in fig. 1, an embodiment of the present invention provides a delay circuit 10, which includes an inverting receiving circuit INVC, a reference point generating circuit RGC, a first buffer gate BG and a first inverter INV1.
The inverted receiving circuit INVC includes a first transistor M1 and a first switch circuit SW. The first transistor M1 has a first terminal connected to the first node N1, a second terminal receiving the input signal vin, and a third terminal connected to the output node No. In some embodiments, the first transistor M1 may be a P-type metal oxide semiconductor (Metal Oxide Semiconductor, MOS) field effect transistor, and the first, second and third terminals thereof may be a source, a gate and a drain, respectively.
In addition, the first switch circuit SW has a first end connected to the output node No, a second end receiving the input signal vin, and a third end connected to the second reference voltage Vss. In this embodiment, the first switch circuit SW may include a N-type metal oxide semiconductor (Metal Oxide Semiconductor, MOS) field effect transistor M1', and the first, second and third terminals of the first switch circuit SW may be the drain, gate and source of the NMOS transistor M1', respectively.
Further, the reference point generating circuit RGC includes a compensation resistor Rc, a capacitive component C1, and a first current source S1.
The compensation resistor Rc is connected between the first node N1 and the first reference voltage VDD. The capacitor element C1 is connected between the first node N1 and the second terminal of the first transistor M1. The first current source S1 is connected between the first node N1 and the second reference voltage Vss. The first current source S1 may be a third transistor M3, a first terminal thereof is connected to the first node N1, a third terminal thereof is connected to the second reference voltage Vss, and the first current source S1 may be equivalently a first current source capable of controlling a current level.
Referring further to fig. 3, a voltage waveform diagram of an input signal, an output node voltage, and an output signal according to an embodiment of the present invention is shown. As shown, when the input signal vin is at a first potential, such as a high potential, the first transistor M1 is turned off, the NMOS transistor M1' of the first switch circuit SW is turned on, and the voltage aVx of the output node No decreases from the voltage reference point avvref.
Further, when the input signal vin is at a second potential, for example, a low potential, the first transistor M1 is turned on, the NMOS transistor M1' of the first switch circuit SW is turned off, so that the voltage aVx of the output node No returns to the voltage reference point avvref and charges the capacitor element C1.
In addition, the input end of the first buffer gate BG is connected to the output node No, the input end of the first inverter INV1 is connected to the output end of the first buffer gate BG, and the output end thereof is used for outputting the output signal vout delayed by a delay time. Wherein the first buffer gate BG is connected to the output node No to generate a pre-output signal in response to a change in the voltage aVx of the output node No. For example, when the voltage aVx of the output node No is higher than the threshold voltage of the first buffer gate BG, the pre-output signal is enabled (high logic level), and the first inverter INV1 is further configured to output the output signal vout in phase with the input signal vin because the voltage aVx of the output node No changes in phase with the input signal vin.
Here, the level of the voltage reference point avvref depends on the voltage level of the first reference voltage VDD and the resistance value of the compensation resistor Rc. The resistance of the compensation resistor Rc also depends on the process conditions used in the delay circuit 10 and the current operating temperature. Therefore, when at least one of the process, the first reference voltage and the temperature is changed, the compensation resistor Rc can be used to correct the voltage reference point avvref, which can be changed following the PVT change, so that the delay circuit 10 can generate a delay time independent of the PVT.
In addition, the third transistor M3 is provided to offset PVT effects with the compensation resistor Rc to generate the voltage reference point avvref, thereby further precisely controlling the delay time of the output signal vout.
In addition to the above embodiments, please further refer to fig. 2, fig. 2 is another circuit configuration diagram of a delay circuit according to an embodiment of the present invention.
As shown in fig. 2, the delay circuit 10 further includes a second current source S2 and a second transistor M2. The second current source S2 is connected between the first reference voltage VDD and the second reference voltage Vss, the second transistor M2 is further connected between the second current source S2 and the second reference voltage Vss, the first terminal of the second transistor M2 is connected to the second current source S2, the second terminal thereof is connected to the first terminal thereof, and the third terminal thereof is connected to the second reference voltage Vss. In addition, in the present embodiment, the first current source S1 includes a third transistor M3, a first terminal thereof is connected to the first node N1, a second terminal thereof is connected to the second terminal of the second transistor M2, and a third terminal thereof is connected to the second reference voltage Vss. Here, the second transistor M2 and the third transistor M3 form the first current mirror circuit MR1, so that the current I1 generated at the second transistor M2 will be mirrored to the third transistor M3 to generate the same current I2. Preferably, the second transistor M2 and the third transistor M3 may be N-type MOS transistors.
As also shown in fig. 2, the delay circuit 10 further includes a second inverter INV2 and a third inverter INV3. An input end of the second inverter INV2 receives the input signal dhin, an input end of the third inverter INV3 is connected with the second inverter INV2, and an output end of the third inverter INV3 is connected with a second end of the first transistor M1.
Here, the second inverter INV2 and the third inverter INV3 may be used as buffer gates, to enhance the input signal vin, or to waveform-shape the input signal vin, and the inverted signal of the input signal vin may be used to control the first switch circuit SW, so that the output signal of the second inverter INV2 is supplied to the first switch circuit SW through the output of the second inverter INV2, and then the output signal of the second inverter INV2 is recovered to the original signal through the third inverter INV3, and at the same time, the shaping and the balanced signal delay effects may be generated on the original input signal vin.
Further, as shown in fig. 2, the delay circuit 10 further includes a fourth transistor M4. The fourth transistor M4 has a first end connected to the first reference voltage VDD, and a second end connected to the second end of the first transistor M1 and the output end of the third inverter INV3.
In addition, the first switching circuit includes a transmission gate TG and a fifth transistor M5. The first end of the transmission gate TG is connected to the output node No, the second end thereof is connected to the third end of the fourth transistor M4 and the second reference voltage Vss, the first control end thereof is connected to the output end of the third inverter INV3, and the second control end thereof is connected to the output end of the second inverter INV 2. The first end of the fifth transistor M5 is connected to the second end of the transmission gate TG and the third end of the fourth transistor M4, the second end thereof is connected to the second end of the second transistor M2, and the third end thereof is connected to the second reference voltage Vss. Preferably, the fifth transistor M5 may be an N-type MOS transistor.
Here, the first control terminal of the transmission gate TG receives the input signal vin equivalently, and the second control terminal receives the inverted signal of the input signal vin equivalently, so that when the input signal vin is at a first potential, for example, a high potential, a conducting path is formed between the output node No and the fifth transistor M5, and when the input signal vin is at a second potential, for example, a low potential, the transmission gate TG is turned off.
Since the fourth transistor M4 is a P-type MOS transistor, the fourth transistor M4 is turned off when the input signal vin is at a high potential, and the fourth transistor M4 is turned on when the input signal vin is at a low potential.
The second transistor M2 and the fifth transistor M5 form a second current mirror circuit MR2. Referring further to fig. 3, a voltage waveform diagram of an input signal, an output node voltage, and an output signal according to an embodiment of the present invention is shown. As shown in the figure, when the input signal vin is at a first potential, such as a high potential, the first transistor M1 is turned off, the transmission gate TG of the first switch circuit SW is turned on, and a conduction path is formed between the output node No and the fifth transistor M5. At this time, the voltage aVx' of the output node No starts to fall from the voltage reference point avvref. As can be seen, by setting the second current source S2 and controlling the second current source S2 to mirror at the fifth transistor M5 to generate the current I3, the voltage aVx 'of the output node No can be more linearly changed to precisely control the level of the voltage aVx' relative to the threshold voltage of the first buffer gate BG, thereby further precisely controlling the delay time of the output signal dvut.
Advantageous effects of the embodiment
The delay circuit provided by the invention has the beneficial effects that the voltage reference point following PVT variation is generated through the design of the compensation resistor, so that the output signal is not influenced by the process, the supply voltage and the temperature, and has fixed delay time relative to the input signal.
In addition, by setting the second current source and generating the mirror current, the voltage change of the output node can be more linear, so that the level of the voltage relative to the critical voltage of the first buffer gate can be precisely controlled, and the delay time of the output signal can be further precisely controlled.
The foregoing disclosure is only illustrative of the preferred embodiments of the present invention and is not to be construed as limiting the scope of the appended claims, and all equivalent technical changes that come within the meaning and range of equivalency of the specification and drawings are therefore intended to be embraced therein.
[ symbolic description ]
Delay circuit: 10
An inverting receiving circuit: INVC (INVC)
Reference point generation circuit: RGC (RGC)
A first buffer gate: BG (BG)
A first inverter: INV1
A first transistor: m1
A first switching circuit: SW (switch)
The first node: n1
Input signal: dVin
And (3) an output node: no. No
First reference voltage: VDD (VDD)
Second reference voltage: vss (Vss)
Compensation resistance: rc (Rc)
A capacitor assembly: C1C 1
A first current source: s1
NMOS transistor: m1'
Voltage: aVx, aVx'
Voltage reference point: aVref (active oxygen potential)
A second current source: s2
A second transistor: m2
A third transistor: m3
Current flow: i1
Current flow: i2
A second inverter: INV2
Third inverter: INV3
A fourth transistor: m4
Transmission gate: TG (TG)
A fifth transistor: m5
Current flow: i3
And (3) outputting a signal: dVout
A first current mirror circuit: MR1
A second current mirror circuit: MR2.
Claims (10)
1. A delay circuit, comprising:
an inverting receiver circuit comprising:
a first transistor, the first end connects a first node, the second end receives an input signal, the third end connects an output node; and
The first switch circuit is connected with the output node at a first end, receives the input signal at a second end and is connected with a second reference voltage at a third end;
a reference point generation circuit comprising:
the compensation resistor is connected between the first node and a first reference voltage;
a capacitor element connected between the first node and the second end of the first transistor; and
A first current source connected between the first node and a second reference voltage;
the input end of the first buffer gate is connected with the output node; and
a first inverter, the input end of which is connected with the output end of the first buffer gate, the output end is used for outputting an output signal delayed by a delay time,
wherein when the input signal is at a first potential, the first transistor is turned off, the first switch circuit is turned on, the voltage of the output node decreases from a voltage reference point,
wherein the compensation resistor is used to correct the voltage reference point when at least one of the process, the first reference voltage and the temperature changes.
2. The delay circuit of claim 1, wherein the first transistor is a P-type mosfet.
3. The delay circuit of claim 1, wherein the first potential is a high potential.
4. The delay circuit of claim 1, wherein the first switching circuit comprises an N-type mosfet.
5. The delay circuit of claim 1, further comprising:
a second current source connected between the first reference voltage and the second reference voltage; a second transistor, the first end is connected to the second current source, the second end is connected to the first end, the third end is connected to the second reference voltage;
the first current source comprises a third transistor, a first end of the third transistor is connected with the first node, a second end of the third transistor is connected with a second end of the second transistor, a third end of the third transistor is connected with the second reference voltage, and the second transistor and the third transistor form a first current mirror circuit.
6. The delay circuit of claim 5, wherein the second transistor and the third transistor are N-type metal oxide semiconductor field effect transistors.
7. The delay circuit of claim 5, further comprising:
a second inverter, the input end receives the input signal; and
and the input end of the third inverter is connected with the second inverter, and the output end of the third inverter is connected with the second end of the first transistor.
8. The delay circuit of claim 7, further comprising:
a fourth transistor having a first end connected to the first reference voltage and a second end connected to the second end of the first transistor and the output end of the third inverter,
wherein the first switching circuit comprises:
the first end of the transmission gate is connected with the output node, the second end of the transmission gate is connected with the third end of the fourth transistor and the second reference voltage, the first control end of the transmission gate is connected with the output end of the third inverter, and the second control end of the transmission gate is connected with the output end of the second inverter.
9. The delay circuit of claim 8, wherein the fourth transistor is a P-type mosfet.
10. The delay circuit of claim 8, wherein the first switching circuit further comprises a fifth transistor having a first terminal coupled to the second terminal of the pass gate and a third terminal coupled to the second terminal of the second transistor, the third terminal coupled to the second reference voltage,
wherein the second transistor and the fifth transistor form a second current mirror circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910537471.9A CN112117992B (en) | 2019-06-20 | 2019-06-20 | Delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910537471.9A CN112117992B (en) | 2019-06-20 | 2019-06-20 | Delay circuit |
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| Publication Number | Publication Date |
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| CN112117992A CN112117992A (en) | 2020-12-22 |
| CN112117992B true CN112117992B (en) | 2024-01-26 |
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| CN201910537471.9A Active CN112117992B (en) | 2019-06-20 | 2019-06-20 | Delay circuit |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7154324B1 (en) * | 2004-09-07 | 2006-12-26 | Altera Corporation | Integrated circuit delay chains |
| CN103427804A (en) * | 2012-05-17 | 2013-12-04 | 晶豪科技股份有限公司 | Delay circuit and delay level of delay circuit |
| CN107786185A (en) * | 2016-08-26 | 2018-03-09 | 瑞昱半导体股份有限公司 | Phase interpolator |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10425064B2 (en) * | 2016-12-08 | 2019-09-24 | Micron Technology, Inc. | Apparatus and method for a PVT independent RC delay |
| US10320374B2 (en) * | 2017-04-17 | 2019-06-11 | Ciena Corporation | Fine resolution high speed linear delay element |
-
2019
- 2019-06-20 CN CN201910537471.9A patent/CN112117992B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7154324B1 (en) * | 2004-09-07 | 2006-12-26 | Altera Corporation | Integrated circuit delay chains |
| CN103427804A (en) * | 2012-05-17 | 2013-12-04 | 晶豪科技股份有限公司 | Delay circuit and delay level of delay circuit |
| CN107786185A (en) * | 2016-08-26 | 2018-03-09 | 瑞昱半导体股份有限公司 | Phase interpolator |
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