CN112117992A

CN112117992A - Delay circuit

Info

Publication number: CN112117992A
Application number: CN201910537471.9A
Authority: CN
Inventors: 陈建文
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2019-06-20
Filing date: 2019-06-20
Publication date: 2020-12-22
Anticipated expiration: 2039-06-20
Also published as: CN112117992B

Abstract

The invention discloses a delay circuit, which comprises an inverting receiving circuit, a reference point generating circuit, a first buffer gate and a first inverter. The inverting receiving circuit comprises a first transistor and a first switch circuit. The reference point generating circuit comprises a compensation resistor, a capacitor component and a first current source. When the input signal is at the first potential, the voltage of the output node drops from the voltage reference point. The compensation resistor is used for correcting the voltage reference point when at least one of the process, the first reference voltage and the temperature changes.

Description

Delay circuit

Technical Field

The present invention relates to a delay circuit, and more particularly, to a delay circuit having an accurate delay time without being affected by a process, a supply voltage, and a temperature.

Background

It is well known that the operating characteristics of a transistor change with temperature, and that it operates at a slower speed at high temperatures and at a faster speed at low temperatures. Therefore, the delay time of the delay circuit varies with the temperature, which is not a good phenomenon.

Similarly, the operating speed of a transistor also varies with process or supply voltage. In other words, the rise or fall time of the voltage at the internal node of the transistor, the threshold voltage and the current vary with the process, the supply voltage and the temperature (PVT), and therefore, the output signals vary under different PVT conditions.

Since the performance under different PVT conditions varies greatly, it is necessary to ensure performance within a certain range at the beginning of IC design in order to alleviate the difficulty in designing the front-end circuit. For example, variations in doping concentration may cause performance variations that increase as processing techniques expand to smaller geometries. It is known to use so-called process corners (process corner) to classify process variations. One naming convention for process corners is to use a two letter designator, where the first letter represents an N-channel MOSFET (NMOS) corner and the second letter represents a P-channel MOSFET (PMOS) corner. In this naming convention, there are three corners, namely a typical (T) corner, a fast (F) corner and a slow (S) corner. The fast and slow turns exhibit higher and lower carrier mobility than normal, respectively.

In view of the above disadvantages of the delay circuit, the present invention provides a delay circuit with a fixed delay time without being affected by the process, the supply voltage and the temperature, which can improve the above disadvantages.

Disclosure of Invention

The present invention is directed to a delay circuit, which is designed to overcome the shortcomings of the prior art, and which has a fixed delay time with respect to an input signal without being affected by a process, a supply voltage, and a temperature through a design of a compensation resistor.

In order to solve the above technical problem, one of the technical solutions of the present invention is to provide a delay circuit, which includes an inverting receiving circuit, a reference point generating circuit, a first buffer gate and a first inverter. The inverting receiving circuit comprises a first transistor and a first switch circuit. The first transistor has a first terminal connected to the first node, a second terminal receiving an input signal, and a third terminal connected to the output node. The first switch circuit has a first terminal connected to the output node, a second terminal receiving the input signal, and a third terminal connected to a second reference voltage. The reference point generating circuit comprises a compensation resistor, a capacitor component and a first current source. The compensation resistor is connected between the first node and a first reference voltage. The capacitor component is connected between the first node and the second end of the first transistor. The first current source is connected between the first node and the second reference voltage. The input end of the first buffer gate is connected to the output node, the input end of the first inverter is connected to the output end of the first buffer gate, and the output end of the first inverter is used for outputting the output signal with delayed delay time. When the input signal is at the first potential, the first transistor is turned off, the first switch circuit is turned on, and the voltage of the output node drops from the voltage reference point. When at least one of the process, the first reference voltage and the temperature changes, the compensation resistor is used for correcting the voltage reference point.

One of the advantages of the present invention is that the delay circuit provided by the present invention generates the voltage reference point following the PVT variation through the design of the compensation resistor, so that the output signal is not affected by the process, the supply voltage and the temperature, and has a fixed delay time relative to the input signal.

For a better understanding of the features and technical content of the present invention, reference should be made to the following detailed description and accompanying drawings, which are provided for purposes of illustration and description only and are not intended to limit the invention.

Drawings

Fig. 1 is a circuit architecture diagram of a delay circuit according to an embodiment of the present invention.

Fig. 2 is another circuit architecture diagram of the delay circuit according to the embodiment of the invention.

FIG. 3 is a voltage waveform diagram of an input signal, an output node voltage and an output signal according to an embodiment of the invention.

Detailed Description

The following is a description of the embodiments of the "delay circuit" disclosed in the present application with reference to specific embodiments, and those skilled in the art will understand the advantages and effects of the present invention from the disclosure of the present application. The invention is capable of other and different embodiments and its several details are capable of modifications and various changes in detail, all without departing from the spirit and scope of the present invention. The drawings of the present invention are for illustrative purposes only and are not intended to be drawn to scale. The following embodiments will further explain the related art of the present invention in detail, but the disclosure is not intended to limit the scope of the present invention.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are used primarily to distinguish one element from another element or from one signal to another signal. In addition, the term "or" as used herein should be taken to include any one or combination of more of the associated listed items as the case may be.

Fig. 1 is a block diagram of a delay circuit according to an embodiment of the invention. As shown in fig. 1, the embodiment of the invention provides a delay circuit 10, which includes an inverting receiving circuit INVC, a reference point generating circuit RGC, a first buffer gate BG and a first inverter INV 1.

The inverting receiving circuit INVC includes a first transistor M1 and a first switch circuit SW. The first transistor M1 has a first terminal connected to the first node N1, a second terminal receiving the input signal dVin, and a third terminal connected to the output node No. In some embodiments, the first transistor M1 may be a Metal Oxide Semiconductor (MOS) field effect transistor, and the first terminal, the second terminal, and the third terminal may be a source, a gate, and a drain, respectively.

In addition, the first switch circuit SW has a first terminal connected to the output node No, a second terminal receiving the input signal dVin, and a third terminal connected to the second reference voltage Vss. In this embodiment, the first switch circuit SW may include a Metal Oxide Semiconductor (MOS) field effect transistor M1 ', and the first, second, and third terminals of the first switch circuit SW may be the drain, gate, and source of the NMOS transistor M1', respectively.

Further, the reference point generating circuit RGC includes a compensation resistor Rc, a capacitor element C1 and a first current source S1.

The compensation resistor Rc is connected between the first node N1 and the first reference voltage VDD. The capacitor C1 is connected between the first node N1 and the second terminal of the first transistor M1. The first current source S1 is connected between the first node N1 and the second reference voltage Vss. The first current source S1 can be a third transistor M3, a first terminal of which is connected to the first node N1, and a third terminal of which is connected to the second reference voltage Vss, and can be equivalent to the first current source S1 capable of controlling the current.

Reference may be further made to FIG. 3, which is a voltage waveform diagram of the input signal, the output node voltage and the output signal according to an embodiment of the invention. As shown, when the input signal dVin is at the first potential, for example, the high potential, the first transistor M1 is turned off, the NMOS transistor M1' of the first switch circuit SW is turned on, and the voltage aVx at the output node No drops from the voltage reference point aVref.

Further, when the input signal dVin is at a second potential, for example, a low potential, the first transistor M1 is turned on, the NMOS transistor M1' of the first switch circuit SW is turned off, so that the voltage aVx at the output node No returns to the voltage reference point aVref, and the capacitor element C1 is charged.

In addition, an input end of the first buffer gate BG is connected to the output node No, an input end of the first inverter INV1 is connected to an output end of the first buffer gate BG, and an output end thereof is used for outputting the output signal dvut delayed by a delay time. Wherein the first buffer gate BG is connected to the output node No to generate the pre-output signal in response to the change of the voltage aVx of the output node No. For example, when the voltage aVx at the output node No is higher than the threshold voltage of the first buffer gate BG, the pre-output signal is enabled (logic level high), and since the voltage aVx at the output node No is inverse to the input signal dVin, the first inverter INV1 is further configured to output the output signal dVout in phase with the input signal dVin.

Here, it should be noted that the level of the voltage reference point aVref depends on the voltage magnitude of the first reference voltage VDD and the resistance value of the compensation resistor Rc. The resistance value of the compensation resistor Rc also depends on the process conditions adopted by the delay circuit 10 and the current operating temperature. Therefore, when at least one of the process, the first reference voltage and the temperature changes, the compensation resistor Rc can be used to correct the voltage reference point aVref, which can change along with the PVT change, so that the delay circuit 10 can generate a delay time independent of the PVT.

In addition, the third transistor M3 is provided to counteract the PVT effect with the compensation resistor Rc to generate the voltage reference point aVref, thereby further precisely controlling the delay time of the output signal dVout.

In addition to the above embodiments, please further refer to fig. 2, fig. 2 is another circuit architecture diagram of the delay circuit according to the embodiment of the invention.

As shown in fig. 2, the delay circuit 10 further includes a second current source S2 and a second transistor M2. The second current source S2 is connected between the first reference voltage VDD and the second reference voltage Vss, the second transistor M2 is further connected between the second current source S2 and the second reference voltage Vss, the first terminal of the second transistor M2 is connected to the second current source S2, the second terminal thereof is connected to the first terminal thereof, and the third terminal thereof is connected to the second reference voltage Vss. In addition, in the present embodiment, the first current source S1 includes a third transistor M3, a first terminal of which is connected to the first node N1, a second terminal of which is connected to the second terminal of the second transistor M2, and a third terminal of which is connected to the second reference voltage Vss. Here, the second transistor M2 and the third transistor M3 form the first current mirror circuit MR1, so the current I1 generated at the second transistor M2 will mirror to the third transistor M3 to generate the same current I2. Preferably, the second transistor M2 and the third transistor M3 may be N-type MOS transistors.

As also shown in fig. 2, the delay circuit 10 further includes a second inverter INV2 and a third inverter INV 3. The input end of the second inverter INV2 receives the input signal dVin, the input end of the third inverter INV3 is connected to the second inverter INV2, and the output end of the third inverter INV3 is connected to the second end of the first transistor M1.

Here, the second inverter INV2 and the third inverter INV3 may be used as a buffer gate to enhance the input signal dVin or perform waveform shaping on the input signal dVin, and an inverted signal of the input signal dVin may be used to control the first switch circuit SW, so that the output signal of the second inverter INV2 may be supplied to the first switch circuit SW through the second inverter INV2, and the original signal may be restored through the third inverter INV3, and the shaping and signal delay effects may be generated on the original input signal dVin.

Further, as shown in fig. 2, the delay circuit 10 further includes a fourth transistor M4. A first terminal of the fourth transistor M4 is connected to the first reference voltage VDD, and a second terminal thereof is connected to the second terminal of the first transistor M1 and the output terminal of the third inverter INV 3.

In addition, the first switch circuit includes a transmission gate TG and a fifth transistor M5. The transmission gate TG has a first terminal connected to the output node No, a second terminal connected to the third terminal of the fourth transistor M4 and the second reference voltage Vss, a first control terminal connected to the output terminal of the third inverter INV3, and a second control terminal connected to the output terminal of the second inverter INV 2. The first terminal of the fifth transistor M5 is connected to the second terminal of the transmission gate TG and the third terminal of the fourth transistor M4, the second terminal thereof is connected to the second terminal of the second transistor M2, and the third terminal thereof is connected to the second reference voltage Vss. Preferably, the fifth transistor M5 may be an N-type MOS transistor.

Here, the first control terminal of the transmission gate TG equivalently receives the input signal dVin, and the second control terminal equivalently receives the inverted signal of the input signal dVin, so that when the input signal dVin is at a first potential, for example, a high potential, a conducting path is formed between the output node No and the fifth transistor M5, and when the input signal dVin is at a second potential, for example, a low potential, the transmission gate TG is turned off.

Since the fourth transistor M4 is a P-type MOS transistor, the fourth transistor M4 is turned off when the input signal dVin is high, and the fourth transistor M4 is turned on when the input signal dVin is low.

The second transistor M2 and the fifth transistor M5 form a second current mirror circuit MR 2. Reference may be further made to FIG. 3, which is a voltage waveform diagram of the input signal, the output node voltage and the output signal according to an embodiment of the invention. As shown, when the input signal dVin is at a first voltage level, such as a high voltage level, the first transistor M1 is turned off, the transmission gate TG of the first switch circuit SW is turned on, and a conduction path is formed between the output node No and the fifth transistor M5. At this time, the voltage aVx' of the output node No falls from the voltage reference point aVref. As can be seen, by providing the second current source S2 and controlling the current I3 mirrored at the fifth transistor M5, the voltage aVx 'at the output node No can be changed more linearly, so as to precisely control the level of the voltage aVx' relative to the threshold voltage of the first buffer gate BG, thereby further precisely controlling the delay time of the output signal dvut.

[ advantageous effects of the embodiments ]

In addition, by arranging the second current source and generating the mirror current, the voltage change of the output node can be more linear so as to accurately control the level of the voltage relative to the critical voltage of the first buffer gate, thereby further accurately controlling the delay time of the output signal.

The disclosure is only a preferred embodiment of the invention and should not be taken as limiting the scope of the invention, which is defined by the appended claims.

[ notation ] to show

A delay circuit: 10

An inverting receiving circuit: INVC

Reference point generating circuit: RGC

A first buffer gate: BG

A first inverter: INV1

A first transistor: m1

A first switching circuit: SW

A first node: n1

Inputting a signal: dVin

An output node: no

First reference voltage: VDD

Second reference voltage: vss

Compensation resistance: rc (Rc)

A capacitor assembly: c1

A first current source: s1

An NMOS transistor: m1'

Voltage: aVx, aVx'

Voltage reference point: aVref

A second current source: s2

A second transistor: m2

A third transistor: m3

Current: i1

Current: i2

A second inverter: INV2

The third inverter: INV3

A fourth transistor: m4

A transmission gate: TG (gamma-

A fifth transistor: m5

Current: i3

Outputting a signal: dVout

The first current mirror circuit: MR1

The second current mirror circuit: MR 2.

Claims

1. A delay circuit, comprising:

an inverting receiving circuit, comprising:

the first end of the first transistor is connected with a first node, the second end of the first transistor receives an input signal, and the third end of the first transistor is connected with an output node; and

a first switch circuit, the first end is connected with the output node, the second end receives the input signal, and the third end is connected with a second reference voltage;

a reference point generating circuit comprising:

a compensation resistor connected between the first node and a first reference voltage;

a capacitor element connected between the first node and the second end of the first transistor; and

a first current source connected between the first node and a second reference voltage;

a first buffer gate, the input end of which is connected to the output node; and

a first inverter, the input terminal of which is connected to the output terminal of the first buffer gate, the output terminal of which is used to output an output signal delayed by a delay time,

wherein when the input signal is at a first potential, the first transistor is turned off, the first switch circuit is turned on, the voltage of the output node drops from a voltage reference point,

wherein the compensation resistor is used for correcting the voltage reference point when at least one of the process, the first reference voltage and the temperature changes.

2. The delay circuit of claim 1, wherein the first transistor is a P-type metal oxide semiconductor field effect transistor.

3. The delay circuit of claim 1, wherein the first potential is a high potential.

4. The delay circuit of claim 1, wherein the first switch circuit comprises an N-type mosfet.

5. The delay circuit of claim 1, further comprising:

a second current source connected between the first reference voltage and the second reference voltage; a second transistor, the first end is connected to the second current source, the second end is connected to the first end, and the third end is connected to the second reference voltage;

the first current source includes a third transistor, the first end of which is connected to the first node, the second end of which is connected to the second end of the second transistor, and the third end of which is connected to the second reference voltage, wherein the second transistor and the third transistor form a first current mirror circuit.

6. The delay circuit of claim 5, wherein the second and third transistors are N-type metal oxide semiconductor field effect transistors.

7. The delay circuit of claim 5, further comprising:

the input end of the second inverter receives the input signal; and

and the input end of the third inverter is connected with the second inverter, and the output end of the third inverter is connected with the second end of the first transistor.

8. The delay circuit of claim 7, further comprising:

a fourth transistor having a first terminal connected to the first reference voltage and a second terminal connected to the second terminal of the first transistor and the output terminal of the third inverter,

wherein the first switching circuit comprises:

and the first end of the transmission gate is connected with the output node, the second end of the transmission gate is connected with the third end of the fourth transistor and the second reference voltage, the first control end of the transmission gate is connected with the output end of the third inverter, and the second control end of the transmission gate is connected with the output end of the second inverter.

9. The delay circuit of claim 8, wherein the fourth transistor is a P-type metal oxide semiconductor field effect transistor.

10. The delay circuit of claim 8, wherein the first switch circuit further comprises a fifth transistor having a first terminal connected to the second terminal of the transmission gate and a third terminal of the fourth transistor, a second terminal connected to the second terminal of the second transistor, and a third terminal connected to the second reference voltage,

wherein the second transistor and the fifth transistor form a second current mirror circuit.