JP7348059B2 - voltage detection circuit - Google Patents

Description

The present invention relates to a voltage detection circuit.

FIG. 9 shows a general voltage detection circuit 100 with a hysteresis function. The voltage detection circuit 100 includes a comparator 101, a constant current source 102, a reference voltage source 103, resistors R101 to R105 that are voltage dividing resistors, an inverter INVa, an inverter INVb, and a transistor M101. .

A comparison target voltage Va obtained by dividing the detection target voltage IN by resistors R101 and R102 is applied to the inverting input terminal (-) of the comparator 101.

The reference voltage source 103 is configured with a bandgap reference and generates a reference voltage VBG that is a stable DC voltage. The resistors R103 to R105 are connected in series, and the reference voltage VBG is applied to the series circuit formed by the resistors R103 to R105. Specifically, the reference voltage VBG is applied to one end of the resistor R103. One end of a resistor R104 is connected to the other end of the resistor R103. One end of a resistor R105 is connected to the other end of the resistor R104. The other end of the resistor R105 is connected to a ground potential application end.

A node Nd101 to which the resistor R103 and the resistor R104 are connected is connected to the non-inverting input terminal (+) of the comparator 101. As a result, the reference voltage VREF obtained by dividing the reference voltage VBG by the resistors R103 to R105 is applied to the non-inverting input terminal (+) of the comparator 101.

The comparator 101 compares the comparison target voltage Va and the reference voltage VREF, and outputs a signal CMP having a level corresponding to the magnitude relationship between the comparison target voltage Va and the reference voltage VREF. When the comparison target voltage Va is higher than the reference voltage VREF, the signal CMP is at a low level, and when the comparison target voltage Va is lower than the reference voltage VREF, the signal CMP is at a high level.

The output terminal of comparator 101 is connected to the input terminal of inverter INVa. The output terminal of inverter INVa is connected to the input terminal of inverter INVb. As a result, when the signal CMP output from the comparator 101 is at a high level, the output of the inverter INVa becomes a low level, and the output of the inverter INVb (output signal OUT of the voltage detection circuit 100) becomes a high level. When the signal CMP output from the comparator 101 is at a low level, the output of the inverter INVa is at a high level, and the output of the inverter INVb (output signal OUT of the voltage detection circuit 100) is at a low level.

Transistor M101 is constituted by an NMOS transistor (N-channel MOSFET), and is connected in parallel to resistor R105. Transistor M101 is a switch that opens or shorts both ends of resistor R105. The drain of the transistor M101 is connected to a node between the resistors R104 and R105, and the source of the transistor M101 is connected to a terminal to which a ground potential is applied. The gate of transistor M101 is connected to a node Nda to which the output terminal of inverter INVAa and inverter INVb are connected.

When the signal at the node Nda is at a low level, the transistor M101 is turned off, thereby opening the terminals of the resistor R105. In this case, the reference voltage VREF=VREF1=VBG×(R104+R105)/(R103+R104+R105). When the signal at the node Nda is at a high level, the transistor M101 is turned on and the ends of the resistor R105 are short-circuited. In this case, the reference voltage VREF=VREF2=VBG×R104/(R103+R104). Therefore, VREF1>VREF2 holds true. In this way, the resistors R103 to R105 generate the reference voltage VREF by dividing the reference voltage VBG, but the ratio of the voltage division changes depending on the signal at the node Nda (that is, the signal CMP). This gives hysteresis to the comparator CMP.

Japanese Patent Application Publication No. 2008-103995

However, the voltage detection circuit 100 described above requires a comparator 101 composed of a plurality of transistors and the like, a constant current source 102 for driving the comparator 101, and a reference voltage source 102 to generate the reference voltage VREF. 103 and resistors R103 and R104 for voltage division were required. This has caused problems such as increased circuit area and increased current consumption.

In view of the above circumstances, an object of the present invention is to provide a voltage detection circuit that allows reduction in circuit area and current consumption.

In order to achieve the above object, a voltage detection circuit according to one embodiment of the present invention includes an inverter including a first transistor and a second transistor connected in series between a power supply voltage application terminal and a ground potential application terminal. The first transistor is an enhancement type MOS transistor having a gate to which an input voltage is applied, and the second transistor is a depletion type MOS transistor whose gate and source are connected. (First configuration).

Further, in the first configuration, the second transistor is a depletion type NMOS transistor having a drain connected to the application terminal of the power supply voltage, and the first transistor is connected to the source of the second transistor. The second structure may be an enhancement type NMOS transistor having a drain connected to the terminal to which the ground potential is applied, and a source connected to the terminal to which the ground potential is applied.

Further, in the first configuration, the second transistor is a depletion type PMOS transistor having a source connected to the application terminal of the power supply voltage, and the first transistor is connected to the drain of the second transistor. The transistor may be an enhancement type NMOS transistor having a drain connected to the ground potential and a source connected to the ground potential application terminal (third configuration).

Further, in the first configuration, the first transistor is an enhancement type PMOS transistor having a source connected to the application terminal of the power supply voltage, and the second transistor is connected to the drain of the first transistor. A depletion type NMOS transistor having a drain and a source connected to the end to which the ground potential is applied may be used (fourth configuration).

Further, in the first configuration, the first transistor is an enhancement type PMOS transistor having a source connected to the application terminal of the power supply voltage, and the second transistor is connected to the drain of the first transistor. A depletion type PMOS transistor having a source connected to the terminal to which the ground potential is applied and a drain connected to the end to which the ground potential is applied may be used (fifth configuration).

Further, in any one of the first to fifth configurations above, a configuration having a multi-stage configuration of the inverter formed by connecting at least one stage of an inverter having the same configuration as the inverter after the inverter; (sixth configuration).

Further, in the sixth configuration, an inverter may be further provided at a subsequent stage of the multi-stage configuration (seventh configuration).

Further, in any one of the first to seventh configurations above, hysteresis is provided by changing a voltage division ratio when dividing the detection target voltage to generate the input voltage according to the output of the inverter. (eighth configuration).

In the eighth configuration, the inverter outputs a resistor voltage divider circuit to which the detection target voltage is applied to generate the input voltage, and an open/short circuit between both ends of a resistor included in the resistor voltage divider circuit. It is also possible to have a configuration including a switch that changes according to the following (ninth configuration).

Another aspect of the present invention is a semiconductor device in which any of the voltage detection circuits described above is formed using a semiconductor integrated circuit.

According to the voltage detection circuit of the present invention, it is possible to reduce the circuit area and current consumption.

1 is a circuit diagram showing the configuration of a voltage detection circuit according to a first embodiment. FIG. FIG. 3 is a diagram showing the behavior of the output signal OUT with respect to the detection target voltage IN in the voltage detection circuit according to the first embodiment. FIG. 3 is a diagram showing the behavior of the input voltage VA, output voltage VB, and output signal OUT with respect to the detection target voltage IN in the voltage detection circuit according to the first embodiment. FIG. 2 is a circuit diagram showing the configuration of a voltage detection circuit according to a second embodiment. 7 is a diagram showing the behavior of output voltages VA, VB, VC and output signal OUT with respect to detection target voltage IN in a voltage detection circuit according to a second embodiment. FIG. FIG. 7 is a circuit diagram showing the configuration of a voltage detection circuit according to a third embodiment. FIG. 7 is a circuit diagram showing the configuration of a voltage detection circuit according to a fourth embodiment. FIG. 7 is a circuit diagram showing the configuration of a voltage detection circuit according to a fifth embodiment. FIG. 2 is a circuit diagram showing the configuration of a conventional voltage detection circuit.

Exemplary embodiments of the present invention will be described below with reference to the drawings.

<First embodiment>
FIG. 1 is a circuit diagram showing the configuration of a voltage detection circuit 10 according to the first embodiment. As shown in FIG. 1, the voltage detection circuit 10 includes a first inverter IVN1, a second inverter INV2, a third inverter INV3, resistors R1 to R3 as voltage dividing resistors, and a transistor M3. There is.

The first inverter INV1 includes a depletion type NMOS transistor M1 and an enhancement type NMOS transistor M2. The depletion type NMOS transistor M1 and the enhancement type NMOS transistor M2 are connected in series between the power supply voltage VDD and the ground potential. Specifically, the drain of the depletion type NMOS transistor M1 is connected to the application terminal of the power supply voltage VDD. The source of the depletion type NMOS transistor M1 is connected to the drain of the enhancement type NMOS transistor M2 at a node Nd11. The source of the enhancement type NMOS transistor M2 is connected to a ground potential application terminal. Further, the gate of the depletion type NMOS transistor M1 is connected to the source of the depletion type NMOS transistor M1 at a node Nd11.

The resistors R1 to R3 are connected in series, and the detection target voltage IN is applied to the series circuit of the resistors R1 to R3. Specifically, the detection target voltage IN is applied to one end of the resistor R1. One end of a resistor R2 is connected to the other end of the resistor R1. One end of a resistor R3 is connected to the other end of the resistor R2. The other end of the resistor R3 is connected to a ground potential application end. A resistive voltage divider circuit 10A is formed by a series circuit of resistors R1 to R3.

A node Nd12 to which the resistor R1 and the resistor R2 are connected is connected to the gate of the enhancement type NMOS transistor M2. As a result, the input voltage VA obtained by dividing the detection target voltage IN by the resistors R1 to R3 is applied to the gate of the enhancement type NMOS transistor M2. The input voltage VA is the voltage input to the first inverter INV1.

The second inverter INV2 and the third inverter INV3 each have a CMOS configuration including a P-channel MOSFET and an N-channel MOSFET.

The input end of the second inverter INV2 is connected to the node Nd11. Since the output voltage VB of the first inverter INV1 is generated at the node Nd11, the output voltage VB is input to the second inverter INV2. The input terminal of the third inverter INV3 is connected to the output terminal of the second inverter INV2. The voltage generated at the output terminal of the third inverter INV3 becomes the output signal OUT of the voltage detection circuit 10.

Transistor M3 is constituted by an NMOS transistor, and is connected in parallel to resistor R3. Transistor M3 is a switch that opens or shorts both ends of resistor R3. The drain of the transistor M3 is connected to a node between the resistors R2 and R3, and the source of the transistor M3 is connected to a ground potential application terminal. The gate of transistor M3 is connected to the output terminal of third inverter INV3.

Here, the threshold voltage Vref of the first inverter INV1 will be described. The depletion type NMOS transistor M1 becomes a constant current source when used in the saturation region. If the current flowing through the depletion type NMOS transistor M1 in this case is I1, then I1 is expressed by the following equation (1).
I1=(1/2)・μ _n1・_Cox・(W1/L1)・(V _GS1 -Vth1) ² (1)
However, μ _n1 : Carrier mobility of depletion type NMOS transistor M1
C _ox : Gate capacitance per unit area
V _GS1 : Gate-source voltage of depletion type NMOS transistor M1
Vth1: Threshold voltage of depletion type NMOS transistor M1
W1: Gate width of depletion type NMOS transistor M1
L1: Gate length of depletion type NMOS transistor M1

Here, since V _GS1 =0V, the above equation (1) becomes the following equation (2).
I1=(1/2)・μ _n1・_Cox・(W1/L1)・(Vth1) ² (2)

Further, when the enhancement type NMOS transistor M2 is used in the saturation region, if the current flowing through the enhancement type NMOS transistor M2 is I2, I2 is expressed by the following equation (3).
I2=(1/2)・μ _n2・_Cox・(W2/L2)・(V _GS2 -Vth2) ² (3)
However, μ _n2 : Carrier mobility of enhancement type NMOS transistor M2
V _GS2 : Gate-source voltage of enhancement type NMOS transistor M2
Vth2: Threshold voltage of enhancement type NMOS transistor M2
W2: Gate width of enhancement type NMOS transistor M2
L2: Gate length of enhancement type NMOS transistor M2

Since I1=I2 and V _GS2 =Vref, the following equation (4) holds true.
Vref=Vth2+|Vth1|・√μ _n1・(W1/L1)/(μ _n2・(W2/L2)) (4)

From the above equation (4), the threshold voltage Vref of the first inverter INV1 becomes a stable voltage that does not depend on the power supply voltage VDD. Furthermore, since Vth1 has a positive temperature characteristic and Vth2 has a negative temperature characteristic, by adjusting W1, L1, W2, and L2, it is also possible to suppress fluctuations in the threshold voltage Vref due to temperature. .

When input voltage VA<threshold voltage Vref, output voltage VB becomes high level, and when input voltage VA>threshold voltage Vref, output voltage VB becomes low level.

Next, the operation of the voltage detection circuit 10 will be explained. FIG. 2 is a diagram showing the behavior of the output signal OUT with respect to the detection target voltage IN. Here, it is assumed that the threshold voltage of the second inverter INV2 is the same as the value of the output voltage VB when the input voltage VA=Vref.

First, when the detection target voltage IN is 0V, the input voltage VA=0V, and since the input voltage VA<Vref, the output voltage VB becomes high level. Therefore, the output signal OUT becomes high level, the transistor M3 is turned on, and both ends of the resistor R3 are short-circuited. As a result, the output voltage VA becomes a voltage obtained by dividing the detection target voltage IN by the resistors R1 and R2.

Then, as the detection target voltage IN rises from 0V, the output voltage VA rises. When the output voltage VA exceeds the threshold voltage Vref, the output voltage VB becomes low level. As a result, the output of the second inverter INV2 becomes high level, and the output signal OUT, which is the output of the third inverter INV3, becomes low level. If the detection target voltage IN at this time is the threshold voltage VDET1 (FIG. 2),
VDET1=Vref・(R1+R2)/R2
becomes.

At this time, transistor M3 is turned off, and both ends of resistor R3 are opened. Therefore, the input voltage VA is a voltage obtained by dividing the detection target voltage IN by the resistors R1 to R3.

Thereafter, as the detection target voltage IN decreases, the output voltage VA decreases, and when the output voltage VA falls below the threshold voltage Vref, the output voltage VB becomes high level. As a result, the output of the second inverter INV2 becomes low level, and the output signal OUT, which is the output of the third inverter INV3, becomes high level. If the detection target voltage IN at this time is the threshold voltage VDET2 (FIG. 2),
VDET2=Vref・(R1+R2+R3)/(R2+R3)
becomes. In this way, hysteresis can be provided to the voltage detection circuit 10.

According to the voltage detection circuit 10 according to this embodiment, the circuit area and current consumption can be reduced. Furthermore, according to the voltage detection circuit 10, the reference voltage source 103 as in the conventional configuration shown in FIG. 9 is not required, and the minimum operating voltage can be lowered.

<Issues of the first embodiment>
Although the voltage detection circuit 10 according to the first embodiment has excellent effects as described above, it also has the following problems. FIG. 3 is a diagram showing the behavior of the input voltage VA, output voltage VB, and output signal OUT with respect to the detection target voltage IN in the voltage detection circuit 10.

The depletion type NMOS transistor M1 functions as a constant current source when used in a saturated region, but when used in a non-saturated region, the constant current property is lost and the impedance changes. As shown in FIG. 3, as the detection target voltage IN rises from 0V, the input voltage VA rises, and when the output voltage VB changes, the drain-source voltage of the depletion type NMOS transistor M1 changes. As a result, the waveform of the output voltage VB becomes dull in the region A1 shown in FIG. 3 near where the depletion type NMOS transistor M1 switches from the non-saturated region to the saturated region. Furthermore, in the enhancement type NMOS transistor M2, the waveform of the output voltage VB is rounded in a region A2 shown in FIG. 3 near where it switches from the saturated region to the non-saturated region.

As a result, if the threshold voltage Vth_INV2 of the second inverter INV2 placed after the first inverter INV1 varies or changes due to temperature characteristics, etc., the threshold voltage VDET1 at which the output signal OUT switches from high level to low level will vary. It will happen. For example, FIG. 3 shows a variation ΔVDET1 in the threshold voltage VDET1 that occurs when a variation (or variation) ΔVth_INV2 in the threshold voltage Vth_INV2 occurs. That is, variations occur in the threshold voltage VDET1 of the voltage detection circuit 10.

<Second embodiment>
In view of the above-mentioned problems, a second embodiment will be described, which has a configuration that is further improved. FIG. 4 is a circuit diagram showing the configuration of the voltage detection circuit 20 according to the second embodiment.

The voltage detection circuit 20 shown in FIG. 4 differs from the voltage detection circuit 10 according to the first embodiment (FIG. 1) in that the second inverter INV2 has the same configuration as the first inverter INV1. Specifically, the second inverter INV2 includes a depletion type NMOS transistor M4 and an enhancement type NMOS transistor M5.

The depletion type NMOS transistor M4 and the enhancement type NMOS transistor M5 are connected in series between the power supply voltage VDD and the ground potential. Specifically, the drain of the depletion type NMOS transistor M4 is connected to the application terminal of the power supply voltage VDD. The source of the depletion type NMOS transistor M4 is connected to the drain of the enhancement type NMOS transistor M5 at a node Nd21. The source of the enhancement type NMOS transistor M5 is connected to a ground potential application terminal. Further, the gate of the depletion type NMOS transistor M4 is connected to the source of the depletion type NMOS transistor M4 at a node Nd21.

The gate of enhancement type NMOS transistor M5 is connected to node Nd11. Node Nd21 is connected to the input terminal of third inverter INV3.

In this way, this embodiment has a two-stage configuration including the first inverter INV1 and the second inverter INV2. As a result, the logic of the output voltage VB, which is the output of the first inverter INV1, and the output voltage VC, which is the output of the second inverter INV2, is inverted. However, since the first inverter INV1 and the second inverter INV2 have the same configuration, their threshold voltages are the same, and the threshold voltages do not depend on the power supply voltage VDD, and fluctuations due to temperature are also suppressed.

Here, FIG. 5 shows the behavior of the output voltages VA, VB, VC and the output signal OUT with respect to the detection target voltage IN. As shown in FIG. 5, the waveform of the output voltage VB is almost perpendicular to the axis of the detection target voltage IN near the threshold voltage of the first inverter INV1, so the waveform of the output voltage VC is This results in a more vertical waveform, resulting in a more ideal waveform.

Thereby, even if the threshold voltage Vth_INV3 of the third inverter INV3 disposed after the second inverter INV2 varies or fluctuates, variations in the threshold voltage VDET1 of the voltage detection circuit 20 can be suppressed. For example, in FIG. 5, the variation ΔVDET1 in the threshold voltage VDET1 that occurs when the variation (or variation) ΔVth_INV3 in the threshold voltage Vth_INV3 occurs has almost disappeared.

<Third embodiment>
FIG. 6 is a circuit diagram showing the configuration of the voltage detection circuit 30 according to the third embodiment. The voltage detection circuit 30 according to the present embodiment has a configuration in which the depression type NMOS transistor M1 included in the first inverter INV1 is replaced with a depression type PMOS transistor M6 in the voltage detection circuit 10 (FIG. 1) according to the first embodiment. .

More specifically, the source of the depletion type PMOS transistor M6 is connected to the application terminal of the power supply voltage VDD. The drain of the depletion type PMOS transistor M6 is connected to the drain of the enhancement type NMOS transistor M2. The gate of the depletion type PMOS transistor M6 is connected to the source of the depletion type PMOS transistor M6.

Even in this embodiment, the same effects as in the first embodiment can be achieved.

<Fourth embodiment>
FIG. 7 is a circuit diagram showing the configuration of a voltage detection circuit 40 according to the fourth embodiment. The difference between the voltage detection circuit 40 according to this embodiment and the voltage detection circuit 10 (FIG. 1) according to the first embodiment is the first inverter INV1.

More specifically, the first inverter INV1 includes an enhancement type PMOS transistor M7 and a depletion type NMOS transistor M8. The source of the enhancement type PMOS transistor M7 is connected to the application terminal of the power supply voltage VDD. The drain of the enhancement type PMOS transistor M7 is connected to the drain of the depletion type NMOS transistor M8 at a node Nd41. The source of the depletion type NMOS transistor M8 is connected to a ground potential application terminal. The gate of the depletion type NMOS transistor M8 is connected to the source of the depletion type NMOS transistor M8. Node Nd41 is connected to the input terminal of second inverter INV2. The gate of enhancement type PMOS transistor M7 is connected to node Nd12 between resistors R1 and R2.

Even in this embodiment, the same effects as in the first embodiment can be achieved.

<Fifth embodiment>
FIG. 8 is a circuit diagram showing the configuration of a voltage detection circuit 50 according to the fifth embodiment. The voltage detection circuit 50 according to the present embodiment has a configuration in which the depression type NMOS transistor M8 included in the first inverter INV1 is replaced with a depression type PMOS transistor M9 in the voltage detection circuit 40 (FIG. 7) according to the fourth embodiment. .

More specifically, the drain of enhancement type PMOS transistor M7 is connected to the source of depletion type PMOS transistor M9. The drain of the depletion type PMOS transistor M9 is connected to a ground potential application terminal. The gate of the depletion type PMOS transistor M9 is connected to the source of the depletion type PMOS transistor M9.

Even in this embodiment, the same effects as in the first embodiment can be achieved.

<Others>
The above embodiments should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention is defined by the claims rather than the description of the above embodiments. It should be understood that all changes that come within the meaning and range of equivalency of the claims are included.

For example, the second embodiment may be applied to the third to fifth embodiments. That is, the second inverter INV2 in the third to fifth embodiments may have the same configuration as the first inverter INV1, and may have a two-stage configuration.

Further, for example, in the second embodiment, the number of inverters having the same configuration is not limited to two stages, but may be a configuration in which three or more stages are connected.

Further, for example, it is not essential to provide hysteresis to the voltage detection circuit.

Further, for example, the output voltage of the first inverter INV1 or the output voltage of a plurality of stages of inverters having the same configuration may be applied not only to the inverter but also to the gate of a MOS transistor.

Furthermore, the voltage detection circuits according to the various embodiments described above can be installed in any device. For example, a voltage comparison circuit can be installed in in-vehicle equipment installed in a vehicle such as an automobile, or a portable information terminal such as a smartphone or tablet.

Furthermore, the voltage detection circuits according to the various embodiments described above may be formed in the form of a semiconductor integrated circuit. A semiconductor device can be constructed in which a semiconductor integrated circuit including a voltage detection circuit is packaged.

INDUSTRIAL APPLICATION This invention can be utilized for the voltage detection circuit with which various apparatuses are equipped, for example.

10 to 50 Voltage detection circuit INV1 First inverter INV2 Second inverter INV3 Third inverter M1 Depression type NMOS transistor M2 Enhancement type NMOS transistor M3 Transistor M4 Depression type NMOS transistor M5 Enhancement type NMOS transistor M6 Depression type PMOS transistor M7 Enhancement type P MOS transistor M8 Depression type NMOS transistor M9 Depression type PMOS transistor R1 to R3 Resistor

Claims (8)

a first inverter including a first transistor and a second transistor connected in series between a power supply voltage application end and a ground potential application end;
The first transistor is an enhancement type MOS transistor having a gate to which an input voltage is applied;
The second transistor is a depletion type MOS transistor whose gate and source are connected,
having a multi-stage inverter configuration formed by connecting at least one stage of a second inverter having the same configuration and the same threshold voltage as the first inverter after the first inverter;
further comprising a third inverter disposed at a subsequent stage of the multi-stage configuration,
The third inverter is a voltage detection circuit whose threshold voltage varies more with temperature than the first inverter and the second inverter . The second transistor is a depletion type NMOS transistor having a drain connected to the application terminal of the power supply voltage,
The voltage detection circuit according to claim 1, wherein the first transistor is an enhancement type NMOS transistor having a drain connected to the source of the second transistor and a source connected to the ground potential application terminal. . The second transistor is a depletion type PMOS transistor having a source connected to the application terminal of the power supply voltage,
2. The voltage detection circuit according to claim 1, wherein the first transistor is an enhancement NMOS transistor having a drain connected to the drain of the second transistor and a source connected to the ground potential application terminal. . The first transistor is an enhancement type PMOS transistor having a source connected to the application terminal of the power supply voltage,
2. The voltage detection circuit according to claim 1, wherein the second transistor is a depletion type NMOS transistor having a drain connected to the drain of the first transistor and a source connected to the ground potential application terminal. . The first transistor is an enhancement type PMOS transistor having a source connected to the application terminal of the power supply voltage,
2. The voltage detection circuit according to claim 1, wherein the second transistor is a depletion type PMOS transistor having a source connected to the drain of the first transistor and a drain connected to the ground potential application terminal. . Any one of claims 1 to 5 , wherein hysteresis is provided by changing a voltage division ratio when dividing the detection target voltage to generate the input voltage according to the output of the third inverter. Voltage detection circuit described in section. a resistive voltage divider circuit to which the detection target voltage is applied to generate the input voltage;
7. The voltage detection circuit according to claim 6 , further comprising a switch that switches open/short circuit between both ends of the resistor included in the resistor voltage divider circuit according to the output of the third inverter. A semiconductor device in which the voltage detection circuit according to any one of claims 1 to 7 is formed using a semiconductor integrated circuit.

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