JP2021103860A - Voltage detection circuit - Google Patents

Abstract

To provide a voltage detection circuit that enables reduction of a circuit area and current consumption.SOLUTION: A voltage detection circuit includes an inverter including a first transistor and a second transistor connected in series between the application end of a power supply voltage and the application end of a ground potential, and the first transistor is an enhancement type MOS transistor having a gate to which an input voltage is applied, and the second transistor is a depletion type MOS transistor to which its own gate and source are connected.SELECTED DRAWING: Figure 1

Description

The present invention relates to a voltage detection circuit.

FIG. 9 shows a voltage detection circuit 100 with a general hysteresis function. The voltage detection circuit 100 includes a comparator 101, a constant current source 102, a reference voltage source 103, resistors R101 to R105 which are voltage dividing resistors, an inverter INVa, an inverter INVb, and a transistor M101. ..

A comparison target voltage Va obtained by dividing the detection target voltage IN by the resistors R101 and R102 is applied to the inverting input terminal (−) of the comparator 101.

The reference voltage source 103 is composed of a bandgap reference and generates a reference voltage VBG which is a stable DC voltage. The resistors R103 to R105 are connected in series, and a reference voltage VBG is applied to the series circuit by the resistors R103 to R105. Specifically, a reference voltage VBG is applied to one end of the resistor R103. One end of the resistor R104 is connected to the other end of the resistor R103. One end of the resistor R105 is connected to the other end of the resistor R104. An application end of the ground potential is connected to the other end of the resistor R105.

The node Nd101 to which the resistor R103 and the resistor R104 are connected is connected to the non-inverting input end (+) of the comparator 101. As a result, the reference voltage VREF obtained by dividing the reference voltage VBG by the resistors R103 to R105 is applied to the non-inverting input end (+) of the comparator 101.

The comparator 101 compares the comparison target voltage Va and the reference voltage VREF, and outputs a signal CMP at a level corresponding to the magnitude relationship between the comparison target voltage Va and the reference voltage VREF. When the comparison target voltage Va is higher than the reference voltage VREF, the signal CMP is at a low level, and when the comparison target voltage Va is lower than the reference voltage VREF, the signal CMP is at a high level.

The output end of the comparator 101 is connected to the input end of the inverter INVa. The output end of the inverter INVa is connected to the input end of the inverter INVb. As a result, when the signal CMP output by the comparator 101 is at a high level, the output of the inverter INVa becomes low level, and the output of the inverter INVb (output signal OUT of the voltage detection circuit 100) becomes high level. When the signal CMP output by the comparator 101 is low level, the output of the inverter INVa becomes high level, and the output of the inverter INVb (output signal OUT of the voltage detection circuit 100) becomes low level.

The transistor M101 is composed of an NMOS transistor (N-channel MOSFET) and is connected in parallel to the resistor R105. The transistor M101 is a switch that opens or short-circuits between both ends of the resistor R105. The drain of the transistor M101 is connected to the node between the resistors R104 and R105, and the source of the transistor M101 is connected to the application end of the ground potential. The gate of the transistor M101 is connected to the node Nda to which the output end of the inverter INVAa and the inverter INVb are connected.

When the signal of the node Nda is low level, the transistor M101 is turned off to open the space between both ends of the resistor R105. In this case, the reference voltage VREF = VREF1 = VBG × (R104 + R105) / (R103 + R104 + R105). When the signal of the node Nda is high level, the transistor M101 is turned on, so that both ends of the resistor R105 are short-circuited. In this case, the reference voltage VREF = VREF2 = VBG × R104 / (R103 + R104). Therefore, VREF1> VREF2 is established. In this way, the resistors R103 to R105 generate the reference voltage VREF by dividing the reference voltage VBG, and the ratio at the divided voltage changes according to the signal (that is, the signal CMP) at the node Nda. Will give hysteresis to the comparator CMP.

Japanese Unexamined Patent Publication No. 2008-103995

However, the voltage detection circuit 100 requires a comparator 101 composed of a plurality of transistors and the like, and a constant current source 102 for driving the comparator 101, and further, a reference voltage source for generating a reference voltage VREF. 103 and resistors R103 and R104 for voltage division were required. This has caused problems such as an increase in circuit area and an increase in current consumption.

In view of the above circumstances, it is an object of the present invention to provide a voltage detection circuit capable of reducing the circuit area and the current consumption.

In order to achieve the above object, the voltage detection circuit according to one aspect of the present invention includes an inverter including a first transistor and a second transistor connected in series between an application end of a power supply voltage and an application end of a ground potential. The first transistor is an enhancement type MOS transistor having a gate to which an input voltage is applied, and the second transistor is a depletion type MOS transistor in which its own gate and source are connected. (First configuration).

Further, in the first configuration, the second transistor is a depletion type NMOS transistor having a drain connected to the application end of the power supply voltage, and the first transistor is connected to the source of the second transistor. The configuration may be an enhancement type NMOS transistor having a drain and a source connected to the application end of the ground potential (second configuration).

Further, in the first configuration, the second transistor is a depletion type epitaxial transistor having a source connected to the application end of the power supply voltage, and the first transistor is connected to the drain of the second transistor. The configuration may be an enhancement type NMOS transistor having a drain and a source connected to the application end of the ground potential (third configuration).

Further, in the first configuration, the first transistor is an enhancement type MIMO transistor having a source connected to the application end of the power supply voltage, and the second transistor is connected to the drain of the first transistor. The configuration may be a depletion type NMOS transistor having a drain and a source connected to the application end of the ground potential (fourth configuration).

Further, in the first configuration, the first transistor is an enhancement type MIMO transistor having a source connected to the application end of the power supply voltage, and the second transistor is connected to the drain of the first transistor. The configuration may be a depletion type MIMO transistor having a source and a drain connected to the application end of the ground potential (fifth configuration).

Further, in any of the first to fifth configurations, the configuration has a plurality of stages of the inverter formed by connecting at least one stage of an inverter having the same configuration as the inverter to the subsequent stage of the inverter. It may be (sixth configuration).

Further, in the sixth configuration, an inverter arranged after the plurality of stages may be further provided (seventh configuration).

Further, in any of the first to seventh configurations, hysteresis is imparted by changing the voltage division ratio when the detection target voltage is divided to generate the input voltage according to the output of the inverter. It may be the configuration (eighth configuration).

Further, in the eighth configuration, the output of the inverter opens / short-circuits between the resistance voltage divider circuit to which the detection target voltage is applied to generate the input voltage and the resistors included in the resistance voltage divider circuit. The configuration may include a switch that switches according to the above (ninth configuration).

Further, another aspect of the present invention is a semiconductor device in which any of the above voltage detection circuits is formed by a semiconductor integrated circuit.

According to the voltage detection circuit of the present invention, the circuit area and the current consumption can be reduced.

It is a circuit diagram which shows the structure of the voltage detection circuit which concerns on 1st Embodiment. It is a figure which shows the behavior of the output signal OUT with respect to the detection target voltage IN in the voltage detection circuit which concerns on 1st Embodiment. It is a figure which shows the behavior of the input voltage VA, the output voltage VB, and the output signal OUT with respect to the detection target voltage IN in the voltage detection circuit which concerns on 1st Embodiment. It is a circuit diagram which shows the structure of the voltage detection circuit which concerns on 2nd Embodiment. It is a figure which shows the behavior of the output voltage VA, VB, VC and the output signal OUT with respect to the detection target voltage IN in the voltage detection circuit which concerns on 2nd Embodiment. It is a circuit diagram which shows the structure of the voltage detection circuit which concerns on 3rd Embodiment. It is a circuit diagram which shows the structure of the voltage detection circuit which concerns on 4th Embodiment. It is a circuit diagram which shows the structure of the voltage detection circuit which concerns on 5th Embodiment. It is a circuit diagram which shows the structure of the conventional voltage detection circuit.

An exemplary embodiment of the present invention will be described below with reference to the drawings.

<First Embodiment>
FIG. 1 is a circuit diagram showing the configuration of the voltage detection circuit 10 according to the first embodiment. As shown in FIG. 1, the voltage detection circuit 10 includes a first inverter IVN1, a second inverter INV2, a third inverter INV3, resistors R1 to R3 as voltage dividing resistors, and a transistor M3. There is.

The first inverter INV1 includes a depletion type NMOS transistor M1 and an enhancement type NMOS transistor M2. The depletion type NMOS transistor M1 and the enhancement type NMOS transistor M2 are connected in series between the power supply voltage VDD and the ground potential. Specifically, the drain of the depletion type NMOS transistor M1 is connected to the application end of the power supply voltage VDD. The source of the depletion type NMOS transistor M1 is connected to the drain of the enhancement type MOSFET transistor M2 at the node Nd11. The source of the enhancement type NMOS transistor M2 is connected to the application end of the ground potential. Further, the gate of the depletion type MOSFET transistor M1 is connected to the source of the depletion type MOSFET transistor M1 at the node Nd11.

The resistors R1 to R3 are connected in series, and the detection target voltage IN is applied to the series circuit by the resistors R1 to R3. Specifically, the detection target voltage IN is applied to one end of the resistor R1. One end of the resistor R2 is connected to the other end of the resistor R1. One end of the resistor R3 is connected to the other end of the resistor R2. An application end of the ground potential is connected to the other end of the resistor R3. The resistance voltage dividing circuit 10A is formed by the series circuit of the resistors R1 to R3.

The node Nd12 to which the resistor R1 and the resistor R2 are connected is connected to the gate of the enhancement type NMOS transistor M2. As a result, the input voltage VA obtained by dividing the detection target voltage IN by the resistors R1 to R3 is applied to the gate of the enhancement type NMOS transistor M2. The input voltage VA is the voltage input to the first inverter INV1.

The second inverter INV2 and the third inverter INV3 are configured by a CMOS configuration consisting of a P-channel MOSFET and an N-channel MOSFET, respectively.

The input end of the second inverter INV2 is connected to the node Nd11. Since the output voltage VB of the first inverter INV1 is generated at the node Nd11, the output voltage VB is input to the second inverter INV2. The input end of the third inverter INV3 is connected to the output end of the second inverter INV2. The voltage generated at the output end of the third inverter INV3 becomes the output signal OUT of the voltage detection circuit 10.

The transistor M3 is composed of an NMOS transistor and is connected in parallel to the resistor R3. The transistor M3 is a switch that opens or short-circuits between both ends of the resistor R3. The drain of the transistor M3 is connected to the node between the resistors R2 and R3, and the source of the transistor M3 is connected to the application end of the ground potential. The gate of the transistor M3 is connected to the output end of the third inverter INV3.

Here, the threshold voltage Vref of the first inverter INV1 will be described. The depletion type NMOS transistor M1 serves as a constant current source when used in the saturation region. Assuming that the current flowing through the depletion type NMOS transistor M1 in this case is I1, I1 is represented by the following equation (1).
_{I1 = (1/2) · μ n1} · C ox · (W1 / L1) · (V GS1 -Vth1) 2 (1)
However, μ _n1 : carrier mobility of the depletion type NMOS transistor M1.
_Cox : Gate capacity per unit area
V _GS1 : Gate-source voltage of depletion type NMOS transistor M1
Vth1: Threshold voltage of depletion type NMOS transistor M1
W1: Gate width of depletion type NMOS transistor M1
L1: Gate length of depletion type NMOS transistor M1

Here, since _VGS1 = 0V, the above equation (1) becomes the following equation (2).
I1 = (1/2) · μ _n1 · _Cox · (W1 / L1) · (Vth1) ² (2)

Further, when the enhancement type MOSFET transistor M2 is used in the saturation region, if the current flowing through the enhancement type MOSFET transistor M2 is I2, I2 is represented by the following equation (3).
_{I2 = (1/2) · μ n2} · C ox · (W2 / L2) · (V GS2 -Vth2) 2 (3)
However, μ _n2 : Carrier mobility of the enhancement type NMOS transistor M2
_VGS2 : Gate-source voltage of enhancement type NMOS transistor M2
Vth2: Threshold voltage of enhancement type NMOS transistor M2
W2: Gate width of enhancement type NMOS transistor M2
L2: Gate length of enhancement type NMOS transistor M2

Then, since I1 = I2 and _VGS2 = Vref, the following equation (4) holds.
Vref = Vth2 + | Vth1 | ・ √μ _n1・ (W1 / L1) / (μ _n2・ (W2 / L2)) (4)

From the above equation (4), the threshold voltage Vref of the first inverter INV1 is a stable voltage that does not depend on the power supply voltage VDD. Further, since Vth1 has a positive temperature characteristic and Vth2 has a negative temperature characteristic, it is possible to suppress the fluctuation of the threshold voltage Vref due to the temperature by adjusting W1, L1, W2, and L2. ..

When the input voltage VA <threshold voltage Vref, the output voltage VB becomes a high level, and when the input voltage VA> the threshold voltage Vref, the output voltage VB becomes a low level.

Next, the operation of the voltage detection circuit 10 will be described. FIG. 2 is a diagram showing the behavior of the output signal OUT with respect to the detection target voltage IN. Here, it is assumed that the threshold voltage of the second inverter INV2 is the same as the value of the output voltage VB when the input voltage VA = Vref.

First, when the detection target voltage IN is 0V, the input voltage VA = 0V and the input voltage VA <Vref, so that the output voltage VB becomes a high level. Therefore, the output signal OUT becomes high level, the transistor M3 is turned on, and both ends of the resistor R3 are short-circuited. As a result, the output voltage VA becomes a voltage obtained by dividing the detection target voltage IN by the resistors R1 and R2.

Then, as the detection target voltage IN rises from 0V, the output voltage VA rises. When the output voltage VA exceeds the threshold voltage Vref, the output voltage VB becomes a low level. As a result, the output of the second inverter INV2 becomes high level, and the output signal OUT, which is the output of the third inverter INV3, becomes low level. If the detection target voltage IN at this time is the threshold voltage VDET1 (FIG. 2),
VDET1 = Vref ・ (R1 + R2) / R2
Will be.

At this time, the transistor M3 is turned off, and both ends of the resistor R3 are opened. Therefore, the input voltage VA is a voltage obtained by dividing the detection target voltage IN by the resistors R1 to R3.

After that, as the detection target voltage IN decreases, the output voltage VA decreases, and when the output voltage VA falls below the threshold voltage Vref, the output voltage VB becomes a high level. As a result, the output of the second inverter INV2 becomes low level, and the output signal OUT, which is the output of the third inverter INV3, becomes high level. If the detection target voltage IN at this time is the threshold voltage VDET2 (FIG. 2),
VDET2 = Vref ・ (R1 + R2 + R3) / (R2 + R3)
Will be. In this way, hysteresis can be applied to the voltage detection circuit 10.

Then, according to the voltage detection circuit 10 according to the present embodiment, it is possible to reduce the circuit area and the current consumption. Further, according to the voltage detection circuit 10, the reference voltage source 103 as in the conventional configuration shown in FIG. 9 is not required, and the minimum operating voltage can be lowered.

<Problems of the first embodiment>
The voltage detection circuit 10 according to the first embodiment has excellent effects as described above, but also has the following problems. FIG. 3 is a diagram showing the behavior of the input voltage VA, the output voltage VB, and the output signal OUT with respect to the detection target voltage IN in the voltage detection circuit 10.

The depletion type NMOS transistor M1 functions as a constant current source when used in a saturated region, but when used in a non-saturated region, the constant current property is lost and the impedance changes. As shown in FIG. 3, as the detection target voltage IN rises from 0V, the input voltage VA rises and the output voltage VB changes, so that the drain-source voltage of the depletion type NMOS transistor M1 changes. As a result, the waveform of the output voltage VB is blunted in the region A1 shown in FIG. 3 near the switching of the depletion type NMOS transistor M1 from the non-saturated region to the saturated region. Further, in the region A2 shown in FIG. 3 near the switching from the saturated region to the non-saturated region of the enhancement type NMOS transistor M2, the waveform of the output voltage VB is blunted.

As a result, when the threshold voltage Vth_INV2 of the second inverter INV2 arranged after the first inverter INV1 varies or changes due to temperature characteristics or the like, the threshold voltage VDET1 that switches the output signal OUT from the high level to the low level varies. It will occur. For example, FIG. 3 shows the variation ΔVDET1 of the threshold voltage VDET1 that occurs when the variation (or variation) ΔVth_INV2 of the threshold voltage Vth_INV2 occurs. That is, the threshold voltage VDET1 of the voltage detection circuit 10 varies.

<Second Embodiment>
In view of the above problems, a second embodiment having a configuration for further improvement will be described. FIG. 4 is a circuit diagram showing the configuration of the voltage detection circuit 20 according to the second embodiment.

The difference from the voltage detection circuit 10 (FIG. 1) according to the first embodiment of the voltage detection circuit 20 shown in FIG. 4 is that the second inverter INV2 has the same configuration as the first inverter INV1. Specifically, the second inverter INV2 has a depletion type NMOS transistor M4 and an enhancement type NMOS transistor M5.

The depletion type NMOS transistor M4 and the enhancement type NMOS transistor M5 are connected in series between the power supply voltage VDD and the ground potential. Specifically, the drain of the depletion type NMOS transistor M4 is connected to the application end of the power supply voltage VDD. The source of the depletion type NMOS transistor M4 is connected to the drain of the enhancement type MOSFET transistor M5 at the node Nd21. The source of the enhancement type NMOS transistor M5 is connected to the application end of the ground potential. Further, the gate of the depletion type NMOS transistor M4 is connected to the source of the depletion type NMOS transistor M4 at the node Nd21.

The gate of the enhancement type NMOS transistor M5 is connected to the node Nd11. The node Nd21 is connected to the input end of the third inverter INV3.

As described above, in the present embodiment, the first inverter INV1 and the second inverter INV2 have a two-stage configuration. As a result, the logic of the output voltage VB, which is the output of the first inverter INV1, and the output voltage VC, which is the output of the second inverter INV2, is reversed. However, since the first inverter INV1 and the second inverter INV2 have the same configuration, their threshold voltages are the same, the threshold voltage does not depend on the power supply voltage VDD, and fluctuations due to temperature are suppressed.

Here, FIG. 5 shows the behavior of the output voltages VA, VB, VC and the output signal OUT with respect to the detection target voltage IN. As shown in FIG. 5, since the waveform of the output voltage VB is substantially perpendicular to the axis of the detection target voltage IN near the threshold voltage of the first inverter INV1, the waveform of the output voltage VC is relative to the above axis. The waveform becomes closer to vertical, and the waveform becomes more ideal.

As a result, even if the threshold voltage Vth_INV3 of the third inverter INV3 arranged after the second inverter INV2 varies or fluctuates, the variation of the threshold voltage VDET1 of the voltage detection circuit 20 can be suppressed. For example, in FIG. 5, the variation ΔVDET1 of the threshold voltage VDET1 that occurs when the variation (or fluctuation) ΔVth_INV3 of the threshold voltage Vth_INV3 occurs is almost eliminated.

<Third Embodiment>
FIG. 6 is a circuit diagram showing the configuration of the voltage detection circuit 30 according to the third embodiment. The voltage detection circuit 30 according to the present embodiment has a configuration in which the voltage detection circuit 10 (FIG. 1) according to the first embodiment replaces the depletion type NMOS transistor M1 included in the first inverter INV1 with the depletion type MOSFET transistor M6. ..

More specifically, the source of the depletion type PRIVATE transistor M6 is connected to the application end of the power supply voltage VDD. The drain of the depletion type MOSFET transistor M6 is connected to the drain of the enhancement type NMOS transistor M2. The gate of the depletion type epitaxial transistor M6 is connected to the source of the depletion type epitaxial transistor M6.

Even in such an embodiment, the same effect as that of the first embodiment can be obtained.

<Fourth Embodiment>
FIG. 7 is a circuit diagram showing the configuration of the voltage detection circuit 40 according to the fourth embodiment. The difference between the voltage detection circuit 40 according to the present embodiment and the voltage detection circuit 10 (FIG. 1) according to the first embodiment is the first inverter INV1.

More specifically, the first inverter INV1 includes an enhancement type MOSFET transistor M7 and a depletion type NMOS transistor M8. The source of the enhancement type MPa transistor M7 is connected to the application end of the power supply voltage VDD. The drain of the enhancement type MOSFET transistor M7 is connected to the drain of the depletion type NMOS transistor M8 at the node Nd41. The source of the depletion type NMOS transistor M8 is connected to the application end of the ground potential. The gate of the depletion type NMOS transistor M8 is connected to the source of the depletion type NMOS transistor M8. The node Nd41 is connected to the input end of the second inverter INV2. The gate of the enhancement type PRIVATE transistor M7 is connected to the node Nd12 between the resistors R1 and R2.

Even in such an embodiment, the same effect as that of the first embodiment can be obtained.

<Fifth Embodiment>
FIG. 8 is a circuit diagram showing the configuration of the voltage detection circuit 50 according to the fifth embodiment. The voltage detection circuit 50 according to the present embodiment has a configuration in which the voltage detection circuit 40 (FIG. 7) according to the fourth embodiment replaces the depletion type NMOS transistor M8 included in the first inverter INV1 with the depletion type MOSFET transistor M9. ..

More specifically, the drain of the enhancement type MIMO transistor M7 is connected to the source of the depletion type epitaxial transistor M9. The drain of the depletion type polyclonal transistor M9 is connected to the application end of the ground potential. The gate of the depletion type polyclonal transistor M9 is connected to the source of the depletion type epitaxial transistor M9.

Even in such an embodiment, the same effect as that of the first embodiment can be obtained.

<Others>
It should be considered that the above-described embodiment is an example in all respects and is not restrictive, and the technical scope of the present invention is not the description of the above-mentioned embodiment but the scope of claims. It is shown and should be understood to include all modifications that fall within the meaning and scope of the claims.

For example, the second embodiment may be applied to the third to fifth embodiments. That is, the second inverter INV2 in the third to fifth embodiments may have the same configuration as the first inverter INV1 and may have a two-stage configuration.

Further, for example, in the second embodiment and the like, the inverter having the same configuration is not limited to the two stages, and may be configured to connect three or more stages.

Further, for example, it is not essential to impart hysteresis to the voltage detection circuit.

Further, for example, the output voltage of the first inverter INV1 or the output voltage of a plurality of stages of inverters having the same configuration may be applied not only to the inverter but also to the gate of the MOS transistor.

Further, the voltage detection circuits according to the various embodiments described above can be mounted on any device. For example, a voltage comparison circuit can be mounted on an in-vehicle device installed in a vehicle such as an automobile or a mobile information terminal such as a smartphone or tablet.

Further, the voltage detection circuit according to the above various embodiments may be formed in the form of a semiconductor integrated circuit. A semiconductor device in which a semiconductor integrated circuit including a voltage detection circuit is packaged can be configured.

The present invention can be used, for example, in a voltage detection circuit provided in various devices.

10 to 50 Voltage detection circuit INV1 1st inverter INV2 2nd inverter INV3 3rd inverter M1 Depression type NMOS transistor M2 Enhancement type NMOS transistor M3 transistor M4 Depression type NMOS transistor M5 Enhancement type NMOS transistor M6 Depression type NMOS transistor M7 Enhancement type NMOS transistor M8 Depression Type NMOS Transistor M9 Depression Type NMOS Transistor R1 to R3 Resistors

Claims (10)

It has an inverter including a first transistor and a second transistor connected in series between an application end of a power supply voltage and an application end of a ground potential.
The first transistor is an enhancement type MOS transistor having a gate to which an input voltage is applied.
The second transistor is a voltage detection circuit which is a depletion type MOS transistor in which its own gate and source are connected. The second transistor is a depletion type NMOS transistor having a drain connected to the application end of the power supply voltage.
The voltage detection circuit according to claim 1, wherein the first transistor is an enhancement type NMOS transistor having a drain connected to the source of the second transistor and a source connected to the application end of the ground potential. .. The second transistor is a depletion type polyclonal transistor having a source connected to the application end of the power supply voltage.
The voltage detection circuit according to claim 1, wherein the first transistor is an enhancement type NMOS transistor having a drain connected to the drain of the second transistor and a source connected to the application end of the ground potential. .. The first transistor is an enhancement type MPa transistor having a source connected to the application end of the power supply voltage.
The voltage detection circuit according to claim 1, wherein the second transistor is a depletion type NMOS transistor having a drain connected to the drain of the first transistor and a source connected to the application end of the ground potential. .. The first transistor is an enhancement type MPa transistor having a source connected to the application end of the power supply voltage.
The voltage detection circuit according to claim 1, wherein the second transistor is a depletion type MIMO transistor having a source connected to the drain of the first transistor and a drain connected to the application end of the ground potential. .. The voltage according to any one of claims 1 to 5, which has a multi-stage configuration of the inverter formed by connecting at least one stage of an inverter having the same configuration as the inverter to the subsequent stage of the inverter. Detection circuit. The voltage detection circuit according to claim 6, further comprising an inverter arranged after the plurality of stages. According to any one of claims 1 to 7, hysteresis is applied by changing the voltage division ratio when the detection target voltage is divided to generate the input voltage according to the output of the inverter. Described voltage detection circuit. A resistance voltage divider circuit to which the detection target voltage is applied to generate the input voltage,
The voltage detection circuit according to claim 8, further comprising a switch for switching between opening and closing between both ends of a resistor included in the resistance voltage dividing circuit according to the output of the inverter. A semiconductor device in which the voltage detection circuit according to any one of claims 1 to 9 is formed of a semiconductor integrated circuit.

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