JP2015142210A - level shift circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a level shift circuit and a semiconductor device capable of making a voltage higher after a level shift while suppressing an increase in a circuit scale.SOLUTION: A level shift circuit includes: a first transistor and a second transistor to the first current end and the back gate of each which a second voltage is applied; a third transistor to the gate of which a first voltage is applied, to the first current end and the back gate of which a second current end of the first transistor and a gate of the second transistor are connected, and to the second current end of which a first line is connected; a fourth transistor to the gate of which the first voltage is applied, to the first current end and the back gate of which a second current end of the second transistor and a gate of the first transistor are connected, and to the second current end of which a second line is connected; a fifth transistor which becomes one state of an on-state and off-state according to an input signal, and applies a ground voltage to the first line in the case of the on-state; and a sixth transistor which becomes the other state of the on-state or off-state according to the input signal, and applies the ground voltage to the second line in the case of the on-state.

Description

  The present invention relates to a level shift circuit formed in a semiconductor device and a semiconductor device.

  Various voltages are applied to word lines of, for example, a NAND flash memory as a nonvolatile semiconductor memory device in order to optimize program characteristics and read characteristics. For example, in a flash memory that stores 8-level or 16-level multilevel data in one memory cell, for example, a data read voltage of 8 volts is applied to the word line. On the other hand, the voltage of the control signal for controlling whether or not to apply such a data read voltage to the word line is, for example, 1.8 to 2 volts, which is lower than the data read voltage.

  In view of this, a NAND flash memory equipped with a cross-coupling type level shift circuit has been proposed in order to control the application of a higher voltage data read voltage by such a low voltage control signal ( For example, see Patent Document 1). In this level shift circuit, an n-channel MOS (Metal Oxide Semiconductor) transistor that is turned on in response to a low voltage input signal (Vin) and sends out a ground potential (VSS), and a ground potential are supplied to the gate. And a p-channel MOS transistor which is turned on and sends out a high voltage data read voltage (VBST). At this time, since a data read voltage (VBST) is applied to the source and back gate of the p-channel MOS transistor, a voltage (VBST-VSS) is applied to the gate insulating film. Therefore, the data read voltage, that is, the voltage after level conversion has to be made lower than the breakdown voltage of the p-channel MOS transistor.

JP 2008-236720 A

  Here, as the data read voltage is increased, the interval between thresholds for determining each of the multi-values is increased, so that the data read accuracy can be increased. However, in the level shift circuit described in Patent Document 1, since the data read voltage needs to be lower than the breakdown voltage of the p-channel MOS transistor as described above, the data read voltage cannot be increased unnecessarily. At this time, if a p-channel MOS transistor having a high withstand voltage is used, the data read voltage can be increased. However, the size of the transistor itself is increased by that amount, resulting in a problem that the entire device becomes larger.

  The present invention has been made to solve such a problem, and an object of the present invention is to provide a level shift circuit and a semiconductor device capable of increasing the voltage after level shift while suppressing an increase in device scale. .

  The level shift circuit according to the present invention converts an input signal having a level corresponding to a first potential into an output signal having a level corresponding to a second potential higher than the first potential, and converts the output signal through a first line. A first and second transistors having the second potential applied to the first current terminal and the back gate, respectively, and the first potential applied to the gate. A third transistor having a first current terminal and a back gate connected to a second current terminal of the first transistor and a gate of the second transistor; a second current terminal connected to the first line; The first potential is applied, the second current terminal of the second transistor and the gate of the first transistor are connected to the first current terminal and the back gate, and the second current terminal is connected to the second current terminal. A fourth transistor to which a line is connected, a fifth transistor that is in one of an on state and an off state according to the input signal, and that applies a ground potential to the first line in the on state; A sixth transistor that enters the other of the on state and the off state in response to the input signal and applies a ground potential to the second line in the on state.

  The semiconductor device according to the present invention converts an input signal having a level corresponding to a first potential into an output signal having a level corresponding to a second potential higher than the first potential, and converts the output signal to a first line. A first and second transistors to which the second potential is applied to the first current terminal and the back gate, respectively, and the first potential is applied to the gate. A third transistor having a first current terminal and a back gate connected to a second current terminal of the first transistor and a gate of the second transistor, and a second current terminal connected to the first line; and a gate; The first potential is applied to the first current terminal and the back gate, and the second current terminal of the second transistor and the gate of the first transistor are connected to the first current terminal and the back gate. A fourth transistor to which a line is connected, a fifth transistor that is in one of an on state and an off state according to the input signal, and that applies a ground potential to the first line in the on state; A level shift circuit having a sixth transistor that is in an on state or an off state according to the input signal and applies a ground potential to the second line in the on state; A first terminal for receiving, a second terminal for receiving the first potential, and a third terminal for receiving the second potential.

  According to the present invention, when an input signal having a level corresponding to the first potential is level-shifted to an output signal having a second potential higher than the first potential, the voltage applied to the gate insulating film of the transistor is changed from the second potential. Can also be lowered. Therefore, since an output signal having a second potential higher than the breakdown voltage of the transistor can be output, the voltage of the second potential after the level shift can be increased without increasing the device scale.

1 is a circuit diagram showing a configuration of a level shift circuit 100 according to the present invention. 3 is a time chart showing an internal operation of the level shift circuit 100. It is a figure which shows an example of the voltage applied to the transistors 1-4. 3 is a circuit diagram showing another example of the level shift circuit 100. FIG. 3 is a circuit diagram showing another example of the level shift circuit 100. FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a circuit diagram showing an example of a level shift circuit 100 formed in a semiconductor device. The level shift circuit 100 generates an input signal Vin having a level of 0 to VDD generated based on a power supply potential VDD of 1.8 to 2.0 volts, for example, higher than the power supply potential VDD, for example, 10 volts. Based on the power supply potential VBST, the signal is converted into an output signal Vout having a level of 0 to VBST.

  As shown in FIG. 1, the level shift circuit 100 includes p-channel MOS transistors 1 to 4, n-channel MOS transistors 5 to 10, and inverters 21 and 22. A power source potential VBST is applied to the source and back gate of the transistor 1, and the source and back gate of the transistor 3, the gate of the transistor 2, and the drain of the transistor 9 are connected to the drain via a line L1. Has been. Further, the drain of the transistor 2, the source and back gate of the transistor 4, and the drain of the transistor 10 are connected to the gate of the transistor 1 through a line N1. The power supply potential VDD is applied to the gate of the transistor 3, and the drain of the transistor 5, the drain of the transistor 7, and the gate of the transistor 10 are connected to the drain via a line L0. The output signal Vout is output via the line L0. A power supply potential VBST is applied to the source and back gate of the transistor 2. A power supply potential VDD is applied to the gate of the transistor 4, and the drain of the transistor 9, the drain of the transistor 6, and the drain of the transistor 8 are connected to the drain of the transistor 4 through a line N 0. A power supply potential VDD is applied to the source and back gate of the transistor 9. A ground potential VSS is applied to the source and back gate of the transistor 5. A power supply potential VBST is applied to the source of the transistor 7, and a ground potential VSS is applied to its back gate. A power supply potential VDD is applied to the source and back gate of the transistor 10. A ground potential VSS is applied to the source and back gate of the transistor 6. A power supply potential VBST is applied to the source of the transistor 8, and a ground potential VSS is applied to its back gate.

  The inverter 21 generates an inverted input signal VBin obtained by inverting the logic level of the input signal Vin based on the power supply potential VDD. That is, when the level of the input signal Vin is the ground potential VSS corresponding to the logic level 0, the inverter 21 converts the input signal Vin into the inverted input signal VBin having the power supply potential VDD corresponding to the logic level 1. On the other hand, when the level of the input signal Vin is the power supply potential VDD corresponding to the logic level 1, the inverter 21 converts this to the inverted input signal VBin having the ground potential VSS corresponding to the logic level 0. The inverter 21 supplies the inverted input signal VBin to the gates of the transistors 5 and 8 and the inverter 22.

  The inverter 22 generates an input signal VCin obtained by inverting the logic level of the inverted input signal VBin based on the power supply potential VDD. That is, when the level of the inverting input signal VBin is the ground potential VSS corresponding to the logic level 0, the inverter 22 converts this to the input signal VCin having the power supply potential VDD corresponding to the logic level 1. On the other hand, when the level of the inverted input signal VBin is the power supply potential VDD corresponding to the logic level 1, the inverter 22 converts this into the input signal VCin having the ground potential VSS corresponding to the logic level 0. The inverter 22 supplies the input signal VCin to the gates of the transistors 6 and 7. As shown in FIG. 1, the semiconductor device in which the level shift circuit is formed receives a first input signal Vin, a power supply potential VDD, and VBST supplied from another functional module or the outside of the semiconductor device, respectively. A terminal P1, a second terminal P2, and a third terminal P3 are formed.

  Hereinafter, the internal operation of the level shift circuit shown in FIG. 1 will be described with reference to the operation time chart of FIG.

  First, when the level of the input signal Vin is the ground potential VSS corresponding to the logic level 0, the inverter 21 converts the inverted input signal VBin having the power supply potential VDD corresponding to the logic level 1 to the gates and inverters of the transistors 5 and 8 respectively. 22 is supplied. The inverter 22 supplies the input signal VCin having the ground potential VSS corresponding to the logic level 0 to the gates of the transistors 6 and 7. Thereby, the transistors 5 and 8 are turned on, while the transistors 6 and 7 are turned off. Since the transistor 5 is turned on, the level of the output signal Vout becomes the ground potential VSS corresponding to the logic level 0. In addition, since the transistor 8 is turned on, the transistor 8 sends a current to the line N0 and raises the voltage level on the line N0. As a result, a voltage exceeding the threshold is applied to the gate of the transistor 9, and the transistor 9 is turned on. At this time, the transistor 9 applies the power supply potential VDD to the source and back gate of the transistor 3 and the gate of the transistor 2 via the line L1. Therefore, the transistor 2 is turned on, and the transistor 2 applies the power supply potential VBST to the gate of the transistor 1 through the line N1. As a result, both the transistors 1 and 3 are turned off. Further, since the level of the output signal Vout is the ground potential VSS, the transistor 10 is turned off. Note that since the transistor 2 is in the on state, the power supply potential VBST is applied to the source and back gate of the transistor 4, and the transistor 4 is turned on. As a result, the power supply potential VBST is stably supplied to the gate of the transistor 9 via the transistors 2 and 4.

  Next, when the level of the input signal Vin is the power supply potential VDD corresponding to the logic level 1, the inverter 21 converts the inverted input signal VBin having the ground potential VSS corresponding to the logic level 0 to the gates of the transistors 5 and 8, And supplied to the inverter 22. The inverter 22 supplies an input signal VCin having a power supply potential VDD corresponding to the logic level 1 to the gates of the transistors 6 and 7. Thereby, the transistors 5 and 8 are turned off, while the transistors 6 and 7 are turned on. Since transistor 7 is turned on, transistor 7 sends current to line L0, raising the voltage level on line L0. Accordingly, a voltage exceeding the threshold is applied to the gate of the transistor 10, and the transistor 10 is turned on. At this time, the transistor 10 applies the power supply potential VDD to the source and back gate of the transistor 4 and the gate of the transistor 1 via the line N1. Accordingly, the transistor 1 is turned on, and the transistor 1 applies the power supply potential VBST to the gate of the transistor 2 through the line L1. As a result, both the transistors 2 and 4 are turned off. Since the transistor 6 is on, the ground potential VSS is applied to the gate of the transistor 9 through the line N0, and the transistor 9 is turned off. Note that since the transistor 1 is in the on state, the power supply potential VBST is applied to the source and back gate of the transistor 3, and the transistor 3 is turned on. As a result, the power supply potential VBST is stably supplied to the gate of the transistor 10 through the transistors 1 and 3, and the output signal Vout having the power supply potential VBST corresponding to the logic level 1 is output through the line L0.

  Here, in the level shift circuit 100 described above, transistors 1 to 4 are provided as MOS transistors that output a power supply potential VBST higher than the power supply potential VDD. The gate insulating film of each of these transistors 1 to 4 includes During the operation shown in FIG. 2, the voltages shown in FIGS. 3A to 3D are applied. 3A shows voltages applied to the respective gates, sources, drains, and back gates when the transistors 1 and 2 are turned off, and FIG. 3B shows voltages applied when the transistors 1 and 2 are turned on. FIG. FIG. 3C shows voltages applied to the respective gates, sources, drains, and back gates when the transistors 3 and 4 are in an off state, and FIG. 3D shows a voltage applied when the transistors 3 and 4 are in an on state. It is.

  As shown in FIG. 3A, the voltage applied to the gate, source, and back gate of the transistors 1 and 2 in the off state is the power supply potential VBST, and the voltage applied to the drain is the power supply potential VDD. For this reason, the voltages between the drain and source of the transistors 1 and 2 in the off state, between the drain and the back gate, and between the gate and the drain are (VBST-VDD), and between the source and the back gate, between the gate and the source, and the gate − The voltage between the back gates is (VBST-VBST). On the other hand, as shown in FIG. 3B, the voltage applied to the gates of the transistors 1 and 2 in the ON state is the power supply potential VDD, and the voltage applied to the source, drain, and back gate is the power supply potential VBST. . Therefore, the gate-drain, gate-source, and gate-back gate voltages of the transistors 1 and 2 in the on state are (VBST-VDD), and the drain-source, drain-back gate, and source- The voltage between the back gates is (VBST-VBST).

  In addition, as shown in FIG. 3C, the voltages applied to the gates, sources, and back gates of the transistors 3 and 4 in the off state are the power supply potential VDD, and the voltages applied to the drains are the ground potential VSS. is there. For this reason, the voltages between the drain and the source of the transistors 3 and 4 in the off state, between the drain and the back gate, and between the gate and the drain are (VDD−VSS). The voltage between the back gates is (VDD−VDD). On the other hand, as shown in FIG. 3D, the voltage applied to the gates of the transistors 3 and 4 in the on state is the power supply potential VDD, and the voltages applied to the source, drain, and back gate are the power supply potential VBST. is there. Therefore, the gate-drain, gate-source, and gate-back gate voltages of the transistors 3 and 4 are (VBST-VDD), and the drain-source, drain-back gate, and source-back gate. The voltage of is (VBST-VBST).

  As described above, a voltage exceeding (VBST-VDD) is not applied to the gate insulating films of the transistors 1 to 4 which are p-channel MOS transistors through the operation shown in FIG. That is, since the voltage applied to the gate insulating film of each of the transistors 1 to 4 is lower than the power supply potential VBST, the output signal Vout having a voltage higher than the withstand voltage of the transistors 1 to 4 can be output. Therefore, it is possible to increase the voltage (VBST) after the level shift without using high breakdown voltage transistors having a large size as the transistors 1 to 4, that is, without increasing the device scale.

  For example, when the level shift circuit 100 shown in FIG. 1 is employed as a level shift circuit for generating a data read voltage in a flash memory, the maximum value that can be taken as the data read voltage (corresponding to VBST) is the gate insulating film of the transistors 1 to 4. Is no longer limited by the maximum voltage that can be applied to the so-called withstand voltage. Here, when the level of the input signal Vin based on the power supply potential VDD is 2 volts and the withstand voltage of the transistor is 8 volts, for example, the data read voltage is limited by the withstand voltage of the transistor, that is, it can be taken as the data read voltage. When the maximum value is equal to the breakdown voltage, the maximum value that can be handled as the data read voltage is 8 volts. On the other hand, in the level shift circuit 100 shown in FIG. 1, since the maximum voltage that can be applied to the gate insulating film of the transistor is (VBST-VDD), the maximum data read voltage is (8 + 2) volts, that is, the data read voltage of 10 volts. Can be handled. Therefore, the level shift circuit 100 shown in FIG. 1 handles a higher data read voltage than the conventional level shift circuit in which the maximum value that can be taken as the data read voltage is limited by the breakdown voltage of the transistor. Is possible.

  In the configuration shown in FIG. 1, the power supply potential VDD higher than the ground potential VSS is fixedly applied to the gates of the transistors 3 and 4 which are p-channel MOS transistors. Thus, the transistors 3 and 4 are immediately switched from the off state to the on state in accordance with the switching of the logic level of the input signal Vin. Therefore, since the level of the output signal Vout quickly shifts from the low (or high) level state to the high (or low) level state, the output response according to the level transition of the input signal is speeded up. Is possible.

  Further, in the configuration shown in FIG. 1, by providing the n-channel MOS transistors 7 and 8, the output response is further speeded up. That is, the transistor 7 (8) cannot output the power supply potential VBST applied to the source from the drain, but the power supply potential VDD applied to the gate in response to the input signal Vin is higher than the threshold potential. Since it is large, it is turned on, and current is sent to the line L0 (N0). As a result, the voltage level on the line L0 (N0) rises. Therefore, when the transistors 1 and 3 (2 and 4) are turned on, the level on the line L0 (N0) immediately reaches the power supply potential VBST. It becomes possible to make it.

  In the embodiment shown in FIG. 1, in order to set the potential of the lines L1 and N1 to the power supply potential VDD when the transistors 3 and 4 are in the off state, the transistor 9 that is on / off controlled based on the voltages on the lines N0 and L0. However, the power supply potential VDD may be always applied to these lines L1 and N1.

  FIG. 4 is a circuit diagram showing a modification of the level shift circuit 100 made in view of this point. In the configuration shown in FIG. 4, transistors 11 and 12 are employed instead of the transistors 9 and 10 shown in FIG. 1, and the other configurations are the same as those shown in FIG.

  The transistors 11 and 12 have their gates, sources, and back gates connected in common, and a power supply potential VDD is applied to each of them. The drain of the transistor 11 is connected to the drain of the transistor 1, the source and back gate of the transistor 3, and the gate of the transistor 2 through a line L1. The drain of the transistor 12 is connected to the drain of the transistor 2, the source and back gate of the transistor 4, and the gate of the transistor 1 through a line N 1. That is, in the configuration shown in FIG. 4, the power supply potential VDD is supplied to the lines (L1, N1) via the diode-connected transistors (11, 12). Therefore, when the transistors 1 to 4 are in the off state, the source and back gate of each of the transistors 3 and 4 and the drain of each of the transistors 1 and 2 have a potential equal to or higher than the power supply potential VDD−Vthn (Vthn: NMOS threshold voltage). Will be applied. On the other hand, when the transistors 1 and 2 are turned on, a potential equal to or higher than the power supply potential VDD-Vthn is applied to each gate.

  Therefore, in the configuration shown in FIG. 4 as well, the voltage exceeding (VBST− (VDD−Vthn)) is not applied to the gate insulating films of the transistors 3 and 4 as in the configuration shown in FIG. It becomes possible to output the output signal Vout having a voltage higher than the withstand voltage. Therefore, it is possible to increase the voltage (VBST) after the level shift without using high breakdown voltage transistors having a large size as the transistors 1 to 4, that is, without increasing the device scale.

  In the configuration shown in FIG. 1 or 4, the transistors 9 and 10 or the transistors 11 and 12 are provided in order to set the potentials of the lines L1 and N1 to the power supply potential VDD or the power supply potential VDD−Vthn. These transistors 9 and 10 or transistors 11 and 12 may be omitted.

  FIG. 5 is a circuit diagram showing another example of the modification of the level shift circuit made in view of the above point. The configuration shown in FIG. 5 is the same as the configuration shown in FIGS. 1 and 4 except for the point that the transistors 9 and 10 shown in FIG. 1 or the transistors 11 and 12 shown in FIG. 4 are omitted. is there.

  In the configuration shown in FIG. 5, similarly to the configuration shown in FIG. 1, a voltage exceeding (VBST−VDD) is not applied to the gate insulating films of the transistors 3 and 4. It is possible to output the output signal Vout. Therefore, it is possible to increase the voltage (VBST) after the level shift without using high breakdown voltage transistors having a large size as the transistors 1 to 4, that is, without increasing the device scale.

  In the above embodiment, transistors 1 to 4 are p-channel transistors and transistors 5 to 12 are n-channel transistors as MOS transistors having a gate as a voltage control terminal and a source and a drain as first and second current terminals. It is said. However, whether each transistor is a p-channel type or an n-channel type is not limited to the above embodiment.

  In short, the level shift circuit according to the present invention outputs an input signal (Vin) having a level corresponding to the first potential (VDD) to an output signal having a level corresponding to the second potential (VBST) higher than the first potential. When converting to (Vout) and outputting this via the first line (L0), the following first to sixth transistors can increase the second potential after the level shift without increasing the device scale. It is a thing. That is, the second potential is applied to the first current terminal (source or drain) and the back gate of each of the first transistor (1) and the second transistor (2). A first potential is applied to the gate of the third transistor (3), and the second current terminal (drain or source) of the first transistor and the gate of the second transistor are connected to the first current terminal and the back gate. It is connected. Further, the first line is connected to the second current terminal of the third transistor. The first potential is applied to the gate of the fourth transistor (4), and the second current terminal of the second transistor and the gate of the first transistor are connected to the first current terminal and the back gate. . Further, the second line (N0) is connected to the second current terminal of the fourth transistor. The fifth transistor (5) is in one of an on state and an off state in accordance with the input signal, and applies the ground potential to the first line when in the on state. The sixth transistor (6) enters the other one of the on state and the off state according to the input signal, and applies the ground potential to the second line when it is in the on state.

  Further, in the level shift circuit according to the present invention, the following seventh transistor (7) and eighth transistor (8) are provided to speed up the output response according to the level transition of the input signal. That is, the seventh transistor (7) is in the other of the on state and the off state in response to the input signal (Vin), and when it is in the on state, it sends a current to the first line (L0), The voltage on this first line is raised. The eighth transistor (8) is in one of an on state and an off state in accordance with the input signal. When the eighth transistor (8) is in the on state, the second transistor (8) sends a current to the second line (N0). Increase the voltage on the line.

  Furthermore, in the level shift circuit according to the present invention, by providing the ninth transistor (9) and the tenth transistor (10), when the third transistor (3) or the fourth transistor (4) is in the OFF state, Alternatively, the first current terminal and the back gate of the fourth transistor are set to the first potential (VDD).

1 to 12 Transistors 21 and 22 Inverter 100 Level shift circuit

Claims (7)

A level shift circuit that converts an input signal having a level corresponding to a first potential into an output signal having a level corresponding to a second potential higher than the first potential, and outputs the output signal via a first line. ,
First and second transistors having the second potential applied to respective first current ends and back gates;
The first potential is applied to the gate, the second current terminal of the first transistor and the gate of the second transistor are connected to the first current terminal and the back gate, and the first current terminal is connected to the first current terminal and the back gate. A third transistor to which the line is connected;
The first potential is applied to the gate, the second current end of the second transistor and the gate of the first transistor are connected to the first current end and the back gate, and the second line is connected to the second current end. A fourth transistor to which
A fifth transistor that is in one of an on state and an off state in response to the input signal and applies a ground potential to the first line in the on state;
A level shift circuit comprising: a sixth transistor that is in an on state or an off state according to the input signal and applies a ground potential to the second line in the on state. A seventh transistor that is in an on state or an off state in response to the input signal and that sends a current to the first line in the on state;
2. The eighth transistor according to claim 1, further comprising: an eighth transistor that is in one of an on state and an off state in response to the input signal and that sends current to the second line when the signal is on. Level shift circuit. The first line is connected to a first current terminal of the seventh transistor, and the second potential is applied to a second current terminal of the seventh transistor,
3. The second current is connected to the first current terminal of the eighth transistor, and the second potential is applied to the second current terminal of the eighth transistor. Level shift circuit. A ninth transistor that is turned on when the third transistor is turned off and applies the first potential to the gate of the second transistor, the first current terminal and the back gate of the third transistor;
A tenth transistor that turns on when the fourth transistor is off and applies the first potential to the gate of the first transistor and to the first current terminal and the back gate of the fourth transistor; The level shift circuit according to claim 1, wherein the level shift circuit is included. The gate of the ninth transistor is connected to the second line;
5. The level shift circuit according to claim 4, wherein a gate of the tenth transistor is connected to the first line. The first potential is applied to the first current terminal and the gate, and the second current terminal is connected to the gate of the second transistor and the first current terminal and the back gate of the third transistor. A transistor,
The first potential is applied to the first current terminal and the gate, and the second current terminal is connected to the gate of the first transistor and the first current terminal and the back gate of the fourth transistor. The level shift circuit according to claim 1, further comprising a transistor. The level shift circuit according to any one of claims 1 to 6,
A first terminal for receiving the input signal;
A second terminal for receiving the first potential;
And a third terminal for receiving the second potential.

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