KR20150068810A - Adjustable delay inverter - Google Patents

Adjustable delay inverter Download PDF

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Publication number
KR20150068810A
KR20150068810A KR1020130154909A KR20130154909A KR20150068810A KR 20150068810 A KR20150068810 A KR 20150068810A KR 1020130154909 A KR1020130154909 A KR 1020130154909A KR 20130154909 A KR20130154909 A KR 20130154909A KR 20150068810 A KR20150068810 A KR 20150068810A
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South Korea
Prior art keywords
inverter circuit
delay
series
delay unit
output terminal
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KR1020130154909A
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Korean (ko)
Inventor
김태환
주덕진
박기태
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서울대학교산학협력단
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Priority to KR1020130154909A priority Critical patent/KR20150068810A/en
Publication of KR20150068810A publication Critical patent/KR20150068810A/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

A delay time adjustable inverter according to the present invention includes a first inverter circuit connected to an input terminal and receiving an input signal, an internal inverter circuit receiving the input signal applied to the input terminal of the first inverter circuit, And a switch section for driving the internal inverter circuit based on a switch signal, a second inverter circuit connected in series with an output terminal of the first delay section, a second inverter circuit connected to the output terminal of the second inverter circuit, A third inverter circuit connected in series between the output terminal of the second delay unit and the output terminal, and a third inverter circuit connected in series between the output terminal and the output terminal of the second delay unit, The first delay unit and the second delay unit are connected to each other, Comprising: a delay control section that, the first delay section and the second delay unit to delay by a predetermined time respectively preset the input signal.

Description

ADJUSTABLE DELAY INVERTER [0002]

The present invention relates to a delay time adjustable inverter.

FIGS. 1A and 1B illustrate an inverter-based delay time adjustment buffer according to the related art.

The inverter-based delay buffer (Adjustable Delay Buffer, ADB) can control the delay time to a large extent compared to the circuit area. The delay time adjustment buffer shown in FIG. 1A can turn on and off the switched inverter by using a switch controlled by the SEL signal at the input terminal.

FIG. 1B is a circuit diagram briefly showing the circuit shown in FIG. 1A in the form of an inverter, which is composed of an inverter circuit connected to an input stage, a delay circuit connected to the inverter circuit, and an inverter circuit connected to the output stage. At this time, the delay circuit is connected to the delay time control unit, receives the switch signal according to the control bit, and turns on and off the inverter. As described above, the inverter-based delay time adjustment buffer shown in FIGS. 1A and 1B can adjust the delay time by varying the driving strength.

2A and 2B illustrate a capacitor-based delay time adjustment buffer according to the related art.

The capacitor-based delay time adjustment buffer can control the delay time with a finer width than the circuit area. That is, the delay time can be adjusted by adjusting a capacitor between an input terminal and an output terminal through a switch.

In this way, there is an inverter-based buffer or capacitor-based buffer capable of adjusting the delay time. However, since the line width of the circuit and the minimum size of the transistor are set to 28 nm and 45 nm for each semiconductor process, The delay time adjustment buffer alone can not produce a small delay time. In addition, the capacitor-based delay time adjustment buffer can produce a smaller delay time than the inverter-based delay time adjustment buffer designed using the minimum size transistor. However, in order to achieve a large delay time using only the capacitor- There is a problem that the size of the capacitor becomes too large because the size of the capacitor is large.

In this connection, Korean Patent Laid-Open Publication No. 1991-0021019 (entitled "Delay Circuit") discloses a technique of connecting a source of a resistance MOS transistor to a power source and fixing the potential, thereby obtaining a delay Circuit.

Korean Patent Laid-Open Publication No. 2005-0105561 discloses a semiconductor device having a CMOS output buffer circuit that simultaneously turns off the output driver section during a short delay time to remove the through current of the output driver circuit. Buffer circuit.

However, the above prior arts have a problem in that the delay time is not easily controlled because the inverter circuit connected to the input stage delays the signal using only the switching element, and does not have a capacitor-based circuit. Therefore, it is necessary to develop a technology capable of adjusting the delay time from the input end to the output end simultaneously with a large width and a small width.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide an inverter-based delay time adjustment buffer capable of adjusting a delay time from an input stage to an output stage, It is an object of the present invention to provide an inverter capable of adjusting a delay time by combining an adjustable capacitor based delay time adjustment buffer and sharing an inverter circuit.

According to a first aspect of the present invention, there is provided a delay time adjustable inverter including a first inverter circuit connected to an input terminal and receiving an input signal, a second inverter circuit connected to an input terminal of the first inverter circuit, An internal inverter circuit receiving the input signal and a switch section connected in series to the internal inverter circuit and driving the internal inverter circuit based on a switch signal; A second inverter circuit connected in series, a capacitor connected in series between the output terminal of the second inverter circuit and the ground, and a switching element, and at least one second delay unit for driving the switching element based on the switch signal, A second inverter connected in series between the output terminal and the output terminal of the second delay unit, And a delay time controller for generating the switch signal and controlling the first delay unit and the second delay unit, wherein the first delay unit and the second delay unit delay the input signal by a predetermined time .

According to a second aspect of the present invention, there is provided a delay time adjustable inverter including a first inverter circuit connected to an input terminal and receiving an input signal, a capacitor connected in series between an output terminal of the first inverter circuit and the ground, A second inverter circuit connected in series with an output terminal of the first delay unit, a second inverter circuit connected to the input terminal of the second inverter circuit, And a switch unit connected in series to the internal inverter circuit and driving the internal inverter circuit based on a switch signal, and at least one second delay unit connected in series between the output terminal and the output terminal of the second delay unit, A third inverter circuit to be connected and the switch signal to generate the first delay And a second delay comprising: a delay control unit for controlling parts of the first delay section and the second delay unit to delay by a predetermined time respectively preset the input signal.

According to an embodiment of the present invention, an inverter-based delay time adjustment buffer having a large delay time adjustment width and a capacitor based delay time adjustment buffer having a small delay time adjustment width are combined to use a conventional delay time adjustment buffer It is easier to adjust the delay time.

In addition, it can be regarded as one circuit from the initial stage of design, and it is possible to reduce the overhead of implementing the circuit, and to easily locate the peripheral power supply source and the circuit.

In addition, the size of the circuit can be reduced by using only one type of delay adjustment buffer.

FIGS. 1A and 1B illustrate an inverter-based delay time adjustment buffer according to the related art.
2A and 2B illustrate a capacitor-based delay time adjustment buffer according to the related art.
3 is a block diagram of a delay time adjusting inverter according to a first embodiment of the present invention.
4 and 5 are circuit diagrams of a delay time adjusting inverter according to the first embodiment of the present invention.
6 is a block diagram of a delay time adjusting inverter according to a second embodiment of the present invention.
7 and 8 are circuit diagrams of a delay time adjusting inverter according to a second embodiment of the present invention.
9 is a diagram for explaining signal transmission time in the delay time adjusting inverter according to the first and second embodiments.
Figs. 10A and 10B are graphs showing the results of Fig. 9. Fig.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between . Also, when an element is referred to as "comprising ", it means that it can include other elements as well, without departing from the other elements unless specifically stated otherwise. The word " step (or step) "or" step "used to the extent that it is used throughout the specification does not mean" step for.

FIG. 3 is a block diagram of a delay time adjusting inverter 100 according to the first embodiment of the present invention, and FIGS. 4 and 5 are circuit diagrams of a delay time adjusting inverter 100 according to the first embodiment of the present invention.

The delay time adjusting inverter 100 according to an embodiment of the present invention includes a first inverter circuit 110, a first delay unit 120, a second inverter circuit 130, a second delay unit 140, An inverter circuit 150 and a delay time controller 160.

First, the connection relation of the delay time controlling inverter 100 according to the present invention will be described.

The first inverter circuit 110 is connected between the input terminal A and the first delay unit 120 and the second inverter circuit 130 is connected between the output terminal of the first delay unit 120 and the output terminal of the second delay unit 140 As shown in Fig. Specifically, the output terminal of the first delay unit 120 may be connected in series with the output terminal of the first inverter circuit 110, and may be connected in series with the input terminal of the second inverter circuit 130. The input terminal of the second delay unit 140 is connected in series with the output terminal of the second inverter circuit 130 and can be connected in series with the input terminal of the second inverter circuit 130.

The delay time control inverter 100 according to the present invention includes the first to third inverter circuits 110 to 130 and the internal inverter circuit 121 included in the first delay unit 120, The same inverter circuit inverts each input signal. The first delay unit 120 and the second delay unit 140 delay the input signal by a predetermined time. In this case, the first to third inverter circuits 110, 130 and 150 and the internal inverter circuit 121 of the first delay unit 120 may be CMOS inverters each including a PMOS transistor and an NMOS transistor connected in series.

The first inverter circuit 110 is connected to an input terminal and receives an input signal. Since the first inverter circuit 110 inverts the input signal, for example, when a high level signal is input, a low level signal is output to the output terminal.

In addition to the first inverter circuit 110, the second to third inverter circuits 130 and 150 can also reverse the input signal. The operation of the first to third inverter circuits 110, 130 and 150 will now be described.

When the input voltage (A) is input to the inverter circuit at a high level, the gate of the NMOS transistor of the inverter circuit is turned on. As a result, the output voltage becomes the potential of the ground voltage, that is, 0V. At this time, the voltage between the gate and the source of the PMOS transistor becomes 0V and the current can not flow.

On the other hand, when the input voltage is input at a low level, the PMOS transistor of the inverter circuit is turned on. Thus, the output voltage becomes the potential of the power supply voltage, that is, VDD. At this time, since the gate voltage of the NMOS transistor does not exceed the threshold voltage and the NMOS transistor is turned off, no current flows.

The delay time control inverter 100 according to the present invention includes three inverter circuits as described above. Accordingly, the input signal to the input terminal is inverted three times through the inverter circuit, so that the input signal of the input terminal and the inverted signal Is output.

The first delay unit 120 includes an internal inverter circuit 121 and a switch unit 123. The internal inverter circuit 121 receives an input signal applied from the input terminal of the first inverter circuit 110. At this time, the internal inverter circuit 121 may include a PMOS transistor and an NMOS transistor which are connected in series to each other, to which an input signal is applied.

The switch unit 123 is connected in series to the internal inverter circuit 121 and drives the internal inverter circuit 121 based on the switch signal generated by the delay time control unit 160 to be described below. At this time, the switch unit 123 may include an NMOS transistor receiving a switch signal and a PMOS transistor receiving a signal whose switch signal is inverted.

Specifically, the PMOS transistor of the switch unit 123 is serially connected between the PMOS transistor of the internal inverter circuit 121 and the power supply voltage to receive the switch signal as a gate, and the NMOS transistor is connected to the NMOS transistor of the internal inverter circuit 121 And the inverted switch signal can be received by the gate in series between the ground voltage. The first delay unit 120 receives the switch signal through the switch unit 123 and can adjust the delay time to a large width of, for example, about 30 ps.

Meanwhile, one or more of the first delay units 120 may be spaced apart and arranged in parallel. In this case, since the first delay units 120 are arranged in parallel, the signal input through the input terminal of the first delay unit 120 is not affected by the polarity irrespective of the number of the first delay units 120 .

The second inverter circuit 130 is connected in series with the output terminal of the first delay unit 120 and is connected in series with the input terminal of the second delay unit 140. The second inverter circuit 130 inverts the input signal in the same manner as the first inverter circuit 110 and outputs the inverted signal.

The second delay unit 140 may include a capacitor 141 and a switching device 143 connected in series between the output terminal of the second inverter circuit 130 and the ground, have. At this time, the second delay unit 140 drives the switching element 143 based on the switch signal generated by the delay time controller 160. Meanwhile, the switching element 143 may be an NMOS transistor. The NMOS transistor connects the capacitor 141 to the output terminal of the second inverter circuit 130 so that the delay time can be adjusted to a small width, for example, about 5 ps based on the switch signal.

The third inverter circuit 150 is connected in series between the output terminal and the output terminal of the second delay unit 140. The third inverter circuit 140 inverts the input signal in the same manner as the first and second inverter circuits 110 and 130 and outputs the inverted signal to an output terminal.

The delay time controller 160 generates a switch signal to control the first delay unit 120 and the second delay unit 140. More specifically, the delay time controller 160 generates a switch signal for controlling the switch unit 123 of the first delay unit 120 and controls the switch unit 143 of the second delay unit 140 A switch signal can be generated. At this time, the delay time controller 160 may generate a switch signal for controlling the first delay unit 120, and then generate a switch signal for controlling the second delay unit 140. This is achieved by first adjusting the first delay unit 120 composed of inverter banks whose delay time is adjusted to a large extent to obtain a delay time close to a desired delay time and then adjusting the second delay unit 140 composed of the capacitor bank This is to reduce errors. However, the sequence of generating the switch signal for controlling the first and second delay units 120 and 140 is not limited thereto. After generating the switch signal for controlling the second delay unit 140, the first delay unit 120 may be generated.

The delay time adjustment inverter 100 according to the present invention combines an inverter-based delay time adjustment buffer having a large delay time adjustment width and a capacitor-based delay time adjustment buffer having a small delay time adjustment width, There is an advantage that delay time adjustment is easier than using. In addition, it can be regarded as one circuit from the initial stage of design, and it is possible to reduce the overhead of implementing the circuit, and to easily locate the peripheral power supply source and the circuit. In addition, there is an advantage in that the size of the circuit can be reduced compared to using only one kind of delay time adjustment buffer.

Meanwhile, the delay time controlling inverter 100 according to the present invention has a structure in which one inverter circuit is omitted, compared with the delay time adjusting buffer circuits shown in FIG. 1A and FIG. 2A connected in series, The polarity can be made the same as the inverter. In addition, distortion of the signal may be prevented through the second inverter circuit 130.

FIG. 6 is a block diagram of a delay time control inverter 200 according to a second embodiment of the present invention, and FIGS. 7 and 8 are circuit diagrams of a delay time control inverter 200 according to the second embodiment of the present invention.

The delay time control inverter 200 according to the second embodiment of the present invention includes a first inverter circuit 210, a first delay unit 220, a second inverter circuit 230, a second delay unit 240, A three-inverter circuit 250 and a delay time controller 260. In this case, the delay time adjusting inverter 200 according to the second embodiment differs from the first embodiment in that the position where the first delay unit 120 and the second delay unit 140 of the delay time adjusting inverter 100 according to the first embodiment are disposed They are opposite to each other.

First, the connection relation of the delay time controlling inverter 200 according to the present invention will be described as follows.

The first inverter circuit 210 is connected between the input terminal A and the first delay unit 220 and the second inverter circuit 230 is connected between the output terminal of the first delay unit 220 and the second delay unit 240 As shown in Fig. The third inverter circuit 250 is connected between the output terminal and the output terminal Z of the second delay unit 240. In addition, the input terminal of the first delay unit 220 may be connected in series with the output terminal of the first inverter circuit 210 and may be connected in series with the input terminal of the second inverter circuit 230. The output terminal of the second delay unit 240 is connected in series with the output terminal of the second inverter circuit 230 and can be connected in series with the input terminal of the third inverter circuit 250.

The first to third inverters 210, 230 and 250 of the delay time adjusting inverter 200 according to the present invention invert the input signal. The internal inverter 241 included in the first to third inverter circuits 210, 230, and 250 and the second delay unit 240 described below includes a CMOS inverter including PMOS transistors and NMOS transistors connected in series, Lt; / RTI > The operation of the inverter circuit has been described in detail with reference to FIG. 3 to FIG. 5, and will not be described below.

The first inverter circuit 210 is connected to the input terminal of the first delay unit 220 and receives the input signal. The first inverter circuit 210 inverts the input signal and transmits the inverted input signal to the input terminal of the first delay unit 220.

One or more of the first delay units 220 may be spaced apart and arranged in parallel. The first delay unit 220 includes a capacitor 221 and a switching element 223 connected in series between the output terminal of the first inverter circuit 210 and the ground. At this time, the switching element 223 drives the switching element 223 based on the switch signal generated by the delay time control unit 260, which will be described below. On the other hand, the switching element 223 may be an NMOS transistor. The NMOS transistor can adjust the delay time to a small width by connecting the capacitor 221 to the output terminal of the first inverter circuit 210 based on the switch signal.

The second inverter circuit 230 is connected to the output terminal of the first delay unit 220 and is connected to the input terminal of the second delay unit 240. The second inverter circuit 230 receives the output signal of the first delay unit 220, And then transmits it to the second delay unit 240. A signal having the same polarity as that of the signal input at the input terminal through the second delay unit 240 is output from the output terminal of the second delay unit 240.

The second delay unit 240 may be disposed in parallel with at least one of the first delay unit 240 and the second delay unit 240. The second delay unit 240 may include an internal inverter circuit 241 and an internal inverter circuit And a switch unit 243 connected in series with the switch circuit 241 for driving the internal inverter circuit 241 based on the switch signal.

The switch unit 243 may include an NMOS transistor receiving the switch signal and a PMOS transistor receiving the inverted signal of the switch signal. Specifically, the PMOS transistor of the switch unit 223 is serially connected between the PMOS transistor of the internal inverter circuit 241 and the power supply voltage to receive the switch signal as a gate, and the NMOS transistor is connected to the NMOS transistor of the internal inverter circuit 241 and the ground And the inverted switch signal can be received by the gate in series between the voltages.

Meanwhile, one or more of the second delay units 240 may be spaced apart and arranged in parallel. In this case, since the second delay units 240 are arranged in parallel, the signal input through the input terminal of the second delay unit 240 is not affected by the polarity irrespective of the number of the second delay units 240 .

The third inverter circuit 250 is connected in series between the output terminal and the output terminal of the second delay unit 240. By passing through the third inverter circuit 250, the polarity of the signal is inverted from that of the input signal of the input terminal, and is output.

The delay time controller 260 generates a switch signal for controlling the first delay unit 220 and the second delay unit 240. More specifically, the delay time controller 260 generates a switch signal for controlling the switching element 223 of the first delay unit 220 and controls the switch unit 243 of the second delay unit 240 And generates a switch signal. The first delay unit 220 and the second delay unit 240 delay the input signal by a predetermined time based on the switch signal generated by the delay time control unit 260, respectively.

Meanwhile, the delay time controller 260 may generate a switch signal for controlling the second delay unit 240, and then generate a switch signal for controlling the first delay unit 220. The second delay unit 240 includes a first delay unit 220 and a second delay unit 240. The second delay unit 240 includes an inverter bank having a large delay time. This is to reduce errors. However, the sequence of generating the switch signal for controlling the first and second delay units 220 and 240 is not limited thereto. After generating the switch signal for controlling the first delay unit 220, the second delay unit 240 may be generated.

Hereinafter, test results of the first and second embodiments according to the present invention will be described with reference to FIGS. 9 to 10B.

FIG. 9 is a view for explaining signal transmission time in the delay time adjusting inverter according to the first and second embodiments, and FIGS. 10A and 10B are graphs showing the results of FIG.

9A and 9B are tables showing signal propagation times from the input terminal A to the output terminal Z in the delay time adjusting inverter according to the first embodiment and the second embodiment, respectively. The specific signal transfer time depends on the size of the capacitor of the capacitor bank and the internal inverter circuit associated with the switch part. FIG. 9 shows a result of a circuit designed using a small inverter and a capacitor, and the propagation delay is not wide. However, according to the result of the second embodiment, the inverter portion and the capacitor portion are crossed with each other. When the number of the inverters is four, the propagation delay time is not continuously increased according to the number of the turned- It can be confirmed that it decreases. On the other hand, it can be confirmed that such a phenomenon does not occur in the delay time adjusting inverter according to the first embodiment.

10A and 10B, it can be seen that the delay time of the delay time adjusting inverter according to the first embodiment is continuously increased as the number of the turned-on capacitors increases. However, in the delay time adjusting inverter according to the second embodiment, It can be seen that the form of the graph indicating the time is uneven.

It will be understood by those skilled in the art that the foregoing description of the present invention is for illustrative purposes only and that those of ordinary skill in the art can readily understand that various changes and modifications may be made without departing from the spirit or essential characteristics of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100, 200: delay time adjusting inverter 110, 210: first inverter circuit
120, 220: first delay unit 130, 230: second inverter circuit
140, 240: second delay unit 150, 250: third inverter circuit
160 and 260: delay time control section

Claims (10)

1. An inverter capable of adjusting a delay time,
A first inverter circuit connected to an input terminal and receiving an input signal,
An internal inverter circuit receiving the input signal applied to an input terminal of the first inverter circuit and a switch section connected in series with the internal inverter circuit and driving the internal inverter circuit based on a switch signal, ,
A second inverter circuit connected in series with the output terminal of the first delay unit,
A capacitor and a switching element connected in series between the output terminal of the second inverter circuit and the ground and one or more second delay units for driving the switching device based on the switch signal,
A third inverter circuit connected in series between the output terminal and the output terminal of the second delay unit,
And a delay time controller for generating the switch signal to control the first delay unit and the second delay unit,
Wherein the first delay unit and the second delay unit delay the input signal by a predetermined time, respectively. The method according to claim 1,
Wherein the internal inverter circuit includes a PMOS transistor and an NMOS transistor which are connected in series to each other and receive the input signal,
The switch unit includes a PMOS transistor connected in series between a PMOS transistor of the internal inverter circuit and a power supply voltage and receiving a switch signal as a gate, and a PMOS transistor connected in series between the NMOS transistor of the internal inverter circuit and a ground voltage, A delay time adjustable inverter comprising an NMOS transistor. The method according to claim 1,
Wherein the at least one first delay unit and the at least one second delay unit are spaced apart and disposed in parallel, respectively. The method according to claim 1,
Wherein the delay time control unit generates a switch signal for controlling the first delay unit and then generates a switch signal for controlling the second delay unit. The method according to claim 1,
The output terminal of the first delay unit is connected in series with the output terminal of the first inverter circuit, and the output terminal of the first delay unit is connected in series with the input terminal of the second inverter circuit,
Wherein the input terminal of the second delay unit is connected in series with the output terminal of the second inverter circuit and is connected in series with the input terminal of the second inverter circuit. 1. An inverter capable of adjusting a delay time,
A first inverter circuit connected to an input terminal and receiving an input signal,
A capacitor and a switching element connected in series between the output terminal of the first inverter circuit and the ground and one or more first delay units for driving the switching device based on a switch signal,
A second inverter circuit connected in series with the output terminal of the first delay unit,
An internal inverter circuit receiving the input signal applied to the input terminal of the second inverter circuit and a switch section connected in series with the internal inverter circuit and driving the internal inverter circuit based on the switch signal, ,
A third inverter circuit connected in series between the output terminal and the output terminal of the second delay unit,
And a delay time controller for generating the switch signal to control the first delay unit and the second delay unit,
Wherein the first delay unit and the second delay unit delay the input signal by a predetermined time, respectively. The method according to claim 6,
Wherein the internal inverter circuit includes a PMOS transistor and an NMOS transistor which are connected in series to each other and receive the input signal,
The switch unit includes a PMOS transistor connected in series between a PMOS transistor of the internal inverter circuit and a power supply voltage and receiving a switch signal as a gate, and a PMOS transistor connected in series between the NMOS transistor of the internal inverter circuit and a ground voltage, A delay time adjustable inverter comprising an NMOS transistor. The method according to claim 6,
Wherein the switch unit includes an NMOS transistor receiving the switch signal and a PMOS transistor receiving the inverted signal of the switch signal. The method according to claim 6,
Wherein the delay time control unit generates a switch signal for controlling the second delay unit and then generates a switch signal for controlling the first delay unit. The method according to claim 6,
Wherein an input terminal of the first delay unit is connected in series with an output terminal of the first inverter circuit and is connected in series with an input terminal of the second inverter circuit,
And an output terminal of the second delay unit is connected in series with an output terminal of the second inverter circuit and is connected in series with an input terminal of the third inverter circuit.
KR1020130154909A 2013-12-12 2013-12-12 Adjustable delay inverter KR20150068810A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022116416A1 (en) * 2020-12-01 2022-06-09 深圳市紫光同创电子有限公司 Schmitt trigger

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022116416A1 (en) * 2020-12-01 2022-06-09 深圳市紫光同创电子有限公司 Schmitt trigger

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