KR100695416B1 - Cmos output driving circuit - Google Patents

Abstract

The present invention is to provide a CMOS output drive circuit that can reduce the current consumption by eliminating the direct current pass, and to adjust the slope of the output voltage, the present invention for this purpose, in the CMOS output drive circuit, ; First and second pull-up transistors connected in series between a power supply voltage terminal and the output terminal, and first and second pull-down transistors connected in series between the output terminal and the ground terminal, and outputting a signal having a slope varying according to an input; Is a natural number) output driver; Two unit inverters having outputs inverted by two identical input signals, respectively, are connected in parallel between a power supply voltage terminal and a ground terminal, and the resistance ratios of the respective unit elements constituting the unit inverters are different from each other. N inverting delay units for outputting two signals having a predetermined time difference respectively controlling the output driver; And a controller configured to control the unit inverter by outputting a signal obtained by adding or subtracting a threshold voltage to the inverted value of the input signal.

Output drive circuit, direct current pass, resistance ratio, pull up and pull down.

Description

CMOS output driving circuit {CMOS OUTPUT DRIVING CIRCUIT}             

1 shows a conventional output drive circuit generally used.

2 is a CMOS output driving circuit diagram according to an embodiment of the present invention.

3 is a timing diagram of the output driving circuit of FIG. 2 in accordance with an embodiment of the present invention.

* Description of the main parts of the drawing

21: inverter

22: control unit

23-1 to 23-n: Reverse delay part

23a, 23b: unit inverter

24-1 to 24-n: output driver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor circuits, and more particularly to an output drive circuit capable of adjusting the slope of an output voltage.

Recently, as semiconductor circuits become more complicated and chip sizes increase, more circuits are simultaneously switched inside the chip, resulting in a sudden change in current, resulting in noise and current consumption.

In addition, when the waveform of the output signal changes abruptly, a problem regarding the stabilization time of the output occurs.

FIG. 1 is a diagram illustrating a conventional output driving circuit which is generally used, and includes two CMOS inverters 11 and 12 each comprising a PMOS transistor and an NMOS transistor that pull up or pull down an output stage (hereinafter referred to as OUT), respectively. It is composed of

The conventional output driving circuit shown in FIG. 1 changes the voltage value of OUT0 from the power supply voltage level (VDD, hereinafter referred to as 'high') to the ground voltage level (VSS, hereinafter referred to as 'low'). The required current is taken directly from the power line. Therefore, a rapid current change occurs during switching by directly bringing the charge required for the voltage of OUT from the power line, and a plurality of inverters are used to drive the output, thus causing a large current consumption. Since it is impossible to adjust the slope of the circuit, it takes a long time for the voltage of OUT to stabilize.

The present invention is to solve the above problems, it is possible to reduce the current consumption by changing the structure of the front-end inverter to eliminate the direct current pass, and to configure the transistors of the output stage to control the gate stage of the output voltage It is an object of the present invention to provide a CMOS output driving circuit that can adjust the slope of.

The present invention for achieving the above object, the CMOS output drive circuit, the output stage; First and second pull-up transistors connected in series between a power supply voltage terminal and the output terminal, and first and second pull-down transistors connected in series between the output terminal and the ground terminal, and outputting a signal having a slope varying according to an input; Is a natural number) output driver; Two unit inverters having outputs inverted by two identical input signals, respectively, are connected in parallel between a power supply voltage terminal and a ground terminal, and the resistance ratios of the respective unit elements constituting the unit inverters are different from each other. N inverting delay units for outputting two signals having a predetermined time difference respectively controlling the output driver; And a controller for controlling the unit inverter by outputting a signal obtained by adding or subtracting a threshold voltage to the inverted value of the input signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2 is a CMOS output driving circuit diagram according to an embodiment of the present invention, Figure 3 is a timing diagram of each signal according to the FIG.

Referring to FIG. 2, the CMOS output driving circuit of the present invention includes first and second pull-up transistors P24-1 and P24 connected in series between an output terminal F, a power supply voltage terminal VDD, and the output terminal F. FIG. And second and second pull-down transistors N24-1 and N24-2 connected in series between the output terminal F and the ground terminal VSS, and outputting a signal having a slope varying according to an input. N (N is a natural number) output driving units 24-1 to 24-n, and two unit inverters 23a and 23b each having an inverted output by the same two different input signals are connected to each other. ) And a ground terminal (VSS) connected in parallel, so that the resistance ratio of each unit element constituting each unit inverter (23a, 23b) is different from each other to control the corresponding output driver (24-1 to 24-n), respectively N inversion delay units 23-1 to 23-n for outputting two signals having a predetermined time difference, and a threshold voltage V at an inverted value of the input signal IN. and a controller 22 for outputting a signal obtained by subtracting t) to control the unit inverters 23a and 23b.

The controller 22 may include a PMOS transistor P21 and an NMOS transistor N21 connected in series between a power supply voltage terminal VDD and a ground terminal VSS, and share an input signal IN with a gate terminal. The input of the inverter 21 and the input signal IN are input to the gate terminal, and the source terminal is connected to the power supply voltage terminal VDD. The output of the drain terminal is input to the unit delay units 23a and 23b. Is connected between the PMOS transistor P22 and the output terminal B of the inverter 21 and the drain terminal of the PMOS transistor P22, and the input terminal IN is 'high'. Diode transistor N22a outputs a voltage level higher than 'low' by a threshold voltage (Vt), but allows the resistance ratio to be variable to adjust the delay of the inversion delay unit 23 by an output having a predetermined pitch. ) And the input signal IN as the gate terminal, and the source terminal is connected to the ground terminal VSS. The input signal IN is connected between the NMOS transistor N22 having the output of the in stage as the unit inverters 23a and 23b type force and the output terminal B of the inverter 21 and the drain terminal of the NMOS transistor N22. Is low, it outputs a voltage level lower than the high of the output terminal B by the threshold voltage (Vt), but allows the resistance ratio to be variable, thereby inverting the delay unit 23 by an output having a predetermined slope. A diode transistor N22b is provided to adjust the delay of -1 to 23-n.

Here, the diode transistors N22a and N22b are NMOS transistors or PMOS transistors.

The unit inverters 23a and 23b are PMOS transistors P23 having the output of the PMOS transistor P22 as the gate terminal input and NMOS transistors having the output of the NMOS transistor N22 as the gate terminal input. PMOS transistor P24 and NMOS in which the N23 is connected in series between the power supply voltage terminal VDD and the ground terminal VSS, and the output of the PMOS transistor P22 is a gate terminal input. The NMOS transistor N24 having the output of the transistor N22 as the gate terminal input includes a unit inverter 23b connected in series between the power supply voltage terminal VDD and the ground terminal VSS.

The unit inverter 23a controls the gate ends of the pull-up transistor P24-1 and the pull-down transistor N24-1, and the unit inverter 23b controls the pull-up transistor P24-2 and the pull-down transistor N24-. The gate terminal of 2) is controlled, and the PMOS and NMOS transistors P23-1, P23-2, N23-1, and N23-2 have different resistance ratios.

The output driving circuit of the present invention having the above-described configuration will be described in detail with reference to FIG. 3. For convenience of description, only one inversion delay unit 23-1 and one output driving unit 24-1 are taken as an example. Explain.

First, when the input signal (hereinafter referred to as IN) is changed from the ground voltage level (VSS, hereinafter referred to as 'low') to the power supply voltage level (VDD, hereinafter referred to as 'high'), the inverter 21 generates a 'B'. The node becomes 'low', PMOS transistor P22 is turned off, and NMOS transistor N22 is turned on. Therefore, since the node 'C' becomes 'low', the NMOS transistors N23-1 and N23-2 are both turned off.

Accordingly, the node 'A' is at a voltage level higher than the 'low' of the node 'B' by the diode transistor N22a by the threshold voltage of the diode transistor N22a (hereinafter referred to as Vt1), which is the diode transistor N22a. As shown in FIG. 3, the slope changes as the area of ie, the resistance ratio is adjusted.

Specifically, as the resistance ratio of the diode transistor N22a is increased (as the area is decreased), the slope of the diode transistor N22a has a gentle slope in the direction of 'ga', and the voltage becomes higher by Vt1 than 'low'.

Therefore, when the resistance ratios of the PMOS transistors P23-1 to P23-2 are different from each other, the PMOS transistors P23-1 and P23-2 are turned on with a slight delay in time. When the resistance ratios of -1 and P23-2 are different, a pair of waveforms of the node 'D' and the node 'E' form almost the same curve, but a predetermined delay difference is shown as 'I' shown in FIG. With 'high'.

Therefore, the output (hereinafter, referred to as OUT) according to the time difference between the node 'D' and the node 'E' is as shown in FIG. 3, and the diode transistor N22a and the PMOS transistors P23-1 and P23-2. Depending on the resistance ratio of, the output is possible with various slopes.

On the other hand, when IN transitions from 'high' to 'low', the node 'B' becomes 'high' by the inverter 21, the PMOS transistor P22 is turned on, and the second NMOS transistor N22. Is turned off. Therefore, since the node 'C' becomes 'high', the NMOS transistors N23-1 and N23-2 are both turned on, and the node 'B' is 'high' of the node 'B' by the diode transistor N22b. The voltage level is lower by the threshold voltage (hereinafter referred to as Vt2) of the diode transistor N22b, which is changed as shown in FIG. 3 by adjusting the area of the diode transistor N22b, that is, the resistance ratio.

Specifically, as the resistance ratio of the diode transistor N22b is increased (as the area is decreased), it has a gentle slope in the direction of 'da', and the voltage becomes as low as Vt2 than 'high'.

Accordingly, when the resistance ratios of the NMOS transistors N23-1 and N23-2 are different from each other, the NMOS transistors N23-1 and N23-2 are turned on with a predetermined time difference, at which time the NMOS transistors N23- When the resistance ratios of 1 and N23-2 are different, the node 'D' and the node 'E' are 'low' with a predetermined delay difference as shown in FIG.                     

Accordingly, due to the time difference between the node 'D' and the node 'E', the output OUT is the diode transistor N22b and the NMOS transistors N23-1 and N23-2 as shown in FIG. 3. It is output at various slopes by the resistance ratio of.

According to the present invention made as described above, by avoiding a full swing from 'high' to 'low' by two diode transistors, it is possible to reduce the direct current path to reduce the overall current consumption, diode The slope of the output waveform can be adjusted by adjusting the size of the transistor and the size of each transistor constituting the inversion delay unit, and the diode transistor may use an NMOS transistor or a PMOS transistor.

Further, in order to obtain an output having various inclinations pursued by the present invention, by increasing the number of stages of the inverted delay unit and increasing the number of stages of the output driver by the number corresponding to the increased number of inverted delay units, a region waveform having various slopes can be obtained. It becomes possible.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention made as described above, by controlling the size of the diode-connected transistor of the control unit and the size of each transistor by the multi-stage inversion delay unit, it is possible to reduce the current consumption to a sudden current change, and to adjust the slope of the output voltage. .

Claims (6)

CMOS output drive circuit, Output stage; First and second pull-up transistors connected in series between a power supply voltage terminal and the output terminal, and first and second pull-down transistors connected in series between the output terminal and the ground terminal, and outputting a signal having a slope varying according to an input; Is a natural number) output driver; Two unit inverters having outputs inverted by two identical input signals, respectively, are connected in parallel between a power supply voltage terminal and a ground terminal, and the resistance ratios of the respective unit elements constituting the unit inverters are different from each other. N inverting delay units for outputting two signals having a predetermined time difference respectively controlling the output driver; A control unit for controlling the unit inverter by outputting a signal obtained by adding or subtracting a threshold voltage to an inverted value of the input signal Output drive circuit comprising a. The method of claim 1, The control unit, An inverter having a first PMOS transistor and a first NMOS transistor connected in series between a power supply voltage terminal and a ground terminal, and having an input signal as a common input of a gate terminal; A second PMOS transistor having the input signal as an input of a gate terminal, a source terminal connected to a power supply voltage terminal, and a output of the drain terminal being one input of the unit delay unit; Is connected between the output terminal of the inverter and the drain terminal of the second PMOS transistor, when the input signal is 'high' outputs a voltage level higher than the threshold voltage 'low' by allowing a variable resistance ratio A first diode transistor configured to adjust a delay of each inversion delay unit by an output having a predetermined slope; A second NMOS transistor having the input signal as an input of a gate terminal, a source terminal connected to a ground terminal, and an output of the drain terminal as a type force of the unit inverter; And It is connected between the output terminal of the inverter and the drain terminal of the second NMOS transistor, when the input signal is 'low' outputs a voltage level lower than the 'high' of the output terminal by a threshold voltage, the resistance ratio is variable A second diode transistor to enable adjustment of the delay of each inverting delay portion by an output having a predetermined tint Output drive circuit comprising a. The method of claim 2, And the first and second diode transistors are NMOS transistors or PMOS transistors. The method of claim 1, The unit inverter, A third PMOS transistor having an output of the second PMOS transistor as a gate terminal input and a third NMOS transistor having an output of the second NMOS transistor as a gate terminal input connected in series between a power supply voltage terminal and a ground terminal; 1 unit inverter; And A fourth PMOS transistor having an output of the second PMOS transistor as a gate end input and a fourth NMOS transistor having an output of the second NMOS transistor as a gate end input connected in series between a power supply voltage terminal and a ground terminal; 2 units inverter Output drive circuit comprising a. The method of claim 4, wherein In the first and second unit inverter, The first unit inverter controls a gate terminal of the first pull-up transistor and the first pull-down transistor, And the second unit inverter controls gate ends of the second pull-up transistor and the second pull-down transistor. The method of claim 4, wherein And the third, fourth PMOS and third and fourth NMOS transistors have different resistance ratios.

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