JP2001068986A - Output buffer circuit for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a large slew rate adjustment width and to realize a high processing speed. SOLUTION: In the output buffer, a pre-driver D1 that receives a data signal, resistive elements R11-R14, R21-R24 that delay an output signal of the pre-driver D1, an output transistor(TR) that is driven by pre-drivers D1, D2 via the resistive elements, simultaneous interruption control means (PA01, PA02, NA01, NA02) that inactivates the output TR uniquely with the data signal of an L level, and a conduction control means (PT01, PT02, NT01, NT02) that uniquely activates the output TR with a data signal of an H level and invalidates the output of a resistive element, when a slew rate selection signal SELECT 1 is activated, are interposed for each output TR gate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit of a semiconductor device, and more particularly, to a circuit configuration in which a slew rate adjustment width can be increased even if a transistor size of a pre-driver for receiving a data signal and driving an output transistor is minimized. The present invention relates to an output buffer circuit of a semiconductor device.

[0002]

2. Description of the Related Art One of the causes of a malfunction in a recent semiconductor device is noise generated from an internal circuit of the semiconductor device itself. For the purpose of reducing the noise and realizing low power consumption, a power supply potential and a ground are required. There is a need for an output buffer circuit with a low slew rate in which a through current flowing between potentials is kept low.

In general, the slew rate means that an output voltage of an amplifier does not faithfully respond to an input voltage, and a change in output voltage per fixed time becomes a constant value irrespective of the input voltage. That is. An example in which improvement of the slew rate in this semiconductor device is proposed is described in Japanese Patent Application Laid-Open No. 9-8639.

Referring to FIG. 6 showing the configuration of an output buffer circuit disclosed in the publication, a pre-driver D1 receiving a data signal IN1, a pre-driver D2 receiving a data signal IN2, and a P-channel receiving an output of the pre-driver D1 are provided. Output transistor in which the type transistor PM01 and the N-channel type transistor NM01 receiving the output of the pre-driver D2 are connected in series, and an output terminal connected in parallel to this transistor is output together with the output terminal of the first output transistor. P-channel transistor PM02 and N-channel transistor NM02 commonly connected to terminals
Output transistor composed of P-channel transistor PM03 and N-channel transistor NM
A third output transistor made of P.03, a resistance element R11 inserted between the gates of P-channel transistors PM01 and PM02, a resistance element R21 inserted between the gates of N-channel transistors NM01 and NM02, and P A resistor R12 inserted between the gates of channel type transistors PM02 and PM03;
A resistance element R22 inserted between the gates of channel transistors NM02 and NM03, and a P-channel transistor PA connected between P-channel transistor PM02 and power supply potential VDD to receive data signal IN1.
01, an N-channel transistor NA01 connected between the N-channel transistor NM02 and the ground potential GND and receiving the data signal IN2, and a P-channel transistor connected between the P-channel transistor PM03 and the power supply potential VDD and receiving the data signal IN1 PA0
2 and an N-channel transistor NA01 connected between the N-channel transistor NM03 and the ground potential GND to receive the data signal IN2.
1, R12, R21, and R22 are delay elements.

In this conventional configuration, the inverters D1, D
The input data signal given through the resistor element R1
1, R12, R21, and R22, respectively,
Output transistors PM01 to PM03, NM01 to N
The side of M03 that switches to the conductive state is sequentially conductive.

The side that switches to the cutoff state is cut off simultaneously by the data signal without being affected by the resistance elements by the P-channel transistors PA01 and PA02 and the N-channel transistors NA01 and NA02.

Therefore, a low slew rate output is realized while suppressing an increase in a through current flowing from the power supply potential to the ground potential via the P-channel transistor and the N-channel transistor.

However, in this configuration, adjustment of the slew rate is not considered, and it is not possible to cope with a change in the slew rate value due to a variation in a diffusion condition, a use temperature, a use voltage, and the like when manufacturing a semiconductor device.

On the other hand, a technique generally used for adjusting the slew rate is a technique called a pre-driver adjustment method, and the configuration is shown in FIG. Referring to FIG. 7, the difference from the configuration of FIG. 6 described above is that a transistor (pre-driver) for driving the final stage output transistor is provided.
The ability to adjust the slew rate by changing the ability.

At the time of implementation, the pre-driver D shown in FIG.
1. The configuration is such that the transistor size of D2 can be switched by an external signal.

However, in this method, the pre-driver D1,
Since D2 drives the output transistors via the resistors R11, R12, R21, and R22, the pre-driver D
1. It was necessary to design the transistor size of D2 large in advance, which involved a problem that the chip size became large.

On the other hand, another example in which the slew rate can be adjusted is described in JP-A-6-152373. Referring to FIG. 8 which shows a circuit diagram of a semiconductor device described in the publication, a pre-driver D9 and an output transistor P05
Are provided to cancel the signal delay resistance elements R21 and R22 respectively connected between the pre-driver D10 and the output transistor N05.

The bypass circuits BP1 and BP2 have the same circuit configuration. For example, the bypass circuit BP1 is driven by an inverter D11 receiving an output signal of a pre-driver D9, and its activation is controlled by a low voltage detection signal. Consisting of clocked inverters.

This clocked inverter has a power supply potential V
It comprises P-channel transistors P01 and P02 and N-channel transistors N01 and N02 connected in series between DD and the ground potential GND. The output of the inverter D11 is connected to the gate electrodes of the P-channel transistors P01 and N02. Input the signal,
A low voltage detection signal is supplied to the gate electrode of the N-channel transistor N01, and a polarity inversion signal of the low voltage detection signal by the inverter D13 is supplied to the gate electrode of the P-channel transistor P02.

In this circuit, by providing a bypass circuit, noise generated due to rapid conduction of the output transistor is reduced, but by passing the bypass circuit at the time of low voltage operation in which the delay of data output becomes large,
Data output delay is reduced.

[0016]

As described above, among the conventional output buffer circuits, in the first conventional example, no measures are taken for adjusting the slew rate, so that the diffusion conditions, operating temperature, operating voltage, etc. The change of the slew rate value due to the variation of the above cannot be dealt with.

In the second prior art, the pre-driver D
1, D2 drives the output transistor via the resistance elements R11, R12, R21, R22, so that the transistor size of the pre-driver must be increased in order to secure a large slew rate adjustment width.

Further, in the third conventional example, the delay of data output can be reduced, but the signal transmission speed is reduced because three inverters are inserted in the path from the input terminal to the output transistor. And cannot cope with high speed.

SUMMARY OF THE INVENTION An object of the present invention has been made in view of the above-mentioned disadvantages of the related art. Even when the transistor size of a pre-buffer that receives a data signal and drives an output transistor is minimized, a slew rate adjustment width can be increased, and An object of the present invention is to provide an output buffer circuit of a semiconductor device having a circuit configuration capable of realizing high speed.

[0020]

The output buffer circuit according to the present invention is characterized in that a pre-driver for receiving a data signal, a resistor for delaying an output signal of the pre-driver, and a pre-driver via the resistor are used. An output transistor to be driven; a simultaneous cut-off control means for uniquely inactivating the output transistor with a logic-level low-level or high-level data signal; and a predetermined first slew-rate selection signal being activated. When this is done, the output transistor is uniquely activated by the data signal of high level or low level, and conduction control means for invalidating the output of the resistance element are connected in series to constitute the output transistor. Interposing each gate electrode of P-channel and N-channel transistors One of the P-channel type and N-channel type transistors inactivated by the simultaneous cutoff control means is controlled in a low slew rate direction by the resistance element output, and is controlled in a high slew rate direction by the conduction control means. Control is to control.

Further, the resistance element, the simultaneous cutoff control means, the conduction control means, and the output transistor include:
A plurality of sets may be connected in parallel.

Further, the conduction control means on the side of the P-channel type transistor is uniquely activated only by a second selection control signal, and the second selection control signal has a polarity of the first slew rate selection signal. The output signal of the pre-driver on the side of the P-channel type transistor constituting the output transistor is selected by the inverted signal, and the conduction control means on the side of the N-channel type transistor is uniquely activated only by the third selection control signal. And the third selection control signal is a signal generated by selecting the output signal of the pre-driver on the side of the N-channel transistor constituting the output transistor with the first slew rate selection signal. You can also.

Further, a plurality of sets of slew rate selection signals are provided as control signals for independently controlling each of the plurality of sets, and the plurality of sets of slew rate selection signals are individually supplied from an external or internal predetermined control unit. It may be a slew rate selection signal whose activation can be controlled.

Also, when the plurality of sets of slew rate select signals which can be individually activated are both at one level, the output signal has the lowest slew rate, and when the slew rate select signals are at the other level, the output signal has the highest slew rate. The signal may be an output signal having a slew rate obtained by subdividing between the minimum slew rate and the maximum slew rate according to a combination of other levels of the slew rate selection signal.

Another feature of the output buffer circuit of the present invention is that
A first pre-driver for receiving the first data signal, a second pre-driver for receiving the second data signal,
A pair of output transistors each having a channel type transistor and a first N-channel type transistor connected in series, and a first pre-driver unit and a gate electrode of the first P-channel type transistor interposed therebetween; A first resistive element for signal delay, first slew rate selecting means for canceling the resistive element, and a first for interrupting conduction of the first P-channel transistor in response to the first data signal A second resistor for signal delay interposed between the cutoff control transistor, the second pre-driver means, and the gate electrode of the first N-channel transistor, and a second resistor for canceling this resistor And a second shutoff control for interrupting conduction of the second N-channel transistor in response to the second data signal. And a plurality of sets of output circuits connected in parallel to the corresponding first and second pre-driver means, and in response to a predetermined selection control signal, It is to control the slew rate adjustment of the output circuit output in response to the output signals of the first and second slew rate selection means.

Still another feature of the present invention is that a first pre-driver receiving a first data signal, a second pre-driver receiving a second data signal, a P-channel transistor and an N-channel transistor are provided. A first, a second, and a third output transistor that are connected in series and that commonly connect the series connection point to an output terminal;
Are connected in series between a pre-driver output terminal of the first transistor and a corresponding gate electrode of the third output transistor.
A first resistance element, a second resistance element, a third resistance element, a third resistance element, a third resistance element, a fourth resistance element, and a simultaneous cutoff control transistor, a conduction control transistor, and a selection control transistor inserted in series between a power supply potential and a ground potential. , A second, a third, and a fourth series-connected body, the first output transistor corresponding to a gate electrode of a P-channel transistor and a gate electrode of an N-channel transistor, respectively.
And the second pre-driver output terminals are connected together, and the first and second series-connected bodies corresponding to the gate electrodes of the P-channel transistor and the N-channel transistor of the second output transistor, respectively, A series connection point of the cut-off control transistor and a series connection point of the conduction control transistor are respectively connected, and a series connection point of the first and second resistance elements is further connected to a gate electrode of the P-channel transistor. The third and fourth gate electrodes are further provided on the gate electrode.
At the same time, the third and fourth series-connected bodies corresponding to the gate electrodes of the P-channel transistor and the N-channel transistor of the third output transistor are cut off simultaneously. The series connection points of the control transistor and the conduction control transistor are connected to each other, and the first and third series-connected bodies have the gate electrode of the selection control transistor connected to the first node.
And a polarity inversion signal of the first slew rate selection signal is supplied to the gate electrodes of the selection control transistors of the second and fourth series-connected bodies, respectively.

In addition, instead of the first, second, third and fourth series-connected bodies, a transistor for simultaneous cutoff control inserted in series between a power supply potential and a ground potential and a selection control Fifth, sixth, and seventh transistors
And an eighth series-connected body, wherein a polarity inversion of the first slew-rate selected signal is provided as a circuit for generating a slew-rate selection signal to be provided to the selection control transistors of the first and third series-connected bodies. A first OR circuit that takes a logic of a signal and the first pre-driver output signal; and a circuit that generates a slew rate selection signal to be applied to selection control transistors of the second and fourth series-connected bodies. And a logical AND circuit for calculating the logic of the second pre-driver output signal and the slew rate selection signal of the second pre-driver.

Further, when the transistor having the simultaneous cutoff control means and the conduction control means and each of the plurality of output transistors connected in parallel has the same transistor size, the size of the transistor constituting the pre-driver is reduced. It can be formed in advance by setting the same transistor size as the constituent transistor size of the simultaneous cutoff control means and the conduction control means.

Furthermore, in addition to the first and second resistance elements, a third to an eighth resistance element is further provided, and a power supply potential is provided instead of the first and the fourth series connection elements. A fifth transistor comprising a simultaneous cut-off control transistor inserted in series between the ground potential and the third or fourth resistor element, a conduction control transistor, and a selection control transistor.
To an eighth series-connected body, one end of which is connected to the output end of the first pre-driver, and the other end of the first resistance element is connected to the fifth resistor of the fifth series-connected body. The other end of the second resistance element, which is connected to a series connection point of an element and the conduction control transistor and one end of which is connected to an output end of the second pre-driver, is connected to the sixth connection point of the sixth series connection body.
Is connected to a series connection point of the resistance element and the conduction control transistor, and one end of the third resistance element is connected in series with the simultaneous cutoff control transistor and the fifth resistance element of the fifth series connection body. And the other end is connected to a series connection point of the seventh resistance element and the conduction control transistor of the seventh series connection body, and one end of the fourth resistance element is connected to the sixth series connection body. Is connected to a series connection point of the simultaneous cutoff control transistor and the sixth resistance element, and the other end is connected to a series connection point of the eighth resistance element and the conduction control transistor of the eighth series connection body. The other end of the seventh resistance element is connected to the third resistance element.
The other end of the eighth resistance element is connected to the gate electrode of an N-channel transistor of the third output transistor, and the other end of the eighth resistance element is connected to the gate electrode of an N-channel transistor of the third output transistor. A second slew rate selection signal as a slew rate selection signal to be applied to the selection control transistor of the connector, and a second slew rate signal as a slew rate selection signal to be applied to the selection control transistor of the eighth series connection. It may further include a polarity inversion signal of the selection signal.

Further, the first and third resistance elements have the same resistance value, the second and fourth resistance elements have the same resistance value, and the first or third resistance element has the same resistance value. The resistance value of the resistance element may be set in advance to be approximately twice the resistance value of the second or fourth resistance element.

Further, in the signal path from the input terminal of the pre-driver to the output transistor, only one inverter and a plurality of resistance elements are provided in cascade connection, so that data delay is applied only to the resistance elements. The element size can be formed in advance.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described first with reference to the drawings. FIG. 1 is a circuit diagram of an output buffer circuit showing a first embodiment of the present invention. Referring to FIG. 1, the circuit includes a first pre-driver D1 receiving a first data signal IN1, a second pre-driver D2 receiving a second data signal IN2, a P-channel transistor PM01 and an N-channel transistor Type transistor NM0
1, similarly PM02 and NM02, PM03 and N
M03 is connected to power supply potential VDD and ground potential GND, respectively.
Connected in series, and these series connection points are connected to the output terminal OUT.
, And first, second, and third output transistors connected in common. That is, these first, second and third
Are connected in parallel with each other.

The output terminals of the pre-drivers D1 and D2 and the third output transistors PM03 and NM03
First and second resistance elements R11 and R21, and third and fourth resistance elements R11 and R21 connected in series between
Resistance elements R12 and R22.

Further, the power supply potential VDD and the ground potential GND
Simultaneous shutoff control transistors PA01, PA02, NA01, NA02 and conduction control transistors NT01, NT02, PT01, PT02 and selection control transistors NS01, NS02, PS inserted in series between them.
01, PS02 and a slew rate selection circuit CK
1, CK2, CK3, and CK4.

P-channel type transistor and N-channel type transistor PM01 as first output transistors
And NM01 are the corresponding pre-drivers D1 and D2
Of the P-channel transistor PM02 and the N-channel transistor NM0
2 are connected to corresponding pre-drivers D1 and D2 via corresponding resistance elements R11 and R21, respectively.
Connect to the output terminal of

The gate electrodes of P-channel transistor PM03 and N-channel transistor NM03 are connected to the output terminals of corresponding resistance elements R11 and R21 via corresponding resistance elements R12 and R22, respectively.

Second output transistor P-channel transistor PM02 and N-channel transistor N
Simultaneous shutoff control transistor PA01 and slew rate selection circuit CK1 (conduction control transistor NT01), which are first series-connected bodies respectively corresponding to the gate electrode of M02.
And a selection control transistor NS01) and a simultaneous cutoff control transistor NA01, which is a second series connection, and a slew rate selection circuit CK2.
(Consisting of a conduction control transistor PT01 and a selection control transistor PS01).

The third output transistor P02 and the simultaneous cutoff control transistor PA02, which is the third series-connected body corresponding to the gate electrodes of the N-channel transistors PM03 and NM03, respectively, and the slew rate selection circuit CK3 (conduction) Control transistor N
A simultaneous connection control transistor NA02 and a slew rate selection circuit CK4 (consisting of a conduction control transistor PT02 and a selection control transistor PS02), which are a series connection point with the transistor T02 and the selection control transistor NS02, and a fourth series connection. Are connected in series.

Further, the first slew rate selection signal SELECT1 is supplied to the gate electrodes of the first and third selection control transistors NS01 and NS02 by the selection control signal S1.
And a configuration in which the gate electrodes of the second and fourth selection control transistors PS01 and PS02 supply a polarity inversion signal of the first slew rate selection signal as the selection control signal S2.

That is, the point of this circuit configuration is that the input I
Data signals input from N1 and IN2 via inverters D1 and D2 are connected to resistance elements R11, R12, R21 and R2.
And P-channel transistors PM01 and N-channel transistors NM01, PM02 and NM0 as output transistors.
2. Propagate the data signal in the order of PM03 and NM03 and output the signal from the output terminal OUT. Simultaneous cutoff control transistors PA01, PA02, NA01, N
A02 is the input IN1, I2 without passing through a resistor as in the conventional example.
N2, and the conduction control transistors PT01, PT02, NT0 according to the present invention.
1, NT02, selection control transistors PS01, PS
02, NS01, NS02, and slew rate selection circuits CK1 to CK4 are provided, and PT01, PT02, NT
01 and NT02 are directly and uniquely controlled by the data signals IN1 and IN2 without being affected by the delay element. The selection of the slew rate is made by the slew rate selection signal SELECT1.
(Corresponding to the selection control signals S1 and S2).

That is, the selection control transistor PS0
1, when PS02, NS01, and NS02 are off, input data signals IN1 and IN2 are delayed by corresponding resistance elements R11, R12 and R21, R22, respectively, so that first, second, and third outputs are provided. , And these output transistors are sequentially turned on.

Selection control transistors PS01, PS0
2, NS01 and NS02 are in the non-conductive state, the simultaneous shutoff control transistors PA01, PA02, NA01, N
The operation of the resistance elements R11, R12, R21, and R22 is canceled by the action of the data signals IN1 and IN2 directly input to A02, and the P-channel transistors and the N-channel transistors of the first, second, and third output transistors are cancelled. One of the three type transistors is simultaneously turned on.

Further, these output transistors are simultaneous cutoff control transistors PA01, PA02, NA0.
1, data signals IN1, IN2 directly input to NA02
Controls the three sides of each of the P-channel type transistors and the N-channel type transistors of the output transistors to be non-conductive at the same time.

As a result, the slew rate selection signal SELE
With CT1, it is possible to change the timing at which one of the P-channel transistor and the N-channel transistor of a plurality of output transistors connected in parallel to share the output terminal is simultaneously turned on. Next, the operation of the embodiment will be described more specifically.

First, in the first initial state, data signals IN1, IN2 and a slew rate selection signal SEL are used as signal inputs.
It is assumed that a low level (hereinafter, referred to as L level) is applied to ECT1.

The inverters D1 and D2 output an H level in response to the L levels of the data inputs IN1 and IN2, and the P-channel type simultaneous cutoff control transistor P
A01 and PA02 conduct to give an H level to the gate electrodes of P-channel transistors PM01 and PM02,
Simultaneous cutoff control transistors NA01 and NA02, which are channel type transistors, become non-conductive and apply an L level to the gate electrodes of N channel type transistors NM01 and NM02, so that P channel type transistors PM01, PM02 and PM03 as output transistors are simultaneously set. It becomes a cutoff state.

Now, the slew rate selection signal SELECT1
Of the selection control transistors PS01, PS02, NS01, NS0.
2 are in a blocking state, so that PT01, PT02,
Since NT01 and NT02 are not affected by the data signals IN1 and IN2, the slew rate selection circuits CK1 to CK4
Does not operate, and the resistance elements R11, R12, and R21,
The N-channel transistors NM01, NM02, and NM03 are successively delayed by R22, respectively, and become conductive, so that the output OUT outputs the L level. That is, the state is a low slew rate output.

Here, when the H level is input to IN1 and IN2, the simultaneous cutoff control transistors PA01 and PA02 are turned off, and the L level is output from the predriver D1. The L-level signal from the pre-driver D1 is delayed by the resistance elements R11 and R12, and P-channel transistors PM01, PM02, and PM as output transistors.
The signals are transmitted in the order of 03, and are sequentially turned on.

On the other hand, the pre-driver D2 also sets the L level to the simultaneous cutoff control transistor NA01,
NA02 becomes conductive and outputs its L level simultaneously, so that the N-channel transistors NM01 to NM03 of the output transistors are cut off simultaneously without being affected by the delay due to the resistance element, and the output OUT becomes the resistance element R11, An output transistor P-channel transistor PM0 that is delayed by R12 and is sequentially turned on.
1, H level is output by PM02 and PM03.
That is, the state is a low slew rate output.

After a lapse of a predetermined time, the data signals IN1, I
When N2 goes to L level again, the transistors NA01 and NA02 for simultaneous cutoff control are turned off, and the H level is output from the pre-driver D2, so that the resistance element R2
1 and R22, the N-channel transistors NM01, NM02 and NM03 of the output transistors are turned on in this order.

On the other hand, the H level is also output from the pre-driver D1, and the transistors PA01 and PA for simultaneous cutoff control are output.
02 also becomes conductive due to the data signal and outputs an H level, so that both output the H level at the same time, and the P-channel transistor P
M01 to PM03 are cut off at the same time, and the output OUT
Outputs the L level. That is, the state is a low slew rate output.

As described above, the slew rate selection signal S
It can be seen that the H-level and L-level output waveforms from the output terminal OUT have a low slew rate during the switching operation when the slew rate selection circuits CK1 to CK4 are deactivated by giving L1 to the ELECT1.

Next, as a second state, the slew rate selection signal SELECT1 is set to H level and the data signals IN1 and I
Consider a case where the L level is applied as N2. At this time, the selection control transistors PS01, PS0
2, NS01 and NS02 are conducting, conduction controlling transistors PT01 and PT02 are conducting, NT01 and NT
02 is a non-conductive state.

The outputs of the pre-drivers D1 and D2 are at the H level, and the simultaneous cutoff control transistors PA01 and PA02 supply the H level in the conductive state.
M0N1 to PM03 are in a non-conductive state, the simultaneous cutoff control transistors NA01 and NA02 are in a non-conductive state, and the conduction control transistors PT01 and PT02 and the selection control transistor are all in a conductive state to supply an H level. The N-channel transistors NM01 to NM03 of the output transistors thus turned on, and the output terminal OUT outputs the L level. That is,
This is a low slew rate output state. It is.

Here, the data signals IN1 and IN2 are set to H
Level (the slew rate selection signal SELE)
CT1 is maintained at an H level), and the H level causes the simultaneous shutoff control transistors PA01 and PA0.
2 is turned off, and the conduction control transistor NT0
1, NT02 and selection control transistors NS01,
Since NS02 is both conductive and supplies the L level, the P-channel transistors PM01 to PM03 of the output transistors receiving the L level are conductive, and the output terminal OUT outputs the H level.

At this time, the output of the pre-driver D1 becomes L level, but the P-channel transistors PM02 and PM03 as output transistors are not affected by the activation of the slew rate selection circuits CK1 and CK2. That is, the state is a high slew rate output.

On the other hand, the conduction control transistors PT01 and PT02 are rendered non-conductive by the H level of the data signal IN2, and the selection control transistors PS01 and PS02 are rendered non-conductive by the slew rate selection signal. NA02 is turned on to supply the L level, so that the N-channel type transistors NM01 to NM01 to NM01 of the output transistor receiving the L level are output.
NM03 is turned off.

At this time, the output of the pre-driver D2 goes to L level, but the simultaneous cutoff control transistors NA01,
The P-channel transistors PM02 and PM03 as output transistors are not affected by the conduction state of NA02. That is, the state is a high slew rate output.

Further, when the data signals IN1 and IN2 become L level (the slew rate selection signal SELECT1 becomes H level).
Level), the simultaneous cutoff control transistors NA01 and NA02 are turned off, and the conduction control transistors PT01 and PT02 and the selection control transistors PS01 and PS02 are both turned on to supply the H level. , N-channel transistors NM01 to NM01 of output transistors receiving this H level
NM03 is turned on, and the output terminal OUT outputs L level.

At this time, the output of the pre-driver D2 becomes H level, but the N-channel transistors NM02 and NM03 of the output transistors are not affected by the activation of the slew rate selection circuits CK2 and CK4. That is, the state is a high slew rate output.

On the other hand, the conduction control transistors NT01 and NT02 are turned off by the L level of the data signal IN1, and the simultaneous cutoff control transistors PA01 and PA0 are turned off.
2 becomes conductive and supplies the H level, so that the P-channel transistors PM01 to PM03 of the output transistors receiving the H level become nonconductive.

At this time, the output of the pre-driver D1 becomes H level, but the simultaneous cutoff control transistors PA01, PA01,
The P-channel transistors PM02 and PM03 as output transistors are not affected by the conduction state of PA02.

Referring to FIG. 2 showing a conceptual diagram of output waveforms at the time of the low and high slew rate operations described above, waveform a shows a buffer operation when L level is given to selection control signal SELECT1, and the output is This shows a waveform having a low slew rate.

A waveform b shows a buffer operation when an H level is given to the selection control signal SELECT1, and shows a waveform whose output has a high slew rate.

That is, in the present invention, the output transistor P
To the gate electrodes of M02 and PM03 (output side of resistance element)
Is controlled by the selection control signal SELECT1 to control the slew rate selection circuits CK1 to CK4 provided in
The output slew rate is adjusted by canceling the delay caused by the resistance element.

In actual use, when performing a wide slew rate adjustment such as optimizing the slew rate of the output waveform in accordance with the magnitude of the output terminal load or filling in the slew rate difference due to variations after manufacturing, Even when transistors of the same size are used, a wider slew rate can be adjusted.

That is, in the case where there are simultaneous cutoff control means and conduction control means and the transistor sizes of a plurality of output transistors connected in parallel have the same value,
The size of the transistor constituting the pre-driver can be set in advance to the same value as the size of the transistor constituting the simultaneous cutoff control means and the conduction control means.

The reason for this is that the resistance element for delay is canceled by the slew rate selection circuit, so that the load on the transistor of the pre-driver for driving the output transistor is lightened. As a result, conduction control in the pre-driver and the slew rate selection circuit is reduced. This is because the total transistor size of the transistors can be reduced.

Next, a second embodiment will be described. Referring to FIG. 3 showing a circuit diagram of the second embodiment, the difference from the first embodiment is that the slew rate selection circuit C
K1 to CK4 are simplified and the slew rate selection control circuit C
That is, TL1 is newly provided.

That is, selection control transistors NS01 and NS are connected between the gate electrodes of P-channel transistors PM02 and PM03 as output transistors and the power supply voltage.
02, and N-channel transistors NM02, NM
Selection control transistors PS01 and PS02 are provided between the gate electrode 03 and the ground potential.

Selection control transistors NS01, NS0
The selection control signal S11 is supplied to the gate electrode 2 and the selection control signal S21 is supplied to the gate electrodes of the selection control transistors PS01 and PS02.

Slew rate selection control circuit CTL1 for generating slew rate selection control signals S11 and S21
Uses the output signal S3 of the pre-driver D1 as a second slew rate selection signal,
NOR circuit D4 that takes a logic of ECT1 and a polarity inversion signal by inverter D5 and outputs selection control signal S11
And the output signal S4 of the pre-driver D2 as a third slew rate selection signal S4.
A NAND circuit D6 that takes the logic of the signal ELECT1 and outputs a selection control signal S21.

The other configuration is the same as that of the first embodiment, and the description of the configuration here is omitted.

The operation of the output buffer circuit according to this embodiment is such that the signals S3 and S4 from the inverters D1 and D2 are connected to the NOR gate in the slew rate selection control circuit CTL1.
The circuit D4 and the NAND circuit D6 control the slew rate selection signal SELECT1 as a control signal and transmit the selection control signals S11 and S21.

At this time, if the data signals IN1 and IN2 are at L level and the slew rate selection signal SELECT1 is at L level, the P-channel transistors PM01 to PM03 of the output transistors are non-conductive and the N-channel transistors NM01 to NM03 are conductive. State, and the output terminal OUT becomes L level.

If the data signals IN1 and IN2 are at the H level and the slew rate selection signal SELECT1 is at the L level, the P-channel transistor P
M01 to PM03 are conductive with resistance elements R11 and R12 interposed therebetween, and N-channel transistors NMS01 to NM
03 is a conductive state, and the output terminal OUT is at the H level, which is a low slew rate output state.

When the data signals IN1 and IN2 are at L level again and the slew rate selection signal SELECT1 is at L level, the P-channel transistors PM01 to PM03 of the output transistors are non-conductive, and the N-channel transistors NM01 to NM03 are the resistance element R21. , R22 are interposed and the output terminal OUT is at the L level, which is a low slew rate output state.

Next, the data signals IN1 and IN2 are set at L level.
When the level and the slew rate selection signal SELECT1 is at the H level, the P-channel transistors PM01 to PM03 of the output transistors are non-conductive, and the N-channel transistors NM01 to NM03 are the slew rate selection signal S.
3, S4 and conduction control transistors PT01, PT02
Is activated, the intervention of the resistance elements R21 and R22 is cancelled, the conduction state is uniquely determined, and the output terminal OUT is at the L level, and thus the output state is at a high slew rate.

If the data signals IN1 and IN2 are at the H level and the slew rate selection signal SELECT1 is at the H level, the P-channel transistors and the N-channel transistors PM01 to PM03 of the output transistors output the slew rate selection signal S3 and the conduction control transistor NM.
01, NM02 are activated to activate the resistance elements R11, R12.
Cancels the intervening state, and the N-channel transistors NM01 to NM03 are uniquely non-conductive, and the output terminal OUT is at the H level, which is a high slew rate output state.

The configuration of the second embodiment requires the slew rate selection control circuit CTL1. However, even when a large number of output transistors are connected in parallel and a large number of corresponding slew rate selection circuits CK are connected. There is an advantage that the number of elements does not increase so much.

FIG. 4 shows a circuit diagram of the third embodiment.
The difference from the first embodiment is that four kinds of selection control signals for the slew rate selection circuit are provided, thereby performing a step-by-step slew rate adjustment, and further adding two delay resistance elements. Increase slew rate selection circuits CK1-C
That is, the connection point of K4 is devised. The other components are the same as those of the first embodiment, and the description of the configuration here is omitted.

That is, the configuration of this embodiment is different from the configuration of the first embodiment in that the resistor R1
3, R14, R23, R24, and pre-driver D1
Connected in series between the output terminal of P11 and the gate electrode of the P-channel transistor PM03 of the output transistor.
The resistors R21 to R24 are connected in series between R14 and the gate electrode of the N-channel transistor NM03.

Further, power supply potential VDD and ground potential GND
Simultaneous shutoff control transistor PA01, resistor R13 and conduction control transistor NT inserted in series between
01 and a selection control transistor NS01, and PA02, R14, NT02 and NS0
2 and a series connection including a selection control transistor PS01, a conduction control transistor PT01, a resistance element R23, and a simultaneous cutoff control transistor NA01 inserted in series between the power supply potential VDD and the ground potential GND. And a series-connected body similarly composed of PS02, PT02, R24 and NA02.

The other end of the resistance element R11, to which one end corresponding to the output end of the pre-driver D1 is connected, is connected to the resistance element R13 of the corresponding series connection body and the conduction control transistor NT.
01 is connected to the series connection point.

One end of the resistance element R12 is connected to the series connection point of the transistor PA01 and the resistance element R13 for simultaneous cutoff control of the corresponding series connection, and the other end of the resistance element R12 is connected to the resistance element R14 of the corresponding series connection. It is connected to the series connection point of the conduction control transistor NT02.

The slew rate selection signal SELECT1 is applied to the gate electrode of the selection control transistor NS01 as the selection control signal S1, and the selection control transistor PS0 is provided.
1 has a slew rate selection signal SELECT on its gate electrode.
A polarity inversion signal from one inverter D7 is given as a selection control signal S2.

A slew rate selection signal SELECT2 is supplied as a selection control signal S5 to the gate electrode of the selection control transistor NS02, and the selection control transistor PS0 is provided.
The second gate electrode has a slew rate selection signal SELECT.
A polarity inversion signal from the second inverter D8 is given as a selection control signal S6.

That is, the slew rate selection signal SELE
Signals S1 and S2 generated from CT1 and inverter D7 control slew rate selection circuits CK1 and CK2. Similarly, slew rate selection signal SELECT2 and inverter D8
Signals S5 and S6 generated from the slew rate selection circuit C
Since K3 and CK4 are controlled, the slew rate selection signal S
Slew rate adjustment can be made variable by selectively inputting ELECT1 and SELECT2.

The insertion position of the slew rate selection circuit is set between the resistance elements R11 and R13, the resistance element R12.
And R14, between the resistance elements R21 and R33,
By configuring between the resistance elements R22 and R24, the slew rate adjustment width can be changed.

The operation of the output buffer according to this embodiment is as follows. For example, the data signals IN1 and IN2 are at L level, the slew rate selection signal SELECT1 is at L level,
When SELECT2 is at the H level, the P-channel transistors PS01 to PS03 of the output transistors are non-conductive, and the N-channel transistor NM02 is the resistance element R
22 intervenes, NM03 becomes conductive with the resistance element R24 interposed therebetween, and the output terminal OUT becomes L level. At this time, since the N-channel transistors NM02 and NM03 are both driven via the resistance element, the N-channel transistors NM02 and NM03 are dropped from the corresponding slew-rays.

Data signals IN1 and IN2 are at H level, slew rate select signal SELECT1 is at L level,
When SELECT2 is at the H level, the P-channel transistor PS02 of the output transistor is connected to the resistor R11,
R13 is interposed, and PM03 is conductive with the interposition of resistance element R14, and N-channel transistors NS01 to NS0
3 is uniquely turned off, and the output terminal OUT goes to H level. At this time, the P-channel transistor PM
Since both 02 and PM03 are driven via the resistance element, they fall off from the slew-rays.

When data signals IN1 and IN2 are at L level again, slew rate select signal SELECT1 is at H level, and SELECT2 is at L level, P-channel transistors PM01 to PS03 of the output transistor are non-conductive, and N-channel transistor NM02 is The resistance element R23 is interposed, and NM03 is connected to the resistance elements R22 and R2.
3, R24 intervenes and becomes conductive, and the output terminal OUT
Becomes L level. At this time, the P-channel transistor PM02 is driven via one resistance element and the PM03 is driven via three resistance elements, so that the slew rate is determined by the delay amount of these three resistance values.

Next, the data signals IN1 and IN2 are at H level.
If the level and slew rate selection signal SELECT1 is at H level and SELECT2 is at L level, the P-channel transistor PM02 of the output transistor is connected to the resistor R1
3 and PM03 are conductive with a resistor R14 interposed therebetween, and the N-channel transistor NM
01 to NM03 cancel the intervention of the resistive element, and become non-conducting, and the output terminal OUT becomes H level.
At this time, the P-channel transistors PM02, PM0
3 are driven via one resistance element, the slew rate is determined by the delay amount of these resistance values.

The data signals IN1 and IN2 are at H level, and the slew rate selection signals SELECT1, SELECT
If both T2 are at L level, the P-channel transistor PM02 of the output transistor is connected to the resistance elements R11 and R13.
Are connected and PM03 is connected to the resistance elements R11 and R1.
3, R12 and R14 are interposed, the N-channel transistors NM01 to NM03 are unconducted, and the output terminal OUT goes high. At this time,
Since the P-channel transistor PM02 is driven via two resistance elements and the PM03 is driven via four resistance elements, the slew rate is the lowest, and the slew rate is determined by the delay amount of these resistance values.

Data signals IN1 and IN2 are at H level, and slew rate select signals SELECT1, SELECT
When both T2 are at the H level, the P-channel transistor PM02 of the output transistor is conductive with the resistor R13 interposed therebetween, the PM03 is conductive with the resistor R14 interposed, and the N-channel transistors NM01 to NM03 are uniquely defined. The non-conducting state is established, and the output terminal OUT becomes H level. At this time, the P-channel transistor PM0
2. Since both PM03 and PM03 are driven via one resistor element, the slew rate is the highest, and the slew rate is determined by the delay amount of these resistance values.

Referring to FIG. 5 showing a conceptual diagram of the output operation waveform at this time, waveform a is the output waveform having the lowest slew rate. SELECT1, SELECT in FIG.
T2 indicates an operation waveform when the L level is input.

Waveform b is the output with the highest slew rate.
Both ELECT1 and SELECT2 show the case where the H level is input. When an H level is input to either SELECT1 or SELECT2, the waveform becomes a waveform like a waveform c or a waveform d.

The correspondence between the inputs of SELECT1 and SELECT2 and the waveforms c and d depends on the values of R11 to R14 and R21 to R24.
For example, let R11, 12, 21, and 22 be Ra,
The resistance value of R13, 14, 23, 24 is Rb. At this time, the delay value Ta due to Ra is 2 of the delay value Tb due to Rb.
Assume that the relationship is doubled.

Since there is a difference in the delay value due to the resistance, the time required for the slew rate selection circuits CK1 and CK2 to turn on the output transistors is later than the time required for CK3 and CK4 to turn on the output transistors.

For example, the delay value due to the resistance element is Ta
(Delay value of Ra) = 2 nsec, Tb (Delay value of Rb)
= 1 nsec, and the main P channel side (PM01 to
Pay attention to PM04).

The conduction control transistor NT01 is in the conduction state, and the selection control transistor NS01 is in the conduction state (NS
02 is in a non-conducting state), the conduction order of the main part is PM
01 becomes conduction → R13 delays 1 nsec → PM02 conducts → R12 and R14 delays 3 nsec → PM03 becomes the conduction path 1.

The conduction control transistor NT02 is conducting, and the selection control transistor NS02 is conducting (NS
01 is non-conducting state), the conduction order of the main part is PM
01 is conduction → R12 is 2 nsec delay → PM02 is conduction path 2 and PM01 is conduction → R14 is 1 nsec delay → PM03 is conduction path 3.

Of the above routes, the route 2 is more than the route 1
It is clear that No. 3 has a higher slew rate. That is, when the slew rate selection signal SELECT1 is at the H level (path 1), the waveform becomes d, and SELECT2 is at the H level.
At the level (paths 2 and 3), the waveform is c.

Therefore, it is better to apply the H level to SELECT1 to operate CK1 and CK2.
, The output waveform has a lower slew rate than when CK3 and CK4 are operated.

That is, when the H level is input to SELECT1, the output waveform becomes the waveform d in FIG.
When ELECT2 is at the H level, the output waveform is the waveform c.

[0106]

As described above, the output buffer circuit of the present invention is driven by the pre-driver for receiving the data signal, the resistor for delaying the output signal of the pre-driver, and the pre-driver via the resistor. An output transistor, a simultaneous cut-off control means for uniquely inactivating the output transistor with the logic-level low-level or high-level data signal, and a predetermined first slew-rate selection signal is activated. When the high-level or low-level data signal is used, the output transistor is also uniquely activated and conduction control means for invalidating the output of the resistance element is connected to a series-connected P-channel constituting the output transistor. Interposed between each gate electrode of the N-channel and N-channel transistors, One of the P-channel type and N-channel type transistors inactivated by the simultaneous cutoff control means is controlled in a low slew rate direction by the resistance element output, and is controlled in a high slew rate direction by the conduction control means. Therefore, when performing slew rate adjustment with a wide width, such as optimizing the slew rate of the output waveform according to the magnitude of the output terminal load during actual use, or filling in the slew rate difference due to variations after manufacturing, etc. Even when transistors of the same size are used, a wider slew rate can be adjusted.

In other words, the load on the transistor driving the output transistor is reduced because the resistance is canceled by the slew rate selection circuit. As a result, the total transistor size of the pre-driver and the conduction control transistor in the slew rate selection circuit may be small. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram according to a first embodiment of the present invention.

FIG. 2 is an output operation waveform diagram of the output buffer circuit according to the first embodiment.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a third embodiment of the present invention.

FIG. 5 is an output operation waveform diagram of the output buffer circuit according to the third embodiment.

FIG. 6 is a circuit diagram of a conventional low slew rate output buffer circuit.

FIG. 7 is a circuit diagram of a conventional example using a pre-driver adjustment method.

FIG. 8 is a circuit diagram of another conventional example.

[Explanation of symbols]

D1, D2, D9, D10 Pre-driver D3, D4, D5 D6, D7, D8, D11, D12,
D13 Inverter PM01, PM02, PM03, P01, P02, P0
3, P04, P05 P-channel type transistors NM01, NM02, NM03, N01, N02, N0
3, N04, N05 N-channel transistors PA01, PA02, PA03, NA01, NA02,
NA03 Simultaneous cutoff control transistors PT01, PT02, PT03, NT01, NT02,
NT03 conduction control transistors PS01, PS02, PS03, NS01, NS02,
NS03 Selection control transistor SELECT1, SELECT2 Slew rate selection signal S1, S2, S11, S21 Selection control signal IN1, IN2 Data signal OUT Output terminal CK1, CK2, CK3, CK4 Slew rate selection circuit R11, R12, R13, R14, R21, R22, R
23, R24 resistance element

Claims (12)

[Claims] A pre-driver for receiving a data signal; a resistance element for delaying an output signal of the pre-driver; an output transistor driven by the pre-driver via the resistance element; A simultaneous cut-off control means for inactivating the data signal at a low level or a high level, and a high level or a low level when the first slew rate selection signal is activated. A conduction control means for uniquely activating the output transistor and invalidating the output of the resistance element, for each gate electrode of a series-connected P-channel type transistor and an N-channel type transistor constituting the output transistor; By intervening, the simultaneous shutoff control means deactivated An output buffer circuit for a semiconductor device, wherein one of a P-channel type transistor and an N-channel type transistor is controlled in a low slew rate direction by the resistance element output, and is controlled in a high slew rate direction by the conduction control means. 2. The output buffer circuit of a semiconductor device according to claim 1, wherein a plurality of sets of said resistance element, said simultaneous cutoff control means, said conduction control means, and said output transistor are connected in parallel. 3. The conduction control means on the side of the P-channel transistor is uniquely activated by only a second selection control signal, and the second selection control signal has a polarity of the first slew rate selection signal. The output signal of the pre-driver on the side of the P-channel type transistor constituting the output transistor is selected by the inverted signal, and the conduction control means on the side of the N-channel type transistor is uniquely activated only by the third selection control signal. And the third selection control signal is a signal generated by selecting the output signal of the pre-driver on the side of the N-channel transistor constituting the output transistor with the first slew rate selection signal. An output buffer circuit of the semiconductor device according to claim 1. 4. A plurality of sets of slew rate selection signals are provided as control signals for independently controlling each of the plurality of sets, and the plurality of sets of slew rate selection signals are individually activated from a predetermined external or internal control unit. 3. The output buffer circuit of a semiconductor device according to claim 2, wherein said output buffer circuit is a slew rate selection signal capable of controlling the conversion. 5. A plurality of sets of slew rate selection signals, each of which can be individually activated, are output at the lowest slew rate when they are at one level, and are at the highest slew rate when both slew rate selection signals are at the other level. 5. The output buffer circuit according to claim 4, wherein the output signal is a slew rate signal obtained by subdividing the lowest slew rate and the highest slew rate according to a combination of other levels of the slew rate selection signal. . 6. A pre-driver for receiving a first data signal, a second pre-driver for receiving a second data signal, a first P-channel transistor and a first N-channel transistor.
A first resistor for signal delay, interposed between a pair of output transistors formed by connecting channel type transistors in series and the first pre-driver means and a gate electrode of the first P-channel type transistor An element, first slew rate selecting means for canceling the resistance element, a first cutoff control transistor for cutting off conduction of the first P-channel transistor in response to the first data signal, and a second cutoff control transistor. A second resistor element for signal delay interposed between the pre-driver means and the gate electrode of the first N-channel transistor, a second slew rate selecting means for canceling the resistance element, and the second An output circuit comprising: a second shut-off control transistor for shutting off the conduction of the second N-channel transistor in response to the data signal of No. 2; And a plurality of sets of the output circuits are connected in parallel to the corresponding first and second pre-driver means, and the first and second slew rates are responsive to a predetermined selection control signal. An output buffer circuit for a semiconductor device, comprising: controlling slew rate adjustment of an output of the output circuit in response to an output signal of a selection unit. 7. A first pre-driver receiving a first data signal, a second pre-driver receiving a second data signal, a P-channel transistor and an N-channel transistor connected in series, and the serial connection point , A second output transistor commonly connected to an output terminal, and a series connection between the first and second pre-driver output terminals and a corresponding gate electrode of the third output transistor. First and second resistance elements and third and fourth resistance elements to be connected, a simultaneous cutoff control transistor, a conduction control transistor, and a selection control transistor inserted in series between a power supply potential and a ground potential A first, a second, a third and a fourth series-connected body comprising: a P-channel transistor and an N-channel transistor of the first output transistor; The first and second pre-driver output terminals respectively corresponding to the gate electrodes of the channel type transistors are connected to correspond to the gate electrodes of the P-channel type transistor and the N-channel type transistor of the second output transistor, respectively. The first and second series-connected bodies are connected at the same time to the series connection points of the simultaneous cutoff control transistor and the conduction control transistor, respectively, and the gate electrode of the P-channel transistor is further connected to the first and second transistors. A series connection point of the resistance element is further connected to a gate electrode of the N-channel transistor, and a series connection point of the third and fourth resistance elements is further connected.
Connecting the series connection points of the simultaneous cutoff control transistor and the conduction control transistor of the third and fourth series connection bodies respectively corresponding to the gate electrodes of the channel type transistor and the N channel type transistor,
The first slew rate selection signal is applied to the gate electrodes of the selection control transistors of the first and third series-connected bodies, and the gate electrodes of the selection control transistors of the second and fourth series-connected bodies are set to the gate electrodes of the second and fourth series-connected bodies. Is a configuration in which a polarity inversion signal of the first slew rate selection signal is provided, respectively. 8. A simultaneous cut-off control transistor and a selection control transistor inserted in series between a power supply potential and a ground potential instead of the first, second, third and fourth series-connected bodies. And a fifth, sixth, seventh and eighth series-connected body comprising a transistor.
An OR circuit which takes a logic of a polarity inversion signal of the first slew rate selection signal and the first pre-driver output signal, as a circuit for generating a slew rate selection signal to be given to the selection control transistor of the series-connected body of The logic of the first slew rate selection signal and the second pre-driver output signal is used as a circuit for generating a slew rate selection signal to be given to the selection control transistors of the second and fourth series-connected bodies. 8. A circuit according to claim 7, further comprising an AND circuit.
An output buffer circuit of the semiconductor device according to claim 1. 9. A transistor having the simultaneous cut-off control means and the conduction control means and having the same transistor size of each of the plurality of output transistors connected in parallel, wherein the size of the transistor constituting the pre-driver is reduced. 8. The output buffer circuit of a semiconductor device according to claim 7, wherein said output buffer circuit is set in advance to have the same value as the size of a constituent transistor of said simultaneous cutoff control means and said conduction control means. 10. The semiconductor device according to claim 1, further comprising third to eighth resistance elements in addition to said first and second resistance elements.
Instead of the fourth series connection body, a simultaneous cutoff control transistor inserted in series between a power supply potential and a ground potential, the third or fourth resistance element, a conduction control transistor, and a selection control transistor. And the other end of the first resistance element, one end of which is connected to the output end of the first pre-driver, and the other end of the fifth series connection The other end of the second resistance element is connected to a series connection point of a fifth resistance element and the conduction control transistor, and one end is connected to an output terminal of the second pre-driver. Is connected to a series connection point of the sixth resistance element and the conduction control transistor, and one end of the third resistance element is connected to the simultaneous cutoff control transistor and the fifth resistance element of the fifth series connection body. Series connection The other end is connected to a series connection point of the seventh resistance element and the conduction control transistor of the seventh series connection body, and one end of the fourth resistance element is connected to the sixth series connection. The other end is connected to the series connection point of the eighth resistance element and the conduction control transistor of the eighth series connection body. The other end of the seventh resistance element is connected to the gate electrode of a P-channel transistor of the third output transistor, and the other end of the eighth resistance element is connected to the third output transistor. A second slew rate selection signal, which is connected to a gate electrode of an N-channel transistor and is provided to the selection control transistor of the seventh series connection body, as a slew rate selection signal; The output buffer circuit of a semiconductor device according to claim 7, further comprising a polarity inverted signal of the as slew rate selection signal a second slew rate selection signal given to 8 the selection control transistor of the series connection of. 11. The resistance value of each of the first and third resistance elements is made equal, the resistance value of each of the second and fourth resistance elements is made equal, and the first or third resistance element is made equal. 11. The output buffer circuit of a semiconductor device according to claim 10, wherein the resistance value of said resistance element is set in advance to be approximately twice the resistance value of said second or fourth resistance element. 12. A configuration in which only one inverter and a plurality of resistance elements are provided in a cascade connection in a signal path from an input terminal of the pre-driver to an output transistor, so that data delay is applied only to the resistance elements. 11. The output buffer circuit for a semiconductor device according to claim 7, wherein the element size is formed in advance.