CN114189151B - DC-DC boost converter - Google Patents

DC-DC boost converter Download PDF

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Publication number
CN114189151B
CN114189151B CN202010966600.9A CN202010966600A CN114189151B CN 114189151 B CN114189151 B CN 114189151B CN 202010966600 A CN202010966600 A CN 202010966600A CN 114189151 B CN114189151 B CN 114189151B
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Prior art keywords
control signal
tube
boost converter
power tube
switching tube
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CN202010966600.9A
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CN114189151A (en
Inventor
肖飞
于翔
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SG Micro Beijing Co Ltd
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SG Micro Beijing Co Ltd
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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses a DC-DC boost converter, comprising: the first power tube, the second power tube and the inductor are used for boosting and outputting the input voltage received by the input end of the boost converter based on the first control signal and the second control signal; further comprises: the grid driving circuit is respectively connected with the grid of the first power tube and the grid of the second power tube and is used for respectively providing a first control signal for the first power tube and a second control signal for the second power tube, wherein the first control signal controls the first power tube to be turned off and then turned on in a delayed manner after the second control signal controls the second power tube to be turned on. The boost converter disclosed by the invention can avoid the condition that the first power tube and the second power tube in the boost converter are simultaneously conducted, and meanwhile, the efficiency of a boost converter chip is not influenced.

Description

DC-DC boost converter
Technical Field
The invention relates to the technical field of DC-DC conversion power supplies, in particular to a DC-DC boost converter.
Background
In order to supply a direct current voltage inputted to an Active Matrix Organic Light Emitting Diode (AMOLED) panel, it is necessary to change a level of the direct current input voltage supplied from a battery or a predetermined direct current power source to a direct current output voltage suitable for the above active matrix organic light emitting diode panel, which can be performed by a DC-DC boost converter.
Alternatively, in order to provide a DC output voltage to be input to a battery charged when wireless charging is performed, it is necessary to change the level of the DC input voltage provided by the wireless charging device to a DC output voltage suitable for the battery, and this function may be performed by a DC-DC boost converter.
In addition, there are a variety of applications for applying DC-DC boost converters. DC-DC boost converters are mainly used in portable electronic devices such as cellular phones and notebook computers powered by batteries. Such electronic devices typically include several sub-circuits, but each sub-circuit has its own voltage level requirements, and such voltage levels are different from those provided by the battery.
The traditional DC-DC boost converter comprises two MOS tubes such as double NMOS power tubes, but the double MOS tubes can be conducted simultaneously under certain conditions, so that the false output or efficiency reduction and even damage of the boost converter chip can be caused.
The existing solution is to make non-overlapping treatment on control signals of two MOS tubes, so as to avoid simultaneous conduction of the two MOS tubes.
Accordingly, there is a need to provide an improved solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In order to solve the technical problems, the invention provides a DC-DC boost converter, which can avoid the condition that two NMOS switching tubes in the boost converter are simultaneously conducted, and simultaneously does not influence the on-resistance and the chip efficiency of the switching tubes in the boost converter.
According to the present invention, there is provided a DC-DC boost converter comprising: the first power tube, the second power tube and the inductor are sequentially connected in series between the output end and the grounding end of the boost converter; the inductor is connected between the input end of the boost converter and a connection node of the first power tube and the second power tube, and the inductor, the first power tube and the second power tube are used for boosting and outputting the input voltage received by the input end based on a first control signal and a second control signal;
the boost converter further includes: the grid driving circuit is respectively connected with the grid of the first power tube and the grid of the second power tube and is used for respectively providing the first control signal for the first power tube and the second control signal for the second power tube, wherein the first control signal controls the first power tube to be turned on after the second control signal controls the second power tube to be turned off.
Preferably, the first power transistor and the second power transistor are both NMOS transistors.
Preferably, the gate driving circuit further includes: a first inverter, the input end of which receives an initial control signal; the input end of the second inverter receives the initial control signal; the input end of the delay unit is connected with the output end of the first inverter and is used for carrying out delay output on the output signal of the first inverter; the first switching tube receives the power supply voltage, the second channel end outputs the first control signal, and the control end is connected with the output end of the delay unit; the second switching tube, the first access end receives the supply voltage, the second access end outputs the said first control signal, the control end is connected with output end of the said first inverter; and the first passage end of the third switching tube is connected with the second passage end of the first switching tube, the second passage end is grounded, and the control end is connected with the output end of the second inverter.
Preferably, the first switching transistor and the second switching transistor are PMOS transistors, and the third switching transistor is an NMOS transistor.
Preferably, the delay unit is a buffer.
Preferably, the delay unit comprises a plurality of inverters connected in series.
Preferably, the delay unit is a resistor-capacitor delay network, including: the first end of the first resistor is connected with the input end of the delay unit, and the second end of the first resistor is connected with the output end of the delay unit; the first capacitor is connected between the second end of the first resistor and the grounding end.
Preferably, when the first switch tube is turned off and the second switch tube is turned on, the rising edge time of the first control signal is the same as the delay time of the delay unit, and the rising speed of the rising edge of the first control signal is positively correlated with the size of the second switch tube; when the first switching tube and the second switching tube are both conducted, the rising speed of the rising edge of the first control signal is positively correlated with the size of the first switching tube.
Preferably, the second switching tube has a smaller size than the first switching tube.
Preferably, when the first switching tube is turned off and the second switching tube is turned on, the rising edge time of the first control signal is the same as the delay time of the delay unit and is longer than the rising edge time of the first control signal when both the first switching tube and the second switching tube are turned on.
The beneficial effects of the invention are as follows: the invention discloses a DC-DC boost converter, which realizes boost output of input voltage through combination of a first power tube, a second power tube and an inductor, and meanwhile, in the boost process, a grid driving circuit connected with a grid electrode of the first power tube outputs a first control signal to control the first power tube to be conducted for a period of time after the second power tube controlled by a second control signal is turned off, under the premise of not changing an initial control signal of the grid driving circuit, the condition that the first power tube is conducted when the grid electrode of the second power tube is coupled to cause the conduction of the second power tube when the voltage at a connecting node of the first power tube and the second power tube rises is avoided, and further, the situation that the chip of the boost converter is erroneously output or the efficiency of the boost converter is reduced due to the simultaneous conduction of the two switch tubes is avoided, and the chip of the boost converter is prevented from being damaged.
The first control signal output by the grid driving circuit is controlled to be delayed to be conducted by the mode of adding the delay unit and the second switching tube in the grid driving circuit, the circuit structure is simple, and meanwhile, the first power tube can be driven to be firstly driven, then the first power tube is driven in a grading mode, the first power tube is delayed to be conducted, the normal work of the boost converter is not influenced, and the working efficiency of the boost converter is guaranteed.
The delay unit in the grid driving circuit has a plurality of selectable circuit structures, and can meet different scene requirements.
In the grid driving circuit, the size of the second switching tube is smaller than that of the first switching tube, and the first power tube is driven by a first control signal provided by the pilot conduction of the second switching tube with a small size, so that the condition that the first power tube and the second power tube are simultaneously conducted in the working process of the boost converter is avoided. After a period of delay, the first switch tube with the size larger than that of the second switch tube is conducted, and the first control signal with the rising speed fast enough to the rising edge is provided by combining the second switch tube to drive the first power tube to conduct, so that the conduction impedance of the first power tube in the circuit is not influenced, and further the working efficiency of the boost converter chip is not influenced when the first power tube and the second power tube are prevented from being conducted simultaneously.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.
FIG. 1 shows a partial circuit block diagram of a DC-DC boost converter;
FIG. 2 shows a circuit block diagram of a gate drive circuit of a switching tube in a prior art DC-DC boost converter;
fig. 3 shows a circuit configuration diagram of a gate driving circuit of a switching tube in a DC-DC boost converter provided according to an embodiment of the present invention;
fig. 4 is a timing chart of a control signal provided by the gate driving circuit according to an embodiment of the invention.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The specific voltage values shown in the embodiments described below are specific for convenience of explanation, and it should be noted that the idea of the present invention will be maintained even if the voltage values are changed.
The present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 shows a partial circuit configuration diagram of a DC-DC boost converter.
As shown in fig. 1, in this embodiment, the DC-DC boost converter or chip mainly includes: the switch pin is connected with an input voltage through an inductor; an enable pin for determining whether the boost converter or the chip is turned on by an external input high/low level; the output pin is used for outputting fixed (such as 5V) output voltage after the input voltage is boosted; the ground pin provides a reference ground for the entire chip.
The DC-DC boost converter internal circuit includes: first power transistor MNHS, second power transistor MNLS, inductance L1, and gate drive circuit 100. The first power tube MNHS and the second power tube MNLS are sequentially connected in series between an output end Vout and a ground end of the DC-DC boost converter, a first end of the inductor L1 is connected with an input end of the DC-DC boost converter to receive an input voltage Vin, and a second end of the inductor L1 is connected with a connection node SW of the first power tube MNHS and the second power tube MNLS. The input voltage Vin is input to the connection node SW of the first power transistor MNHS and the second power transistor MNLS after passing through the inductor L1, i.e. the switch pin of the aforementioned chip.
Further, the inductor L1, the first power transistor MNHS and the second power transistor MNLS are configured to boost the input voltage Vin received by the input terminal based on the first control signal and the second control signal. In one embodiment of the present invention, the first power transistor MNHS and the second power transistor MNLS are NMOS transistors.
The Gate driving circuit 100 is connected to the Gate of the first power transistor MNHS and the Gate of the second power transistor MNLS, respectively, and is configured to provide a first control signal hs_gate to the first power transistor MNHS and a second control signal ls_gate to the second power transistor MNLS, respectively.
In order to make the DC-DC boost converter work normally, the first control signal hs_gate and the second control signal ls_gate should be able to be generated in a manner of respectively periodically switching high level and low level to respectively control the first power transistor MNHS and the second power transistor MNLS not to be turned on at the same time. In an embodiment of the invention, the first control signal hs_gate and the second control signal ls_gate may have complementary values. The value of the output voltage of the DC-DC boost converter may be different when the duty ratio of the control signal is defined according to the proportion of the length of time for which the on state, i.e., the off state, of the first power transistor MNHS and the second power transistor MNLS is maintained based on the first control signal hs_gate and the second control signal ls_gate, respectively.
The boosting process of a DC-DC boost converter includes the following: first, the gate driving circuit 100 controls the first power transistor MNHS to be turned off and controls the second power transistor MNLS to be turned on. At this time, the first control signal hs_gate may be at a low level, the second control signal ls_gate may be at a high level, and a current formed based on the input voltage Vin in the circuit flows through the second power transistor MNLS, and the potential at the node SW is 0.
Then, the gate driving circuit 100 controls the first power transistor MNHS to be turned on and controls the second power transistor MNLS to be turned off. At this time, the first control signal hs_gate may be at a high level, the second control signal ls_gate may be at a low level, and a current formed based on the input voltage Vin in the circuit flows through the first power transistor MNHS. In the section of the circuit portion shown in fig. 1 in which the power transistor performs state transition, the continuity of the current flowing in the inductor L1 is ensured, the potential at the node SW is gradually pulled up, and finally the potential of the output terminal Vout is gradually increased.
It should be noted that, in an embodiment of the present invention, the Gate driving circuit 100 may provide the first control signal hs_gate based on the initial control signal, and then convert the first control signal hs_gate to provide the second control signal ls_gate, or provide an intermediate signal during the first control signal hs_gate based on the initial control signal as the second control signal ls_gate. In another embodiment of the present invention, the Gate driving circuit 100 may include a first Gate driving control module and a second Gate driving control module, wherein the first Gate driving control module provides a first control signal hs_gate based on an initial control signal, and the second Gate driving control module provides a second control signal ls_gate based on the initial control signal.
It is understood that the internal circuit structure of the DC-DC boost converter may further include an internal power supply selection module, an internal reference and bias module, an inductor current detection resistor, a leading edge blanking unit, an overcurrent protection module, a PWM (pulse width modulation) comparison module, a control logic and a driving module. The DC-DC boost converter comprises an oscillator, an enabling module, an idle detection comparison module, an input voltage feedback voltage dividing resistor, an output voltage feedback voltage dividing resistor, a control switch and the like, so that stable and safe operation of the DC-DC boost converter is realized. Some internal circuit structures of the DC-DC boost converter do not affect the solution of the technical problem in the present application, and will not be described herein.
The following mainly describes the circuit configuration of the gate drive circuit in the DC-DC boost converter and the corresponding operation principle with the first power transistor MNHS and the second power transistor MNLS.
Fig. 2 shows a circuit configuration diagram of a gate driving circuit of a switching tube in a DC-DC boost converter in the prior art.
In the existing DC-DC boost converter, a circuit structure for providing a first control signal hs_gate portion in a Gate driving circuit includes: the first inverter U1, the second inverter U2, the first switching tube MP1 and the third switching tube MN1. The input end of the first inverter U1 and the input end of the second inverter U2 both receive an initial control signal hs_on, the output end of the first inverter U1 is connected to the control end of the first switching tube MP1, the output end of the second inverter U2 is connected to the control end of the third switching tube MN1, the first switching tube MP1 and the third switching tube MN1 are sequentially connected in series between the power supply end VCC and the ground end, and at the same time, the connection node of the first switching tube MP1 and the third switching tube MN1 outputs a first control signal hs_gate.
It can be understood that the circuit structure of the Gate driving circuit for providing the second control signal ls_gate part may be that an inverter is added between the connection nodes of the first switching tube MP1 and the third switching tube MN1 and the output end of the first control signal hs_gate, and the first control signal hs_gate generates the second control signal ls_gate after passing through the inverter based on the circuit structure shown in fig. 2; or the first control signal hs_gate is generated at the connection junction of the two other switching tubes like the first switching tube MP1 and the third switching tube MN1, which are directly driven by the initial control signal hs_on. It should be noted that, in actual operation, the control signals received by the first switching tube MP1 and the third switching tube MN1 (i.e., the output signal of the first inverter U1 and the output signal of the second inverter U2) need to be processed in a non-overlapping manner, so as to avoid the situation that the first switching tube MP1 and the third switching tube MN1 are turned on simultaneously. Meanwhile, the control signals received by the other two switching tubes similar to the first switching tube MP1 and the third switching tube MN1 are processed in the same way.
Further, referring to fig. 1, when the second power tube MNLS is turned off and the first power tube MNHS is turned on, due to the parasitic capacitance C1 of the second power tube MNLS, the rising edge of the node SW is coupled to the gate of the second power tube MNLS, so that the first power tube MNHS is turned on and the second power tube MNLS is turned on at the same time, at this time, a large current flows from the output end Vout into the ground end through the first power tube MNHS and the second power tube MNLS, which reduces the efficiency of the chip and even damages the chip.
In the conventional Gate driving circuit, the size of the first switch tube Mp1 determines the rising edge speed of the first control signal hs_gate, and the rising speed of the first control signal hs_gate determines the rising speed of the node SW, so as to determine the time for simultaneously conducting the first power tube MNHS and the second power tube MNLS. When the size of the first switch tube Mp1 is very small, the first power tube MNHS and the second power tube MNLS can be prevented from being turned on simultaneously, but the impedance of the first power tube MNHS can be increased, so that the boosting efficiency of the boost converter is affected. If the size of the first switch tube Mp1 is large, the first power tube MNHS and the second power tube MNLS are turned on simultaneously.
Therefore, the embodiment of the invention improves the circuit structure of the gate driving circuit as shown in fig. 3 on the basis of the circuit structure shown in fig. 2 to solve the technical problems.
Fig. 3 is a circuit diagram of a gate driving circuit of a switching tube in a DC-DC boost converter according to an embodiment of the present invention, and fig. 4 is a timing chart of a control signal provided by the gate driving circuit according to an embodiment of the present invention.
As shown in fig. 3, in the present embodiment, the gate driving circuit 100 includes: the circuit comprises a first inverter U1, a second inverter U2, a delay unit 10, a first switching tube MP1, a second switching tube MP2 and a third switching tube MN1. The input end of the first inverter U1 and the input end of the second inverter U2 both receive an initial control signal hs_on, the output end of the first inverter U1 is connected with the input end of the delay unit 10, the output end of the delay unit 10 is connected with the control end of the first switching tube MP1, the output end of the second inverter U2 is connected with the control end of the third switching tube MN1, the first path end of the first switching tube MP1 is connected with the power supply end VCC, the second path end of the first switching tube MP1 is connected with the first control signal output end to output the first control signal hs_gate, the first path end of the second switching tube MP2 is connected with the first control signal output end to output the first control signal hs_gate, the first path end of the third switching tube MN1 is connected with the second path end of the first switching tube MP1, and the second path end of the third switching tube MN1 is connected with the ground. The connection node of the first switching tube MP1 and the third switching tube MN1 is a first control signal output end, so as to output a first control signal hs_gate.
In this embodiment, the first control signal hs_gate provided by the Gate driving circuit 100 controls the first power transistor MNHS to be turned on after the second control signal ls_gate controls the second power transistor MNLS to be turned off. And further, the situation that after the second power tube MNLS is turned off, the first power tube MNLS is also turned on when the second power tube MNLS is turned on again due to the fact that the grid electrode of the second power tube MNLS is coupled when the voltage at the connection node SW of the first power tube MNLS and the second power tube MNLS is increased is avoided, and on the premise that an initial control signal of a grid driving circuit is not changed, wrong output or efficiency reduction of a boost converter chip caused by the fact that two switch tubes are simultaneously turned on is avoided, and the boost converter chip can be prevented from being damaged.
Further, the first switch tube MP1 and the second switch tube MP2 are PMOS transistors, and the third switch tube MN1 is an NMOS transistor.
Note that fig. 3 described above only shows a circuit configuration of the Gate driving circuit 100 in which the first control signal hs_gate output section is provided. In one embodiment of the present invention, the Gate driving circuit 100 may provide the first control signal hs_gate based on the initial control signal, and then use an intermediate signal in the process of providing the first control signal hs_gate based on the initial control signal as the second control signal ls_gate. In yet another embodiment of the present invention, the Gate driving circuit 100 may include a first Gate driving control module and a second Gate driving control module, wherein the first Gate driving control module provides the first control signal hs_gate based on the initial control signal, and the second Gate driving control module provides the second control signal ls_gate based on the initial control signal.
Further, the delay unit 10 is one of a buffer, a plurality of series connected inverters/NOT gates (even number) and a resistor-capacitor delay network. And when the delay unit 10 is a resistor-capacitor delay network, it includes a first resistor and a first capacitor. The first end of the first resistor is connected to the input end of the delay unit 10 (i.e., the output end of the first inverter U1), the second end of the first resistor is connected to the output end of the delay unit 10 (i.e., the control end of the first switching tube MP 1), and the first capacitor is connected between the second end of the first resistor and the ground end. In this embodiment, the delay unit 10 of the gate driving circuit 100 has a plurality of selectable circuit structures, and can meet different scene requirements.
The first control signal HS_Gate output by the Gate driving circuit 100 is used for controlling the delay conduction of the first power tube MNCS by adding the delay unit 10 and the second switch tube MP2 in the Gate driving circuit, so that the circuit structure is simple, and meanwhile, the hierarchical driving of a part of the first power tube MNCS and the other part of the first power tube MNCS can be realized when the first power tube MNCS is driven, the normal operation of the boost converter is not influenced while the delay conduction of the first power tube MNCS is realized, and the working efficiency of the boost converter is ensured.
Referring to fig. 1, 3 and 4, the rising edge of the first control signal hs_gate outputted from the Gate driving circuit 100 includes two parts, i.e., a t1 period and a t2 period.
When the initial control signal hs_on is at a high level, the first inverter U1 and the second inverter U2 both output a low level, and at this time, in the period t1, the first switching tube MP1 and the third switching tube MN1 are both controlled to be in an off state, and the second switching tube MP2 is controlled to be in an on state, and at this time, the first control signal hs_gate is provided from the power supply terminal VCC through the second switching tube MP2 at the output terminal of the Gate driving circuit 100. Because the size of the second switch tube MP2 is small, the rising edge of the first control signal hs_gate has small amplitude, and in this period, even if the second power tube MNLS is conductive due to the coupling of the rising edge of the voltage at the node SW, the first power tube MNHS is still in a non-conductive or slightly conductive high-impedance state in this period, so that the situation that the first power tube MNHS and the second power tube MNLS are conductive at the same time is well avoided.
At this time, in the period t2, the first switch tube MP1 is also turned on, and the power supply end VCC passes through the first switch tube MP1 and the second switch tube MP2 at the same time to provide the first control signal hs_gate at the output end of the Gate driving circuit 100, so that the rising speed, i.e. the amplitude of the rising edge of the first control signal hs_gate changes faster, and the period t2 is fast enough, so that the on-resistance of the first power tube MNHS is not affected, and the working efficiency of the chip is not affected.
Further, when the first switch tube MP1 is turned off and the second switch tube MP2 is turned on, the rising edge time of the first control signal hs_gate, i.e. the time period t1, is the same as the delay time of the delay unit 10, and at this time, the rising speed of the rising edge of the first control signal hs_gate is positively correlated with the size of the second switch tube MP2 (i.e. the smaller the size of the second switch tube MP2, the slower the rising speed of the rising edge of the first control signal hs_gate in the time period t 1). When both the first switch tube MP1 and the second switch tube MP2 are turned on, the rising speed of the rising edge of the first control signal hs_gate is positively correlated with the size of the first switch tube MP1 (i.e., the larger the size of the first switch tube MP1 is, the more the rising speed of the rising edge of the first control signal hs_gate is in the t1 time period). Therefore, by reasonably selecting the sizes of the second switching tube MP2 and the first switching tube MP1, the effect of avoiding the simultaneous conduction of the first power tube MNCS and the second power tube MNLS is better, and the working efficiency and the quality of the DC-DC boost converter can be better ensured.
In this embodiment, for the control signals (i.e., the output signal of the first inverter U1 and the output signal of the second inverter U2) received by the first switching tube MP1 and the third switching tube MN1 respectively, non-overlapping processing is further required to avoid the situation that the first switching tube MP1 and the third switching tube MN1 are turned on simultaneously, so that the better protection circuit is not damaged. For example, a comparison module may be provided in the circuit to compare the output potential of the first inverter U1 with the output potential of the second inverter U2, and when the high and low states of the two potentials are not identical, the output potential of the first inverter U1 is made identical to the high and low state of the output potential of the second inverter U2 by, for example, pulling down the output signal of the high potential or pulling up the output signal of the low potential, or the like. It can be understood that a corresponding delay device may be further disposed at the output end of the first inverter U1 or the output end of the second inverter U2, so that the output potential of the first inverter U1 is consistent with the high-low state of the output potential of the second inverter U2. The invention is not limited by the comparison.
Preferably, the size of the second switching tube MP2 is smaller than that of the first switching tube MP1, and in this embodiment, the rising edge speed of the first control signal hs_gate in the t1 period is small, and the rising edge speed of the first control signal hs_gate in the t2 period is fast. The second switch tube MP2 with small size is firstly conducted to drive the first power tube MNCS, so that the condition that the first power tube MNCS and the second power tube MNLS are conducted simultaneously in the working process of the boost converter is avoided. After a period of time, the first switch tube MP1 with the size larger than that of the second switch tube MP2 is turned on, and then the first control signal HS_Gate which is fast enough to provide rising speed of rising edge together with the second switch tube MP2 drives the first power tube MNCS to be turned on.
On the other hand, by controlling the delay time of the delay unit 10 in the gate control circuit 100, that is, setting the appropriate on time of the second switching tube MP2 and the delay time of the first switching tube MP1, it can be better ensured that the working efficiency of the boost converter chip is not affected when the first power tube MNHS and the second power tube MNLS are prevented from being simultaneously turned on under the condition of affecting the on resistance of the first power tube in the circuit. Preferably, when the first switching tube MP1 is turned off and the second switching tube MP2 is turned on, the rising edge time (t 1 period) of the first control signal hs_gate is the same as the delay time of the delay unit 10 and is greater than the rising edge time (t 2 period) of the first control signal hs_gate when both the first switching tube MP1 and the second switching tube MP2 are turned on, so as to ensure that the t2 period is sufficiently fast.
In summary, the boost output of the input voltage is realized through the combination of the first power tube, the second power tube and the inductor, meanwhile, in the boost process, the grid driving circuit connected with the grid electrode of the first power tube outputs the first control signal to control the first power tube to be conducted for a period of time after the second power tube controlled by the second control signal is turned off, on the premise that the initial control signal of the grid driving circuit is not changed, the condition that the first power tube is conducted when the grid electrode of the second power tube is coupled to cause the conduction of the second power tube when the voltage at the connecting node of the first power tube and the second power tube rises is avoided, and further, the situation that the boost converter chip is erroneously output or efficiency is reduced due to the fact that the two switch tubes are conducted simultaneously is avoided, and the boost converter chip is not damaged is avoided.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it is apparent that the above examples are only illustrative of the present invention and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present invention.

Claims (10)

1. A DC-DC boost converter, comprising: the first power tube, the second power tube and the inductor,
the first power tube and the second power tube are sequentially connected in series between the output end of the boost converter and the grounding end;
the inductor is connected between the input end of the boost converter and the connection node of the first power tube and the second power tube,
the inductor, the first power tube and the second power tube are used for boosting and outputting the input voltage received by the input end based on a first control signal and a second control signal;
the boost converter further includes:
the grid driving circuit is respectively connected with the grid of the first power tube and the grid of the second power tube and is used for respectively providing the first control signal for the first power tube and the second control signal for the second power tube,
the first control signal controls the first power tube to be turned on in a delay manner after the second control signal controls the second power tube to be turned off;
the rising edge of the first control signal comprises a first time period and a second time period, the rising speed of the rising edge of the first control signal in the first time period is smaller than that in the second time period, and the first power tube is controlled by the first control signal and is in a high impedance state in the first time period.
2. A DC-DC boost converter in accordance with claim 1, wherein said first power transistor and said second power transistor are NMOS transistors.
3. A DC-DC boost converter according to any one of claims 1 and 2, wherein the gate drive circuit further comprises:
a first inverter, the input end of which receives an initial control signal;
the input end of the second inverter receives the initial control signal;
the input end of the delay unit is connected with the output end of the first inverter and is used for carrying out delay output on the output signal of the first inverter;
the first switching tube receives the power supply voltage, the second channel end outputs the first control signal, and the control end is connected with the output end of the delay unit;
the second switching tube, the first access end receives the supply voltage, the second access end outputs the said first control signal, the control end is connected with output end of the said first inverter;
and the first passage end of the third switching tube is connected with the second passage end of the first switching tube, the second passage end is grounded, and the control end is connected with the output end of the second inverter.
4. A DC-DC boost converter according to claim 3, wherein the first and second switching transistors are PMOS transistors and the third switching transistor is an NMOS transistor.
5. A DC-DC boost converter according to claim 3, wherein the delay element is a buffer.
6. A DC-DC boost converter according to claim 3, wherein the delay element comprises a plurality of inverters connected in series.
7. A DC-DC boost converter according to claim 3, wherein the delay element is a resistor-capacitor delay network comprising:
the first end of the first resistor is connected with the input end of the delay unit, and the second end of the first resistor is connected with the output end of the delay unit;
the first capacitor is connected between the second end of the first resistor and the grounding end.
8. A DC-DC boost converter according to claim 3, wherein the rising speed of the rising edge of the first control signal is positively correlated with the size of the second switching tube when the first switching tube is turned off and the second switching tube is turned on;
when the first switching tube and the second switching tube are both conducted, the rising speed of the rising edge of the first control signal is positively correlated with the size of the first switching tube.
9. A DC-DC boost converter in accordance with claim 8, wherein the size of said second switching tube is smaller than the size of said first switching tube.
10. The DC-DC boost converter of claim 8, wherein a rising edge time of said first control signal is the same as a delay time of said delay unit when said first switching tube is turned off and said second switching tube is turned on, and is greater than a rising edge time of said first control signal when both said first switching tube and said second switching tube are turned on.
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