CN105978553A - High speed output driver circuit - Google Patents
High speed output driver circuit Download PDFInfo
- Publication number
- CN105978553A CN105978553A CN201610395870.2A CN201610395870A CN105978553A CN 105978553 A CN105978553 A CN 105978553A CN 201610395870 A CN201610395870 A CN 201610395870A CN 105978553 A CN105978553 A CN 105978553A
- Authority
- CN
- China
- Prior art keywords
- pmos
- nmos tube
- output
- outfan
- connects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
Abstract
The invention discloses a high speed output driver circuit, comprising a prepositioned driving stage and a power tube driving stage. The high speed output driver circuit is characterized in that: between the input terminal IN of the prepositioned driving stage and the output OUT of the power tube driving stage, a driver circuit adopts the diversified technology of the signal path and the distributed and weighting switch driving technology; a signal goes through two different transmission paths for transmission from the input to the output; in the prepositioned driving stage, a combination of two groups of buffers which are different in sizes is adopted; a combination of two groups of output transistors which are different in sizes and correspond to the buffers in the prepositioned driving stage is adopted in the power tube driving stage; the output terminals of the two groups of output transistors are connected in parallel; the prepositioned driving stage activates the transistors of the output driving stage in sequence in order to reduce transmission time delay and reduce an output current changing rate di/di of an output signal changing from one logic state to another logic state while without reducing current driving capability of the output driver.
Description
Technical field
The present invention relates to output driver, particularly to a kind of speedy carding process drive circuit, belong to technical field of integrated circuits.
Background technology
Along with the development of submicron CMOS integrated circuit technique, improving constantly of cmos device operating rate, elder generation
The speed of service entering cmos device has evolved to the scope of 100MHz.Two-forty causes current transformation rate di/dt to be accelerated,
Some side effect produce therewith.Side effect includes crosstalk, transmission line effect, power supply transient and ground wire bounce-back.IC input
Entering output module and carry the responsibility of data communication inside and outside chip, its importance is self-evident.In input/output module, output
The effect of driver is exactly the interior data signal provided of blank film, and produces the output signal driving with extraneous Matching of the interfaces circuit
Off-chip loads thus reaches the purpose of data output, if these side effect are serious, the worst result is the system failure.Therefore,
Quickly processing of data is more and more higher to the requirement of deep sub-micron technique with quickly processing of interface rate.Such as USB interface,
Serial ATA and mnemonic are required for interface at a high speed, and this is accomplished by the output driver of a high speed.In order to improve
Speed, rises, declining switching rate must be sufficiently fast to meet rate request.But, increase switching rate and can cause electric current
Interconversion rate is accelerated, and can cause the above side effect such as ground wire bounce-back in high-speed interface.Rate of change due to charge or discharge electric current
Di/dt depends on the switching rate of output signal, therefore to suppression ground wire bounce-back, it is necessary to reduce switching rate, and then subtract
The rate of change di/dt of little switching current.There is several methods that the switching rate controlling output drive signal is to reduce switching current
Rate of change di/dt, but most of circuit design is based on three main principle: feedback control, digital control, distributed
And weighting technique, the conversion rate control principle of these technology is different.Feedback control controls the output driver of switching rate and leads to
Often it is to provide a good fixing switching rate independent of external loading of designed in advance；Digital control control switching rate
Output driver is to provide a switching rate independent of technique, temperature and change in voltage.Distributed weighting controls conversion speed
The output driver of rate can make the variable of conversion ratio adjust (as by selecting signal), more flexibly.
Summary of the invention
The current transformation rate for the operating frequency that integrated circuit is the highest causes that it is an object of the invention to is accelerated, and produces ground, ground
The problem of the side effect such as line bounce-back, crosstalk, transmission line effect, it is provided that a kind of speedy carding process drive circuit, based on distributed
With weighting Drive technology, the amplitude of ground wire bounce-back can be greatly reduced, the system failure can be prevented effectively from.
For achieving the above object, the present invention takes techniques below scheme: a kind of speedy carding process drive circuit, including before
Putting driving stage and power tube driving stage, the input IN of pre-driver stage accepts the pwm signal of higher level's modulation circuit, front
The output putting driving stage connects power tube driving stage, and the output OUT of power tube driving stage drives off-chip load；Its feature exists
In: from the input IN to the outfan OUT of power tube driving stage of pre-driver stage, drive circuit have employed
The diversified technology of signal path, uses the buffer in combination that two groups of large and small sizes are different in pre-driver stage, meanwhile,
Drive circuit additionally uses distributed and weighted switch actuation techniques, is sequentially activated the transistor of out drive stage, in merit
The same output transistor group using the two group large and small size corresponding from buffer in pre-driver stage different in rate pipe driving stage
Closing, the outfan parallel join of two groups of output transistors that large and small size is different, the output of undersized buffer drives little chi
Very little output transistor gates, the output of large-sized buffer drives large-sized output transistor gates, and signal is from being input to
Export and transmitted by two different transmission path, to realize reducing while not reducing output driver current driving ability passing
Defeated time delay and reduce output signal from a logic state transition be another logic state time output electric current rate of change di/dt,
It addition, in the large scale buffer of pre-driver stage, be provided with dead-time control circuit, to prevent upside in buffer
MOSFET and downside MOSFET simultaneously turns on and produces and puncture；
Pre-driver stage includes two parts circuit, and the output of a part of circuit is for driving the PMOS in power tube driving stage
Output transistor, including the first phase inverter being sequentially connected with, two input nor gates, first large scale buffer and first
Small size buffer；The output of another part circuit, for driving the nmos output transistor in power tube driving stage, is wrapped
Include the second phase inverter, two input nand gates, second large scale buffer and second the small size buffer being sequentially connected with；
Power tube driving stage includes one group of large scale output transistor and one group of small size output transistor, large scale output transistor bag
Including a large-sized PMOS and a large-sized NMOS tube, small size output transistor includes a small size
PMOS and a undersized NMOS tube, the output of first large scale buffer drives large-sized PMOS
Pipe, the output of second large scale buffer drives large-sized NMOS tube, and the output of first small size buffer is driven
Dynamic undersized PMOS, the output of second small size buffer drives undersized NMOS tube.
Described for driving in power tube driving stage in the pre-driver stage of PMOS output transistor, PMOS P4 and
NMOS tube N4 constitutes the first phase inverter, and PMOS P5, P6 and NMOS tube N5, N6 constitute two inputs or non-
Door, PMOS P7 and NMOS tube N7, N8, N9 constitute first large scale buffer, wherein NMOS tube N7,
N8 is dead-time control circuit, and PMOS P8 and NMOS tube N10 constitute first small size buffer；First
In phase inverter, the source electrode of PMOS P4 connects VDD, the source ground of NMOS tube N4, the grid of PMOS P4
The gate interconnection of pole and NMOS tube N4 the input IN as pre-driver stage, the drain electrode of PMOS P4 and NMOS
The drain interconnection of pipe N4 the outfan as the first phase inverter；In two input nor gates, the source electrode of PMOS P5 is even
Meeting VDD, the drain electrode of PMOS P5 connects the source electrode of PMOS P6, and the drain electrode of PMOS P6 connects NMOS
The drain electrode of pipe N5, N6, the source ground of NMOS tube N6, the grid of PMOS P6 connects NMOS tube N6
Grid is as an input of two input nor gates and by resistance R1 ground connection, the grid of PMOS P5 and NMOS
The gate interconnection of pipe N5 the outfan as two another inputs inputting nor gates and the first phase inverter connect,
The source ground of NMOS tube N5, the drain electrode of NMOS tube N5 and the drain interconnection of NMOS tube N6 as two inputs or
The outfan of not gate；In first large scale buffer, the source electrode of PMOS P7 connects VDD, PMOS P7
Drain electrode connects the drain electrode of NMOS tube N7 and as the outfan of first large scale buffer, the source electrode of NMOS tube N7
Connecting the drain electrode of NMOS tube N8, the source electrode of NMOS tube N8 connects the drain electrode of NMOS tube N9, NMOS tube N9
Source ground, the grid of PMOS P7 links together with the grid of NMOS tube N7, N8 and N9 and is connected two
The outfan of input nor gate；In first small size buffer, the source electrode of PMOS P8 connects VDD, PMOS
The drain electrode of pipe P8 connects the drain electrode of NMOS tube N10 and as the outfan of first small size buffer, NMOS tube
The source ground of N10, the grid of PMOS P8 and the gate interconnection of NMOS tube N10 are also connected two input nor gates
Outfan；
Described for driving in power tube driving stage in the pre-driver stage of nmos output transistor, PMOS P9 and
NMOS tube N11 constitutes the second phase inverter, and PMOS P10, P11 and NMOS tube N12, that N13 constitutes two is defeated
Entering NAND gate, PMOS P12, P13, P14 and NMOS tube N14 constitute second large scale buffer, wherein
PMOS P13, P14 are another dead-time control circuit, and PMOS P15 and NMOS tube N16 constitute the
Two small size buffers；In second phase inverter, the source electrode of PMOS P9 connects VDD, the source of NMOS tube N11
Pole ground connection, the grid of PMOS P9 and the gate interconnection of NMOS tube N11 also are connected to drive power tube driving stage
Middle PMOS output transistor pre-driver stage two inputs PMOS P6 grid and NMOS tube N6 grid in nor gate
Interconnection end, the drain electrode of PMOS P9 and the drain interconnection of NMOS tube N11 the outfan as the second phase inverter；
In two input nand gates, PMOS P10, the source electrode of P11 connect VDD, PMOS P10, the drain electrode of P11 and NMOS
The drain electrode connection of pipe N12 the outfan as two input nand gates, the source electrode of NMOS tube N12 connects NMOS tube
The drain electrode of N13, the source ground of NMOS tube N13, the grid of NMOS tube N13 is mutual with the grid of PMOS P10
Continuous cropping is an input of two input nand gates and connects the outfan of the first phase inverter, the grid of NMOS tube N12 with
The gate interconnection of PMOS P11 is as another inputs of two input nand gates and connects the outfan of the second phase inverter；
In second large scale buffer, the source electrode of PMOS P12 connects VDD, and the drain electrode of PMOS P12 connects PMOS
The source electrode of pipe P13, the drain electrode of PMOS P13 connects the source electrode of PMOS P14, and the drain electrode of PMOS P14 is even
Connect the drain electrode of NMOS tube N14 and as the outfan of second large scale buffer, the source ground of NMOS tube N14,
The grid of NMOS tube N14 links together with the grid of PMOS P12, P13, P14 and is connected two input nand gates
Outfan；In second small size buffer, the source electrode of PMOS P15 connects VDD, the leakage of PMOS P15
Pole connects the drain electrode of NMOS tube N15 and as the outfan of second small size buffer, the source electrode of NMOS tube N15
Ground connection, the grid of PMOS P15 and the gate interconnection of NMOS tube N15 the outfan being connected two input nand gates；
Described power tube driving stage includes one group of large scale output transistor and one group of small size output transistor, and small size exports
Transistor includes PMOS P1 and NMOS tube N1, and the source electrode of PMOS P1 connects VDD, PMOS P1
Drain electrode connect the drain electrode of NMOS tube N1 and as the outfan of this group small size output transistor, NMOS tube N1
Source ground, the grid of PMOS P1 connects the outfan of first small size buffer, the grid of NMOS tube N1
Pole connects the outfan of second small size buffer；Large scale output transistor include pipe include PMOS P2 and
NMOS tube N2, the source electrode of PMOS P2 connects VDD, and the drain electrode of PMOS P2 connects NMOS tube N2
Drain electrode the outfan as this group large scale output transistor, the source ground of NMOS tube N2, PMOS P2
Grid connects the outfan of first large scale buffer, and the grid of NMOS tube N2 connects second large scale buffer
Outfan, the outfan of small size output transistor links together collectively as merit with the outfan of large scale output transistor
The outfan OUT of rate pipe driving stage also can pass through resistance R2 ground connection, by uncertain signal by resistance clamped
Low level.
For the impact preventing electrostatic that chip internal circuits is likely to result in, it is provided with ESD electrostatic discharge protective circuit, including PMOS
Pipe P3 and NMOS tube N3, the grid of PMOS P3 interconnects and is connected VDD with source electrode, the grid of NMOS tube N3
The interconnection of pole and source electrode ground connection, the drain electrode of PMOS P3 and the drain interconnection of NMOS tube N3 are also connected power tube driving
The outfan OUT of level.
Advantages of the present invention and remarkable result: the diversified technology and the distributed and weighting that have employed signal path in the present invention are opened
Closing actuation techniques, owing to various sizes of signal buffer is used, signal is from input node IN to output node OUT
Path transmission by two different transmission delays.Undersized signal buffer has little transmission delay, but owing to it is little
Current driving ability cause big rise/fall time.Otherwise, large-sized signal buffer has big transmission delay,
But owing to its current driving ability is big, so rise/fall time is little.One small size and large scale signal buffer
Appropriately combined can reduce transmission delay T while big current driving ability is provideddWith rise/fall time Tr/f.Separately
In the present invention, in order to prevent upside MOSFET and downside MOSFET from simultaneously turning on, i.e. the generation of breakdown problem,
Dead band time interval is inserted between large-sized gate drive signal.In dead band interim, upside MOSFET and under
Side MOSFET simultaneously turns off, and electric current is flowed by the body diode of MOSFET.Dead Time generation module is led in upside
Logical turn on downside between provide a blank time, it is to avoid the upper side and lower side MOSFET simultaneously turns on and causes and hit
Wear problem.The present invention reduces transmission delay while providing big current driving ability, and then reduces the switch of whole signal
Time.Using distributed and weighted switch actuation techniques, out drive stage is by two groups of various sizes of PMOS and NMOS
Realize.Their output connects together, and the gate input of PMOS and NMOS is connected to two and varies in size simultaneously
The outfan of signal buffer.Present invention decreases the rate of change di/dt of switching current, greatly reduce ground wire bounce-back
Amplitude, effectively prevent the system failure.
Accompanying drawing explanation
Fig. 1 output buffer structured flowchart；
The diversified technology of Fig. 2 signal path；
Fig. 3 is distributed and weighted switch driver；
Fig. 4 output driver circuit of the present invention schematic diagram.
Detailed description of the invention
Fig. 1 is general output driver circuit structure chart.When the output of a circuit to drive a load capacitance the biggest
Time, in order to ensure that circuit has certain operating rate, it is necessary to make circuit have certain electric current output to be provided that sufficiently large driving
Electric current.Represent with following formula because the delay time of circuit can approximate: td∝CLV1/ID, wherein CLFor load capacitance, V1
For output voltage, IDFor output driving current.In the case of certain load capacitance and logic swing, prolonging of circuit to be reduced
Time must increase the driving electric current of metal-oxide-semiconductor late；Large-drive-current to be increased only increases the breadth length ratio of output stage metal-oxide-semiconductor,
And so will increase the load capacitance of previous stage, affect the operating rate of previous stage.Therefore when very heavy load electric capacity, such as fan
Go out the biggest situation or receive the outfan of off-chip, needing through an i.e. output driver of output buffer circuit.Output
Driver is made up of two parts, and one is pre-driver stage, and one is power tube driving stage, and power tube driving stage is driven by preposition
Dynamic level drives.Pre-driver stage part independently controls the grid level of power tube driving stage output transistor.In the former, input IN
Terminating the pwm signal by higher level's modulation circuit, its output signal U p and Dn drive the upside of power tube driving stage respectively
Transistor PMOS and the grid of lower side transistor NMOS, power tube driving stage is the core of whole output driving circuit.
Its design determines the performance of whole output stage, thus largely affects the aggregate performance of system.And, power tube
In driving stage, the parasitic capacitance of power tube is very big, in order to ensure that circuit has certain operating rate, it is necessary to make the output of circuit
Driver can provide sufficiently large driving electric current.
Referring to Fig. 2, along with improving constantly of cmos device operating rate, high speed data transfer passage increasingly enjoys pass
Note.Two-forty causes current transformation rate di/dt to be accelerated, and produces the side effect such as ground wire bounce-back.In order to suppress ground wire to rebound, put
Rate of change di/dt and the discharge current of electricity electric current all should reduce.In order to reduce the di/dt of out drive stage, it is necessary to assure defeated
Go out driving stage and have a linear raising and lowering electric current.It is derived from a constant di/dt, thus subtracts to greatest extent
Drive noise less.This can be by using distributed and weighted switch actuation techniques realization, meanwhile, output driver transistor
Size should meet the requirement of maximum current drive ability.The present invention have employed the diversified technology of signal path, in order to
While big current driving ability is provided, reduces transmission delay, and then reduces T switch time of whole signalswitch。
TswitchIt is defined as: Tswitch=Td+Tr/f, T hereindAnd Tr/fIt is transmission delay and rising, fall time respectively.In Fig. 2,
Owing to various sizes of signal buffer is used, signal passes through two differences from input node IN to output node OUT
The path transmission of transmission delay.Undersized signal buffer has little transmission delay, but owing to its little electric current drives energy
Power causes big rise/fall time.Otherwise, large-sized signal buffer has big transmission delay, but due to its electricity
Stream driving force is big, so rise/fall time is little.One small size and large scale signal buffer appropriately combined permissible
Transmission delay T is reduced while big current driving ability is provideddWith rise/fall time Tr/f。
Fig. 3 is distributed and weighted switch actuation techniques.By VN=L*di/dt understands, and current changing rate di/dt causes VDD
The change of voltage, this " pressure drop (V on stray inductance and electric capacity between GNDN) " effect is referred to as ground wire bounce-back (or VDD
Saltus step), wherein, L is the equivalent parasitic inductance between VDD to GND, and di/dt is current changing rate, VNFor ground wire
The voltage drop that bounce-back causes.In order to suppress ground wire to rebound, the rate of change di/dt of discharge current and discharge current all should reduce.
In order to reduce the di/dt of out drive stage, it is necessary to assure out drive stage has a linear raising and lowering electric current.Thus
Obtain a constant di/dt, thus decrease driving noise to greatest extent.This can be by using distributed and weighting
Switch actuation techniques realizes.So-called distributed and weighting technique basic thought is the crystal of Sequential Activation out drive stage
Pipe.Distributed with in weighting technique, the output transistor that driving stage is big is split into several less crystal varied in size
Pipe, exports parallel join.The grid of these transistors is connected by well-designed delay line, to reduce output signal from one
The di/dt part of electric current is exported when individual logic state transition is another.Thus produce the raising and lowering of a smoothed slope
The signal on edge, thus reduce earthy saltus step.Due to time delay module, each PMOS and NMOS in Fig. 3
Grid the most independently controls.These discrete output transistor sizes increase step by step, such as P1 ＜ P2 and N1 ＜ N2.Now open
Close electric current and flow through the transistor current path of different " distributed ", therefore " weight " at these transistors.The change of electric current can
With by the time that the is switched on and off control of different crystal pipe.In order to realize the smooth transition of output signal, first invention beats
Opening undersized transistor, open large-sized transistor through certain time delay, the most all transistors are all beaten
Open.The size of output transistor should meet the requirement of maximum current drive ability.
Fig. 4 is the of the present invention output driver circuit schematic diagram corresponding with Fig. 3, is made up of two parts, and one is pre-driver
Level, one is power tube driving stage.Wherein pre-driver stage part include two groups of phase inverters (P4, N4 and P9, N11),
One two input nor gate (P5, P6, N5, N6), two input nand gate (P10, P11, N12, N13), two groups
Large scale buffer (P7, N7, N8, N9 and P12, P13, P14, N14) and two groups of small sizes buffer (P8, N10
And P15, N15)；Wherein, two groups of phase inverters (P4, N4 and P9, N11), two input nor gate (P5, P6, N5,
N6), two input nand gate (P10, P11, N12, N13) and two groups of large scales buffer (P7, N7, N8, N9
And P12, P13, P14, N14), two groups of small size buffers (P8, N10 and P15, N15) constitute in Fig. 3 anti-
Phase device chain.Power tube driving stage includes two groups of PMOS and NMOS tube (P1, N1 and P2, N2)；Simultaneously in order to anti-
The impact that only chip internal circuits is likely to result in by electrostatic, plus ESD electrostatic discharge protective circuit (P3, N3) in invention.In order to
Driving the biggest load capacitance, in the present invention, essence is the use chain of inverters pre-driver stage as output driver, to this end,
In nor gate (P5, P6, N5, N6), the input of P6, N6 grid end is always " 0 ", NAND gate (P10, P11, N12, N13)
The input of middle P11, N12 grid end is always " 1 ", it is achieved inverter drive function；Meanwhile, two groups of large scale buffers (P7,
N7, N8, N9 and P12, P13, P14, N14) and two groups of small size buffers (P8, N10 and P15, N15) are also in fact
Existing anti-phase driving function.Pre-driver stage uses the diversified technology of signal path, due to various sizes of signal buffer quilt
Using, signal passes through the path transmission of two different transmission delays from input node IN to output node OUT.Wherein,
In two groups of large scale buffers (P7, N7, N8, N9 and P12, P13, P14, N14), N7, N8 and P13, P14 divide
Yong Yu the control of Dead Time.Power tube driving stage uses distributed and weighted switch actuation techniques, and output transistor is by two
Group vary in size transistor (P1, N1 and P2, N2) composition, P1 ＜ P2, N1 ＜ N2, two group transistor outfans connect parallel
Connect.In order to realize the smooth transition of output signal, large scale signal buffer and small size signal buffer in pre-driver stage
There is certain time delay, therefore, be first turned on the small-geometry transistor (P1, N1) of power tube driving stage, through certain
Opening large-size crystals pipe (P2, N2) time delay, the most all transistors are all opened.Use above signal path
Variation technology can make output driver reduce transmission delay while meeting maximum current drive Capability Requirement.So based on
The speedy carding process driver of distributed and weighting technique, reduce output signal from a logic state transition be another time defeated
Go out the di/dt part of electric current, reduce the rate of change di/dt of switching current, greatly reduce the amplitude of ground wire bounce-back, effectively
Avoid the system failure.The most in the present invention, in order to prevent upside MOSFET and downside MOSFET from simultaneously turning on, i.e.
The generation of breakdown problem, inserts dead band time interval between large-sized gate drive signal.In dead band interim,
Upside MOSFET and downside MOSFET simultaneously turns off, and electric current is flowed by the body diode of MOSFET.During dead band
Between generation module between upside conducting and downside turn on, provide a blank time, it is to avoid the upper side and lower side
MOSFET simultaneously turns on and causes breakdown problem.
The present invention use the diversified technology of signal path in order to reduce transmission while providing big current driving ability
Time delay.The diversified technology of signal path, uses various sizes of signal buffer, due to difference between being input to export
The signal buffer of size is used, and signal is passed by the path of two different transmission delays from input node to output node
Defeated.Undersized signal buffer has little transmission delay, but its current driving ability is little.Otherwise, large-sized signal delays
Rush device and have a big transmission delay, but its current driving ability is big, so a small size and large scale signal buffer is suitable
Combination reduces transmission delay while can not reducing out drive stage current driving ability.Simultaneously in order to prevent upside
MOSFET and downside MOSFET simultaneously turns on, i.e. the generation of breakdown problem, and the grid at large scale signal buffer drives
Dead band time interval is inserted between dynamic signal.In dead band interim, upside MOSFET and downside MOSFET is simultaneously
Turning off, electric current is flowed by the body diode of MOSFET.Meanwhile, use distributed and weighted switch actuation techniques to protect
Card out drive stage has a linear raising and lowering electric current, reduces the rate of change di/dt of switching current, it is thus achieved that a perseverance
Fixed di/dt, last out drive stage need to be realized by two groups of various sizes of PMOS and NMOS.Their output is even
Receiving together, the gate input of PMOS and NMOS is connected to two signal buffers varied in size simultaneously.Use
The advantage of two signal buffers varied in size is PMOS and the nmos switch time can individually control.When in input
When end has signal intensity, due to the signal lag between the signal buffer that two above varies in size, PMOS and NMOS
Switching sequence be P1/N1, then P2/N2, the most all transistors are all opened, it is achieved do not reducing output drive
Transmission delay is reduced while device current driving ability.
The feature of this patent is and content has revealed that as above, but those skilled in the art is potentially based on the explanation of the present invention
And do all substitutions and modifications without departing substantially from spirit.Therefore, protection scope of the present invention should comprise all based on using letter
The speedy carding process driver electricity that the diversified technology in number path and distributed and weighted switch technology and interlock circuit thereof realize
Line structure.
Claims (4)
1. a speedy carding process drive circuit, including pre-driver stage and power tube driving stage, the input of pre-driver stage
End IN accepts the pwm signal of higher level's modulation circuit, and the output of pre-driver stage connects power tube driving stage, and power tube drives
The output OUT of dynamic level drives off-chip load；It is characterized in that: drive from the input IN of pre-driver stage to power tube
Between the outfan OUT of level, drive circuit have employed the diversified technology of signal path, uses in pre-driver stage
The buffer in combination that two groups of large and small sizes are different, meanwhile, drive circuit additionally uses distributed and weighted switch driving skill
Art, is sequentially activated the transistor of out drive stage, same employing and buffer in pre-driver stage in power tube driving stage
The output transistor combination that two groups of corresponding large and small sizes are different, the output of two groups of output transistors that large and small size is different
End parallel join, the output of undersized buffer drives undersized output transistor gates, the output of large-sized buffer to drive
Dynamic large-sized output transistor gates, signal is from being input to export by two different transmission path transmission, to realize not
Reduce transmission delay while reducing output driver current driving ability and reduce output signal from a logic state transition
For exporting the rate of change di/dt of electric current during another logic state, it addition, in the large scale buffer of pre-driver stage,
It is provided with dead-time control circuit, to prevent upside MOSFET and downside MOSFET in buffer from simultaneously turning on and producing
Puncture；
Pre-driver stage includes two parts circuit, and the output of a part of circuit is for driving the PMOS in power tube driving stage
Output transistor, including the first phase inverter being sequentially connected with, two input nor gates, first large scale buffer and first
Small size buffer；The output of another part circuit, for driving the nmos output transistor in power tube driving stage, is wrapped
Include the second phase inverter, two input nand gates, second large scale buffer and second the small size buffer being sequentially connected with；
Power tube driving stage includes one group of large scale output transistor and one group of small size output transistor, large scale output transistor bag
Including a large-sized PMOS and a large-sized NMOS tube, small size output transistor includes a small size
PMOS and a undersized NMOS tube, the output of first large scale buffer drives large-sized PMOS
Pipe, the output of second large scale buffer drives large-sized NMOS tube, and the output of first small size buffer is driven
Dynamic undersized PMOS, the output of second small size buffer drives undersized NMOS tube.
Speedy carding process drive circuit the most according to claim 1, it is characterised in that: it is used for driving power tube to drive
In Ji in the pre-driver stage of PMOS output transistor, PMOS P4 and NMOS tube N4 constitute the first phase inverter,
PMOS P5, P6 and NMOS tube N5, N6 constitute two input nor gates, PMOS P7 and NMOS tube
N7, N8, N9 constitute first large scale buffer, and wherein NMOS tube N7, N8 are dead-time control circuit,
PMOS P8 and NMOS tube N10 constitute first small size buffer；In first phase inverter, PMOS P4
Source electrode connects VDD, and the source ground of NMOS tube N4, the grid of PMOS P4 is mutual with the grid of NMOS tube N4
Company the input IN as pre-driver stage, the drain electrode of PMOS P4 and the drain interconnection of NMOS tube N4 conduct
The outfan of the first phase inverter；In two input nor gates, the source electrode of PMOS P5 connects VDD, PMOS P5
Drain electrode connects the source electrode of PMOS P6, and the drain electrode of PMOS P6 connects NMOS tube N5, the drain electrode of N6, NMOS
The source ground of pipe N6, the grid of PMOS P6 connects the grid of NMOS tube N6 as the one of two input nor gates
Individual input also passes through resistance R1 ground connection, the grid of PMOS P5 and the gate interconnection of NMOS tube N5 and as two
Another input of input nor gate and the outfan of the first phase inverter connect, the source ground of NMOS tube N5, NMOS
The drain electrode of pipe N5 and the drain interconnection of NMOS tube N6 are as two outfans inputting nor gates；First large scale buffering
In device, the source electrode of PMOS P7 connects VDD, and the drain electrode of PMOS P7 connects the drain electrode of NMOS tube N7 and makees
Being the outfan of first large scale buffer, the source electrode of NMOS tube N7 connects the drain electrode of NMOS tube N8, NMOS
The source electrode of pipe N8 connects the drain electrode of NMOS tube N9, the source ground of NMOS tube N9, the grid of PMOS P7
Link together with the grid of NMOS tube N7, N8 and N9 and be connected the outfan of two input nor gates；First little
In size buffer, the source electrode of PMOS P8 connects VDD, and the drain electrode of PMOS P8 connects NMOS tube N10
Drain electrode and as the outfan of first small size buffer, the source ground of NMOS tube N10, PMOS P8
The gate interconnection of grid and NMOS tube N10 and be connected the outfan of two input nor gates；
For driving in power tube driving stage in the pre-driver stage of nmos output transistor, PMOS P9 and NMOS
Pipe N11 constitutes the second phase inverter, and PMOS P10, P11 and NMOS tube N12, N13 constitute two inputs with non-
Door, PMOS P12, P13, P14 and NMOS tube N14 constitute second large scale buffer, wherein PMOS
Pipe P13, P14 are another dead-time control circuit, and PMOS P15 and NMOS tube N16 composition second are little
Size buffer；In second phase inverter, the source electrode connection VDD of PMOS P9, the source ground of NMOS tube N11,
The grid of PMOS P9 and the gate interconnection of NMOS tube N11 also are connected to drive PMOS in power tube driving stage
Output transistor pre-driver stage two inputs PMOS P6 grid and the interconnection end of NMOS tube N6 grid in nor gate,
The drain electrode of PMOS P9 and the drain interconnection of NMOS tube N11 the outfan as the second phase inverter；Two input with
In not gate, PMOS P10, the source electrode of P11 connect VDD, PMOS P10, the drain electrode of P11 and NMOS tube
The drain electrode connection of N12 the outfan as two input nand gates, the source electrode of NMOS tube N12 connects NMOS tube N13
Drain electrode, the source ground of NMOS tube N13, the gate interconnection of the grid of NMOS tube N13 and PMOS P10 is made
It is an input of two input nand gates and connects the outfan of the first phase inverter, the grid of NMOS tube N12 and PMOS
The gate interconnection of pipe P11 is as another inputs of two input nand gates and connects the outfan of the second phase inverter；Second
In individual large scale buffer, the source electrode of PMOS P12 connects VDD, and the drain electrode of PMOS P12 connects PMOS
The source electrode of P13, the drain electrode of PMOS P13 connects the source electrode of PMOS P14, and the drain electrode of PMOS P14 connects
The drain electrode of NMOS tube N14 the outfan as second large scale buffer, the source ground of NMOS tube N14,
The grid of NMOS tube N14 links together with the grid of PMOS P12, P13, P14 and is connected two input nand gates
Outfan；In second small size buffer, the source electrode of PMOS P15 connects VDD, the leakage of PMOS P15
Pole connects the drain electrode of NMOS tube N15 and as the outfan of second small size buffer, the source electrode of NMOS tube N15
Ground connection, the grid of PMOS P15 and the gate interconnection of NMOS tube N15 the outfan being connected two input nand gates；
Power tube driving stage includes one group of large scale output transistor and one group of small size output transistor, small size output crystal
Pipe includes PMOS P1 and NMOS tube N1, and the source electrode of PMOS P1 connects VDD, the leakage of PMOS P1
Pole connects the drain electrode of NMOS tube N1 and as the outfan of this group small size output transistor, the source electrode of NMOS tube N1
Ground connection, the grid of PMOS P1 connects the outfan of first small size buffer, and the grid of NMOS tube N1 connects
The outfan of second small size buffer；Large scale output transistor includes that pipe includes PMOS P2 and NMOS tube
N2, the source electrode of PMOS P2 connects VDD, and the drain electrode of PMOS P2 connects drain electrode the conduct of NMOS tube N2
The outfan of this group large scale output transistor, the source ground of NMOS tube N2, the grid of PMOS P2 connects the
The outfan of one large scale buffer, the grid of NMOS tube N2 connects the outfan of second large scale buffer, little
The outfan of size output transistor links together collectively as power tube driving with the outfan of large scale output transistor
The outfan OUT of level.
Speedy carding process drive circuit the most according to claim 2, it is characterised in that: for uncertain signal is led to
Cross a resistance clamped in low level, between the outfan OUT and ground end of power tube driving stage, be provided with resistance R2.
4. according to the speedy carding process drive circuit described in claim 1 or 2 or 3, it is characterised in that: for preventing electrostatic
The impact being likely to result in chip internal circuits, is provided with ESD electrostatic discharge protective circuit, including PMOS P3 and NMOS
Pipe N3, the grid of PMOS P3 interconnects and is connected VDD with source electrode, and the grid of NMOS tube N3 interconnects also with source electrode
Ground connection, the drain electrode of PMOS P3 and the drain interconnection of NMOS tube N3 the outfan OUT being connected power tube driving stage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610395870.2A CN105978553A (en) | 2016-06-06 | 2016-06-06 | High speed output driver circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610395870.2A CN105978553A (en) | 2016-06-06 | 2016-06-06 | High speed output driver circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105978553A true CN105978553A (en) | 2016-09-28 |
Family
ID=57010859
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610395870.2A Pending CN105978553A (en) | 2016-06-06 | 2016-06-06 | High speed output driver circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105978553A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107085132A (en) * | 2017-05-18 | 2017-08-22 | 东南大学 | A kind of positive voltage power under high-precision detection of negative pressure circuit |
| CN110784206A (en) * | 2018-07-27 | 2020-02-11 | 美格纳半导体有限公司 | Control buffer in source driver and source driver of display panel |
| CN111146931A (en) * | 2019-12-23 | 2020-05-12 | 广东美的白色家电技术创新中心有限公司 | Drive circuit of power device and electronic equipment |
| CN113037253A (en) * | 2021-02-25 | 2021-06-25 | 中国电子科技集团公司第五十八研究所 | Open drain output circuit |
| WO2022048246A1 (en) * | 2020-09-07 | 2022-03-10 | 长鑫存储技术有限公司 | Drive circuit |
| CN114189151A (en) * | 2020-09-15 | 2022-03-15 | 圣邦微电子（北京）股份有限公司 | DC-DC boost converter |
| US11444619B2 (en) | 2020-09-07 | 2022-09-13 | Changxin Memory Technologies, Inc. | Driving circuit |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4987324A (en) * | 1985-04-22 | 1991-01-22 | Lsi Logic Corporation | High-speed CMOS buffer with controlled slew rate |
| US5331228A (en) * | 1992-07-31 | 1994-07-19 | Sgs-Thomson Microelectronics, Inc. | Output driver circuit |
| CN1375934A (en) * | 2002-03-20 | 2002-10-23 | 威盛电子股份有限公司 | Output buffer capable of reducing power source and earthing pop-corn noise and its method |
| CN1518224A (en) * | 2002-11-20 | 2004-08-04 | 威盛电子股份有限公司 | Output driver with low ground jump noise |
| CN101394177A (en) * | 2008-10-24 | 2009-03-25 | 华中科技大学 | Output buffer circuit |
| CN101498946A (en) * | 2008-02-01 | 2009-08-05 | 瑞昱半导体股份有限公司 | Voltage-stabilizing circuit and method for chips |
-
2016
- 2016-06-06 CN CN201610395870.2A patent/CN105978553A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4987324A (en) * | 1985-04-22 | 1991-01-22 | Lsi Logic Corporation | High-speed CMOS buffer with controlled slew rate |
| US5331228A (en) * | 1992-07-31 | 1994-07-19 | Sgs-Thomson Microelectronics, Inc. | Output driver circuit |
| CN1375934A (en) * | 2002-03-20 | 2002-10-23 | 威盛电子股份有限公司 | Output buffer capable of reducing power source and earthing pop-corn noise and its method |
| CN1518224A (en) * | 2002-11-20 | 2004-08-04 | 威盛电子股份有限公司 | Output driver with low ground jump noise |
| CN101498946A (en) * | 2008-02-01 | 2009-08-05 | 瑞昱半导体股份有限公司 | Voltage-stabilizing circuit and method for chips |
| CN101394177A (en) * | 2008-10-24 | 2009-03-25 | 华中科技大学 | Output buffer circuit |
Non-Patent Citations (1)
| Title |
|---|
| RAVEENDRAN ARUN PRASATH 等: "Design of Low Power Level Shifter Circuit with Sleep Transistor Using MultiSupply Voltage Scheme", 《HTTP://WWW.SCIRP.ORG/JOURNAL/PAPERDOWNLOAD.ASPX?PAPERID=66921》 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107085132A (en) * | 2017-05-18 | 2017-08-22 | 东南大学 | A kind of positive voltage power under high-precision detection of negative pressure circuit |
| CN110784206A (en) * | 2018-07-27 | 2020-02-11 | 美格纳半导体有限公司 | Control buffer in source driver and source driver of display panel |
| CN111146931A (en) * | 2019-12-23 | 2020-05-12 | 广东美的白色家电技术创新中心有限公司 | Drive circuit of power device and electronic equipment |
| WO2022048246A1 (en) * | 2020-09-07 | 2022-03-10 | 长鑫存储技术有限公司 | Drive circuit |
| US11444619B2 (en) | 2020-09-07 | 2022-09-13 | Changxin Memory Technologies, Inc. | Driving circuit |
| CN114189151A (en) * | 2020-09-15 | 2022-03-15 | 圣邦微电子（北京）股份有限公司 | DC-DC boost converter |
| CN114189151B (en) * | 2020-09-15 | 2024-02-06 | 圣邦微电子（北京）股份有限公司 | DC-DC boost converter |
| CN113037253A (en) * | 2021-02-25 | 2021-06-25 | 中国电子科技集团公司第五十八研究所 | Open drain output circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105978553A (en) | High speed output driver circuit | |
| CN107710620B (en) | Input/output (I/O) driver | |
| US6897696B2 (en) | Duty-cycle adjustable buffer and method and method for operating same | |
| US7245156B2 (en) | Pre-drivers for current-mode I/O drivers | |
| CN104521146B (en) | Semiconductor integrated circuit | |
| CN110679088B (en) | Level shifter for wide low voltage supply range | |
| CN101888178B (en) | Charge pump circuit used for reducing current mismatch at extra-low voltage in phase-locked loop | |
| US20090195270A1 (en) | Output buffer device | |
| CN103915990A (en) | Drive circuit for GaN power devices | |
| US20100289526A1 (en) | Level shifter | |
| TWI756707B (en) | Off chip driving circuit and signal compensation method | |
| CN111555595B (en) | GaN power tube gate drive circuit with controllable opening rate | |
| CN105591643B (en) | The method for having the integrated circuit of output buffer and controlling output buffer | |
| CN101174829A (en) | Slew rate controlled output buffer and circuits | |
| CN106505990A (en) | There is the input buffer of optional delayed and speed | |
| US20060103446A1 (en) | Driver circuit | |
| CN104836570B (en) | It is a kind of based on transistor level and/NOR gate circuit | |
| CN108809296A (en) | High-pressure level shift circuit and driving device | |
| CN103888118A (en) | Gate driver circuit and operating method thereof | |
| US9225333B2 (en) | Single supply level shifter with improved rise time and reduced leakage | |
| CN105703761B (en) | Input/output driving circuit | |
| CN104079289B (en) | Output circuit with ground bounce resistance | |
| US7768311B2 (en) | Suppressing ringing in high speed CMOS output buffers driving transmission line load | |
| US8811096B2 (en) | Output driver circuit and semiconductor storage device | |
| US20100164556A1 (en) | Converting dynamic repeaters to conventional repeaters |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160928 |