CN110011521B - Drive circuit, drive chip and drive method thereof - Google Patents
Drive circuit, drive chip and drive method thereof Download PDFInfo
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- CN110011521B CN110011521B CN201810007352.8A CN201810007352A CN110011521B CN 110011521 B CN110011521 B CN 110011521B CN 201810007352 A CN201810007352 A CN 201810007352A CN 110011521 B CN110011521 B CN 110011521B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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Abstract
The invention provides a driving circuit, a driving chip and a driving method thereof, comprising the following steps: the device comprises a first pull-up driving pipe, a second pull-up driving pipe, a delay control module and a pull-down driving pipe; the first pull-up driving tube is connected with a driving signal, power voltage and a grid electrode of an external power switch tube; the first pull-up driving tube is switched on at a high level and switched off at a low level; the second pull-up driving tube is connected with the delay control module, the power supply voltage and the power switch tube; the second pull-up driving tube is switched on at a low level and switched off at a high level; the delay control module is connected with the driving signal, an enabling signal and a grid electrode of the power switch tube; the pull-down driving tube is connected with a driving signal. The invention can give consideration to the performance requirements of saving the size cost of the device and outputting higher driving voltage under the condition of smaller device size; different requirements can be met without changing a metal plate, and the operation cost and the production cost are further saved.
Description
Technical Field
The invention relates to the technical field of circuit design, in particular to a driving circuit, a driving chip and a driving method thereof.
Background
In the application of the existing power control chip, how to realize the functions and performances which the chip is intended to realize with fewer devices and smaller device sizes is the most important determinant factor of the cost of the control chip. The functions that the drive circuit needs to realize include: the method provides large driving current to drive an external power tube, electromagnetic interference (EMI) control and logic sequence control. These functions are well implemented and the driver circuit requires a large number of integrated devices, making the driver circuit a significant fraction of the overall cost of the chip, many approaching 1/5 or even 1/2. Therefore, how to use the optimized driving circuit will directly determine the chip cost, especially, the driving circuit applied in the AC/DC power control chip, since the driving power needs to be provided by the high voltage power supply, the driving upper tube can only use the high voltage MOS tube with high voltage resistance, such as 12V, 25V, 40V high voltage technology device. And the device size of the high-voltage tube is much larger than that of the low-voltage tube, and the cost of the driving part accounts for much more of the cost of the whole chip. Therefore, in an AC/DC chip, the need for how to implement the driving with more optimized circuits is especially critical for cost saving. In addition, in the current application environment, there is a need to switch on the power transistor as soon as possible, considering the EMI application environment and having little influence on the EMI due to the switching speed. The chip designer usually deals with the problem by changing the photolithography of the chip and dividing the chip into one or several chips, which undoubtedly increases a great deal of research and development and operation cost.
The structure of the existing driving circuit is various, but in the existing driving circuit, the driving circuit with stronger driving capability generally has the problem of lower driving voltage output, and the driving circuit with higher driving voltage output generally has the problem of poorer driving capability. That is, the existing driving circuit can not give consideration to the requirements of both driving capability and outputting higher driving voltage, or the existing driving circuit can not give consideration to the performance requirements of saving the size cost of the device and outputting higher driving voltage. Meanwhile, the existing driving circuit cannot give consideration to both an application environment requiring EMI and an environment not requiring EMI, and when the EMI environment is not required, a redundant delay part exists, the metal plate needs to be changed in a manner of the metal plate, the cost for changing the metal plate is high, the operation cost is increased, and the cost is wasted.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a driving circuit, a driving chip and a driving method thereof, which are used to solve the problems that the performance requirements of saving the device size cost and outputting higher driving voltage cannot be satisfied, and the operation cost is higher, resulting in cost waste in the driving circuit in the prior art.
To achieve the above and other related objects, the present invention provides a driving circuit, including at least: the device comprises a first pull-up driving pipe, a second pull-up driving pipe, a delay control module and a pull-down driving pipe; wherein the content of the first and second substances,
the first pull-up driving tube is connected with a driving signal, power voltage and a grid electrode of an external power switching tube and used for conducting to provide driving current for the power switching tube when the driving signal is at a high level; the first pull-up driving tube is switched on at a high level and switched off at a low level;
the second pull-up driving tube is connected with the delay control module, the power supply voltage and the grid electrode of the power switch tube; the second pull-up driving tube is switched on at a low level and switched off at a high level;
the delay control module is connected with the driving signal, an enabling signal and the grid electrode of the power switch tube; when the enable signal is at a high level, the delay control module controls the second pull-up driving tube to be conducted and provide driving current for the power switching tube together with the first pull-up driving tube when the grid voltage of the power switching tube crosses the Miller platform; when the enable signal is at a low level, the delay control module controls the second pull-up driving tube and the first pull-up driving tube to be simultaneously conducted so as to simultaneously provide driving current for the power switching tube;
the pull-down driving tube is connected with the driving signal and used for providing pull-down current for the grid electrode of the power switch tube when the driving signal is at a low level.
Preferably, the first pull-up driving tube is an NMOS tube, a gate of the first pull-up driving tube is connected to the driving signal, a drain of the first pull-up driving tube is connected to the power supply voltage, and a source of the first pull-up driving tube is connected to the gate of the power switching tube; the second pull-up driving tube is a PMOS tube, a grid electrode of the second pull-up driving tube is connected with the delay control module, a source electrode of the second pull-up driving tube is connected with the power supply voltage, and a drain electrode of the second pull-up driving tube is connected with a grid electrode of the power switch tube.
Preferably, the first pull-up driving tube is an NPN-type triode, a base of the first pull-up driving tube is connected to the driving signal, a collector of the first pull-up driving tube is connected to the power supply voltage, and an emitter of the first pull-up driving tube is connected to a gate of the power switching tube; the second pull-up driving tube is a PNP type triode, the base of the second pull-up driving tube is connected with the delay control module, the emitting electrode of the second pull-up driving tube is connected with the power voltage, and the collecting electrode of the second pull-up driving tube is connected with the grid electrode of the power switch tube.
Preferably, the driving circuit further comprises a first not gate, and an input end of the first not gate is connected with the driving signal; the pull-down driving tube is an NMOS tube, a grid electrode of the pull-down driving tube is connected with an output end of the first NOT gate, a drain electrode of the pull-down driving tube is connected with a grid electrode of the power switch tube, and a source electrode of the pull-down driving tube is grounded.
Preferably, the delay control module includes: the delay unit, the second not gate, the third not gate, the first nor gate, the second nor gate and the fourth not gate; wherein the content of the first and second substances,
the input end of the second NOT gate is connected with the enabling signal; the input end of the third NOT gate is connected with the driving signal; a first input end of the first NOR gate is connected with an output end of the second NOR gate, and a second input end of the first NOR gate is connected with an output end of the delay unit; a first input terminal of the second nor gate is connected to an output terminal of the first nor gate, and a second input terminal of the second nor gate is connected to an output terminal of the third nor gate; the input end of the fourth not gate is connected with the output end of the second nor gate, and the output end of the fourth not gate is connected with the second pull-up driving tube; and the input end of the delay unit is connected with the grid electrode of the power switch tube.
Preferably, the driving circuit further comprises an enable signal generating circuit, wherein the enable signal generating circuit comprises a current source and a fuse; the current source is connected with the fuse in series, the input end of the current source is connected with a power supply, and the output end of the current source is connected with the connecting node of the fuse and the delay control module; and one end of the fuse far away from the current source is grounded.
The present invention also provides a driving chip, including: a chip body and a driving circuit as described in any of the above schemes; wherein the content of the first and second substances,
the driving circuit is positioned in the chip main body;
the chip main body is provided with an enable pin, a drive pin, a grounding pin, a power supply voltage pin and a grid pin; the enabling pin is connected with the delay control module; the driving pin is connected with the delay control module, the first pull-up driving tube and the pull-down driving tube; the grounding pin is connected with the pull-down driving tube and the source electrode of the power switch tube; the power supply voltage pin is connected with the first pull-up driving tube and the second pull-up driving tube; the grid pin is connected with the grid of the power switch tube.
The present invention also provides a driving chip, including: a chip body and a driving circuit as described in the above one embodiment; wherein the content of the first and second substances,
the driving circuit is positioned in the chip main body;
the chip main body is provided with a driving pin, a grounding pin, a power supply voltage pin and a grid pin; the driving pin is connected with the delay control module, the first pull-up driving tube and the pull-down driving tube; the grounding pin is connected with the pull-down driving tube and the source electrode of the power switch tube; the power supply voltage pin is connected with the first pull-up driving tube and the second pull-up driving tube; the grid pin is connected with the grid of the power switch tube.
In order to achieve the above and other related objects, the present invention provides a driving method of a driving circuit as set forth in any one of the above aspects, when the driving signal is at a high level, the first pull-up driving transistor is turned on by the driving signal and provides a driving current to the power switching transistor; if the enable signal is at a high level, when the grid voltage of the power switching tube crosses over the miller platform, the delay control module controls the second pull-up driving tube to be conducted, and the second pull-up driving tube and the first pull-up driving tube together provide driving current for the power switching tube so as to drive the power switching tube to be conducted; if the enable signal is at a low level, the delay control module controls the second pull-up driving tube and the first pull-up driving tube to be simultaneously conducted so as to simultaneously provide a driving current for the power switching tube and drive the power switching tube to be conducted;
when the driving signal is at a low level, the pull-down driving tube is turned on, and the pull-down driving tube provides pull-down current for the power switching tube so as to turn off the power switching tube.
As described above, the driving circuit, the driving chip and the driving method thereof according to the present invention have the following advantages:
the driving circuit can meet the performance requirements of saving the size cost of the device and outputting higher driving voltage under the condition of smaller device size; the requirements of an EMI environment and an EMI environment are met without changing a metal plate, so that the operation cost and the production cost are further saved; when the requirement of an EMI environment needs to be met, the invention can obtain a better driving waveform through the enabling signal, thereby meeting the requirement of EMI.
Drawings
Fig. 1 to 4 are schematic structural diagrams of the driving circuit of the present invention.
Fig. 5 is a diagram showing the relationship between the current changes of the first pull-up driving transistor, the second pull-up driving transistor and the power switch transistor with time in the scheme of the present invention in which the second pull-up driving transistor is turned on in a delayed manner under the control of the delay control module.
Fig. 6 is a diagram showing the relationship between the current of the first pull-up driving transistor, the current of the second pull-up driving transistor and the current of the power switch transistor in the scheme that the second pull-up driving transistor is simultaneously conducted with the first pull-up driving transistor under the control of the delay control module.
Fig. 7 to 10 are schematic structural diagrams of the driving chip of the invention.
Description of the element reference numerals
1 drive circuit
11 delay control module
111 delay control unit
112 second not gate
113 third not gate
114 first nor gate
115 second nor gate
116 fourth not gate
12 first not gate
13 enable circuit
131 current mirror
132 fuse
2 chip
21 chip body
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 10. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1, the present invention provides a driving circuit 1, where the driving circuit 1 at least includes: the device comprises a first pull-up driving tube M1, a second pull-up driving tube M2, a delay control module 11 and a pull-down driving tube M3; the first pull-up driving transistor M1 is connected to a driving signal DRV, a power supply voltage VCC, and a gate of an external power switch M0, and is configured to conduct and provide a driving current for the power switch M0 when the driving signal DRV is at a high level; the first pull-up driving tube M1 is switched on at a high level and switched off at a low level; the second pull-up driving transistor M2 is connected to the delay control module 11, the power supply voltage VCC, and the gate of the power switch transistor M0; the second pull-up driving tube M2 is switched on at a low level and switched off at a high level; the delay control module 11 is connected to the driving signal DRV, an enable signal SEL and the gate of the power switch M0; when the enable signal SEL is at a high level, the delay control module 11 controls the second pull-up driving transistor M2 to be turned on to provide a driving current for the power switch M0 together with the first pull-up driving transistor M1 when the gate voltage of the power switch M0 crosses the miller plateau; when the enable signal SEL is at a low level, the delay control module 11 controls the second pull-up driving transistor M2 and the first pull-up driving transistor M1 to be turned on simultaneously to provide a driving current for the power switch M0 simultaneously; the pull-down driving transistor M3 is connected to the driving signal DRV, and is configured to provide a pull-down current to the gate of the power switch M0 when the driving signal DRV is at a low level.
For example, the external power switch transistor M0 may be, but is not limited to, an NMOS transistor, the gate of the power switch transistor M0 is connected to the first pull-up driving transistor M1, the second pull-up driving transistor M2 and the pull-down driving transistor M3, and the source of the power switch transistor M0 is grounded.
In an example, as shown in fig. 1, the first pull-up driving transistor M1 is an NMOS transistor, the gate of the first pull-up driving transistor M1 is connected to the driving signal DRV, the drain of the first pull-up driving transistor M1 is connected to the power supply voltage VCC, and the source of the first pull-up driving transistor M1 is connected to the gate of the power switch transistor M0; the second pull-up driving tube M2 is a PMOS tube, the gate of the second pull-up driving tube M2 is connected to the delay control module 11, the source of the second pull-up driving tube M2 is connected to the power voltage VCC, and the drain of the second pull-up driving tube M2 is connected to the gate of the power switch tube M0.
In another example, as shown in fig. 2, the first pull-up driving transistor M1 is an NPN transistor, the base of the first pull-up driving transistor M1 is connected to the driving signal DRV, the collector of the first pull-up driving transistor M1 is connected to the power supply voltage VCC, and the emitter of the first pull-up driving transistor M1 is connected to the gate of the power switch transistor M0; the second pull-up driving tube M2 is a PNP type triode, the base of the second pull-up driving tube M2 is connected to the delay control module 11, the emitter of the second pull-up driving tube M2 is connected to the power voltage VCC, and the collector of the second pull-up driving tube M2 is connected to the gate of the power switch tube M0.
As an example, the driving circuit 1 further includes a first not gate 12, and an input terminal of the first not gate 12 is connected to the driving signal DRV; the pull-down driving tube M3 is an NMOS tube, a gate of the pull-down driving tube M3 is connected to an output end of the first not gate 12, a drain of the pull-down driving tube M3 is connected to a gate of the power switch tube M0, and a source of the pull-down driving tube M0 is grounded. When the driving signal DRV is at a high level, the driving signal DRV at the high level changes to a low level after passing through the first not gate 12, and the pull-down driving transistor M3 is turned off; when the driving signal DRV is at a low level, the driving signal DRV at the low level changes to a high level after passing through the first not gate 12, and the pull-down driving transistor M3 is turned on.
Preferably, as shown in fig. 3, the delay control module 11 includes: a delay unit 111, a second not gate 112, a third not gate 113, a first nor gate 114, a second nor gate 115, and a fourth not gate 116; wherein, the input terminal of the second not gate 112 is connected to the enable signal SEL; the input end of the third not gate 113 is connected to the driving signal DRV; a first input terminal of the first nor gate 114 is connected to an output terminal of the second nor gate 112, and a second input terminal of the first nor gate 114 is connected to an output terminal of the delay unit 111; a first input terminal of the second nor gate 115 is connected to an output terminal of the first nor gate 114, and a second input terminal of the second nor gate 115 is connected to an output terminal of the third nor gate 113; an input end of the fourth not gate 116 is connected to an output end of the second nor gate 115, an output end of the fourth not gate 116 is connected to the second pull-up driving transistor M2, and specifically, an output end of the fourth not gate 116 is connected to a gate of the second pull-up driving transistor M2; the input end of the delay unit 111 is connected to the gate of the power switch M0.
As an example, as shown in fig. 4, the driving circuit 1 further includes an enable signal generating circuit 13, and the enable signal generating circuit 13 includes a current source 131 and a fuse 132; the current source 131 is connected in series with the fuse 132, an input terminal of the current source 131 is connected to a power supply, a connection node between an output terminal of the current source 131 and the fuse 132 is connected to the delay control module 11, and specifically, a connection node between an output terminal of the current source 131 and the fuse 132 is connected to the second not gate 112 in the delay control module 11; the end of the fuse 132 away from the current source 131 is grounded. The current source 131 can provide a current of μm level, if the fuse 132 is not blown, the enable signal SEL output by the connection node between the output terminal of the current source 131 and the fuse 132 is at low level (i.e., the enable signal generation circuit 13 generates the enable signal SEL at low level); if the fuse 132 is blown, the enable signal SEL output from the connection node between the output terminal of the current source 131 and the fuse 132 is at a high level (that is, the enable signal generation circuit 13 generates the enable signal SEL at a high level).
It should be noted that, in fig. 3 and 4, only the first pull-up driving transistor M1 is an NMOS transistor, and the second pull-up driving transistor M2 is a PMOS transistor, for example, when the first pull-up driving transistor M1 is an NPN type transistor, and the second pull-up driving transistor M2 is a PNP type transistor, the structures of the driving circuits are the same as those shown in fig. 3 and 4 except for the first pull-up driving transistor M1 and the second pull-up driving transistor M2.
The working principle of the driving circuit 1 of the present invention is as follows: when the enable signal SEL is at a high level, the driving of the first pull-up driving transistor M2 is controlled by the delay control module 11, and at this time, if the driving signal DRV is at a high level, the pull-down driving transistor M3 is turned off, and the first pull-up driving transistor M1 is turned on. When the voltage of the driving transistor M0 crosses the miller platform, the delay control module 11 controls the second pull-up driving transistor M2 to be turned on, and the second pull-up driving transistor M2 provides the gate driving voltage for the power switch M0; when the enable signal SEL is at a low level, the second pull-up driving transistor M2 is not controlled by the delay of the delay control module 11, the second pull-up driving transistor M2 is turned on together with the first pull-up driving transistor M1 (i.e., the second pull-up driving transistor M2 is turned on at the fastest speed), and the second pull-up driving transistor M2 and the first pull-up driving transistor M1 provide a driving current for the power switch transistor M0 to drive the power switch transistor M0 together. Since the first pull-up driving transistor M1 is an NMOS transistor or an NPN transistor, the first pull-up driving transistor M1 has a high electron mobility. Therefore, the first pull-up driving pipe M1 has a smaller size with the same driving capability. Under the two conditions that the enable signal SEL is at a high level or a low level, the voltage of the grid electrode of the power switch tube M0 is determined by subtracting the saturated conduction voltage drop of the second pull-up driving tube M2 from the power supply voltage VCC, and can reach VCC-100mV at most.
Compared with the conventional driving method in the prior art, the driving circuit 1 of the present invention has the advantage that the first pull-up driving transistor M1 can provide the same or even larger driving current with a smaller driving transistor device size. As shown in fig. 5, fig. 5 is a graph showing the time-varying current of the first pull-up driving transistor M1, the second pull-up driving transistor M2 and the power switch transistor M0 in the scheme of the present invention in which the second pull-up driving transistor M2 is turned on in a delayed manner under the control of the delay control module 11 in the driving circuit 1. As shown in fig. 5, in the driving start stage, the first pull-up driving transistor M1 is used as a sub-driving transistor to provide the driving current I1, and since the first pull-up driving transistor M1 is an NMOS transistor or an NPN transistor, it has a higher electron mobility and can provide a larger driving current with a smaller device size; the driving current I1 charges the external power switch tube M0, and at the time T2 when the Gate voltage of the power switch tube M0 (i.e., the voltage at the Gate in fig. 1 to 4) passes through the miller stage, the delay control module 11 controls the second pull-up driving tube M2 to be turned on to provide another driving current I2 for the power switch tube M0, so as to charge the power switch tube M0, which can provide a good EMI effect; in fig. 2, IGate is the current flowing through the Gate of the power switch M0, i.e. the current flowing through the Gate. Because the second pull-up driving tube M2 is a PMOS transistor or a PNP triode, the second pull-up driving tube M2 can provide a higher driving voltage for the power switch tube M0 due to saturation voltage drop of the second pull-up driving tube M2, so that the system can obtain higher efficiency, and thus the power switch tube M0 with a higher conduction threshold can be driven. The second pull-up driving tube M2 is used as a main driving tube, and its main function is to provide a higher output voltage, and the operation of turning on the external power switch tube M0 is already performed by the first pull-up driving tube M1 as a secondary driving tube, so that the second pull-up driving tube M1 does not need a strong driving capability, that is, the second pull-up driving tube M2 does not need a large device size; thus, the first pull-up driving tube M1 and the second pull-up driving tube M2 both minimize the requirement of the starting size, and do not cause the excessive use of the device and the waste of the cost. After the Gate voltage of the external power switch M0 of the first pull-up driving transistor M1 reaches the maximum driving voltage, since the source of the first pull-up driving transistor M1 is higher than the Gate, the first pull-up driving transistor M1 is in a cut-off state, i.e. a self-turn-off effect, so that when the actual driving output is high, a weak pull-up condition is performed on the Gate point, which can provide an advantage: when the driving signal DRV is at a low level and the external power switch tube M0 needs to be turned off, the Gate point can be pulled down by the pull-down driving tube M3 quickly, so that the turn-off speed of the external power switch tube M0 is increased significantly. Since the power switch M0 is turned on by the driving current provided by the first pull-up driving transistor M1 and the second pull-up driving transistor M2, a low voltage drop path from a power supply voltage VCC to a Gate point is left. If there is also a strong pull-up, the power disturbance to the power switch M0, or to the supply voltage VCC to Gate point, is negative. Therefore, it is only necessary to give a relatively weak pull-up to the Gate point as in the case of the second pull-up driving pipe M2 provided in the present application, so as to perfectly solve the problem of strong pull-up.
In addition, the invention has another advantage that under the condition that the metal plate is not required to be changed, the requirements of an EMI environment and an environment without the EMI environment can be met, and the operation cost and the production cost are further saved. When the driving circuit 1 drives the power switch M0 without affecting the system EMI, the second pull-up driving transistor M2 and the first pull-up driving transistor M1 are turned on simultaneously to provide a driving current for the external power switch M0, fig. 6 shows a relationship diagram of the current changes with time of the first pull-up driving transistor M1, the second pull-up driving transistor M2 and the power switch M0 in the driving circuit 1 of the invention, in which the second pull-up driving transistor M2 and the first pull-up driving transistor M1 are turned on simultaneously under the control of the delay control module 11, I1 is the current flowing through the first pull-up driving transistor M1, I2 is the current flowing through the second pull-up driving transistor M2, and ignate is the current flowing through the gate of the power switch M0. Since the first pull-up driving tube M1 and the second pull-up driving tube M2 are turned on simultaneously, at the time T1, the voltage at the Gate reaches the turn-on threshold value faster, and continues to turn on at the time T2, and at the time T3, due to the self-turn-off effect of the first pull-up driving tube M1, the voltage at the Gate changes as described above, but at this time, the external power switch tube M0 is already driven to turn on, so that the performance is not greatly affected, and the overall turn-on speed is still faster than that of any conventional structure.
Referring to fig. 7 to 9, the present invention further provides a driving chip 2, where the driving chip 2 includes: a chip body 21 and a driving circuit 1 as described in fig. 1 to 3 in the above scheme; the driving circuit 1 is located in the chip main body 21, and the specific structure of the driving circuit 1 is not described here; the chip main body 21 is provided with an enable pin SEL, a drive pin DRV, a ground pin GND, a power supply voltage pin VCC and a grid pin Gate; the enable pin SEL is connected with the delay control module 11 and is used for accessing an externally input enable signal; the driving pin DRV is connected to the delay control module 11, the first pull-up driving transistor M1 and the pull-down driving transistor M2, and is used for receiving an externally input driving signal; the ground pin GND is connected with the pull-down driving tube M3 and the source electrode of the power switch tube M0; the power supply voltage pin VCC is connected with the first pull-up driving tube M1 and the second pull-up driving tube M2; the Gate pin Gate is connected with the Gate of the power switch tube M0.
Referring to fig. 10, the present invention further provides a driving chip 2, where the driving chip 2 includes: a chip body 21 and a driving circuit 1 as described in fig. 4 in the above scheme; the driving circuit 1 is located in the chip main body 21, and the specific structure of the driving circuit 1 is not described here; the chip main body 21 is provided with a driving pin DRV, a grounding pin GND, a power supply voltage pin VCC and a grid pin Gate; the driving pin DRV is connected to the delay control module 11, the first pull-up driving transistor M1 and the pull-down driving transistor M3, and is configured to receive an externally provided driving signal; the ground pin GND is connected with the pull-down driving tube M3 and the source electrode of the power switch tube M0; the power supply voltage pin VCC is connected with the first pull-up driving tube M1 and the second pull-up driving tube M2; the Gate pin Gate is connected with the Gate of the power switch tube M0.
The present invention provides a driving method of a driving circuit as set forth in any of the above aspects, the driving method of the driving circuit at least including:
when the driving signal DRV is at a high level, the first pull-up driving transistor M1 is turned on by the driving signal DRV, and provides a driving current to the power switch M0; if the enable signal SEL is at a high level, when the gate voltage of the power switch M0 crosses the miller platform, the delay control module 11 controls the second pull-up driving transistor M2 to be turned on, and the second pull-up driving transistor M2 and the first pull-up driving transistor M1 together provide a driving current for the power switch M0 to drive the power switch M0 to be turned on; if the enable signal SEL is at a low level, the delay control module 11 controls the second pull-up driving transistor M2 and the first pull-up driving transistor M1 to be turned on simultaneously to provide a driving current for the power switch M0 simultaneously, so as to drive the power switch M0 to be turned on; when the driving signal DRV is at a low level, the pull-down driving transistor M3 is turned on, and the pull-down driving transistor M3 provides a pull-down current for the power switch transistor M0 to turn off the power switch transistor M0.
In summary, the present invention provides a driving circuit, a driving chip and a driving method thereof, wherein the driving circuit at least includes: the device comprises a first pull-up driving pipe, a second pull-up driving pipe, a delay control module and a pull-down driving pipe; the first pull-up driving tube is connected with a driving signal, power voltage and a grid electrode of an external power switching tube and used for conducting to provide driving current for the power switching tube when the driving signal is at a high level; the first pull-up driving tube is switched on at a high level and switched off at a low level; the second pull-up driving tube is connected with the delay control module, the power supply voltage and the power switch tube; the second pull-up driving tube is switched on at a low level and switched off at a high level; the delay control module is connected with the driving signal, an enabling signal and the grid electrode of the power switch tube; when the enable signal is at a high level, the delay control module controls the second pull-up driving tube to be conducted and provide driving current for the power switching tube together with the first pull-up driving tube when the grid voltage of the power switching tube crosses the Miller platform; when the enable signal is at a low level, the delay control module controls the second pull-up driving tube and the first pull-up driving tube to be simultaneously conducted so as to simultaneously provide driving current for the power switching tube; the pull-down driving tube is connected with the driving signal and used for providing pull-down current for the grid electrode of the power switch tube when the driving signal is at a low level. The driving circuit can meet the performance requirements of saving the size cost of the device and outputting higher driving voltage under the condition of smaller device size; the requirements of an EMI environment and an EMI environment are met without changing a metal plate, so that the operation cost and the production cost are further saved; when the requirement of an EMI environment needs to be met, the invention can obtain a better driving waveform through the enabling signal, thereby meeting the requirement of EMI.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A driving circuit, characterized in that the driving circuit comprises at least: the device comprises a first pull-up driving pipe, a second pull-up driving pipe, a delay control module and a pull-down driving pipe; wherein the content of the first and second substances,
the first pull-up driving tube is connected with a driving signal, power voltage and a grid electrode of an external power switching tube and used for conducting to provide driving current for the power switching tube when the driving signal is at a high level; the first pull-up driving tube is switched on at a high level and switched off at a low level;
the second pull-up driving tube is connected with the delay control module, the power supply voltage and the grid electrode of the power switch tube; the second pull-up driving tube is switched on at a low level and switched off at a high level;
the delay control module is connected with the driving signal, an enabling signal and the grid electrode of the power switch tube; when the enable signal is at a high level, the delay control module controls the second pull-up driving tube to be conducted and provide driving current for the power switching tube together with the first pull-up driving tube when the grid voltage of the power switching tube crosses the Miller platform; when the enable signal is at a low level, the delay control module controls the second pull-up driving tube and the first pull-up driving tube to be simultaneously conducted so as to simultaneously provide driving current for the power switching tube;
the pull-down driving tube is connected with the driving signal and used for providing pull-down current for the grid electrode of the power switch tube when the driving signal is at a low level.
2. The drive circuit according to claim 1, wherein: the first pull-up driving tube is an NMOS tube, a grid electrode of the first pull-up driving tube is connected with the driving signal, a drain electrode of the first pull-up driving tube is connected with the power supply voltage, and a source electrode of the first pull-up driving tube is connected with a grid electrode of the power switch tube; the second pull-up driving tube is a PMOS tube, a grid electrode of the second pull-up driving tube is connected with the delay control module, a source electrode of the second pull-up driving tube is connected with the power supply voltage, and a drain electrode of the second pull-up driving tube is connected with a grid electrode of the power switch tube.
3. The drive circuit according to claim 1, wherein: the first pull-up driving tube is an NPN type triode, the base electrode of the first pull-up driving tube is connected with the driving signal, the collector electrode of the first pull-up driving tube is connected with the power supply voltage, and the emitter electrode of the first pull-up driving tube is connected with the grid electrode of the power switch tube; the second pull-up driving tube is a PNP type triode, the base of the second pull-up driving tube is connected with the delay control module, the emitting electrode of the second pull-up driving tube is connected with the power voltage, and the collecting electrode of the second pull-up driving tube is connected with the grid electrode of the power switch tube.
4. The drive circuit according to claim 1, wherein: the driving circuit further comprises a first not gate, and the input end of the first not gate is connected with the driving signal; the pull-down driving tube is an NMOS tube, a grid electrode of the pull-down driving tube is connected with an output end of the first NOT gate, a drain electrode of the pull-down driving tube is connected with a grid electrode of the power switch tube, and a source electrode of the pull-down driving tube is grounded.
5. The drive circuit according to claim 1, wherein: the delay control module includes: the delay unit, the second not gate, the third not gate, the first nor gate, the second nor gate and the fourth not gate; wherein the content of the first and second substances,
the input end of the second NOT gate is connected with the enabling signal; the input end of the third NOT gate is connected with the driving signal; a first input end of the first NOR gate is connected with an output end of the second NOR gate, and a second input end of the first NOR gate is connected with an output end of the delay unit; a first input terminal of the second nor gate is connected to an output terminal of the first nor gate, and a second input terminal of the second nor gate is connected to an output terminal of the third nor gate; the input end of the fourth not gate is connected with the output end of the second nor gate, and the output end of the fourth not gate is connected with the second pull-up driving tube; and the input end of the delay unit is connected with the grid electrode of the power switch tube.
6. The drive circuit according to any one of claims 1 to 5, wherein: the driving circuit further comprises an enable signal generating circuit, wherein the enable signal generating circuit comprises a current source and a fuse; the current source is connected with the fuse in series, the input end of the current source is connected with a power supply, and the output end of the current source is connected with the connecting node of the fuse and the delay control module; and one end of the fuse far away from the current source is grounded.
7. A driving chip is characterized in that: the driving chip includes: a chip body and a drive circuit according to any one of claims 1 to 5; wherein the content of the first and second substances,
the driving circuit is positioned in the chip main body;
the chip main body is provided with an enable pin, a drive pin, a grounding pin, a power supply voltage pin and a grid pin; the enabling pin is connected with the delay control module; the driving pin is connected with the delay control module, the first pull-up driving tube and the pull-down driving tube; the grounding pin is connected with the pull-down driving tube and the source electrode of the power switch tube; the power supply voltage pin is connected with the first pull-up driving tube and the second pull-up driving tube; the grid pin is connected with the grid of the power switch tube.
8. A driving chip is characterized in that: the driving chip includes: a chip body and a drive circuit according to claim 6; wherein the content of the first and second substances,
the driving circuit is positioned in the chip main body;
the chip main body is provided with a driving pin, a grounding pin, a power supply voltage pin and a grid pin; the driving pin is connected with the delay control module, the first pull-up driving tube and the pull-down driving tube; the grounding pin is connected with the pull-down driving tube and the source electrode of the power switch tube; the power supply voltage pin is connected with the first pull-up driving tube and the second pull-up driving tube; the grid pin is connected with the grid of the power switch tube.
9. A driving method of a driving circuit according to any one of claims 1 to 6, characterized by comprising at least:
when the driving signal is at a high level, the first pull-up driving tube is conducted under the action of the driving signal and provides driving current for the power switch tube; if the enable signal is at a high level, when the grid voltage of the power switching tube crosses over the miller platform, the delay control module controls the second pull-up driving tube to be conducted, and the second pull-up driving tube and the first pull-up driving tube together provide driving current for the power switching tube so as to drive the power switching tube to be conducted; if the enable signal is at a low level, the delay control module controls the second pull-up driving tube and the first pull-up driving tube to be simultaneously conducted so as to simultaneously provide a driving current for the power switching tube and drive the power switching tube to be conducted;
when the driving signal is at a low level, the pull-down driving tube is turned on, and the pull-down driving tube provides pull-down current for the power switching tube so as to turn off the power switching tube.
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| CN201810007352.8A CN110011521B (en) | 2018-01-04 | 2018-01-04 | Drive circuit, drive chip and drive method thereof |
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| CN201810007352.8A CN110011521B (en) | 2018-01-04 | 2018-01-04 | Drive circuit, drive chip and drive method thereof |
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| CN111146931B (en) * | 2019-12-23 | 2021-12-14 | 广东美的白色家电技术创新中心有限公司 | Drive circuit of power device and electronic equipment |
| CN114189151B (en) * | 2020-09-15 | 2024-02-06 | 圣邦微电子（北京）股份有限公司 | DC-DC boost converter |
| CN113114195A (en) * | 2021-04-23 | 2021-07-13 | 广东省大湾区集成电路与系统应用研究院 | Power-off closing circuit, power-off closing chip and switch chip |
| CN114070017B (en) * | 2021-07-26 | 2023-08-29 | 杰华特微电子股份有限公司 | Driving circuit, switching power supply and chip layout structure thereof |
| CN116191843B (en) * | 2023-04-26 | 2023-07-25 | 广东华芯微特集成电路有限公司 | Gate driving circuit architecture, control method and BLDC motor driving circuit |
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| CN102684458A (en) * | 2012-05-09 | 2012-09-19 | 矽力杰半导体技术(杭州)有限公司 | Driving circuit of power switching tube and switching power circuit employing driving circuit |
| CN203675086U (en) * | 2013-12-31 | 2014-06-25 | 上海贝岭股份有限公司 | Chip pin multiplexing circuit |
| CN106208637A (en) * | 2016-09-12 | 2016-12-07 | 中国矿业大学 | A kind of drive circuit of switched reluctance machines MOSFET power inverter |
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| TWI402807B (en) * | 2008-05-08 | 2013-07-21 | Novatek Microelectronics Corp | Power sequence control circuit and applications in gate driver and lcd pannel |
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| CN102684458A (en) * | 2012-05-09 | 2012-09-19 | 矽力杰半导体技术(杭州)有限公司 | Driving circuit of power switching tube and switching power circuit employing driving circuit |
| CN203675086U (en) * | 2013-12-31 | 2014-06-25 | 上海贝岭股份有限公司 | Chip pin multiplexing circuit |
| CN106208637A (en) * | 2016-09-12 | 2016-12-07 | 中国矿业大学 | A kind of drive circuit of switched reluctance machines MOSFET power inverter |
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Effective date of registration: 20210107 Address after: 214135 -6, Linghu Avenue, Wuxi Taihu international science and Technology Park, Wuxi, Jiangsu, China, 180 Patentee after: China Resources micro integrated circuit (Wuxi) Co., Ltd Address before: 9-10 / F, building 4 (i.e. building a), 100 Zixiu Road, Minhang District, Shanghai, 201103 Patentee before: CHINA RESOURCES POWTECH (SHANGHAI) Co.,Ltd. |