CN102970015A - Zero dead area grid driving circuit - Google Patents
Zero dead area grid driving circuit Download PDFInfo
- Publication number
- CN102970015A CN102970015A CN2012104305279A CN201210430527A CN102970015A CN 102970015 A CN102970015 A CN 102970015A CN 2012104305279 A CN2012104305279 A CN 2012104305279A CN 201210430527 A CN201210430527 A CN 201210430527A CN 102970015 A CN102970015 A CN 102970015A
- Authority
- CN
- China
- Prior art keywords
- grid
- gate driver
- power tube
- circuit
- driver circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Electronic Switches (AREA)
Abstract
The invention relates to a grid driving circuit which aims at solving the starting problem of a parasitic diode generated by a grid driving circuit in the prior art. The zero dead area grid driving circuit comprises a starting and current offset circuit and a power tube switch control circuit, wherein the starting and current offset circuit comprises three P-channel metal oxide semiconductor (PMOS) tubes (an MP1, an MP2 and an MP3), an N-channel metal oxide semiconductor (NMOS) tube MN1 and an inverter INV1; and the power tube switch control circuit comprises a PMOS tube (an MP4), four NMOS tubes (an MN2, an MN3, an MN4 and an MN5), two inverters (an INV2 and an INV3), two transmission gates (a TG1 and TG2) and a delay unit (DELAY). The grid driving circuit avoids starting of the parasitic diode and avoids loss and electromagnetic interface caused by the parasitic diode. The grid driving circuit is mainly used in direct current/ direct current (DC/DC) converters and various push-pull output circuits adopting PMOS power tubes and NMOS power tubes.
Description
Technical field
The present invention relates to MOS (metal-oxide-semiconductor) memory or be called for short field-effect transistor (english abbreviation is MOSFET or MOS), Drive and Control Circuit, particularly a kind of gate driver circuit that adopts the voltage reducing type voltage stabilizing circuit of PMOS power tube and NMOS power tube.
Background technology
MOSFET is the critical elements that consists of various functional circuits, is topmost active element in the integrated circuit.Particularly as the DC/DC converter of high-power applications, such as BUCK voltage stabilizing circuit (voltage reducing type voltage stabilizing circuit) etc., and the core parts of push-pull output circuit, have very widely purposes.In the above-mentioned application, according to the conduction type of MOSFET, usually be divided into PMOS power tube and NMOS power tube, its gate driver circuit generally all has similar structure.The PMOS power tube that is connected with power supply in the BUCK voltage stabilizing circuit is commonly referred to switching tube, and the NMOS power tube that is connected between PMOS power tube and the ground then is called synchronous rectifier.Fig. 1 shows BUCK voltage stabilizing circuit typical structure, the square-wave signal MS of loop comparator (not shown) output, produce circuit through Dead Time and produce grid driving signal MSP and the MSN with certain Dead Time, be input to respectively in the grid drive circuit of switching tube PMOS and synchronous rectifier NMOS, be converted to control signal DP and the DN of power ratio control switching device, respectively control switch pipe PMOS and synchronous rectifier NMOS fast conducting and shutoff, convert supply voltage VDC to pulse voltage output, by external inductance L and the backward load R power supply of capacitor C rectification.Under the control of enable signal EN, this gate driver circuit can be realized following function:
(1) utilizes simple logic control circuit, grid are driven grid control signal DP and the DN that signal MSP and MSN convert respectively switching tube PMOS and synchronous rectifier NMOS to, realize basic driving function.
(2) time delay by two chain of inverters realizes Dead Time control, thereby avoids switching tube and simultaneously conducting of synchronous rectifier, prevents punch through, improves the reliability of chip.
But the existence meeting of Dead Time so that circuit work process in, the time that exists switching tube PMOS and synchronous rectifier NMOS to turn-off simultaneously.Because the inductance L electric current can not suddenly change, the parasitic body diode of synchronous rectifier will be opened, thereby produces the voltage jump of a diode current flow pressure drop, and there is reverse recovery current in diode, and this can cause the increase of power consumption.In addition, diode current flow and shutoff exist larger voltage change ratio (dv/dt) and current changing rate (di/dt), can produce larger electromagnetic interference.
Summary of the invention
Technical problem to be solved by this invention just provides a kind of zero dead band gate driver circuit, is used for driving PMOS power tube and NMOS power tube, improves circuit performance.
The present invention solve the technical problem, and the technical scheme of employing is that zero dead band gate driver circuit comprises startup and current biasing circuit and power tube ON-OFF control circuit; Wherein, start with current biasing circuit and comprise 3 PMOS pipes: MP1, MP2, MP3,1 NMOS pipe: MN1, and inverter: INV1, the power tube ON-OFF control circuit comprises 1 PMOS pipe: MP4,4 NMOS pipes: MN2, MN3, MN4, MN5,2 inverter: INV2, INV3,2 transmission gate: TG1, TG2, and delay unit: DELAY; Enable signal EN and the grid of MP1 are connected input and are connected with INV1, the drain electrode of MP1 is connected with the grid of the drain electrode of MP2, grid and MP3, and the electric current that connects outside input, the output of INV1 is connected to the grid of MN1, the drain electrode of MP3 links to each other with the drain electrode of MN1 and links to each other with the input of power tube ON-OFF control circuit with the output of current biasing circuit as starting, the source electrode of MP1, MP2, MP3 meets power vd D, the source ground of MN1 pipe; The input of power tube ON-OFF control circuit and TG1, TG2 and MP4 miss connection, and be connected with the grid of NMOS power tube, be connected with the drain electrode of MN5 in addition, the input of control signal MSN end and INV2, the input of DELAY, the N tube grid of TG1 connects, and be connected with the grid of MP4 pipe, the INV2 output is connected with the P tube grid of TG1, and be connected with the grid of MN2, the grid of MN2 is connected with TG1, and be connected with the grid of MN3, the output of DELAY is connected with the input of INV3, and is connected with the N tube grid of transmission gate TG2, and the output of INV3 is connected with the P tube grid of transmission gate TG2, and be connected with the grid of MN4, TG2 is connected with the grid of MN5, and the source electrode of MP4 meets power vd D, MN2, MN3, MN4, the source ground of MN5.
Preferably, described zero dead band gate driver circuit is used for voltage reducing type voltage stabilizing circuit, consist of PMOS power tube gate driver circuit and NMOS power tube gate driver circuit in the described voltage reducing type voltage stabilizing circuit, described PMOS power tube gate driver circuit is connected to Dead Time and produces between circuit and the PMOS power tube, and described NMOS power tube gate driver circuit is connected to Dead Time and produces between circuit and the NMOS power tube.
Further, described PMOS power tube gate driver circuit and NMOS power tube gate driver circuit and described voltage reducing type voltage stabilizing circuit are integrated in the same chip.
Preferably, described zero dead band gate driver circuit is used for adopting the push-pull output circuit of PMOS power tube and NMOS power tube, consists of the gate driver circuit of described PMOS power tube and NMOS power tube.
Further, described zero dead band gate driver circuit and push-pull output circuit are integrated in the same chip.
Concrete, described delay unit is made of n inverter series connection, and n is positive integer, n 〉=2.
More specifically, a described n inverter has same structure.
The invention has the beneficial effects as follows, can avoid parasitic body diode to open, prevent loss and electromagnetic interference that parasitic body diode causes, thus the further increase system efficiency of energy, and the electromagnetic interference of reduction system.
Description of drawings
Fig. 1 is BUCK voltage regulator circuit structure schematic diagram;
Fig. 2 is the electrical block diagram of embodiment 1;
Fig. 3 zero dead band gate driver circuit waveform schematic diagram.
Among the figure: PMOS is switching tube; NMOS is synchronous rectifier; L is inductance; C is electric capacity; R is load; MN1, MN2, MN3, MN4, MN5 are the NMOS pipe; MP1, MP2, MP3, MP4 are the PMOS pipe; TG1, TG2 are transmission gate; INV1, INV2, INV3 are inverter; DELAY is delay unit.
Embodiment
Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail.
Embodiment 1
Referring to Fig. 2, be zero dead band gate driver circuit of the present invention, be used for the typical structure of voltage reducing type voltage stabilizing circuit.PMOS power tube gate driver circuit and NMOS power tube gate driver circuit have similar structures in this voltage reducing type voltage stabilizing circuit, consist of by zero dead band gate driver circuit of the present invention.PMOS power tube gate driver circuit is connected to Dead Time and produces between circuit and the PMOS power tube, described MOS power tube gate driver circuit is connected to Dead Time and produces between circuit and the NMOS power tube grid, only shows the structure of NMOS power tube gate driver circuit among Fig. 2.In the circuit shown in Figure 2, except inductance L, capacitor C and load R, other elements all are integrated in the same chip, consist of this routine voltage reducing type voltage stabilizing circuit.
This example zero dead band gate driver circuit comprises startup and current biasing circuit and power tube ON-OFF control circuit, as shown in Figure 2.Wherein, startup comprises 3 PMOS pipes with current biasing circuit: MP1, MP2, MP3,1 NMOS pipe: MN1, and inverter: INV1.The power tube ON-OFF control circuit comprises 1 PMOS pipe: MP4,4 NMOS pipes: MN2, MN3, MN4, MN5,2 inverter: INV2, INV3,2 transmission gate: TG1, TG2, and delay unit: DELAY.Enable signal EN and the grid of MP1 are connected input and are connected with INV1, the drain electrode of MP1 is connected with the grid of the drain electrode of MP2, grid and MP3, and the electric current I B that connects outside input, the output of INV1 is connected to the grid of MN1, and the drain electrode of MP3 links to each other with the drain electrode of MN1 and links to each other with the input of power tube ON-OFF control circuit with the output of current biasing circuit as starting.The source electrode of MP1, MP2, MP3 meets power vd D, the source ground of MN1 pipe.The input of rate pipe ON-OFF control circuit is connected with missing of TG1, TG2 and MP4, and is connected with the grid of NMOS power tube, is connected with the drain electrode of MN5 in addition.Control signal MSN end is connected with the input of INV2, the input of DELAY, the N tube grid of TG1, and be connected with the grid of MP4 pipe, the INV2 output is connected with the P tube grid of transmission gate TG1, and be connected with the grid of MN2, the grid of MN2 is connected with transmission gate TG1, and is connected with the grid of MN3.The output of DELAY is connected with the input of INV3, and be connected with the N tube grid of TG2, the output of INV3 is connected with the P tube grid of TG2, and be connected with the grid of MN4, transmission gate TG2 is connected with the grid of MN5, the source electrode of MP4 meets power vd D, the source ground of MN2, MN3, MN4, MN5.This routine delay unit adopts n inverter series connection with same structure to consist of, and n is positive integer, and different time-delay needs can be satisfied in n 〉=2.
The operation principle of this example zero dead band gate driver circuit is described below:
As shown in Figure 3, MS is the alternately square wave of conversion of high-low level, produces circuit by Dead Time and produces grid driving signal MSP, the MSN with certain Dead Time, is input to respectively in the zero dead band gate driver circuit of switching tube PMOS and synchronous rectifier NMOS.Because the gate driver circuit of switching tube PMOS and synchronous rectifier NMOS is similarly, so take the gate driver circuit of synchronous rectification NMOS as example, describe.When the MS signal is low level, the grid of switching tube PMOS and synchronous rectifier NMOS all is high level, switching tube PMOS conducting, synchronous rectifier NMOS turn-offs, when the MS signal is high level, then the grid of switching tube PMOS and synchronous rectifier NMOS is low level simultaneously, so switching tube PMOS turn-offs synchronous rectifier NMOS unlatching.When MS was turned to high level from low level, the MSN signal was followed the MS signal intensity, and transmission gate TG1, MN3 open, and MN2 turn-offs, so that the source electrode of MN3 links to each other with drain electrode, consisted of the structure that diode connects.The voltage of DN discharges by MN3, the lower voltage of DN port, because the existence of inductance L, the electric current of synchronous rectifier NMOS then remains unchanged.Because MN3 is operated in the saturation region, the final voltage that can obtain DN according to metal-oxide-semiconductor saturation region formula is V
1
When the voltage of DN is V
1The time, synchronous rectifier NMOS is operated in the saturation region.Therefore inductive current can flow through and not open the body diode of NMOS synchronous rectifier parasitism from synchronous rectifier NMOS.Then, after the MSN square-wave signal is through the DELAY time-delay, transmission gate TG2, MN5 are opened, MN4 turn-offs.The source electrode of MN5 is connected with drain electrode, consists of the structure that diode connects.But the breadth length ratio of MN5 will be much larger than the breadth length ratio of MN3, and MN5 is operated in sub-threshold region.Therefore DN voltage can drop to and be slightly less than threshold voltage V
Th, since this moment inductance L and switching tube tie point X current potential less than zero, then synchronous rectifier NMOS generating source, leak exchange, and be operated in the saturation region, continue to keep inductive current.At control signal DN voltage drop to threshold voltage V
ThIn near the process, the MSP signal produces circuit so that control signal DP is reversed to low level by high level by Dead Time.Switching tube PMOS grid voltage descends rapidly, thereby X point current potential is drawn high gradually.The source of synchronous rectifier NMOS, leak when X point current potential is greater than zero and again exchange, and be operated in sub-threshold region, thereby in the very little situation of the electric current on the assurance synchronous rectifier NMOS, opening switch pipe PMOS.By can allow synchronous rectifier NMOS parasitic body diode when turn-offing to open with upper type, reduce power consumption and electromagnetic interference, and avoided the alive generation of excessive string.
When MS is turned to low level from high level, the MSP signal is low level by high level upset also thereupon, and the gate driver circuit of switching tube PMOS is elevated to certain value with the control signal DP voltage of the grid of switching tube PMOS, pass through again delay circuit, control signal DP is risen to be slightly larger than V
DD-V
THNear, thereby so that switching tube PMOS is operated in sub-threshold region.When switching tube PMOS progresses into sub-threshold region, the MSN signal produces circuit by Dead Time synchronous rectifier NMOS is opened, so that in the very little situation of switching tube PMOS electric current, open synchronous rectifier NMOS, thereby the parasitic body diode that prevents synchronous rectifier NMOS is opened, reduce loss and electromagnetic interference, and avoided the alive generation of excessive string.
Embodiment 2
This example zero dead band gate driver circuit is used for adopting the push-pull output circuit of PMOS power tube and NMOS power tube, such as the various push-pull power amplifier circuits that field-effect transistor forms, consists of the gate driver circuit of PMOS power tube and NMOS power tube.This routine circuit can adopt integrated circuit technique equally, and zero dead band gate driver circuit and push-pull output circuit are integrated in the same chip, consists of mmic power amplifier.
Claims (7)
1. zero dead band gate driver circuit comprises startup and current biasing circuit and power tube ON-OFF control circuit; Wherein, start with current biasing circuit and comprise 3 PMOS pipes: MP1, MP2, MP3,1 NMOS pipe: MN1, and inverter: INV1, the power tube ON-OFF control circuit comprises 1 PMOS pipe: MP4,4 NMOS pipes: MN2, MN3, MN4, MN5,2 inverter: INV2, INV3,2 transmission gate: TG1, TG2, and delay unit: DELAY; Enable signal EN and the grid of MP1 are connected input and are connected with INV1, the drain electrode of MP1 is connected with the grid of the drain electrode of MP2, grid and MP3, and the electric current that connects outside input, the output of INV1 is connected to the grid of MN1, the drain electrode of MP3 links to each other with the drain electrode of MN1 and links to each other with the input of power tube ON-OFF control circuit with the output of current biasing circuit as starting, the source electrode of MP1, MP2, MP3 meets power vd D, the source ground of MN1 pipe; The input of power tube ON-OFF control circuit and TG1, TG2 and MP4 miss connection, and be connected with the grid of NMOS power tube, be connected with the drain electrode of MN5 in addition, the input of control signal MSN end and INV2, the input of DELAY, the N tube grid of TG1 connects, and be connected with the grid of MP4 pipe, the INV2 output is connected with the P tube grid of TG1, and be connected with the grid of MN2, the grid of MN2 is connected with TG1, and be connected with the grid of MN3, the output of DELAY is connected with the input of INV3, and is connected with the N tube grid of transmission gate TG2, and the output of INV3 is connected with the P tube grid of transmission gate TG2, and be connected with the grid of MN4, TG2 is connected with the grid of MN5, and the source electrode of MP4 meets power vd D, MN2, MN3, MN4, the source ground of MN5.
2. zero dead band gate driver circuit according to claim 1, it is characterized in that, described zero dead band gate driver circuit is used for voltage reducing type voltage stabilizing circuit, consist of PMOS power tube gate driver circuit and NMOS power tube gate driver circuit in the described voltage reducing type voltage stabilizing circuit, described PMOS power tube gate driver circuit is connected to Dead Time and produces between circuit and the PMOS power tube, and described NMOS power tube gate driver circuit is connected to Dead Time and produces between circuit and the NMOS power tube.
3. zero dead band gate driver circuit according to claim 2 is characterized in that described PMOS power tube gate driver circuit and NMOS power tube gate driver circuit and described voltage reducing type voltage stabilizing circuit are integrated in the same chip.
4. zero dead band gate driver circuit according to claim 1, it is characterized in that, described zero dead band gate driver circuit is used for adopting the push-pull output circuit of PMOS power tube and NMOS power tube, consists of the gate driver circuit of described PMOS power tube and NMOS power tube.
5. zero dead band gate driver circuit according to claim 4 is characterized in that, described zero dead band gate driver circuit and push-pull output circuit are integrated in the same chip.
6. the described zero dead band gate driver circuit of any one is characterized in that according to claim 1～5, and described delay unit is made of n inverter series connection, and n is positive integer, n 〉=2.
7. zero dead band gate driver circuit according to claim 6 is characterized in that a described n inverter has same structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210430527.9A CN102970015B (en) | 2012-11-01 | 2012-11-01 | Zero dead area grid driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210430527.9A CN102970015B (en) | 2012-11-01 | 2012-11-01 | Zero dead area grid driving circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102970015A true CN102970015A (en) | 2013-03-13 |
| CN102970015B CN102970015B (en) | 2015-01-21 |
Family
ID=47799926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210430527.9A Expired - Fee Related CN102970015B (en) | 2012-11-01 | 2012-11-01 | Zero dead area grid driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102970015B (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103944553A (en) * | 2014-04-18 | 2014-07-23 | 京东方科技集团股份有限公司 | Output buffer, gate driving circuit and control method of gate driving circuit |
| CN103944402A (en) * | 2014-04-15 | 2014-07-23 | 广州金升阳科技有限公司 | Control method of excited push-pull converter with zero-voltage switching and excited push-pull converter |
| CN104579267A (en) * | 2013-10-18 | 2015-04-29 | 施耐德电器工业公司 | Pulse drive circuit and pulse drive method |
| CN107026561A (en) * | 2016-02-01 | 2017-08-08 | 华润矽威科技（上海）有限公司 | Gate driving circuit and method |
| CN108390549A (en) * | 2018-04-17 | 2018-08-10 | 电子科技大学 | A kind of gate drive circuit reducing dead time |
| CN109450382A (en) * | 2018-10-10 | 2019-03-08 | 湖南国科微电子股份有限公司 | A kind of operational amplifier and signal amplifying apparatus |
| CN110943718A (en) * | 2019-12-26 | 2020-03-31 | 电子科技大学 | Output stage circuit of high-side switch |
| CN112015093A (en) * | 2019-05-31 | 2020-12-01 | 广东美的制冷设备有限公司 | Drive control method, device, household appliance and computer readable storage medium |
| CN113054839A (en) * | 2021-03-30 | 2021-06-29 | 京东方科技集团股份有限公司 | Power management circuit and display panel |
| CN114189151A (en) * | 2020-09-15 | 2022-03-15 | 圣邦微电子（北京）股份有限公司 | DC-DC boost converter |
| WO2022133691A1 (en) * | 2020-12-21 | 2022-06-30 | 华为技术有限公司 | Switch circuit and switch power supply |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004140423A (en) * | 2002-10-15 | 2004-05-13 | Denso Corp | Load driver circuit with current detecting function |
| US6967520B2 (en) * | 2002-10-21 | 2005-11-22 | Canon Kabushiki Kaisha | Gate drive circuit, which makes the gate-charge flow back to the load and the main power source |
| CN101345474A (en) * | 2007-06-01 | 2009-01-14 | 国际整流器公司 | Intelligent dead time control |
| US7606082B2 (en) * | 2005-09-16 | 2009-10-20 | Fuji Electric Device Technology Co., Ltd. | Semiconductor circuit, inverter circuit, semiconductor apparatus, and manufacturing method thereof |
-
2012
- 2012-11-01 CN CN201210430527.9A patent/CN102970015B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004140423A (en) * | 2002-10-15 | 2004-05-13 | Denso Corp | Load driver circuit with current detecting function |
| US6967520B2 (en) * | 2002-10-21 | 2005-11-22 | Canon Kabushiki Kaisha | Gate drive circuit, which makes the gate-charge flow back to the load and the main power source |
| US7606082B2 (en) * | 2005-09-16 | 2009-10-20 | Fuji Electric Device Technology Co., Ltd. | Semiconductor circuit, inverter circuit, semiconductor apparatus, and manufacturing method thereof |
| CN101345474A (en) * | 2007-06-01 | 2009-01-14 | 国际整流器公司 | Intelligent dead time control |
Non-Patent Citations (1)
| Title |
|---|
| 何惠森等: "一种精简的高速率功率ＭＯＳ驱动器", 《西安电子科技大学学报》 * |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104579267A (en) * | 2013-10-18 | 2015-04-29 | 施耐德电器工业公司 | Pulse drive circuit and pulse drive method |
| CN103944402A (en) * | 2014-04-15 | 2014-07-23 | 广州金升阳科技有限公司 | Control method of excited push-pull converter with zero-voltage switching and excited push-pull converter |
| CN103944402B (en) * | 2014-04-15 | 2016-08-17 | 广州金升阳科技有限公司 | The control method of the independent-excited push-pull converter of a kind of ZVT and changer |
| CN103944553B (en) * | 2014-04-18 | 2017-10-24 | 京东方科技集团股份有限公司 | A kind of output buffer, gate driving circuit and its control method |
| CN103944553A (en) * | 2014-04-18 | 2014-07-23 | 京东方科技集团股份有限公司 | Output buffer, gate driving circuit and control method of gate driving circuit |
| CN107026561A (en) * | 2016-02-01 | 2017-08-08 | 华润矽威科技（上海）有限公司 | Gate driving circuit and method |
| CN108390549A (en) * | 2018-04-17 | 2018-08-10 | 电子科技大学 | A kind of gate drive circuit reducing dead time |
| CN109450382A (en) * | 2018-10-10 | 2019-03-08 | 湖南国科微电子股份有限公司 | A kind of operational amplifier and signal amplifying apparatus |
| CN109450382B (en) * | 2018-10-10 | 2023-03-14 | 湖南国科微电子股份有限公司 | Operational amplifier and signal amplification device |
| CN112015093B (en) * | 2019-05-31 | 2022-02-11 | 广东美的制冷设备有限公司 | Drive control method, device, household appliance and computer readable storage medium |
| CN112015093A (en) * | 2019-05-31 | 2020-12-01 | 广东美的制冷设备有限公司 | Drive control method, device, household appliance and computer readable storage medium |
| CN110943718A (en) * | 2019-12-26 | 2020-03-31 | 电子科技大学 | Output stage circuit of high-side switch |
| CN110943718B (en) * | 2019-12-26 | 2023-03-31 | 电子科技大学 | Output stage circuit of high-side switch |
| CN114189151A (en) * | 2020-09-15 | 2022-03-15 | 圣邦微电子（北京）股份有限公司 | DC-DC boost converter |
| CN114189151B (en) * | 2020-09-15 | 2024-02-06 | 圣邦微电子（北京）股份有限公司 | DC-DC boost converter |
| WO2022133691A1 (en) * | 2020-12-21 | 2022-06-30 | 华为技术有限公司 | Switch circuit and switch power supply |
| CN113054839A (en) * | 2021-03-30 | 2021-06-29 | 京东方科技集团股份有限公司 | Power management circuit and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102970015B (en) | 2015-01-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102970015B (en) | Zero dead area grid driving circuit | |
| US10673426B2 (en) | Switch bootstrap charging circuit suitable for gate drive circuit of GaN power device | |
| CN104022776B (en) | Bootstrapping diode artificial circuit in half-bridge driving circuit | |
| CN101561687B (en) | Synchronous booster circuit with active negative current modulation and control method thereof | |
| CN203206197U (en) | Delay circuit and circuit system with same | |
| CN108768145A (en) | High speed half-bridge gate drive circuit suitable for GaN device for power switching | |
| CN103178694A (en) | Insulated gate bipolar transistor gate driving push-pull circuit | |
| CN101976940A (en) | Drive bootstrap circuit for switching tube of switching power supply converter | |
| CN105187047A (en) | Ultra-high-voltage level shifting circuit for IGBT (Insulated Gate Bipolar Translator) driving chip | |
| CN116742920B (en) | NMOS power switch tube driving circuit and control method thereof | |
| WO2012037806A1 (en) | Power transistor circuit for preventing current backflow | |
| Xue et al. | A 99%-efficiency 1-MHz 1.6-kW zero-voltage-switching boost converter using normally-off GaN power transistors and adaptive dead-time controlled gate drivers | |
| CN111525791B (en) | Low-voltage high-conversion-efficiency charge pump circuit | |
| CN110277914B (en) | Reverse flow comparator suitable for Boost converter | |
| CN103427624A (en) | Anti-ringing circuit for integrated voltage-reducing direct current/direct current (DC/DC) switch converter | |
| CN103715870A (en) | Voltage regulator and resonance gate driver thereof | |
| CN202586786U (en) | Synchronous rectification circuit based on synchronous rectification chip low-voltage-output push-pull converter | |
| CN105811960A (en) | Level shifting circuit using thin gate oxide MOS tubes | |
| CN102545560B (en) | Power switch driver, IC chip, and DC-DC converter | |
| CN102170232B (en) | Self-driven active buffer and flyback switching mode power supply | |
| CN114268219B (en) | Bootstrap circuit for driving high-side NMOS (N-channel metal oxide semiconductor) tube | |
| Zheng et al. | A High-Speed Level Shifter with dV s/dt Noise Immunity Enhancement Structure for 200V Monolithic GaN Power IC | |
| CN113162373A (en) | full-GaN integrated gate drive circuit with dead time control | |
| CN109149925B (en) | A kind of buck circuit | |
| CN102447378B (en) | Buffer switch circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150121 Termination date: 20151101 |
|
| EXPY | Termination of patent right or utility model |