JPH05268009A - Delay circuit - Google Patents

Abstract

PURPOSE:To prevent dispersion in the process and fluctuation of a delay time by forming a current control CMOS inverter circuit. CONSTITUTION:A P-channel MOS transistor(TR) Trp driven by a constant current is connected between a high potential side Vcc and a P-channel MOS TR of a conventional CMOS inverter circuit 1 and an N-channel MOS transistor(TR) Trn driven by a constant current is connected between a low potential side Vss and an N-channel MOS TR of the circuit 1 to form a current control type CMOS inverter circuit 3, the TRs Trp, Trn are driven by a constant current at a current mirror 2, and the circuits 3, 1 are connected in series in multi-stage. Thus, the dispersion in the process and fluctuation of a delay time due to fluctuation in a power supply voltage or ambient temperature are prevented and an unsharpened output signal waveform is not caused.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit formed in a semiconductor integrated circuit. In recent years, semiconductor integrated circuits have become more highly integrated and faster. Therefore, it is required that the delay circuit for generating the timing signal for setting the operation timing of the internal circuit always output the timing signal with an accurate delay time.

[0002]

2. Description of the Related Art In a conventional delay circuit, for example, as shown in FIG. 3, a large number of CMOS inverter circuits 1 are connected in series, and an input signal I is input to the first CMOS inverter circuit 1.
When N is input, the output signal OUT is output from the CMOS inverter circuit 1 at the final stage after a delay time corresponding to the number of stages of all the CMOS inverter circuits 1.

In such a delay circuit, the current amplification factor of each transistor constituting each CMOS inverter circuit 1 and each CMO are changed depending on the process variation or the ambient temperature.
The threshold value of the S inverter circuit 1 may fluctuate, and the delay time of the CMOS inverter circuit 1 in each stage may fluctuate.

In such a case, the desired delay time may not be obtained even if the CMOS inverter circuits 1 having the number of stages corresponding to the delay time are connected to obtain the predetermined delay time.

Further, variations in the power supply voltages of the power supplies Vcc and Vss also cause variations in the delay time. Therefore, in the delay circuit shown in FIG. 4, P is provided between the P-channel MOS transistor of the CMOS inverter circuit and the power supply Vcc.
While connecting the channel MOS transistor Trp,
The N-channel MOS transistor Trn is connected between the N-channel MOS transistor of the CMOS inverter circuit and the power supply Vss, and the P-channel MOS transistor Trp and the N-channel MOS transistor Trn are driven by the current mirror circuit 2 to generate a multi-stage current. The control type CMOS inverter circuit 3 is configured.

The current-controlled CMOS inverter circuit 3 is connected in multiple stages in series, and the first-stage current-controlled C
When the input signal IN is input to the MOS inverter circuit 3, the output signal OUT is output from the current control type CMOS inverter circuit 3 at the final stage after a delay time corresponding to the number of stages.

In such a delay circuit, since the operating current flowing through each current control type CMOS inverter circuit 3 is maintained constant by each P channel MOS transistor Trp and N channel MOS transistor Trn, each current control type CMOS inverter The delay time of the circuit 3 is kept the same.

Further, since the operating current of each current control type CMOS inverter circuit 3 is maintained constant even if the power supply voltage of the power supplies Vcc, Vss or the ambient temperature changes, the delay of each current control type CMOS inverter circuit 3 is delayed. The time is kept constant.

[0009]

However, in the delay circuit including the current control type CMOS inverter circuit 3 as described above, each P channel MOS transistor Trp and N channel MOS transistor Trn are used to control each current control type CM.
Since the peak current of the OS inverter circuit 3 is limited, the rising and falling of the output signal of each current control type CMOS inverter circuit 3 becomes dull.

Therefore, in a delay circuit in which a large number of current-controlled CMOS inverter circuits 3 are connected in series, the waveform of the output signal OUT becomes dull, which makes it difficult to set the delay time accurately and to reduce the load. Driving ability is reduced.

An object of the present invention is to provide a delay circuit which prevents fluctuations in delay time due to fluctuations in processes and fluctuations in power supply voltage or ambient temperature, and which does not dull the output signal waveform.

[0012]

FIG. 1 illustrates the principle of the present invention. That is, the normal type CMOS inverter circuit 1
A P-channel MOS transistor Trp driven by a constant current is connected between the P-channel MOS transistor and the high-potential-side power supply Vcc, and the normal CMOS inverter circuit 1
The N channel MOS transistor Trn driven by a constant current is connected between the N channel MOS transistor and the low-potential-side power source Vss to connect the current control type CMOS inverter circuit 3
The P-channel MOS transistor Trp and the N-channel MOS transistor Trn are driven by the current mirror circuit 2 at a constant current, and the current control type CMOS inverter circuit 3 and the normal type CMOS inverter circuit 1 are mixed in series. Multiple stages are connected.

[0013]

The current control type CMOS inverter circuit 3 suppresses the variation of the delay time due to the variation of the process and the variation of the power supply voltage or the ambient temperature, and the normal type CMOS inverter circuit 1 improves the blunting of the output signal waveform.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will now be described with reference to FIG.
Follow the instructions below. The delay circuit shown in FIG. 2 is a combination of the current control type CMOS inverter circuit 3 and the normal CMOS inverter circuit 1, and the current control type CMOS inverter circuit 3 is connected in series from the first stage to a plurality of stages, and the intermediate stage. 2 stages of normal type CMOS inverter circuit 1
Are connected in series, followed by multiple stages of current control type CMOS
The inverter circuit 3 is connected in series, and the final stage is a normal CM
The OS inverter circuit 1 is connected.

The current control type CMOS inverter circuit 3
The P-channel MOS transistor Trp and the N-channel MOS transistor Trn for controlling the operating current of the are driven by the current mirror circuit 2.

That is, in the current mirror circuit 2, the sources of the P-channel MOS transistors Tr1 and Tr2 are the power source Vcc.
The gates of the transistors Tr1 and Tr2 are connected to each other and to the drain of the transistor Tr1. The drain of the transistor Tr1 is connected to the power supply Vss via the current source 4.

The drain of the transistor Tr2 is connected to the drain of the N-channel MOS transistor Tr3, the gate of the transistor Tr3 is connected to the drain, and the source is connected to the power supply Vss.

The gates of the transistors Tr1 and Tr2 are the P of the current control type CMOS inverter circuit 3.
Connected to the gate of the channel MOS transistor Trp,
The gate of the transistor Tr3 is the current control type CMO.
It is connected to the gate of each N-channel MOS transistor Trn of the S inverter circuit 3.

In the delay circuit thus constructed, when the input signal IN is input to the first-stage current control type CMOS inverter circuit 3, the intermediate stage via the current control type CMOS inverter circuit 3 connected in series. Normal CM
A delayed output signal having a blunt waveform is output to the OS inverter circuit 1.

The blunting of the waveform is improved in the normal CMOS inverter circuit 1 in the intermediate stage, and the delayed output signals of the current-controlled CMOS inverter circuits 3 in a plurality of stages are changed in waveform in the normal CMOS inverter circuit 1 in the final stage. The dullness is improved and the output signal OUT is output.

Therefore, this delay circuit can obtain a constant delay time irrespective of the fluctuation of the power supply voltage and the ambient temperature by the multistage current control type CMOS inverter circuit 3, and also the multistage current control type CMOS inverter circuit. The blunting of the output signal waveform due to No. 3 is the normal type CMO in the intermediate stage.
The S inverter circuit 1 and the normal CMOS inverter circuit 1 at the final stage can be improved to set an accurate delay time, and the load driving capability can be improved.

[0022]

As described above in detail, the present invention provides a delay circuit which prevents fluctuations in delay time due to process variations and fluctuations in power supply voltage or ambient temperature, and which does not blunt the output signal waveform. It can exert an excellent effect.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing an example.

FIG. 3 is a circuit diagram showing a conventional example.

FIG. 4 is a circuit diagram showing another conventional example.

[Explanation of symbols]

 1 Normal type CMOS inverter circuit 2 Current mirror circuit 3 Current control type CMOS inverter circuit Vcc High potential side power source Vss Low potential side power source Trp P channel MOS transistor Trn N channel MOS transistor

Claims (1)

[Claims] 1. A P-channel MOS transistor of a normal type CMOS inverter circuit (1) and a high potential side power source (Vcc)
A P-channel MOS transistor (Trp) driven by a constant current is connected between and, and a constant current is driven between the N-channel MOS transistor of the normal type CMOS inverter circuit (1) and the low potential side power source (Vss). N channel MOS
A transistor (Trn) is connected to form a current control type CMOS inverter circuit (3), and the P-channel MOS transistor (Trp) and the N-channel MOS transistor (Trn) are driven by a current mirror circuit (2) at a constant current.
A delay circuit characterized in that the current control type CMOS inverter circuit (3) and the normal type CMOS inverter circuit (1) are mixed and connected in multiple stages in series.