CN1300943C

CN1300943C - Electric voltage carrying circuit

Info

Publication number: CN1300943C
Application number: CNB2004100040306A
Authority: CN
Inventors: 黄友利
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2004-02-04
Filing date: 2004-02-04
Publication date: 2007-02-14
Anticipated expiration: 2024-02-04
Also published as: CN1558554A

Abstract

The present invention relates to a voltage transfer circuit which mainly comprises an input control circuit, a high standard position voltage supply circuit and a pressure-drop circuit, wherein the input control circuit receives a control signal of a low standard position voltage source to generate a reversed phase control signal. The high standard position voltage supply circuit provides a high standard position voltage source. The pressure-drop circuit is arranged between the input control circuit and a high standard position switch circuit and comprises a high standard position control member and a low standard position control member. The high standard position control member has a pressure-drop function so as to protect the low standard position control member; the low standard position control member uses the control signal and the reversed phase control signal to control switch switching so as to drive the high standard position voltage source of the high standard position voltage supply circuit as output.

Description

Level shift circuit

Technical field

The invention relates to a kind of level shift (Level shifter) circuit, refer to a kind of high-tension level shift circuit of low voltage transition that is applicable to especially.

Background technology

Level shift circuit normally is used for carrying out the voltage transitions action, for example: the control signal that the control signal of low voltage is converted to high voltage.Because the employed electronic component of this circuit is few, and real easily the work, therefore be widely used in the scanning in the driver products such as (Scan Driver) of computer system, flat-panel screens at present.

Fig. 1 shows the schematic diagram of at present common level shift circuit, it is made up of an input stage voltage conversion circuit 11, first output circuit 12 and second output circuit 13, wherein, input stage voltage conversion circuit 11 is by P metal-oxide semiconductor (MOS) (PMOS) 111,112 and N metal-oxide semiconductor (MOS) (NMOS) 113, the inverter 115 that 114 contour compacting journey electronic components and are driven by low reference voltage source VDD is formed, first output circuit 12 is made up of PMOS121 and NMOS122, and second output circuit 13 is made up of PMOS131 and NMOS132.

The input stage voltage conversion circuit 11 main input signal A of seeing through (use low reference voltage source VDD, wherein VDD at high voltage between 2.3～2.5, low-voltage is 0) control these PMOS111,112 and NMOS113,114 export high reference voltage signal VPP (general high voltage is 3.3V down), then see through first output circuit 12 and second output circuit 13 and exported, wherein, first output circuit 12 is opposite with the phase place of the signal that second output circuit 13 is exported.

When the input of this inverter 115 was imported 2.5 volts input signal A, the grid of NMOS113 received 0 volt control signal, and the grid of NMOS114 receives 2.5 volts control signal, is that NMOS113 closes (OFF), NMOS114 conducting (ON).Because NMOS113 closes and the NMOS114 conducting, so the PMOS111 conducting, PMOS112 closes, and PMOS121 is conducting then, and NMOS122 closes, and B names a person for a particular job and exports as height with reference to control signal with 3.3 volts VPP.In addition, PMOS131 then closes, the NMOS132 conducting, and the height that the output of C point is 0 volt is with reference to control signal.

Similar ground, if during the control signal that input signal A input is 0 volt, the NMOS113 conducting, NMOS114 closes, PMOS111 closes, the PMOS112 conducting, PMOS121 closes, the NMOS122 conducting, at the height of one 0 volts of B point outputs with reference to control signal, and the PMOS131 conducting, NMOS132 closes, C point output another with the height of 3.3 volts VPP with reference to control signal.

Yet, foregoing circuit has its shortcoming, because the more and more advanced process that see through of present integrated circuit produce, low reference voltage source VDD is more and more lower (for example reducing between 1～1.5V), the critical voltage that therefore will cause the NMOS that lower low reference voltage source VDD can't conducting high pressure manufacturing process element (for example 113 of Fig. 1 and 114), that is to say, if low reference voltage source is less than the critical voltage of high pressure manufacturing process element, then can't open (ON) high pressure manufacturing process element, and make whole level shift circuit to move.In addition, the high voltage of low reference voltage source VDD is low excessively by (1～1.5V), and only under the critical voltage situation a little more than high voltage devices, the rising/falling waveform of the signal of its output will be uneven, that is the transition time of this circuit is more of a specified duration.

Summary of the invention

Main purpose of the present invention is that a kind of level shift circuit is being provided, so that can provide the work period and the rising/decline transition speed of a balance when different input voltages.

Another object of the present invention is that a kind of level shift circuit is being provided, so that can improve the reliability and the stable operation degree of circuit.

For reaching aforesaid purpose, level shift circuit of the present invention comprises: an input control circuit, a height are with reference to voltage supply circuit, an and pressure drop circuit.This input control circuit receives the control signal with a low reference voltage source, produces an anti-phase control signal; This height provides a high reference voltage source with reference to voltage supply circuit; This pressure drop circuit is between this input control circuit and this height are with reference to the voltage switch circuit; this pressure drop circuit comprises that a height hangs down with reference to control element with reference to control element and; this height provides the pressure drop effect with reference to control element; should be low with protection with reference to control element; should be low with reference to control element by this control signal or should anti-phase control signal control switch switching, with drive this height with reference to the high reference voltage source of voltage supply circuit as output.

By above explanation as can be known, the present invention utilizes the MOS element of general voltage to be serially connected with under the MOS of high voltage devices, so that a pressure reduction falls in the MOS element for voltage as seeing through wherein one to one, the MOS element of general voltage is controlled the action of whole level shift circuit to see through another, so that the work period and the rising/decline transition speed of a balance can be provided, and the reliability and the stable operation degree of raising circuit.

Description of drawings

The schematic diagram of the existing level shift circuit of Fig. 1;

Fig. 2 is the schematic diagram of the level shift circuit of a preferred embodiment of the present invention.

Embodiment

Relevant preferred embodiment of the present invention please be with reference to Fig. 2, the level shift circuit that it is made up of with reference to main circuits such as voltage supply circuit 22, first output circuit 23, second output circuit 24 and pressure drop circuit 25 input control circuit 21, height.

Above-mentioned input control circuit 21 is made up of PMOS211 and NMOS212, and wherein, the grid of PMOS211 and NMOS212 is to link together, to receive a control signal Lo.The source electrode of PMOS211 is connected with low reference voltage source pin VDDIN, to receive a low reference voltage (for example is 1～1.5V), the drain electrode of PMOS211 is connected with the drain electrode of NMOS212, and pull out the grid of a connecting line to NMOS227, to export an anti-phase control signal LoB, the source electrode of NMOS212 is ground connection then.

High form by PMOS221 and 222 with reference to voltage supply circuit 22, this pressure drop circuit 25 is made up of NMOS223,224,225,226,227 and 228, wherein, PMOS221, the 222 and NMOS223, the 224th, be high voltage devices (representing with hV) at this, NMOS225,226,227,228 is general element.PMOS221,222 source electrode are connected with high reference voltage pin VPPIN, to receive high reference voltage (being generally 3.3V).The grid of the drain electrode of PMOS221, the drain electrode of NMOS223 and PMOS222 is to be connected to node NT1.The grid of the drain electrode of PMOS222, the drain electrode of NMOS224 and PMOS221 is to be connected to node NT2.NMOS223,224 grid all are connected with high reference voltage pin VPPIN.The source electrode of NMOS223 is connected with the drain electrode of NMOS225, and the source electrode of NMOS224 is connected with the drain electrode of NMOS226.NMOS225,226 grid all are connected with low reference voltage source pin VDDIN, receive the low reference voltage source of 1～1.5V.The source electrode of NMOS225 is connected with the drain electrode of NMOS227, and the source electrode of NMOS226 is connected with the drain electrode of NMOS228, and NMOS227, and 228 source electrode is ground connection all.

First output circuit 23 is by PMOS231,232 and NMOS233, and 234 compositions, wherein, and PMOS231,232 and NMOS233,234 are all high voltage devices.PMOS231,232 source electrode all are connected with high reference voltage pin VPPIN.The grid of PMOS231 and NMOS233 all is connected with node NT2.The grid of the drain electrode of PMOS231, the drain electrode of NMOS233, PMOS232 and the grid of NMOS344 are to interconnect.The drain electrode of PMOS232 is to be connected with the drain electrode of NMOS234, and pulls out the first output H1B thus.NMOS233,234 source electrode is ground connection all.

Second output circuit 24 is by PMOS241,242 and NMOS243, and 244 compositions, wherein, and PMOS241,242 and NMOS243,244 are all high voltage devices.PMOS241,242 source electrode all are connected with high reference voltage pin VPPIN.The grid of PMOS241 and NMOS243 all is connected with node NT1.The grid of the drain electrode of PMOS241, the drain electrode of NMOS243, PMOS242 and the grid of NMOS44 are to interconnect.The drain electrode of PMOS242 is to be connected with the drain electrode of NMOS244, and pulls out the second output H1 thus.NMOS243,244 source electrode is ground connection all.

When the high reference voltage that is provided as high reference voltage pin VPPIN is 3.3 volts, if the grid of the MOS element that the input signal that directly provides 1.5 volts～2.5 volts is extremely general, NMOS225 for example, 226,227,228 (its tolerable scope falls between 1～1.5V) then will be destroyed these elements or be made the lost of life of entire circuit.Therefore, the present invention design is with the NMOS223 of high voltage devices, is connected in series NMOS225 respectively under 224,227 and NMOS226, general element such as 228 grades is so that can utilize the input control signal of low voltage reference to make whole level shift circuit action, relevant its detailed description please be with reference to following.

Because, NMOS223,224 grid directly is connected with high reference voltage pin VPPIN, therefore when if high reference voltage pin VPPIN provides high reference voltage, NMOS223, the 224th, conducting (ON), it draws source voltage and is about 0.8 volt during this type of high voltage devices conducting usually.Similar ground, NMOS225,226 grid directly is connected with low reference voltage pin VDDIN, therefore if low reference voltage pin VDDIN provides when hanging down reference voltage, the NMOS225 of general voltage component, 228 will conducting, and it draws source voltage and is about 0.5 volt during this type of general voltage component conducting.If node NT1 is 3.3 volts, then be about 2 volts of (3.3V～0.8V～0.5V), therefore, only need to drive with lower input voltage control signal for NMOS227 at node NT5.In the same manner, also only need to use lower input voltage control signal to drive for NMOS228.

When input voltage control signal Lo was 1 volt, PMOS211 closed, and the NMOS212 conducting is so that the grid of NMOS227 is 0 volt.At this moment, NMOS228 is a conducting state, and NMOS227 is a closed condition.Because the NMOS228 conducting, make the current potential of node NT2 be pulled down to 0 volt, then PMOS221 conducting, and PMOS231 also is conducting, NMOS233 is for closing, so that confession PMOS232 closes, the NMOS234 conducting makes HIB export 0 volt voltage signal.In addition, because NMOS227 closes, make node NT1 still keep high potential (3.3 volts), then PMOS222 closes, and PMOS241 is for closing, and NMOS243 is conducting, so that confession PMOS242 conducting, NMOS244 closes, and makes H1 export 3.3 volts high reference voltage signal.

Similar ground, when input voltage control signal Lo is 0 volt, the PMOS211 conducting, NMOS212 closes, so that the grid of NMOS227 is 1 volt.At this moment, NMOS228 is a closed condition, and NMOS227 is a conducting state.Because NMOS228 closes, make the current potential of node NT2 keep high voltage (3.3 volts), then PMOS221 closes, and PMOS231 is for closing, and NMOS233 is conducting, so that confession PMOS232 conducting, NMOS234 closes, and makes HIB export 3.3 volts high reference voltage signal.In addition, because the NMOS227 conducting adds that PMOS221 closes, make the current potential of node NT1 toward being pulled down to 0 volt, then PMOS222 conducting, and PMOS241 is conducting, NMOS243 is conducting, so that close for PMOS242, the NMOS244 conducting makes H1 export 0 volt voltage signal.

Above-mentioned NMOS225, the 226 and NMOS223, the 224th, be mainly used to produce pressure drop; to reduce NMOS227, the pressure drop that 228 its drain electrodes and grid are born is with protection NMOS227; 228; because NMOS227, the 228th, general element has only lower critical voltage; can only bear the pressure drop lower than high voltage devices; therefore just can see through a lower input control voltage and get final product driving N MOS227,228, so that the entire circuit action.Certainly, the also visual demand of circuit of the present invention and set up at least one group of NMOS again and increase pressure drop, and other utilize initiatively or passive device produces the mode of pressure reduction, all can be applied to foregoing circuit in fact.In addition, though foregoing circuit is controlled with the positive input control signal, certainly, if (for example: 0 volt adopt anti-phase input control signal,-VDD) also can be implemented into foregoing circuit, only these PMOS and NMOS must exchange, and the circuit connecting section branch makes an amendment slightly, because this is generally to be familiar with circuit knowledge people all can to do in fact easily, therefore no longer takes off and releases these circuit diagrams and relevant action explanation thereof.

The foregoing description only is to give an example for convenience of description, and the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.

Claims

1. a level shift circuit is characterized in that, comprising:

One input control circuit receives the control signal with a low reference voltage source, produces an anti-phase control signal;

One height has one the 3rd switch element and one the 4th switch element with reference to voltage supply circuit, and the 3rd switch element and the 4th switch element are not conductings simultaneously and do not close simultaneously, and a high reference voltage source is provided; Wherein, the drain electrode of the 3rd switch element grid and the 4th switch element is connected and the drain electrode of the 3rd switch element is connected with the 4th switch element grid;

One pressure drop circuit, be between this input control circuit and this height are with reference to the voltage switch circuit, this pressure drop circuit comprises a high level control element and a low level control element, this high level control element provides the pressure drop effect, to protect this low level control element, this low level control element is switched by the anti-phase control signal control switch of this control signal or this, with drive this height with reference to the high reference voltage source of voltage supply circuit as output; And

One first output circuit and one second output circuit, this first output circuit and this second output circuit are and are connected in this height with reference between voltage supply circuit and this pressure drop circuit, so that for producing an output signal respectively by this first output circuit and this second output circuit.

2. level shift circuit as claimed in claim 1 is characterized in that, described this input control circuit has one first switch element and a second switch element, and this first switch element and this second switch element are not conductings simultaneously and do not close simultaneously.

3. level shift circuit as claimed in claim 2 is characterized in that, described this first switch element and this second switch element are to be low level control metal oxide semiconductcor field effect electric transistor.

4. level shift circuit as claimed in claim 4 is characterized in that, described the 3rd switch element and the 4th switch element are with reference to the control P-type mos for high.

5. level shift circuit as claimed in claim 1, it is characterized in that, the high level control element of described this pressure drop circuit comprises one the 5th switch element and one the 6th switch element, and the 5th switch element and the 6th switch element are that the brilliant pipe of electricity is imitated in the N type metal oxide semiconductor field of high-pressure type.

6. level shift circuit as claimed in claim 1, it is characterized in that, the low level control element of described this pressure drop circuit comprises that a minion is closed element and an octavo is closed element, and this minion closes element and this octavo is closed the brilliant pipe of N type metal oxide semiconductor field effect electricity that element is general voltage-type.

7. level shift circuit as claimed in claim 1, it is characterized in that, described this pressure drop circuit more comprises one the 9th switch element and 1 the tenth switch element, between this high level control element and this low level control element, in order to the pressure drop effect further to be provided, the 9th switch element and the tenth switch element are the N type metal oxide semiconductor field effect electric crystal of general voltage-type.

8. level shift circuit as claimed in claim 1 is characterized in that, the output signal that described this first output circuit is produced is that the output signal that is produced with this second output circuit is anti-phase.