WO2019015318A1 - 像素单元电路、像素电路、驱动方法和显示装置 - Google Patents

像素单元电路、像素电路、驱动方法和显示装置 Download PDF

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Publication number
WO2019015318A1
WO2019015318A1 PCT/CN2018/076516 CN2018076516W WO2019015318A1 WO 2019015318 A1 WO2019015318 A1 WO 2019015318A1 CN 2018076516 W CN2018076516 W CN 2018076516W WO 2019015318 A1 WO2019015318 A1 WO 2019015318A1
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Prior art keywords
transistor
pole
control
gate
pixel unit
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Application number
PCT/CN2018/076516
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English (en)
French (fr)
Inventor
杨盛际
董学
陈小川
王辉
王晏酩
卢鹏程
刘伟
王慧娟
玄明花
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP18769021.9A priority Critical patent/EP3657480A4/en
Priority to US16/087,972 priority patent/US10923031B2/en
Publication of WO2019015318A1 publication Critical patent/WO2019015318A1/zh
Priority to US17/170,196 priority patent/US11386845B2/en

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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G09G2310/0256—Control of polarity reversal in general, other than for liquid crystal displays with the purpose of reversing the voltage across a light emitting or modulating element within a pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
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    • G09G2320/0238—Improving the black level
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2320/0261—Improving the quality of display appearance in the context of movement of objects on the screen or movement of the observer relative to the screen
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel unit circuit, a pixel circuit, a driving method, and a display device.
  • Silicon-based OLED (Organic Light-Emitting Diode) microdisplays are at the intersection of microelectronics and optoelectronics, combining OLED technology and CMOS (Complementary Metal Oxide Semiconductor) technology.
  • CMOS Complementary Metal Oxide Semiconductor
  • the silicon-based OLED microdisplay in the related art cannot effectively adjust the brightness of the Micro (micro) OLED itself, and has a dynamic afterimage, and the data voltage range on the data line is narrow so that the problem of the luminance of the OLED cannot be effectively improved.
  • the present disclosure provides a pixel unit circuit including:
  • the first end is connected to the low level input end
  • a storage capacitor module the first end is connected to the DC voltage input terminal
  • a driving transistor a gate connected to the second end of the storage capacitor module, and a first pole connected to the second end of the light emitting element
  • a light-emitting control module wherein the control end is connected to the light-emitting control line, the first end is connected to the high-level input end, and the second end is connected to the second pole of the driving transistor for controlling the control under the control of the light-emitting control line Whether the second pole of the drive transistor receives a signal from the high level input;
  • a charge compensation control module is coupled to the gate line, the data line, and the gate of the drive transistor, respectively, for controlling whether a gate of the drive transistor receives a signal from the data line under control of the gate line.
  • the pixel unit circuit of the present disclosure further includes: a reset module connected to the light emission control line, the first pole of the driving transistor, and the reset voltage input end, respectively, for the illumination control line Controlling whether the first pole of the driving transistor receives a signal from the reset voltage input terminal; the reset voltage input terminal includes a ground terminal or a low level input terminal.
  • the reset module includes: a reset switch transistor, a gate connected to the light emission control line, a first pole connected to the first pole of the driving transistor, and a second pole and the reset voltage input end connection.
  • the illumination control module includes: a light emission control transistor, a gate connected to the illumination control line, a first pole connected to the high level input terminal, and a second pole connected to the second pole of the driving transistor ;
  • the reset switch transistor When the light emission control transistor is a p-type transistor, the reset switch transistor is an n-type transistor; when the light emission control transistor is an n-type transistor, the reset switch transistor is a p-type transistor.
  • the pixel unit circuit of the present disclosure further includes: a potential control transistor, the gate and the first pole are both connected to the first pole of the driving transistor, and the second pole is grounded; the potential control transistor is p-type Transistor.
  • the gate line includes a first gate switching line and a second gate switching line
  • the charging compensation control module includes:
  • a first charge compensation control transistor having a gate connected to the first gate switch line, a first pole connected to a gate of the drive transistor, and a second pole connected to the data line;
  • a second charge compensation control transistor a gate connected to the second gate switch line, a first pole connected to the data line, and a second pole connected to a gate of the drive transistor;
  • the first charge compensation control transistor is an n-type transistor
  • the second charge compensation control transistor is a p-type transistor.
  • the present disclosure also provides a driving method of a pixel unit circuit for driving the pixel unit circuit described above, and the driving method of the pixel unit circuit includes:
  • the illumination control module controls the second pole of the drive transistor to receive the signal from the high level input terminal; under the control of the gate line, the charge compensation control module controls the data voltage on the data line.
  • Vdata is written to the gate of the driving transistor such that the driving transistor is turned on until the potential of the first electrode of the driving transistor becomes Vdata-Vth, the driving transistor operates in a constant current region;
  • Vth is the driving The threshold voltage of the transistor;
  • the illumination control module controls the second pole of the drive transistor to receive a signal from a high level input terminal, the drive transistor operating in a constant current region to drive the illumination element to emit light.
  • the pixel unit circuit further includes a reset module, respectively connected to the illumination control line, the first pole of the driving transistor, and the reset voltage input terminal, for controlling under the illumination control line Controlling whether the first pole of the driving transistor receives a signal from the reset voltage input terminal;
  • the reset voltage input terminal includes a ground terminal or a low level input terminal, and the driving method of the pixel unit circuit is Before the charge compensation phase, it also includes:
  • the reset module controls whether the first pole of the drive transistor receives a signal from the reset voltage input terminal to reset the potential of the first pole of the drive transistor ;
  • the reset module controls the first pole of the drive transistor not to receive a signal from the reset voltage input terminal.
  • the present disclosure also provides a pixel circuit including a plurality of rows of gate lines, a plurality of columns of data lines, a plurality of rows of light emission control lines, and a plurality of the above-described pixel unit circuits arranged in an array;
  • Pixel unit circuits located in the same row are connected to the same row of gate lines;
  • Pixel unit circuits in the same column are connected to the same column of data lines;
  • the pixel unit circuit further includes a reset module
  • the pixel unit circuits located in the same row are connected to the same row of illumination control lines.
  • the present disclosure also provides a driving method of a pixel circuit for driving the above-mentioned pixel circuit, in one frame display time, one row of pixel unit circuits corresponds to a corresponding charging compensation phase and a corresponding pixel lighting phase;
  • the driving method of the pixel circuit includes: within one frame display time,
  • the pixel unit circuit included in the corresponding row includes a lighting control module that controls the second pole of the driving transistor to receive a signal from the high level input terminal;
  • the charge compensation control module includes controlling the data voltage Vdata of the corresponding column data line to be written to the gate of the driving transistor included in the pixel unit circuit of the corresponding row, so that the driving transistor Turning on until the potential of the first pole of the driving transistor becomes Vdata-Vth, the driving transistor operates in a constant current region; Vth is a threshold voltage of the driving transistor;
  • the illumination control module controls the second pole of the drive transistor to receive a signal from a high level input terminal, the drive transistor operating in a constant current region Driving the light-emitting element to emit light.
  • the pixel unit circuit in the pixel circuit includes a reset module, respectively connected to the light emission control line, the first pole of the driving transistor, and the reset voltage input end, for the illumination control line Controlling, whether the first pole of the driving transistor receives a signal from the reset voltage input terminal;
  • the reset voltage input terminal includes a ground terminal or a low level input terminal
  • a full-screen black insertion period is set between adjacent two frame display times; the driving method of the pixel circuit further includes:
  • all the row emission control lines included in the pixel circuit output a first level signal, so that the second end of the light-emitting element in each pixel unit circuit included in the pixel circuit Both receive signals from the reset voltage input.
  • the pixel unit circuit in the pixel circuit includes a reset module, respectively connected to the light emission control line, the first pole of the driving transistor, and the reset voltage input end, for the illumination control line Controlling whether the first pole of the driving transistor receives a signal from the reset voltage input terminal;
  • the reset voltage input terminal includes a ground terminal or a low level input terminal, and is set at a frame display time interval There are a plurality of full-screen black insertion periods; the driving method of the pixel circuit further includes:
  • all the row emission control lines included in the pixel circuit output a first level signal, so that the second end of the light-emitting element in each pixel unit circuit included in the pixel circuit Receives a signal from the reset voltage input.
  • the pixel unit circuit in the pixel circuit includes a reset module, respectively connected to the light emission control line, the first pole of the driving transistor, and the reset voltage input end, for the illumination control line Controlling whether the first pole of the driving transistor receives a signal from the reset voltage input terminal;
  • the reset voltage input terminal includes a ground terminal or a low level input terminal, and the driving method of the pixel circuit further Including: display time in one frame,
  • the plurality of rows of light emission control lines included in the pixel circuit sequentially output a first level signal such that the second end of the light emitting elements in the plurality of rows of pixel unit circuits included in the pixel circuit sequentially receive signals from the reset voltage input terminal.
  • the driving method of the pixel circuit further includes: in each display period,
  • the plurality of rows of light emission control lines included in the pixel circuit sequentially output a first level signal such that the second end of the light emitting elements in the plurality of rows of pixel unit circuits included in the pixel circuit sequentially receive signals from the reset voltage input terminal.
  • the present invention also provides a display device comprising a silicon substrate and the above-described pixel unit circuit disposed on the silicon substrate.
  • FIG. 1 is a structural diagram of a pixel unit circuit according to an embodiment of the present disclosure
  • FIG. 2 is a structural diagram of a pixel unit circuit according to another embodiment of the present disclosure.
  • FIG. 3 is a structural diagram of a pixel unit circuit according to still another embodiment of the present disclosure.
  • FIG. 4 is a structural diagram of a pixel unit circuit according to still another embodiment of the present disclosure.
  • FIG. 5 is a circuit diagram of a first embodiment of a pixel unit circuit of the present disclosure
  • FIG. 6 is a timing chart showing the operation of the first embodiment of the pixel unit circuit shown in FIG. 5 of the present disclosure
  • FIG. 7A is a schematic view showing the operation of the first embodiment of the pixel unit circuit shown in FIG. 5 in the reset phase;
  • FIG. 7B is a schematic diagram showing the operation of the first embodiment of the pixel unit circuit shown in FIG. 5 in the charging compensation phase;
  • FIG. 7C is a schematic diagram showing the operation of the first embodiment of the pixel unit circuit shown in FIG. 5 in the pixel illumination stage;
  • FIG. 8 is a circuit diagram of a second embodiment of a pixel unit circuit of the present disclosure.
  • FIG. 9 is a timing chart of operation of a full-screen black insertion mode of the pixel circuit according to the present disclosure.
  • FIG. 10 is an operational timing diagram of another full-screen black insertion mode of the pixel circuit according to the present disclosure.
  • FIG. 11 is a circuit diagram of a specific embodiment of a shift register unit that generates an illumination control signal
  • Figure 12 is a timing chart showing the operation of a specific embodiment of the shift register unit shown in Figure 11;
  • FIG. 13 is a timing chart of operation of a progressive interpolation mode of the pixel circuit of the present disclosure
  • FIG. 14 is a timing chart showing another operation of the pixel-by-row black insertion mode of the pixel circuit according to the present disclosure.
  • FIG. 15 is a schematic structural diagram of a pixel circuit according to the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • one of the poles is referred to as a first pole, and the other pole is referred to as a second pole.
  • the first pole may be a drain
  • the second pole may be a source
  • the first pole may be a source
  • the second pole may be a drain.
  • the first end is connected to the low level input end
  • a storage capacitor module the first end is connected to the DC voltage input terminal
  • a driving transistor a gate connected to the second end of the storage capacitor module, and a first pole connected to the second end of the light emitting element
  • a light-emitting control module wherein the control end is connected to the light-emitting control line, the first end is connected to the high-level input end, and the second end is connected to the second pole of the driving transistor for controlling the control under the control of the light-emitting control line Whether the second pole of the driving transistor is connected to the high level input terminal (ie, controlling whether the second pole of the driving transistor and the high level input terminal are turned on under the control of the light emitting control line) To control whether the second pole of the drive transistor receives a signal from the high level input; and,
  • a charge compensation control module respectively connected to the gate line, the data line and the gate of the driving transistor, for controlling whether the gate of the driving transistor is connected to the data line under the control of the gate line (ie, Controlling whether the gate of the driving transistor and the data line are turned on under control of the gate line to control whether a gate of the driving transistor receives a signal from the data line).
  • the pixel unit circuit of the embodiment of the present disclosure can effectively adjust the brightness of the light-emitting element itself by adjusting the data voltage (by the timing of the timing so that the charge compensation control module controls the potential of the second end of the light-emitting element to be Vdata in the charge compensation phase).
  • the light emitting element may include an organic light emitting diode, and may also include other devices capable of emitting light.
  • the light emitting element comprises an organic light emitting diode
  • a first end of the light emitting element is a cathode of the organic light emitting diode
  • a second end of the light emitting element is an organic light emitting diode anode
  • the DC voltage input terminal may be a ground terminal, or may be another terminal that inputs a DC voltage.
  • the pixel unit circuit of the embodiment of the present disclosure includes:
  • An organic light emitting diode OLED having a cathode connected to a low level input terminal of an input low level Vss;
  • the storage capacitor module 11 has a first end connected to the DC voltage input terminal VD;
  • a driving transistor DTFT a gate connected to the second end of the storage capacitor module 11, and a source connected to an anode of the organic light emitting diode OLED;
  • a light-emitting control module 12 the control end is connected to the light-emitting control line EM, the first end is connected to the high-level input end of the input high-level Vdd, and the second end is connected to the drain of the driving transistor DTFT, Controlling whether the drain of the driving transistor DTFT is connected to the high level input terminal of the input high level Vdd under the control of the light emission control line EM;
  • a charge compensation control module 13 connected to the gate line Gate, the data line Data, and the gate of the driving transistor DTFT, respectively, for controlling whether the gate of the driving transistor DTFT is related to the gate under the control of the gate line Gate Data line Data connection.
  • the driving transistor DTFT is taken as an n-type transistor as an example. In actual operation, the driving transistor DTFT may also be a p-type transistor.
  • FIG. 1 An embodiment of the pixel unit circuit shown in FIG. 1 is in operation
  • the illumination control module 12 controls the drain of the driving transistor DTFT to be connected to the high level input terminal of the input high level Vdd; under the control of the gate line Gate, the charging compensation control The module 13 controls the data voltage Vdata on the data line Data to be written to the gate of the driving transistor DTFT such that the driving transistor DTFT is turned on until the potential of the source of the driving transistor DTFT becomes Vdata-Vth, the driving The transistor DTFT operates in a constant current region; Vth is a threshold voltage of the driving transistor DTFT;
  • the illumination control module 12 controls the drain of the driving transistor DTFT to be connected to a high level input terminal of the input high level Vdd, and the driving transistor DTFT operates in a constant current region.
  • the organic light emitting element OLED is driven to emit light.
  • the pixel unit circuit of the embodiment of the present disclosure further includes: a reset module, respectively connected to the light emission control line, the first pole of the driving transistor, and the reset voltage input end, for Controlling, by the control of the illumination control line, whether the first pole of the driving transistor is connected to the reset voltage input terminal (ie, controlling whether the first pole of the driving transistor and the reset voltage input terminal are turned on)
  • the reset voltage input includes a ground or low level input.
  • the reset module in the preferred embodiment of the pixel unit circuit of the present disclosure can control to eliminate the voltage remaining in the anode of the OLED in the previous frame during the reset phase, thereby eliminating dynamic image sticking.
  • the pixel unit circuit of the embodiment of the present disclosure further includes: a reset module 14, respectively, with the light emission control line EM, the driving transistor
  • the source of the DTFT is connected to the ground GND for controlling whether the source of the driving transistor DTFT is connected to the ground GND under the control of the light emission control line EM (ie, controlling the source of the driving transistor DTFT) Whether the pole between the pole and the ground GND is turned on to control whether the source of the driving transistor DTFT receives a signal from the ground GND).
  • a reset phase is further provided before the charge compensation phase
  • the reset module 14 controls the source of the driving transistor DTFT to be connected to the ground GND to reset the potential of the source of the driving transistor DTFT.
  • the reset module 14 controls to open between the source of the driving transistor and the ground GND. connection.
  • the reset module may include: a reset switch transistor, a gate connected to the light emission control line, a first pole connected to the first pole of the driving transistor, a second pole and the reset voltage input End connection.
  • the illuminating control module may include: a illuminating control transistor, the gate is connected to the illuminating control line, the first pole is connected to the high level input end, and the second pole is connected to the second pole of the driving transistor connection;
  • the reset switch transistor When the light emission control transistor is a p-type transistor, the reset switch transistor is an n-type transistor; when the light emission control transistor is an n-type transistor, the reset switch transistor is a p-type transistor.
  • the pixel unit circuit of the present disclosure may further include: a potential control transistor, a gate and a first pole, and the driving The first pole of the transistor is connected and the second pole is grounded; the potential control transistor is a p-type transistor.
  • the pixel unit circuit according to the embodiment of the present disclosure may further include: a potential control transistor P3, a gate and a source, and the driving transistor DTFT.
  • the source is connected, the drain is connected to the ground GND, and the potential control transistor P3 is a p-type transistor.
  • the potential control transistor P3 can effectively protect the anode potential of the organic light emitting diode OLED from being lower than the voltage outputted from the ground GND, thereby protecting the gate-source voltage DTFT.
  • the gate-source voltage does not exceed the maximum drive voltage of the gate-source voltage DTFT itself.
  • the gate line may include a first gate switching line Gate1 and a second gate switching line Gate2;
  • the charging compensation control module 13 includes:
  • a first charge compensation control transistor N1 having a gate connected to the first gate switch line Gate1, a source connected to a gate of the drive transistor DTFT, and a drain connected to the data line Data;
  • a second charge compensation control transistor P1 having a gate connected to the second gate switch line Gate2, a source connected to the data line Data, and a drain connected to a gate of the drive transistor DTFT;
  • the first charge compensation control transistor N1 is an n-type transistor
  • the second charge compensation control transistor P1 is a p-type transistor.
  • the charge compensation control module includes an NMOS transistor (Negative channel Metal Oxide Semiconductor) and a PMOS transistor (Positive channel Metal Oxide).
  • NMOS transistor Negative channel Metal Oxide Semiconductor
  • PMOS transistor Platinum channel Metal Oxide
  • the charge compensation control module includes only the first charge compensation control transistor N1, when the potential of the signal output by Gate1 is not high enough, the higher data voltage of the Data output may not be It will be transferred to the gate of the drive transistor DTFT.
  • the embodiment of the pixel unit circuit shown in FIG. 4 further includes a second charge compensation control transistor P1 through the charge compensation control module, and outputs a low level signal during the charge compensation phase Gate2, even if the data voltage of the Data output is relatively large. It is also ensured that the data voltage is written to the gate of the driving transistor DTFT, so that the effective driving voltage range of the data line output can be increased.
  • the storage capacitor module may include a storage capacitor.
  • the pixel unit circuit of the present disclosure will be described below by two specific embodiments.
  • a first specific embodiment of the pixel unit circuit of the present disclosure includes an organic light emitting diode OLED, a storage capacitor C1, a driving transistor DTFT, an illumination control module, a charge compensation control module, and a reset module.
  • An anode of the organic light emitting diode OLED is connected to a drain of the driving transistor DTFT, and a cathode of the organic light emitting diode OLED is connected to a low level input terminal of an input low level Vss;
  • the first end of the storage capacitor C1 is connected to the DC voltage input terminal VD, and the second end of the storage capacitor C1 is connected to the gate of the driving transistor DTFT;
  • a source of the driving transistor DTFT is connected to an anode of the organic light emitting diode OLED;
  • the charging compensation control module includes:
  • a first charge compensation control transistor N1 having a gate connected to the first gate switch line Gate1, a source connected to a gate of the drive transistor DTFT, and a drain connected to the data line Data;
  • a second charge compensation control transistor P1 having a gate connected to the second gate switch line Gate2, a source connected to the data line Data, and a drain connected to a gate of the drive transistor DTFT;
  • the reset module includes: a reset switch transistor N2, a gate connected to the light emission control line EM, a source connected to a source of the driving transistor DTFT, and a drain connected to a ground terminal GND;
  • the illumination control module includes: an illumination control transistor P2, a gate connected to the illumination control line EM, a source connected to a high level input terminal of the input high level Vdd, and a second pole and a drain of the driving transistor DTFT Pole connection
  • the first charge compensation control transistor N1 is an n-type transistor
  • the second charge compensation control transistor P1 is a p-type transistor
  • the reset switch transistor N2 is an n-type transistor
  • the light emission control transistor P2 is a p-type transistor.
  • the driving transistor DTFT is an n-type transistor.
  • point a is a node connected to the anode of the organic light emitting diode OLED.
  • the first embodiment of the pixel unit circuit shown in FIG. 5 is in operation
  • Gate1 In the reset phase S1, Gate1 outputs a low level, and Gate2 and EM output a high level. As shown in FIG. 7A, N2 is turned on, P1, P2, and N1 are turned off, and a potential is reset and discharged to a low level. Resetting the voltage signal of the anode of the previous frame OLED can effectively improve the problem of dynamic image sticking under high frequency driving;
  • Gate1 outputs a high level, and Gate2 and EM both output a low level.
  • P1, P2, and N1 are both turned on, N2 is turned off, and the data voltage Vdata of the Data output passes through C1 to DTFT.
  • the gate is charged, the potential of the second terminal of C1 is charged to Vdata, the DTFT is turned on until the potential of point a becomes Vdata-Vth, and the DTFT operates in a constant current region (approx. constant current region); N1 and P1 are adopted in the embodiment of the present disclosure. Mainly because it can increase the effective driving voltage range of the Data output;
  • Gate1 and EM both output a low level, and Gate2 outputs a high level.
  • P2 is turned on, N1, P1, and N2 are both turned off, and a point potential is maintained at Vdata-Vth.
  • the DTFT operates in a constant current region (approx. constant current region), and the current is driven to emit light through the turned-on P2 and the DTFT in the constant current region; the pixel unit circuit according to the embodiment of the present disclosure passes The potential of the gate of the driving transistor DTFT is controlled to change the potential at point a, thereby changing the voltage across the OLED and changing the illuminating current of the OLED.
  • the pixel unit circuit of the embodiment of the present disclosure may be disposed on a silicon substrate, and the light emitting element included in the pixel unit circuit may be an organic light emitting diode.
  • the embodiment of the present disclosure provides a silicon based OLED (organic light emitting diode) Pixel drive circuit design, by matching the new timing combined with its own pixel drive design, can effectively adjust the brightness of the Micro (micro) OLED itself, and can also improve the dynamic afterimage problem, and for the pixel unit circuit itself, through the special TFT
  • the gate increases the data voltage range and effectively increases the luminance of the OLED.
  • a second embodiment of the pixel unit circuit of the present disclosure includes an organic light emitting diode OLED, a storage capacitor C1, a driving transistor DTFT, an emission control module, a charge compensation control module, and a potential control transistor P3.
  • the anode of the organic light emitting diode OLED is connected to the drain of the driving transistor DTFT, and the cathode of the organic light emitting diode OLED is connected to the low level input terminal of the input low level Vss;
  • the first end of the storage capacitor C1 is connected to the DC voltage input terminal VD, and the second end of the storage capacitor C1 is connected to the gate of the driving transistor DTFT;
  • a source of the driving transistor DTFT is connected to an anode of the organic light emitting diode OLED;
  • the charging compensation control module includes:
  • a first charge compensation control transistor N1 having a gate connected to the first gate switch line Gate1, a source connected to a gate of the drive transistor DTFT, and a drain connected to the data line Data;
  • a second charge compensation control transistor P1 having a gate connected to the second gate switch line Gate2, a source connected to the data line Data, and a drain connected to a gate of the drive transistor DTFT;
  • the illumination control module includes: an illumination control transistor P2, a gate connected to the illumination control line EM, a source connected to a high level input terminal of the input high level Vdd, and a second pole and a drain of the driving transistor DTFT Pole connection
  • the gate and the source of the potential control transistor P3 are both connected to the source of the driving transistor DTFT, and the drain of the potential control transistor P3 is connected to the ground GND;
  • the potential control transistor P3 is a p-type transistor
  • the first charge compensation control transistor N1 is an n-type transistor
  • the second charge compensation control transistor P1 is a p-type transistor
  • the light emission control transistor P2 is a p-type transistor
  • the drive transistor DTFT is an n-type transistor.
  • the anode potential of the OLED can be effectively protected from being lower than the ground level, thereby ensuring that the gate-source voltage of the DTFT does not exceed The maximum driving voltage of the DTFT.
  • the driving method of the pixel unit circuit according to the embodiment of the present disclosure is used to drive the pixel unit circuit described above, and the driving method of the pixel unit circuit includes:
  • the illumination control module controls the second pole of the driving transistor to be connected with the high level input terminal; under the control of the gate line, the charging compensation control module controls the data voltage Vdata on the data line.
  • Writing a gate of the driving transistor such that the driving transistor is turned on until a potential of the first electrode of the driving transistor becomes Vdata-Vth, the driving transistor operates in a constant current region; Vth is the driving transistor Threshold voltage
  • the illumination control module controls the second pole of the drive transistor to be connected to the high level input terminal, and the drive transistor operates in a constant current region to drive the illumination element to emit light.
  • the driving method of the pixel unit circuit is Before the charging compensation phase, it also includes:
  • the reset module controls the first pole of the drive transistor to be connected to the reset voltage input terminal to reset the potential of the first pole of the drive transistor.
  • the pixel circuit of the embodiment of the present disclosure includes a plurality of rows of gate lines, a plurality of columns of data lines, a plurality of rows of light emission control lines, and a plurality of the above pixel unit circuits arranged in an array;
  • Pixel unit circuits located in the same row are connected to the same row of gate lines;
  • Pixel unit circuits in the same column are connected to the same column of data lines;
  • the pixel unit circuit further includes a reset module
  • the pixel unit circuits located in the same row are connected to the same row of illumination control lines.
  • the pixel circuit described in the embodiment of the present disclosure may be disposed on the silicon substrate 100.
  • the driving method of the pixel circuit according to the embodiment of the present disclosure is used to drive the pixel circuit described above, and one row of pixel unit circuits corresponds to a corresponding charging compensation phase and a corresponding pixel lighting phase in one frame display time;
  • the driving method of the pixel circuit includes: within one frame display time,
  • the pixel unit circuit included in the corresponding row includes an illumination control module that controls the second pole of the driving transistor to be connected with the high level input terminal;
  • the pixel compensation circuit of the pixel unit circuit of the corresponding row controls the data voltage Vdata of the corresponding column data line to be written to the gate of the driving transistor included in the pixel unit circuit of the corresponding row, so that the driving transistor leads Passing until the potential of the first pole of the driving transistor becomes Vdata-Vth, the driving transistor operates in a constant current region;
  • Vth is a threshold voltage of the driving transistor;
  • the illumination control module controls the second pole of the driving transistor to be connected to the high level input terminal, and the driving transistor operates in a constant current region.
  • the light-emitting element is driven to emit light.
  • the pixel unit circuit in the pixel circuit includes a reset module, and is respectively connected to the light emission control line, the first pole of the driving transistor, and the reset voltage input end, for being used in the illumination control line Controlling whether a first pole of the driving transistor is connected to the reset voltage input terminal; and when the reset voltage input terminal includes a ground terminal or a low level input terminal,
  • a full-screen black insertion period is set between adjacent two frame display times; the driving method of the pixel circuit further includes:
  • all the row emission control lines included in the pixel circuit output a first level signal, so that the second end of the light-emitting element in each pixel unit circuit included in the pixel circuit Both are connected to the reset voltage input terminal, so that the second end of the light-emitting element in each pixel unit circuit included in the pixel circuit is performed in a full-screen black insertion period set between adjacent two frame display periods
  • the potential is reset to improve dynamic image sticking.
  • the light emitting element may include an organic light emitting diode, and the second end of the light emitting element may be an anode of the organic light emitting diode.
  • the illumination control module included in the illumination control module is an n-type transistor
  • the first level signal is a high level signal
  • the illumination control module includes a p-type transistor the A level signal is a low level signal.
  • the data is enabled as the data enable signal.
  • DE high
  • the pixel circuit is in one frame display time.
  • DE low
  • the pixel circuit is in a blank time period; the label is EM.
  • the illuminating control line outputs a low-level signal during a frame display time
  • the EM outputs a high-level signal during a full-screen black insertion period set between adjacent two frames of display time, and the illuminating component is The two ends perform a potential reset to improve the dynamic image sticking phenomenon.
  • the first full-screen black insertion period is Sem1
  • the second full-screen black insertion period is Sem2.
  • the driving method of the pixel circuit further includes:
  • all the row emission control lines included in the pixel circuit output a first level signal, so that the second end of the light-emitting element in each pixel unit circuit included in the pixel circuit Connect to the reset voltage input.
  • the illumination control module included in the illumination control module is an n-type transistor
  • the first level signal is a high level signal
  • the illumination control module includes a p-type transistor the A level signal is a low level signal.
  • the data is the data enable signal.
  • the pixel circuit When DE is high, the pixel circuit is in one frame display time.
  • DE When DE is low level, the pixel circuit is in a blank time period; the label is EM.
  • the illumination control line is provided with two full-screen black insertion periods in one frame display time; in the full-screen black insertion period, the EM outputs a high-level signal, and the potential of the second end of the light-emitting element is reset. Thereby improving the dynamic image sticking phenomenon; the EM outputs a low level signal in other time periods than the full screen black insertion period.
  • the first full-screen black insertion period is Sem1
  • the second full-screen black insertion period is Sem2
  • the third full-screen black insertion period is Sem3, and the number is Sem4.
  • Four full screen insertion black time period is Sem1
  • the full-screen black insertion mode is entered after the end of one frame display time, thereby effectively improving the dynamic image sticking phenomenon; in the alternative embodiment shown in FIG. 10, the display time is in one frame. Inside, multiple times into the full screen black insertion mode, can effectively improve the dynamic image sticking phenomenon.
  • the pixel unit circuit in the pixel circuit includes a reset module, respectively connected to the light emission control line, the first pole of the driving transistor, and the reset voltage input end, for the illumination control Controlling whether a first pole of the driving transistor is connected to the reset voltage input terminal under control of a line; and driving the pixel circuit when the reset voltage input terminal includes a ground terminal or a low level input terminal Also included: display time in one frame,
  • the plurality of rows of light-emitting control lines included in the pixel circuit sequentially output a first level signal, so that the second end of the light-emitting elements in the plurality of rows of pixel unit circuits included in the pixel circuit are sequentially connected to the reset voltage input terminal, That is, in one frame display time, the multi-line illumination control line is controlled to sequentially output the first level signal from top to bottom, thereby controlling the progressive insertion of the black line, that is, the plurality of rows of pixel unit circuits included in the pixel circuit include the light-emitting elements.
  • the potentials at both ends are reset in order to improve dynamic image sticking.
  • each frame display time includes at least For two display periods, the driving method of the pixel circuit further includes: in each display period,
  • the plurality of rows of light-emitting control lines included in the pixel circuit sequentially output a first level signal, so that the second end of the light-emitting elements in the plurality of rows of pixel unit circuits included in the pixel circuit are sequentially connected to the reset voltage input terminal, That is, the one frame display time includes at least two display periods.
  • the multi-line illumination control lines are controlled to sequentially output the first level signals from top to bottom, thereby controlling the progressive insertion of the black lines, that is, the pixel circuits are included.
  • the potential of the second end of the light-emitting element included in the row pixel unit circuit is sequentially reset to improve the dynamic image sticking phenomenon.
  • row-by-row black insertion is performed multiple times during one frame display time.
  • the illumination control module included in the illumination control module is an n-type transistor
  • the first level signal is a high level signal
  • the illumination control module includes a p-type transistor the A level signal is a low level signal.
  • Figure 11 is a circuit diagram of a specific embodiment of a shift register unit that generates an illumination control signal.
  • a specific embodiment of the shift register unit includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor.
  • the signal, labeled VL is low level
  • the label is VH is high level
  • the label EO (N) is the Nth level illumination control signal
  • the label is EM_STV(N) is the Nth stage start signal
  • N is an integer greater than one.
  • EM_STV(N) is EO(N-1).
  • all of the transistors are p-type transistors.
  • the above transistors can also be replaced with n-type transistors, and only the timing of the corresponding control signals needs to be changed.
  • Figure 12 is a timing chart showing the operation of a specific embodiment of the shift register unit shown in Figure 11.
  • EO(N+1) is the (N+1)th order illumination control signal.
  • EO(N) and EO(N+1) are sequentially high.
  • V-sync is a synchronous refresh voltage.
  • V-sync is high, the pixel circuit is in one frame display time.
  • V-sync is low, the pixel circuit is in a blank time period; EM_STV(N ) is the Nth start signal, CLK is the first clock signal, according to the circuit shown in FIG. 11 and the timing shown in FIG. 13, the multi-line illumination control line is progressive from top to bottom in one frame display time. Output a high level signal and insert black line by line.
  • V-sync is a synchronous refresh voltage.
  • V-sync is high, the pixel circuit is in one frame display time.
  • V-sync is low, the pixel circuit is in a blank time period; EM_STV(N ) is the Nth start signal, CLK is the first clock signal, according to the circuit shown in FIG. 11 and the timing shown in FIG. 14, the multi-line illumination control line is at least twice from the top to the display time within one frame display time. The next line outputs a high level signal, and at least two lines are inserted black.
  • the length of time that the corresponding illumination control signal is at a high level can be controlled.
  • the display device includes a silicon substrate 100 and the above-described pixel unit circuit disposed on the silicon substrate.
  • the display device further includes a plurality of rows of gate lines, a plurality of columns of data lines, and a plurality of rows of illumination control lines disposed on the silicon substrate;
  • the display device includes a plurality of the pixel unit circuits arranged in an array disposed on the silicon substrate;
  • Pixel unit circuits in the same row are connected to the same row of gate lines; pixel unit circuits in the same column are connected to the same column of data lines;
  • the pixel unit circuit includes a reset module
  • pixel unit circuits located in the same column are connected to the same row of light emission control lines.

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Abstract

一种像素单元电路、像素电路、驱动方法和显示装置。像素单元电路包括：发光元件（OLED），第一端与低电平（Vss）输入端连接；存储电容模块（11），第一端与一直流电压输入端（VD）连接；驱动晶体管（DTFT），栅极与存储电容模块（11）的第二端连接，第一极与发光元件（OLED）的第二端连接；发光控制模块（12），控制端与发光控制线（EM）连接，第一端与高电平（Vdd）输入端连接，第二端与驱动晶体管（DTFT）的第二极连接，用于在发光控制线（EM）的控制下控制驱动晶体管（DTFT）的第二极是否接收来自高电平（Vdd）输入端的信号；充电补偿控制模块（13），分别与栅线（Gate）、数据线（Data）和驱动晶体管（DTFT）的栅极连接，用于在栅线（Gate）的控制下控制驱动晶体管（DTFT）的栅极是否接收来自数据线（Data）的信号。

Description

像素单元电路、像素电路、驱动方法和显示装置
相关申请的交叉引用
本申请主张在2017年7月17日在中国提交的中国专利申请号No.201710581734.7的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素单元电路、像素电路、驱动方法和显示装置。
背景技术
硅基OLED(Organic Light-Emitting Diode，有机发光二极管)微显示器处于微电子技术和光电子技术的交叉点上，结合了OLED技术和CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)技术，是光电子产业和微电子产业的交叉集成，促进了新一代的微型显示的发展，也推进了硅上有机电子，甚至是硅上分子电子的研究和发展。
相关技术中的硅基OLED微显示器不能有效调节Micro(微)OLED自身的亮度，并存在动态残影，并数据线上的数据电压范围窄从而不能有效提高OLED的发光亮度的问题。
发明内容
本公开提供了一种像素单元电路，包括：
发光元件，第一端与低电平输入端连接；
存储电容模块，第一端与一直流电压输入端连接；
驱动晶体管，栅极与所述存储电容模块的第二端连接，第一极与所述发光元件的第二端连接；
发光控制模块，控制端与发光控制线连接，第一端与高电平输入端连接，第二端与所述驱动晶体管的第二极连接，用于在所述发光控制线的控制下控制所述驱动晶体管的第二极是否接收来自所述高电平输入端的信号；以及，
充电补偿控制模块，分别与栅线、数据线和所述驱动晶体管的栅极连接，用于在所述栅线的控制下控制所述驱动晶体管的栅极是否接收来自所述数据线的信号。
实施时，本公开所述的像素单元电路还包括：重置模块，分别与所述发光控制线、所述驱动晶体管的第一极和重置电压输入端连接，用于在所述发光控制线的控制下，控制所述驱动晶体管的第一极是否接收来自所述重置电压输入端的信号；所述重置电压输入端包括地端或低电平输入端。
实施时，所述重置模块包括：重置开关晶体管，栅极与所述发光控制线连接，第一极与所述驱动晶体管的第一极连接，第二极与所述重置电压输入端连接。
实施时，所述发光控制模块包括：发光控制晶体管，栅极与所述发光控制线连接，第一极与所述高电平输入端连接，第二极与所述驱动晶体管的第二极连接；
当所述发光控制晶体管为p型晶体管时，所述重置开关晶体管为n型晶体管；当所述发光控制晶体管为n型晶体管时，所述重置开关晶体管为p型晶体管。
实施时，本公开所述的像素单元电路，还包括：电位控制晶体管，栅极和第一极都与所述驱动晶体管的第一极连接，第二极接地；所述电位控制晶体管为p型晶体管。
实施时，所述栅线包括第一栅极开关线和第二栅极开关线；
所述充电补偿控制模块包括：
第一充电补偿控制晶体管，栅极与所述第一栅极开关线连接，第一极与所述驱动晶体管的栅极连接，第二极与所述数据线连接；以及，
第二充电补偿控制晶体管，栅极与所述第二栅极开关线连接，第一极与所述数据线连接，第二极与所述驱动晶体管的栅极连接；
所述第一充电补偿控制晶体管为n型晶体管，所述第二充电补偿控制晶体管为p型晶体管。
本公开还提供了一种像素单元电路的驱动方法，用于驱动上述的像素单元电路，所述像素单元电路的驱动方法包括：
在充电补偿阶段，在发光控制线的控制下，发光控制模块控制驱动晶体管的第二极接收来自高电平输入端的信号；在栅线的控制下，充电补偿控制模块控制数据线上的数据电压Vdata写入驱动晶体管的栅极，以使得所述驱动晶体管导通，直至所述驱动晶体管的第一极的电位变为Vdata-Vth，所述驱动晶体管工作于恒定电流区；Vth为所述驱动晶体管的阈值电压；
在像素发光阶段，在发光控制线的控制下，发光控制模块控制驱动晶体管的第二极接收来自高电平输入端的信号，所述驱动晶体管工作于恒定电流区，驱动发光元件发光。
实施时，当所述像素单元电路还包括重置模块，分别与所述发光控制线、所述驱动晶体管的第一极和重置电压输入端连接，用于在所述发光控制线的控制下，控制所述驱动晶体管的第一极是否接收来自所述重置电压输入端的信号；所述重置电压输入端包括地端或低电平输入端，所述像素单元电路的驱动方法在所述充电补偿阶段之前还包括：
在重置阶段，在所述发光控制线的控制下，重置模块控制所述驱动晶体管的第一极是否接收来自重置电压输入端的信号，以重置所述驱动晶体管的第一极的电位；
在所述充电补偿阶段和所述像素发光阶段，在所述发光控制线的控制下，所述重置模块控制所述驱动晶体管的第一极不接收来自重置电压输入端的信号。
本公开还提供了一种像素电路，包括多行栅线、多列数据线、多行发光控制线和阵列排布的多个上述的像素单元电路；
位于同一行的像素单元电路与同一行栅线连接；
位于同一列的像素单元电路与同一列数据线连接；
当所述像素单元电路还包括重置模块时，位于同一行的像素单元电路与同一行发光控制线连接。
本公开还提供了一种像素电路的驱动方法，用于驱动上述的像素电路，在一帧显示时间内，一行像素单元电路对应于相应的充电补偿阶段和相应的像素发光阶段；
所述像素电路的驱动方法包括：在一帧显示时间内，
在相应的充电补偿阶段，在相应行发光控制线的控制下，位于相应行的像素单元电路包括的发光控制模块控制驱动晶体管的第二极接收来自高电平输入端的信号；在相应行栅线的控制下，位于相应行的像素单元电路包括的充电补偿控制模块控制相应列数据线上的数据电压Vdata写入位于相应行的像素单元电路包括的驱动晶体管的栅极，以使得所述驱动晶体管导通，直至所述驱动晶体管的第一极的电位变为Vdata-Vth，所述驱动晶体管工作于恒定电流区；Vth为所述驱动晶体管的阈值电压；
在相应的像素发光阶段，在所述相应行发光控制线的控制下，该发光控制模块控制所述驱动晶体管的第二极接收来自高电平输入端的信号，所述驱动晶体管工作于恒定电流区，驱动发光元件发光。
实施时，当所述像素电路中的像素单元电路包括重置模块，分别与所述发光控制线、所述驱动晶体管的第一极和重置电压输入端连接，用于在所述发光控制线的控制下，控制所述驱动晶体管的第一极是否接收来自所述重置电压输入端的信号；所述重置电压输入端包括地端或低电平输入端，
在相邻两帧显示时间之间设置有全屏插黑时间段；所述像素电路的驱动方法还包括：
在所述全屏插黑时间段，所述像素电路包括的所有行发光控制线都输出第一电平信号，从而使得所述的像素电路包括的每一像素单元电路中的发光元件的第二端都接收来自重置电压输入端的信号。
实施时，当所述像素电路中的像素单元电路包括重置模块，分别与所述发光控制线、所述驱动晶体管的第一极和重置电压输入端连接，用于在所述发光控制线的控制下，控制所述驱动晶体管的第一极是否接收来自所述重置电压输入端的信号；所述重置电压输入端包括地端或低电平输入端，在一帧显示时间内间隔设置有多个全屏插黑时间段；所述像素电路的驱动方法还包括：
在所述全屏插黑时间段，所述像素电路包括的所有行发光控制线都输出第一电平信号，从而使得所述像素电路包括的每一像素单元电路中的发光元件的第二端都接收来自重置电压输入端的信号。
实施时，当所述像素电路中的像素单元电路包括重置模块，分别与所述 发光控制线、所述驱动晶体管的第一极和重置电压输入端连接，用于在所述发光控制线的控制下，控制所述驱动晶体管的第一极是否接收来自所述重置电压输入端的信号；所述重置电压输入端包括地端或低电平输入端，所述像素电路的驱动方法还包括：在一帧显示时间，
所述像素电路包括的多行发光控制线依次输出第一电平信号，以使得所述像素电路包括的多行像素单元电路中的发光元件的第二端依次接收来自重置电压输入端的信号。
实施时，当所述像素电路中的像素单元电路包括重置模块，分别与所述发光控制线、所述驱动晶体管的第一极和重置电压输入端连接，用于在所述发光控制线的控制下，控制所述驱动晶体管的第一极是否接收来自所述重置电压输入端的信号；所述重置电压输入端包括地端或低电平输入端，每一帧显示时间包括至少两个显示周期，所述像素电路的驱动方法还包括：在每一显示周期，
所述像素电路包括的多行发光控制线依次输出第一电平信号，以使得所述像素电路包括的多行像素单元电路中的发光元件的第二端依次接收来自重置电压输入端的信号。
本发明还提供了一种显示装置，包括硅基板和设置于所述硅基板上的上述的像素单元电路。
附图说明
图1是本公开实施例所述的像素单元电路的结构图；
图2是本公开另一实施例所述的像素单元电路的结构图；
图3是本公开又一实施例所述的像素单元电路的结构图；
图4是本公开再一实施例所述的像素单元电路的结构图；
图5是本公开所述的像素单元电路的第一具体实施例的电路图；
图6是本公开如图5所示的像素单元电路的第一具体实施例的工作时序图；
图7A是本公开如图5所示的像素单元电路的第一具体实施例在重置阶段的工作示意图；
图7B是本公开如图5所示的像素单元电路的第一具体实施例在充电补偿阶段的工作示意图；
图7C是本公开如图5所示的像素单元电路的第一具体实施例在像素发光阶段的工作示意图；
图8是本公开所述的像素单元电路的第二具体实施例的电路图；
图9是本公开所述的像素电路的一种全屏插黑方式的工作时序图；
图10是本公开所述的像素电路的另一种全屏插黑方式的工作时序图；
图11是生成发光控制信号的移位寄存器单元的一具体实施例的电路图；
图12是如图11所示的移位寄存器单元的具体实施例的工作时序图；
图13是本公开所述的像素电路的一种逐行插黑方式的工作时序图；
图14是本公开所述的像素电路的另一种逐行插黑方式的工作时序图；
图15是本公开所述的像素电路的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。在实际操作时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的像素单元电路包括：
发光元件，第一端与低电平输入端连接；
存储电容模块，第一端与一直流电压输入端连接；
驱动晶体管，栅极与所述存储电容模块的第二端连接，第一极与所述发光元件的第二端连接；
发光控制模块，控制端与发光控制线连接，第一端与高电平输入端连接， 第二端与所述驱动晶体管的第二极连接，用于在所述发光控制线的控制下控制所述驱动晶体管的第二极是否与所述高电平输入端连接(即在所述发光控制线的控制下控制所述驱动晶体管的第二极和所述高电平输入端之间是否导通，以控制所述驱动晶体管的第二极是否接收来自所述高电平输入端的信号)；以及，
充电补偿控制模块，分别与栅线、数据线和所述驱动晶体管的栅极连接，用于在所述栅线的控制下控制所述驱动晶体管的栅极是否与所述数据线连接(即在所述栅线的控制下控制所述驱动晶体管的栅极和所述数据线之间是否导通，以控制所述驱动晶体管的栅极是否接收来自所述数据线的信号)。
本公开实施例所述的像素单元电路可以通过调节数据电压(通过配合时序使得充电补偿控制模块在充电补偿阶段控制发光元件的第二端的电位为Vdata)来有效调节发光元件自身的亮度。
在具体实施时，所述发光元件可以包括有机发光二极管，也可以包括其他的能够发光的器件。
在实际操作时，当所述发光元件包括有机发光二极管时，所述发光元件的第一端为所述有机发光二极管的阴极，所述发光元件的第二端为所述有机发光二级管的阳极。
在实际操作时，所述直流电压输入端可以为地端，也可以为其他输入直流电压的端子。
如图1所示，本公开实施例所述的像素单元电路包括：
有机发光二极管OLED，阴极与输入低电平Vss的低电平输入端连接；
存储电容模块11，第一端与一直流电压输入端VD连接；
驱动晶体管DTFT，栅极与所述存储电容模块11的第二端连接，源极与所述有机发光二极管OLED的阳极连接；
发光控制模块12，控制端与发光控制线EM连接，第一端与输入高电平Vdd的高电平输入端连接，第二端与所述驱动晶体管DTFT的漏极连接，用于在所述发光控制线EM的控制下控制所述驱动晶体管DTFT的漏极是否与所述输入高电平Vdd的高电平输入端连接；以及，
充电补偿控制模块13，分别与栅线Gate、数据线Data和所述驱动晶体 管DTFT的栅极连接，用于在所述栅线Gate的控制下控制所述驱动晶体管DTFT的栅极是否与所述数据线Data连接。
在图1所示的实施例中，以驱动晶体管DTFT为n型晶体管为例说明，在实际操作时，该驱动晶体管DTFT也可以为p型晶体管。
如图1所示的像素单元电路的实施例在工作时，
在充电补偿阶段，在发光控制线EM的控制下，发光控制模块12控制驱动晶体管DTFT的漏极与输入高电平Vdd的高电平输入端连接；在栅线Gate的控制下，充电补偿控制模块13控制数据线Data上的数据电压Vdata写入驱动晶体管DTFT的栅极，以使得所述驱动晶体管DTFT导通，直至所述驱动晶体管DTFT的源极的电位变为Vdata-Vth，所述驱动晶体管DTFT工作于恒定电流区；Vth为所述驱动晶体管DTFT的阈值电压；
在像素发光阶段，在发光控制线EM的控制下，发光控制模块12控制驱动晶体管DTFT的漏极与输入高电平Vdd的高电平输入端连接，所述驱动晶体管DTFT工作于恒定电流区，驱动有机发光元件OLED发光。
可选的，本公开实施例所述的像素单元电路还包括：重置模块，分别与所述发光控制线、所述驱动晶体管的第一极和重置电压输入端连接，用于在所述发光控制线的控制下，控制所述驱动晶体管的第一极是否与所述重置电压输入端连接(即控制所述驱动晶体管的第一极和所述重置电压输入端之间是否导通，以控制所述驱动晶体管的第一极是否接收来自所述所述重置电压输入端的信号)；所述重置电压输入端包括地端或低电平输入端。
本公开所述的像素单元电路优选的实施例中的重置模块可以在重置阶段控制消除上一帧残留于OLED的阳极的电压，从而消除动态残影。
如图2所示，在图1所示的像素单元电路的基础上，本公开实施例所述的像素单元电路还包括：重置模块14，分别与所述发光控制线EM、所述驱动晶体管DTFT的源极和地端GND连接，用于在所述发光控制线EM的控制下，控制所述驱动晶体管DTFT的源极是否与所述地端GND连接(即控制所述驱动晶体管DTFT的源极和地端GND之间是否导通，以控制所述驱动晶体管DTFT的源极是否接收来自所述地端GND的信号)。
在本公开如图2所示的像素单元电路的实施例工作时，在所述充电补偿 阶段之前还设置有一重置阶段；
在所述重置阶段，在所述发光控制线EM的控制下，重置模块14控制所述驱动晶体管DTFT的源极与地端GND连接，以重置所述驱动晶体管DTFT的源极的电位，以有效改善高频驱动下动态残影的问题。
在具体实施时，在所述充电补偿阶段和所述像素发光阶段，在所述发光控制线EM的控制下，重置模块14控制断开所述驱动晶体管的源极与地端GND之间的连接。
具体的，所述重置模块可以包括：重置开关晶体管，栅极与所述发光控制线连接，第一极与所述驱动晶体管的第一极连接，第二极与所述重置电压输入端连接。
具体的，所述发光控制模块可以包括：发光控制晶体管，栅极与所述发光控制线连接，第一极与所述高电平输入端连接，第二极与所述驱动晶体管的第二极连接；
当所述发光控制晶体管为p型晶体管时，所述重置开关晶体管为n型晶体管；当所述发光控制晶体管为n型晶体管时，所述重置开关晶体管为p型晶体管。
根据一种具体实施方式，在图1所示的像素单元电路的实施例的基础上，本公开所述的像素单元电路还可以包括：电位控制晶体管，栅极和第一极都与所述驱动晶体管的第一极连接，第二极接地；所述电位控制晶体管为p型晶体管。
如图3所示，在图1所示的像素单元电路的基础上，本公开实施例所述的像素单元电路还可以包括：电位控制晶体管P3，栅极和源极都与所述驱动晶体管DTFT的源极连接，漏极与地端GND连接；所述电位控制晶体管P3为p型晶体管。
本公开如图3所示的像素单元电路的实施例在工作时，该电位控制晶体管P3可以有效保护有机发光二极管OLED的阳极电位不会低于地端GND输出的电压，从而保护栅源电压DTFT的栅源电压不会超过栅源电压DTFT本身的最大驱动电压。
在具体实施时，如图4所示，所述栅线可以包括第一栅极开关线Gate1 和第二栅极开关线Gate2；
所述充电补偿控制模块13包括：
第一充电补偿控制晶体管N1，栅极与所述第一栅极开关线Gate1连接，源极与所述驱动晶体管DTFT的栅极连接，漏极与所述数据线Data连接；以及，
第二充电补偿控制晶体管P1，栅极与所述第二栅极开关线Gate2连接，源极与所述数据线Data连接，漏极与所述驱动晶体管DTFT的栅极连接；
所述第一充电补偿控制晶体管N1为n型晶体管，所述第二充电补偿控制晶体管P1为p型晶体管。
在图4所示的像素单元电路的实施例中，通过充电补偿控制模块包括一个NMOS管(Negative channel Metal Oxide Semiconductor，N沟道金属氧化物半导体场效应晶体管)和一个PMOS管(Positive channel Metal Oxide Semiconductor，P沟道金属氧化物半导体场效应晶体管)，能够增加数据线上的数据电压范围，提高有机发光二极管OLED的发光亮度。
在图4所示的实施例中，如果所述充电补偿控制模块仅包括第一充电补偿控制晶体管N1，则当Gate1输出的信号的电位不够高时，Data输出的较高数据电压则有可能不会被传输至驱动晶体管DTFT的栅极。而本公开如图4所示的像素单元电路的实施例通过充电补偿控制模块还包括第二充电补偿控制晶体管P1，在充电补偿阶段Gate2输出低电平信号，则即使Data输出的数据电压比较大，也可以保证该数据电压写入驱动晶体管DTFT的栅极，从而可以增加数据线输出的有效驱动电压范围。
在实际操作时，所述存储电容模块可以包括存储电容。
下面通过两具体实施例来说明本公开所述的像素单元电路。
如图5所示，本公开所述的像素单元电路的第一具体实施例包括有机发光二极管OLED、存储电容C1、驱动晶体管DTFT、发光控制模块、充电补偿控制模块和重置模块。
所述有机发光二极管OLED的阳极与所述驱动晶体管DTFT的漏极连接，所述有机发光二极管OLED的阴极与输入低电平Vss的低电平输入端连接；
所述存储电容C1的第一端与一直流电压输入端VD连接，所述存储电容 C1的第二端与所述驱动晶体管DTFT的栅极连接；
所述驱动晶体管DTFT的源极与所述有机发光二极管OLED的阳极连接；
所述充电补偿控制模块包括：
第一充电补偿控制晶体管N1，栅极与所述第一栅极开关线Gate1连接，源极与所述驱动晶体管DTFT的栅极连接，漏极与所述数据线Data连接；以及，
第二充电补偿控制晶体管P1，栅极与所述第二栅极开关线Gate2连接，源极与所述数据线Data连接，漏极与所述驱动晶体管DTFT的栅极连接；
所述重置模块包括：重置开关晶体管N2，栅极与发光控制线EM连接，源极与所述驱动晶体管DTFT的源极连接，漏极与地端GND连接；
所述发光控制模块包括：发光控制晶体管P2，栅极与所述发光控制线EM连接，源极与输入高电平Vdd的高电平输入端连接，第二极与所述驱动晶体管DTFT的漏极连接；
所述第一充电补偿控制晶体管N1为n型晶体管，所述第二充电补偿控制晶体管P1为p型晶体管，所述重置开关晶体管N2为n型晶体管，所述发光控制晶体管P2为p型晶体管；所述驱动晶体管DTFT为n型晶体管。
在图5中，a点为与所述有机发光二极管OLED的阳极连接的节点。
如图6所示，本公开如图5所示的像素单元电路的第一具体实施例在工作时，
在重置阶段S1，Gate1输出低电平，Gate2和EM输出高电平，如图7A所示，N2导通，P1、P2和N1断开，a点电位被重置放电到低电平，将上一帧OLED的阳极的电压信号进行重置，可以有效改善高频驱动下动态残影的问题；
在充电补偿阶段S2，Gate1输出高电平，Gate2和EM都输出低电平，如图7B所示，P1、P2和N1都导通，N2断开，Data输出的数据电压Vdata通过C1对DTFT的栅极充电，C1的第二端的电位被充电到Vdata，DTFT先导通直至a点电势变为Vdata-Vth，DTFT工作于恒定电流区(近似恒流区)；本公开实施例采用N1和P1，主要是由于可以增加Data输出的有效驱动电压范围；
在像素发光阶段S3，Gate1和EM都输出低电平，Gate2输出高电平，如图7C所示，P2导通，N1、P1和N2都断开，a点电势保持在Vdata-Vth，此时DTFT的漏极接入Vdd，DTFT工作于恒定电流区(近似恒流区)，电流通过导通的P2以及处于恒定电流区的DTFT驱动OLED发光；本公开实施例所述的像素单元电路通过控制驱动晶体管DTFT的栅极的电势，改变a点电势，从而改变OLED的两端的跨压，改变OLED的发光电流。
在具体实施时，本公开实施例所述的像素单元电路可以设置于硅基板上，该像素单元电路包括的发光元件可以为有机发光二极管，本公开实施例提出一种硅基OLED(有机发光二极管)像素驱动电路设计，通过匹配新的时序结合本身的像素驱动设计，可以有效调节Micro(微)OLED自身的亮度，还可以改善动态残影的问题，另外针对像素单元电路本身，通过特殊TFT的栅极，增加了数据电压范围，有效提高了OLED的发光亮度。
如图8所示，本公开所述的像素单元电路的第二具体实施例包括有机发光二极管OLED、存储电容C1、驱动晶体管DTFT、发光控制模块、充电补偿控制模块和电位控制晶体管P3。
其中，所述有机发光二极管OLED的阳极与所述驱动晶体管DTFT的漏极连接，所述有机发光二极管OLED的阴极与输入低电平Vss的低电平输入端连接；
所述存储电容C1的第一端与一直流电压输入端VD连接，所述存储电容C1的第二端与所述驱动晶体管DTFT的栅极连接；
所述驱动晶体管DTFT的源极与所述有机发光二极管OLED的阳极连接；
所述充电补偿控制模块包括：
第一充电补偿控制晶体管N1，栅极与所述第一栅极开关线Gate1连接，源极与所述驱动晶体管DTFT的栅极连接，漏极与所述数据线Data连接；以及，
第二充电补偿控制晶体管P1，栅极与所述第二栅极开关线Gate2连接，源极与所述数据线Data连接，漏极与所述驱动晶体管DTFT的栅极连接；
所述发光控制模块包括：发光控制晶体管P2，栅极与所述发光控制线EM连接，源极与输入高电平Vdd的高电平输入端连接，第二极与所述驱动晶体 管DTFT的漏极连接；
所述电位控制晶体管P3的栅极和源极都与所述驱动晶体管DTFT的源极连接，所述电位控制晶体管P3的漏极与地端GND连接；
所述电位控制晶体管P3为p型晶体管；
所述第一充电补偿控制晶体管N1为n型晶体管，所述第二充电补偿控制晶体管P1为p型晶体管，所述发光控制晶体管P2为p型晶体管；所述驱动晶体管DTFT为n型晶体管。
本公开如图8所示的像素单元电路的第二具体实施例在工作时，通过设置P3，可以有效保护OLED的阳极电位不会低于地电平，从而保证DTFT的栅源电压不会超过DTFT的最大驱动电压。
本公开实施例所述的像素单元电路的驱动方法，用于驱动上述的像素单元电路，所述像素单元电路的驱动方法包括：
在充电补偿阶段，在发光控制线的控制下，发光控制模块控制驱动晶体管的第二极与高电平输入端连接；在栅线的控制下，充电补偿控制模块控制数据线上的数据电压Vdata写入驱动晶体管的栅极，以使得所述驱动晶体管导通，直至所述驱动晶体管的第一极的电位变为Vdata-Vth，所述驱动晶体管工作于恒定电流区；Vth为所述驱动晶体管的阈值电压；
在像素发光阶段，在发光控制线的控制下，发光控制模块控制驱动晶体管的第二极与高电平输入端连接，所述驱动晶体管工作于恒定电流区，驱动发光元件发光。
可选的，当所述像素单元电路还包括重置模块，分别与所述发光控制线、所述驱动晶体管的第一极和重置电压输入端连接，用于在所述发光控制线的控制下，控制所述驱动晶体管的第一极是否与所述重置电压输入端连接；所述重置电压输入端包括地端或低电平输入端时，所述像素单元电路的驱动方法在所述充电补偿阶段之前还包括：
在重置阶段，在所述发光控制线的控制下，重置模块控制所述驱动晶体管的第一极与重置电压输入端连接，以重置所述驱动晶体管的第一极的电位。
本公开实施例所述的像素电路，如图15所示，包括多行栅线、多列数据线、多行发光控制线和阵列排布的多个上述的像素单元电路；
位于同一行的像素单元电路与同一行栅线连接；
位于同一列的像素单元电路与同一列数据线连接；
当所述像素单元电路还包括重置模块时，位于同一行的像素单元电路与同一行发光控制线连接。
在具体实施时，本公开实施例所述的像素电路可以设置于硅基板100上。
本公开实施例所述的像素电路的驱动方法，用于驱动上述的像素电路，在一帧显示时间内，一行像素单元电路对应于相应的充电补偿阶段和相应的像素发光阶段；
所述像素电路的驱动方法包括：在一帧显示时间内，
在相应的充电补偿阶段，在相应行发光控制线的控制下，位于相应行的像素单元电路包括的发光控制模块控制驱动晶体管的第二极与高电平输入端连接；在相应行栅线的控制下，位于相应行的像素单元电路包括的充电补偿控制模块控制相应列数据线上的数据电压Vdata写入位于相应行的像素单元电路包括的驱动晶体管的栅极，以使得所述驱动晶体管导通，直至所述驱动晶体管的第一极的电位变为Vdata-Vth，所述驱动晶体管工作于恒定电流区；Vth为所述驱动晶体管的阈值电压；
在相应的像素发光阶段，在所述相应行发光控制线的控制下，该发光控制模块控制所述驱动晶体管的第二极与高电平输入端连接，所述驱动晶体管工作于恒定电流区，驱动有发光元件发光。
可选的，所述像素电路中的像素单元电路包括重置模块，分别与所述发光控制线、所述驱动晶体管的第一极和重置电压输入端连接，用于在所述发光控制线的控制下，控制所述驱动晶体管的第一极是否与所述重置电压输入端连接；所述重置电压输入端包括地端或低电平输入端时，
在相邻两帧显示时间之间设置有全屏插黑时间段；所述像素电路的驱动方法还包括：
在所述全屏插黑时间段，所述像素电路包括的所有行发光控制线都输出第一电平信号，从而使得所述的像素电路包括的每一像素单元电路中的发光元件的第二端都与重置电压输入端连接，从而在设置于相邻两帧显示时间段之间的全屏插黑时间段，对所述像素电路包括的每一像素单元电路中的发光 元件的第二端进行电位重置，从而改善动态残影现象。
在实际操作时，所述发光元件可以包括有机发光二极管，所述发光元件的第二端可以为所述有机发光二极管的阳极。
在实际操作时，当发光控制模块包括的发光控制晶体管为n型晶体管时，所述第一电平信号为高电平信号，当发光控制模块包括的发光晶体管为p型晶体管时，所述第一电平信号为低电平信号。下面以发光控制模块包括的发光控制晶体管为n型晶体管为例说明。
如图9所示，标号为DE的为数据使能信号，当DE为高电平时，像素电路处于一帧显示时间，当DE为低电平时，像素电路处于空白时间段；标号为EM的为所述发光控制线，在一帧显示时间内，EM输出低电平信号，在设置于相邻两帧显示时间之间的全屏插黑时间段，EM输出高电平信号，对发光元件的第二端进行电位重置，从而改善动态残影现象。在图9中，标号为Sem1的为第一全屏插黑时间段，标号为Sem2的为第二全屏插黑时间段。
可选的，当所述像素电路中的像素单元电路包括重置模块，分别与所述发光控制线、所述驱动晶体管的第一极和重置电压输入端连接，用于在所述发光控制线的控制下，控制所述驱动晶体管的第一极是否与所述重置电压输入端连接；所述重置电压输入端包括地端或低电平输入端时，在一帧显示时间内间隔设置有多个全屏插黑时间段；所述像素电路的驱动方法还包括：
在所述全屏插黑时间段，所述像素电路包括的所有行发光控制线都输出第一电平信号，从而使得所述像素电路包括的每一像素单元电路中的发光元件的第二端都与重置电压输入端连接。
在实际操作时，当发光控制模块包括的发光控制晶体管为n型晶体管时，所述第一电平信号为高电平信号，当发光控制模块包括的发光晶体管为p型晶体管时，所述第一电平信号为低电平信号。下面以发光控制模块包括的发光控制晶体管为n型晶体管为例说明。
如图10所示，标号为DE的为数据使能信号，当DE为高电平时，像素电路处于一帧显示时间，当DE为低电平时，像素电路处于空白时间段；标号为EM的为所述发光控制线，在一帧显示时间内设置有两个全屏插黑时间段；在所述全屏插黑时间段，EM输出高电平信号，对发光元件的第二端进 行电位重置，从而改善动态残影现象；在除了全屏插黑时间段之外的其他时间段，EM输出低电平信号。
在图10中，标号为Sem1的为第一全屏插黑时间段，标号为Sem2的为第二全屏插黑时间段，标号为Sem3的为第三全屏插黑时间段，标号为Sem4的为第四全屏插黑时间段。
在如图9所示的可选实施例中，在一帧显示时间结束后进入全屏插黑模式，有效改善动态残影现象；在图10所示的可选实施例中，在一帧显示时间内，多次进入全屏插黑模式，可以有效改善动态残影现象。
可选的，当所述像素电路中的像素单元电路包括重置模块，分别与所述发光控制线、所述驱动晶体管的第一极和重置电压输入端连接，用于在所述发光控制线的控制下，控制所述驱动晶体管的第一极是否与所述重置电压输入端连接；所述重置电压输入端包括地端或低电平输入端时，所述像素电路的驱动方法还包括：在一帧显示时间，
所述像素电路包括的多行发光控制线依次输出第一电平信号，以使得所述像素电路包括的多行像素单元电路中的发光元件的第二端依次与重置电压输入端连接，也即在一帧显示时间内，控制多行发光控制线从上至下依次输出第一电平信号，从而控制进行逐行插黑，即像素电路包括的多行像素单元电路包括的发光元件的第二端的电位依次被重置，以改善动态残影现象。
可选的，当所述像素电路中的像素单元电路包括重置模块，分别与所述发光控制线、所述驱动晶体管的第一极和重置电压输入端连接，用于在所述发光控制线的控制下，控制所述驱动晶体管的第一极是否与所述重置电压输入端连接；所述重置电压输入端包括地端或低电平输入端时，每一帧显示时间包括至少两个显示周期，所述像素电路的驱动方法还包括：在每一显示周期，
所述像素电路包括的多行发光控制线依次输出第一电平信号，以使得所述像素电路包括的多行像素单元电路中的发光元件的第二端依次与重置电压输入端连接，也即一帧显示时间包括至少两个显示周期，在一显示周期内，控制多行发光控制线从上至下依次输出第一电平信号，从而控制进行逐行插黑，即像素电路包括的多行像素单元电路包括的发光元件的第二端的电位依 次被重置，以改善动态残影现象。在该可选的实施例中，在一帧显示时间内，多次进行逐行插黑。
在实际操作时，当发光控制模块包括的发光控制晶体管为n型晶体管时，所述第一电平信号为高电平信号，当发光控制模块包括的发光晶体管为p型晶体管时，所述第一电平信号为低电平信号。下面以发光控制模块包括的发光控制晶体管为n型晶体管为例说明。
图11是生成发光控制信号的移位寄存器单元的一具体实施例的电路图。
如图11所示，该移位寄存器单元的具体实施例包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第一电容Cs1、第二电容Cs2和第三电容Cs3；标号为CLK的为第一时钟信号、标号为CLKB的为第二时钟信号，标号为VL的为低电平，标号为VH的为高电平，标号为EO(N)的为第N级发光控制信号，标号为EM_STV(N)的为第N级起始信号；N为大于1的整数。在实际操作时，EM_STV(N)为EO(N-1)。在图11所示的实施例中，所有的晶体管都为p型晶体管，在实际操作时，以上晶体管也可以被替换为n型晶体管，仅需更改相应的控制信号的时序即可。
图12是图11所示的移位寄存器单元的具体实施例的工作时序图。在图12中，EO(N+1)为第N+1级发光控制信号。
如图12所示，EO(N)、EO(N+1)依次为高电平。
如图13所示，V-sync为同步刷新电压，当V-sync为高电平时，像素电路处于一帧显示时间，当V-sync为低电平时，像素电路处于空白时间段；EM_STV(N)为第N级起始信号，CLK为第一时钟信号，则根据图11所示的电路和图13所示的时序，在一帧显示时间内，多行发光控制线从上至下逐行输出高电平信号，逐行进行插黑。
如图14所示，V-sync为同步刷新电压，当V-sync为高电平时，像素电路处于一帧显示时间，当V-sync为低电平时，像素电路处于空白时间段；EM_STV(N)为第N级起始信号，CLK为第一时钟信号，则根据图11所示的电路和图14所示的时序，在一帧显示时间内，多行发光控制线至少两次从 上至下逐行输出高电平信号，进行至少两次逐行进行插黑。
在具体实施时，通过控制EM_STV(N)的占空比和CLK的占空比，即可控制相应的发光控制信号为高电平的时间长度。CLK的占空比越小，发光控制信号可以调节的范围越大。
本公开实施例所述的显示装置，如图15所示，包括硅基板100和设置于所述硅基板上的上述的像素单元电路。
在实际操作时，本公开实施例所述的显示装置还包括设置于所述硅基板上的多行栅线、多列数据线和多行发光控制线；
所述显示装置包括设置于所述硅基板上的阵列排布的多个所述像素单元电路；
位于同一行的像素单元电路与同一行栅线连接；位于同一列的像素单元电路与同一列数据线连接；
当所述像素单元电路包括重置模块时，位于同一列的像素单元电路与同一行发光控制线连接。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (22)

  1. 一种像素单元电路，包括：
    发光元件，第一端与低电平输入端连接；
    存储电容模块，第一端与一直流电压输入端连接；
    驱动晶体管，栅极与所述存储电容模块的第二端连接，第一极与所述发光元件的第二端连接；
    发光控制模块，控制端与发光控制线连接，第一端与高电平输入端连接，第二端与所述驱动晶体管的第二极连接，用于在所述发光控制线的控制下控制所述驱动晶体管的第二极是否接收来自所述高电平输入端的信号；以及，
    充电补偿控制模块，分别与栅线、数据线和所述驱动晶体管的栅极连接，用于在所述栅线的控制下控制所述驱动晶体管的栅极是否接收来自所述数据线的信号。
  2. 如权利要求1所述的像素单元电路，还包括：重置模块，分别与所述发光控制线、所述驱动晶体管的第一极和重置电压输入端连接，用于在所述发光控制线的控制下，控制所述驱动晶体管的第一极是否接收来自所述重置电压输入端的信号；所述重置电压输入端包括地端或低电平输入端。
  3. 如权利要求2所述的像素单元电路，其中，所述重置模块包括：重置开关晶体管，栅极与所述发光控制线连接，第一极与所述驱动晶体管的第一极连接，第二极与所述重置电压输入端连接。
  4. 如权利要求3所述的像素单元电路，其中，所述发光控制模块包括：发光控制晶体管，栅极与所述发光控制线连接，第一极与所述高电平输入端连接，第二极与所述驱动晶体管的第二极连接；
    所述发光控制晶体管为p型晶体管，所述重置开关晶体管为n型晶体管。
  5. 如权利要求3所述的像素单元电路，其中，所述发光控制模块包括：发光控制晶体管，栅极与所述发光控制线连接，第一极与所述高电平输入端连接，第二极与所述驱动晶体管的第二极连接；
    所述发光控制晶体管为n型晶体管，所述重置开关晶体管为p型晶体管。
  6. 如权利要求1所述的像素单元电路，还包括：电位控制晶体管，栅极 和第一极都与所述驱动晶体管的第一极连接，第二极接地；所述电位控制晶体管为p型晶体管。
  7. 如权利要求1至6中任一权利要求所述的像素单元电路，其中，所述栅线包括第一栅极开关线和第二栅极开关线；
    所述充电补偿控制模块包括：
    第一充电补偿控制晶体管，栅极与所述第一栅极开关线连接，第一极与所述驱动晶体管的栅极连接，第二极与所述数据线连接；以及，
    第二充电补偿控制晶体管，栅极与所述第二栅极开关线连接，第一极与所述数据线连接，第二极与所述驱动晶体管的栅极连接；
    所述第一充电补偿控制晶体管为n型晶体管，所述第二充电补偿控制晶体管为p型晶体管。
  8. 一种像素单元电路的驱动方法，用于驱动如权利要求1所述的像素单元电路，其中，所述像素单元电路的驱动方法包括：
    在充电补偿阶段，在发光控制线的控制下，发光控制模块控制驱动晶体管的第二极接收来自高电平输入端的信号；在栅线的控制下，充电补偿控制模块控制数据线上的数据电压Vdata写入驱动晶体管的栅极，以使得所述驱动晶体管导通，直至所述驱动晶体管的第一极的电位变为Vdata-Vth，所述驱动晶体管工作于恒定电流区；Vth为所述驱动晶体管的阈值电压；
    在像素发光阶段，在发光控制线的控制下，发光控制模块控制驱动晶体管的第二极接收来自高电平输入端的信号，所述驱动晶体管工作于恒定电流区，驱动发光元件发光。
  9. 如权利要求8所述的像素单元电路的驱动方法，其中，所述像素单元电路还包括重置模块，分别与所述发光控制线、所述驱动晶体管的第一极和重置电压输入端连接，用于在所述发光控制线的控制下，控制所述驱动晶体管的第一极是否接收来自所述重置电压输入端的信号；所述重置电压输入端包括地端或低电平输入端；所述像素单元电路的驱动方法在所述充电补偿阶段之前还包括：
    在重置阶段，在所述发光控制线的控制下，重置模块控制所述驱动晶体管的第一极接收来自重置电压输入端的信号，以重置所述驱动晶体管的第一 极的电位；
    在所述充电补偿阶段和所述像素发光阶段，在所述发光控制线的控制下，所述重置模块控制所述驱动晶体管的第一极不接收来自重置电压输入端的信号。
  10. 一种像素电路，包括多行栅线、多列数据线、多行发光控制线和阵列排布的多个如权利要求1所述的像素单元电路；
    其中，位于同一行的像素单元电路与同一行栅线连接；
    位于同一列的像素单元电路与同一列数据线连接。
  11. 如权利要求10所述的像素电路，其中，所述像素单元电路还包括重置模块，位于同一行的像素单元电路与同一行发光控制线连接。
  12. 如权利要求11所述的像素电路，其中，所述重置模块分别与所述发光控制线、所述驱动晶体管的第一极和重置电压输入端连接，用于在所述发光控制线的控制下，控制所述驱动晶体管的第一极是否接收来自所述重置电压输入端的信号；所述重置电压输入端包括地端或低电平输入端。
  13. 如权利要求12所述的像素电路，其中，所述重置模块包括：重置开关晶体管，栅极与所述发光控制线连接，第一极与所述驱动晶体管的第一极连接，第二极与所述重置电压输入端连接。
  14. 如权利要求13所述的像素电路，其中，所述发光控制模块包括：发光控制晶体管，栅极与所述发光控制线连接，第一极与所述高电平输入端连接，第二极与所述驱动晶体管的第二极连接；
    所述发光控制晶体管为p型晶体管，所述重置开关晶体管为n型晶体管；
  15. 如权利要求13所述的像素电路，其中，所述发光控制模块包括：发光控制晶体管，栅极与所述发光控制线连接，第一极与所述高电平输入端连接，第二极与所述驱动晶体管的第二极连接；
    所述发光控制晶体管为n型晶体管，所述重置开关晶体管为p型晶体管。
  16. 如权利要求10所述的像素电路，其中，所述像素单元电路还包括：电位控制晶体管，栅极和第一极都与所述驱动晶体管的第一极连接，第二极接地；所述电位控制晶体管为p型晶体管。
  17. 一种像素电路的驱动方法，用于驱动如权利要求10所述的像素电路， 其中，在一帧显示时间内，一行像素单元电路对应于相应的充电补偿阶段和相应的像素发光阶段；
    所述像素电路的驱动方法包括：在一帧显示时间内，
    在相应的充电补偿阶段，在相应行发光控制线的控制下，位于相应行的像素单元电路包括的发光控制模块控制驱动晶体管的第二极接收来自高电平输入端的信号；在相应行栅线的控制下，位于相应行的像素单元电路包括的充电补偿控制模块控制相应列数据线上的数据电压Vdata写入位于相应行的像素单元电路包括的驱动晶体管的栅极，以使得所述驱动晶体管导通，直至所述驱动晶体管的第一极的电位变为Vdata-Vth，所述驱动晶体管工作于恒定电流区；Vth为所述驱动晶体管的阈值电压；
    在相应的像素发光阶段，在所述相应行发光控制线的控制下，该发光控制模块控制所述驱动晶体管的第二极接收来自高电平输入端的信号，所述驱动晶体管工作于恒定电流区，驱动发光元件发光。
  18. 如权利要求17所述的像素电路的驱动方法，其中，所述像素电路中的像素单元电路包括重置模块，分别与所述发光控制线、所述驱动晶体管的第一极和重置电压输入端连接，用于在所述发光控制线的控制下，控制所述驱动晶体管的第一极是否接收来自所述重置电压输入端的信号；所述重置电压输入端包括地端或低电平输入端；
    所述像素电路的驱动方法还包括：
    在相邻两帧显示时间之间设置有全屏插黑时间段；在所述全屏插黑时间段，所述像素电路包括的所有行发光控制线都输出第一电平信号，从而使得所述的像素电路包括的每一像素单元电路中的发光元件的第二端都接入来自重置电压输入端的信号。
  19. 如权利要求17所述的像素电路的驱动方法，其中，所述像素电路中的像素单元电路包括重置模块，分别与所述发光控制线、所述驱动晶体管的第一极和重置电压输入端连接，用于在所述发光控制线的控制下，控制所述驱动晶体管的第一极是否接收来自所述重置电压输入端的信号；所述重置电压输入端包括地端或低电平输入端；
    所述像素电路的驱动方法还包括：
    在一帧显示时间内间隔设置有多个全屏插黑时间段；
    在所述全屏插黑时间段，所述像素电路包括的所有行发光控制线都输出第一电平信号，从而使得所述像素电路包括的每一像素单元电路中的发光元件的第二端都接收来自重置电压输入端的信号。
  20. 如权利要求17所述的像素电路的驱动方法，其中，所述像素电路中的像素单元电路包括重置模块，分别与所述发光控制线、所述驱动晶体管的第一极和重置电压输入端连接，用于在所述发光控制线的控制下，控制所述驱动晶体管的第一极是否接收来自所述重置电压输入端的信号；所述重置电压输入端包括地端或低电平输入端，
    所述像素电路的驱动方法还包括：在一帧显示时间，
    所述像素电路包括的多行发光控制线依次输出第一电平信号，以使得所述像素电路包括的多行像素单元电路中的发光元件的第二端依次接收来自重置电压输入端的信号。
  21. 如权利要求17所述的像素电路的驱动方法，其中，所述像素电路中的像素单元电路包括重置模块，分别与所述发光控制线、所述驱动晶体管的第一极和重置电压输入端连接，用于在所述发光控制线的控制下，控制所述驱动晶体管的第一极是否接收来自所述重置电压输入端的信号；所述重置电压输入端包括地端或低电平输入端；
    所述像素电路的驱动方法还包括：
    每一帧显示时间包括至少两个显示周期，在每一显示周期，
    所述像素电路包括的多行发光控制线依次输出第一电平信号，以使得所述像素电路包括的多行像素单元电路中的发光元件的第二端依次接收来自重置电压输入端的信号。
  22. 一种显示装置，包括硅基板和设置于所述硅基板上的如权利要求1至7所述的像素单元电路。
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