WO2019010946A1 - 显示面板及其制作方法、显示设备 - Google Patents

显示面板及其制作方法、显示设备 Download PDF

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Publication number
WO2019010946A1
WO2019010946A1 PCT/CN2018/073289 CN2018073289W WO2019010946A1 WO 2019010946 A1 WO2019010946 A1 WO 2019010946A1 CN 2018073289 W CN2018073289 W CN 2018073289W WO 2019010946 A1 WO2019010946 A1 WO 2019010946A1
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type semiconductor
electrode
layer
thin film
film transistor
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PCT/CN2018/073289
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English (en)
French (fr)
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王质武
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深圳市华星光电技术有限公司
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Priority to US15/763,184 priority Critical patent/US10971480B2/en
Publication of WO2019010946A1 publication Critical patent/WO2019010946A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display panel and a method for fabricating the same, and a display device.
  • Micro LEDs consume only one-tenth the power of liquid crystal displays (LCDs). Like the organic light-emitting diode (OLED), the Micro LED is a self-luminous device with low power consumption, small thickness, small mass, small size, low power consumption, fast response, and does not have the disadvantage of OLED color decay, so it becomes a panel. Hot spots in industry research.
  • LCDs liquid crystal displays
  • OLED organic light-emitting diode
  • a micro LED chip when electrically connected to a thin film transistor (TFT), a general N-type semiconductor is adjacent to the TFT, and a P-type semiconductor is disposed on a side of the N-type semiconductor facing away from the TFT.
  • TFT thin film transistor
  • Light is emitted from the light-emitting layer provided between the P-type semiconductor and the N-type semiconductor, and enters the P-type semiconductor layer to be emitted.
  • the light-emitting surface of the P-type semiconductor is a smooth surface, since the total reflection causes a part of the light to re-enter the light-emitting layer and is converted into heat, the light-emitting efficiency is lowered.
  • the P-type semiconductor layer is roughened in the prior art to reduce total reflection of light and increase light extraction efficiency.
  • the P-type semiconductor layer is relatively thin and the thickness is within 200 nm, the coarsening causes the crystal quality of the P-type semiconductor material to decrease, thereby increasing the leakage current of the Micro LED chip.
  • the present invention provides a display panel that reduces the generation of leakage current of the Micro LED chip while increasing light extraction efficiency.
  • the display panel includes a thin film transistor, a micro light emitting diode disposed on the thin film transistor and electrically connected to the thin film transistor, the micro light emitting diode including a P type semiconductor and an N type semiconductor disposed opposite to the P type semiconductor a light-emitting layer disposed between the P-type semiconductor and the N-type semiconductor, wherein the N-type semiconductor is disposed on a side of the P-type semiconductor facing away from the thin film transistor, and a thickness of the N-type semiconductor is greater than In the P-type semiconductor, one side of the N-type semiconductor facing away from the P-type semiconductor is a rough surface.
  • the display panel further includes a passivation layer and an organic layer.
  • the organic layer is stacked on the thin film transistor, and the organic layer is provided with an open slot, and the micro light emitting diode is received in the open slot. Electrically connecting to the thin film transistor; the passivation layer is laminated and covers the organic layer and the micro light emitting diode.
  • the passivation layer is an organic or inorganic insulating film layer.
  • the display panel further includes a first electrode and a second electrode.
  • the first electrode is stacked on the thin film transistor and located at an open slot of the organic layer, and the thin film transistor includes a source drain. One end of the first electrode is connected to the source and the drain, and the other end is electrically connected to the P-type semiconductor; the second electrode is stacked above the passivation layer, and one end of the second electrode passes through The passivation layer is electrically connected to the N-type semiconductor.
  • the P-type semiconductor is laminated with a transparent conductive layer on one surface of the first electrode, and the first electrode is electrically connected to the P-type semiconductor through the transparent conductive layer.
  • the N-type semiconductor is provided with an N-type metal electrode on a side facing away from the P-type semiconductor, and the second electrode is electrically connected to the N-type semiconductor through the N-type metal electrode.
  • the thickness of the N-type semiconductor is greater than 2 ⁇ m, and the thickness of the P-type semiconductor is less than 200 nm.
  • the invention also provides a method for manufacturing a display panel, comprising the steps of:
  • a micro light emitting diode is disposed in the open slot, and the micro light emitting diode is electrically connected to the thin film transistor, and the micro light emitting diode comprises a P-type semiconductor, an N-type semiconductor disposed opposite to the P-type semiconductor, and a light-emitting layer disposed between the P-type semiconductor and the N-type semiconductor, wherein the N-type semiconductor is disposed on a side of the P-type semiconductor facing away from the thin film transistor, and a thickness of the N-type semiconductor is greater than P-type semiconductor;
  • a second electrode is formed on the passivation layer, and one end of the second electrode is electrically connected to the N-type semiconductor.
  • the plasma forming gas in the plasma surface treatment process is any one or more of H 2 , Ar, N 2 or NH 3 .
  • the present invention also provides a display device including a display device body and the above display panel, the display panel being electrically connected to the display device body.
  • the display panel provided by the present invention, when the micro LED chip is electrically connected to a thin film transistor (TFT), the P-type semiconductor is brought close to the TFT, and the N-type semiconductor is disposed on a side of the P-type semiconductor facing away from the TFT, and The side of the N-type semiconductor facing away from the P-type semiconductor is treated as a rough surface. Since the thickness of the N-type semiconductor is larger than the thickness of the P-type semiconductor, when the N-type semiconductor is roughened, the crystal quality of the N-type semiconductor material is not affected, thereby achieving an increase in light-emitting efficiency. At the same time, the generation of leakage current of the Micro LED chip is avoided.
  • TFT thin film transistor
  • FIG. 1 is a schematic structural view of a display panel according to an embodiment of the present invention.
  • FIG. 2 is a flow chart showing the manufacture of the display panel of the embodiment of the present invention shown in FIG. 1;
  • FIG. 3 is a specific flowchart of the steps of "providing a substrate on which a thin film transistor and an organic layer are formed, and forming an open trench on the organic layer” in the manufacture of the display panel according to the embodiment of the present invention
  • 4 to 10 are schematic cross-sectional views showing respective manufacturing steps of the display panel of the present invention.
  • the present invention provides a display panel 100.
  • the display panel 100 includes a substrate 10, a thin film transistor 20 disposed on the substrate 10, and a micro light emitting diode 30 disposed on the thin film transistor 20 and electrically connected to the thin film transistor 20.
  • the substrate 10 may be a rigid substrate or a flexible substrate.
  • the substrate 10 is a rigid glass substrate.
  • the thin film transistor 20 is an LTPS-TFT.
  • the thin film transistor 20 includes a buffer layer 21, an active layer 22, a gate insulating layer 23, a gate electrode 24, a dielectric layer 25, a source and drain electrode 26, a barrier layer 27, and a flat layer 28.
  • the buffer layer 21 is laminated and covered on the substrate 10, and the active layer 22 is laminated on the buffer layer 21.
  • the edge layer 22 includes a channel layer 221 and first doped regions 222 and second doped regions 223 disposed on opposite sides of the channel layer 221 .
  • the gate insulating layer 23 covers the edge layer 22 and the buffer layer 21 not covered by the edge layer 22.
  • the gate electrode 24 is laminated on the gate insulating layer 23, and a projection in a vertical direction thereof is located in the layer 221.
  • the dielectric layer 25 is laminated on the gate electrode 24 and covers the gate electrode 24 and the gate insulating layer 23 not covered by the gate electrode 24.
  • Two via holes extending from the dielectric layer 25 facing away from the gate insulating layer 23 toward the active layer 22, and two of the via holes are respectively located in the first doped region 222 and On the second doping region 223.
  • the source and drain electrodes 26 are disposed on the dielectric layer 25, and the source and drain electrodes 26 include a source and a drain, and the source and the drain respectively pass through the via and through the
  • the dielectric layer 25 and the gate insulating layer 23 are electrically connected to the first doping region 222 and the second doping region 223, respectively.
  • the barrier layer 27 is stacked on the source and drain electrodes 26 and covers the source and drain electrodes 26 and the dielectric layer 25 not covered by the source and drain electrodes 26.
  • the flat layer 28 is laminated on the barrier layer 27.
  • a through hole extends from the flat layer 28 facing away from the barrier layer 27 toward the interior of the planar layer 28, the through hole extending to the source and drain electrodes 26.
  • the thin film transistor 20 can also be other types of thin film transistors, such as ordinary TFTs, LTPS-TFTs, HTPS-TFTs, and the like, according to actual needs.
  • the micro light emitting diode 30 includes a transparent conductive layer 31, a P-type semiconductor 32, a light-emitting layer 33, and an N-type semiconductor 34 which are sequentially stacked.
  • the P-type semiconductor 32 is disposed opposite to and parallel to the N-type semiconductor 34, and the light-emitting layer 33 is provided between the P-type semiconductor 32 and the N-type semiconductor 34.
  • the P-type semiconductor 32 is bonded to the transparent conductive layer 31 to electrically connect the P-type semiconductor 32 and the transparent conductive layer 31. Further, the P-type semiconductor 32 is electrically connected to the thin film transistor 20 through the transparent conductive layer 31.
  • the current or voltage transmitted by the thin film transistor 20 is uniformly distributed on the P-type semiconductor through the transparent conductive layer 31, and uniform light emission at each position of the light-emitting layer 33 can be promoted.
  • the N-type semiconductor 34 is disposed on a side of the P-type semiconductor 32 facing away from the thin film transistor 20, and a surface of the N-type semiconductor 34 facing away from the P-type semiconductor 32 is a rough surface.
  • the light-emitting layer 33 from the N-type semiconductor and the P-type semiconductor emits light from the N-type by providing a surface of the N-type semiconductor 34 facing away from the P-type semiconductor 32 as a rough surface.
  • the light extraction efficiency on the semiconductor side increases.
  • the thickness of the N-type semiconductor 34 is greater than the thickness of the P-type semiconductor 32, and therefore, one side of the N-type semiconductor 34 is set to be rough.
  • the surface does not affect the crystal quality in the N-type semiconductor 34, so that the leakage current of the Micro LED chip 30 is not increased, and the leakage current of the Micro LED chip 30 is reduced while increasing the light extraction efficiency. produce.
  • the thickness of the N-type semiconductor is greater than 2 ⁇ m, and the thickness of the P-type semiconductor is less than 200 nm.
  • an N-type metal electrode is further disposed on a side of the N-type semiconductor 34 facing away from the P-type semiconductor 32.
  • the display panel 100 further includes an organic layer 40, a passivation layer 50, a first electrode 60, and a second electrode 70.
  • the organic layer 40 is laminated on the thin film transistor 20.
  • the organic layer 40 is provided with an open groove 41, and the micro light emitting diode 30 is received in the open groove 41.
  • the passivation layer 50 is laminated on the organic layer 40 and covers the micro light emitting diode 30.
  • the passivation layer 50 is an organic or inorganic insulating film layer.
  • the first electrode 60 is disposed on the flat layer 28 of the thin film transistor 20 and embedded in the organic layer 40, that is, the organic layer 40 covers the first electrode 60 and is not the first The flat layer 28 covered by the electrode 60. Further, the bottom wall of the opening groove 41 is the first electrode 60, that is, an opening groove 41 is formed in the organic layer 40, and a part of the first electrode 60 is exposed.
  • One end of the first electrode 60 is electrically connected to the source and drain electrodes 26 of the thin film transistor 20 through the through holes, and the other end is electrically connected to the P transparent conductive layer 31 through the bonding material layer 35, thereby passing through the The first electrode 60 realizes electrical connection between the micro light emitting diode 30 and the thin film transistor 20.
  • the second electrode 70 is laminated on the passivation layer 40, and one end of the second electrode 70 is electrically connected to the N-type metal electrode 35 through a via provided on the passivation layer 40.
  • the second electrode 70 is disposed on the passivation layer 40, and the first electrode 60 and the second electrode 70 are isolated by the passivation layer 40 to prevent the first electrode. 60 and the second electrode 70 generate a short circuit phenomenon.
  • a current is applied to the micro-light-emitting diode 30 through the first electrode 60 and the second electrode 70, so that the light-emitting layer 33 of the micro-light-emitting diode 30 emits light, and the emitted light passes through the
  • the N-type semiconductor 34 is permeable. Further, since one side of the N-type semiconductor 34 facing away from the P-type semiconductor 32 is a rough surface, total reflection of light by the N-type semiconductor side is reduced, thereby increasing the light-emitting efficiency of the N-type semiconductor side.
  • the thickness of the N-type semiconductor 34 is large, when one surface of the N-type semiconductor 34 is provided as a rough surface, the crystal quality in the N-type semiconductor 34 is not affected, so that the The leakage current of the Micro LED chip 30, in turn, reduces the generation of leakage current of the Micro LED chip 30 while increasing the light extraction efficiency.
  • the method for manufacturing the display panel 100 of the present invention further includes:
  • Step 210 providing a substrate 10 on which a thin film transistor 20 and an organic layer 40 are formed.
  • the organic layer 40 is laminated on the thin film transistor 20, and an open trench 41 is formed on the organic layer 40.
  • the step 210 includes:
  • a substrate 10 is provided on which a thin film transistor 20 is formed.
  • the substrate 10 may be a rigid substrate or a flexible substrate.
  • the substrate 10 is a rigid glass substrate.
  • the thin film transistor 20 is an LTPS-TFT.
  • the thin film transistor 20 includes a buffer layer 21, a rim layer 22, a gate insulating layer 23, a gate electrode 24, a dielectric layer 25, a source and drain electrode 26, a barrier layer 27, and a flat layer 28.
  • the buffer layer 21 is formed on the substrate 10 by a process such as vapor deposition, spin coating or ink jet printing, and the buffer layer 21 is laminated and covered on the substrate 10.
  • An active layer 22 is formed on the buffer layer 21, and the active layer 22 is laminated on the buffer layer 21.
  • N-doping and P-ion doping are respectively performed on the two ends of the active layer 22, so that the active layer 22 forms a channel layer 221 and a first doping disposed on both sides of the channel layer 221 Region 222 and second doped region 223.
  • the gate insulating layer 23 is formed on the active layer 22 and the buffer layer 21 not covered by the active layer 22, and the gate insulating layer 23 covers the active layer 22 and is not The buffer layer 21 covered by the active layer 22.
  • the gate electrode 24 is formed on the gate insulating layer 23, and a projection of the gate electrode 24 in a vertical direction is located in the channel layer 221.
  • the dielectric layer 25 is formed on the gate electrode 24 and the gate insulating layer 23 not covered by the gate electrode 24.
  • the dielectric layer 25 covers the gate electrode 24 and is not covered by the gate electrode 24. Covered gate insulating layer 23. Two via holes are formed from the dielectric layer 25 facing away from the gate insulating layer 23 toward the active layer 22, and the two via holes are respectively located in the first doping region 222 and On the second doping region 223. Forming the source and drain electrodes 26 on the dielectric layer 25, and passing the source and drain electrodes 26 through the dielectric layer 25 and the gate insulating layer 23 to obtain the via holes respectively The doped region 222 and the second doped region 223 are electrically connected.
  • the barrier layer 27 is formed on the source and drain electrodes 26 such that the barrier layer 27 covers the source and drain electrodes 26 and the dielectric layer 25 not covered by the source and drain electrodes 26.
  • the flat layer 28 is formed on the barrier layer 27.
  • a through hole extends from the flat layer 28 facing away from the barrier layer 27 toward the source drain 26, and the through hole is located on the source and drain electrodes 26.
  • the thin film transistor 20 can also be other types of thin film transistors, such as ordinary TFTs, HTPS-TFTs, and the like, according to actual needs.
  • Step 212 referring to FIG. 4, a first electrode 60 is formed on the thin film transistor 20, and the first electrode 60 is electrically connected to the thin film transistor 20.
  • first metal layer Forming a first metal layer on the flat layer 26 of the thin film transistor 20 by a process such as electroplating, magnetron sputtering, vapor deposition, etc., further patterning the first metal layer to obtain the first electrode 60 .
  • the first electrode 60 is electrically connected to the source and drain electrodes 26 through the through holes.
  • Step 213. an organic material layer 42 is deposited on the first electrode 60 and on the thin film transistor 20 not covered by the first electrode 60.
  • the organic material layer 42 is an organic photoresist material.
  • the thin film transistor 20 formed on the first electrode 60 and not covered by the first electrode 60 is deposited by a process such as spin coating or inkjet printing.
  • Step 214 referring to FIG. 7, the organic material layer 42 is patterned to obtain an organic layer 40.
  • the organic layer 40 is provided with an open groove 41.
  • the organic material layer 42 is patterned by exposure, development, or the like to obtain the organic layer 40.
  • the organic layer 40 includes an open groove 41.
  • the open groove 41 has a truncated cone shape, and its opening direction faces away from the thin film transistor 20, and the size of the opening is larger than the size of the bottom wall.
  • the organic material layer 42 is patterned to remove the organic material layer 42 covering the first electrode 60, exposing the first electrode 60 and forming the opening groove 41, so that the The bottom wall of the open groove 41 is the first electrode 60.
  • a micro light emitting diode 30 is disposed in the open slot 41, and the micro light emitting diode 30 is bonded to the first electrode 60.
  • the miniature light emitting diode 30 includes a P type semiconductor. 32.
  • An N-type semiconductor 34 disposed opposite to the P-type semiconductor 32 and a light-emitting layer 33 disposed between the P-type semiconductor 32 and the N-type semiconductor 34.
  • the N-type semiconductor 34 is disposed on a side of the P-type semiconductor 32 facing away from the thin film transistor 20, and the thickness of the N-type semiconductor 34 is larger than that of the P-type semiconductor 32.
  • a side of the P-type semiconductor 32 facing away from the N-type semiconductor 34 is further provided with a transparent conductive layer 31, and the transparent conductive layer 31 and the first electrode 60 are passed through a bonding material layer. Bonding is performed to achieve electrical connection between the micro-light emitting diode 30 and the thin film transistor 20.
  • Step 230 referring to FIG. 9, the surface of the N-type semiconductor 34 facing away from the P-type semiconductor 32 is processed by a plasma surface process, and the N-type semiconductor 34 is roughened toward one side of the P-type semiconductor 32. .
  • one side of the N-type semiconductor 34 facing away from the P-type semiconductor 32 is processed by the plasma surface treatment process.
  • the plasma surface treatment process processes a certain gas to form a plasma, and the surface of the object is processed by the plasma.
  • the gas forming the plasma may also be any one or several of H 2 , Ar, N 2 or NH 3 .
  • the gas forming the plasma is H 2 .
  • Step 240 referring to FIG. 10, a passivation layer 70 is deposited on the organic layer 40 and the micro light emitting diode 30.
  • a passivation material layer 71 is deposited on the organic layer 40 and the micro light emitting diode 30 by a process such as spin coating or inkjet printing, and the passivation material layer 71 covers the organic layer 40 and the micro light emitting diode 30 . Further, the passivation material layer 71 is patterned by an overetching process to obtain a passivation layer 70.
  • the passivation layer 70 includes an opening extending from the passivation layer 70 facing away from the interior of the organic layer 60 toward the interior of the passivation layer 70 onto the N-type semiconductor.
  • Step 250 referring back to FIG. 1, a second electrode 50 is formed on the passivation layer 70, and one end of the second electrode 50 is electrically connected to the N-type semiconductor 34 through the opening.
  • a second metal layer is formed on the passivation layer 70 by a process such as electroplating, magnetron sputtering, vapor deposition, or the like, and the second metal layer is further patterned to obtain the second electrode 50. Further, the second electrode 50 is electrically connected to the N-type semiconductor 32 through the opening. In this embodiment, an N-type metal electrode is further laminated and electrically connected to the N-type semiconductor, and the second electrode 50 and the N-type semiconductor 32 are realized by the N-type metal electrode and the second electrode 50. The electrical connection is such that the electrical connection between the second electrode 50 and the N-type semiconductor 32 is more robust.
  • the invention also provides a display device.
  • the display device includes a display device body and the display panel, and the display panel is electrically connected to the display device body.
  • the display device may be an electronic display device such as a mobile phone, a computer, a tablet, or a television.

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Abstract

一种显示面板（100）及其制作方法，包括微型发光二极管（30）及与所述微型发光二极管（30）电连接的薄膜晶体管（20）。所述微型发光二极管（30）包括N型半导体（34）及P型半导体（32）。所述P型半导体（32）靠近所述薄膜晶体管（20），所述N型半导体（34）设于P型半导体（32）背向薄膜晶体管（20）的一侧。通过等离子体表面处理工艺将所述N型半导体（34）背向所述P型半导体（32）的一面进行粗化。由于所述N型半导体（34）的厚度大于所述P型半导体（32）的厚度，因此，对所述N型半导体（34）进行粗化时，不会影响所述N型半导体（34）材料的晶体质量，进而增加出光效率的同时，减少所述微型发光二极管（30）的漏电流。

Description

显示面板及其制作方法、显示设备 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板及其制作方法，以及一种显示设备。
背景技术
微型发光二极管(Micro LED)的耗电量仅为液晶显示屏(LCD)的十分之一。Micro LED与有机发光二极管(OLED)一样属于自发光器件，具有低功耗、厚度小、质量小、体积小、功耗低、反应快的特点，且不具有OLED色衰的缺点，因此成为面板行业研究的热点。
现有技术中，Micro LED芯片与薄膜晶体管(TFT)电连接时，一般N型半导体靠近TFT，P型半导体设于N型半导体背向TFT的一侧。由于光从设于所述P型半导体及所述N型半导体之间的发光层射出，并进入P型半导体层进行出射。但是，P型半导体的出光面为光面时，由于全反射会导致部分光线重新进入发光层转化为热量，导致出光效率降低。因此，为了增加出光，现有技术中对P型半导体层进行粗化处理，以减少光的全反射，增加出光效率。但是由于P型半导体层相对薄，厚度在200nm以内，粗化会导致P型半导体材料的晶体质量下降，从而使得所述Micro LED芯片的漏电流增加。
发明内容
本发明的提供一种显示面板，在增加出光效率的同时，减少所述Micro LED芯片的漏电流的产生。
所述显示面板包括薄膜晶体管，设于所述薄膜晶体管上并与所述薄膜晶体管电连接的微型发光二极管，所述微型发光二极管包括P型半导体、与所述P型半导体相对设置的N型半导体、设于所述P型半导体与所述N型半导体之间的发光层，所述N型半导体设于所述P型半导体背向所述薄膜晶体管的一侧，所述N型半导体的厚度大于所述P型半导体，所述N型半导体背向所述P型半导体的一面为粗糙面。
其中，所述显示面板还包括钝化层及有机层，所述有机层层叠于所述薄膜晶体管上，且所述有机层上设有开口槽，所述微型发光二极管收容所述开口槽内并与所述薄膜晶体管电连接；所述钝化层层叠并覆盖所述有机层及所述微型发光二极管。
其中，所述钝化层为有机或无机绝缘膜层。
其中，所述显示面板还包括第一电极及第二电极，所述第一电极层叠于所述薄膜晶体管上并位于所述有机层的开口槽位置，所述薄膜晶体管包括源漏极，所述第一电极一端与所述源漏极连接，另一端与所述P型半导体进行电连接；所述第二电极层叠于所述钝化层上方，且所述第二电极的一端通过穿过所述钝化层与所述N型半导体进行电连接。
其中，所述P型半导体朝向所述第一电极的一面层叠有透明导电层，所述第一电极通过所述透明导电层与所述P型半导体进行电连接。
其中，所述N型半导体背向所述P型半导体的一侧设有N型金属电极，所述第二电极通过所述N型金属电极与所述N型半导体进行电连接。
其中，所述N型半导体的厚度大于2μm，所述P型半导体的厚度小于200nm。
本发明还提供一种显示面板的制作方法，包括步骤：
提供一形成有薄膜晶体管及有机层的基板，所述有机层层叠于所述薄膜晶体管上，在所述有机层上形成开口槽；
在所述开口槽内设一微型发光二极管，并将所述微型发光二极管与所述薄膜晶体管电连接，所述微型发光二极管包括P型半导体、与所述P型半导体相对设置的N型半导体及设于所述P型半导体与所述N型半导体之间的发光层，所述N型半导体设于所述P型半导体背向所述薄膜晶体管一侧，且所述N型半导体的厚度大于所述P型半导体；
通过等离子体表面处理工艺处理所述N型半导体背向所述P型半导体的一面，使所述N型半导体背向所述P型半导体的一面粗化；
在所述有机层及所述微型发光二极管上形成钝化层；
在所述钝化层上形成第二电极，且所述第二电极的一端与所述N型半导体电连接。
其中，所述等离子体表面处理工艺中的形成等离子体的气体为H 2、Ar、N 2或NH 3中任意一种或几种。
本发明还提供一种显示设备，包括显示设备本体及上述的显示面板，所述显示面板与所述显示设备本体电连接。本发明提供的所述显示面板，在所述Micro LED芯片与薄膜晶体管(TFT)电连接时，使所述P型半导体靠近TFT，N型半导体设于P型半导体背向TFT的一侧，并对所述N型半导体背向所述P型半导体的一面处理为粗糙面。由于所述N型半导体的厚度大于所述P型半导体的厚度，因此，对所述N型半导体进行粗化时，不会影响所述N型半导体材料的晶体质量，进而实现了增加出光效率的同时，避免所述Micro LED芯片的漏电流的产生。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例的显示面板的结构示意图；
图2是图1所述本发明实施例的显示面板制造流程图；
图3是本发明实施例的显示面板制造中步骤“提供一形成有薄膜晶体管及有机层的基板，并在所述有机层上形成开口槽”的具体流程图；
图4-图10是本发明实施的显示面板各制造步骤中的截面示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，本发明提供一种显示面板100。所述显示面板100包括基板10、设于所述基板10上的薄膜晶体管20，及设于所述薄膜晶体管20上并与 所述薄膜晶体管20电连接的微型发光二极管30。
所述基板10可以为刚性基板或者为柔性基板。本实施例中，所述基板10为刚性的玻璃基板。
本实施例中，所述薄膜晶体管20为LTPS-TFT。所述薄膜晶体管20包括缓冲层21、有源层22、栅极绝缘层23、栅极24、介电层25、源漏极26、阻隔层27及平坦层28。所述缓冲层21层叠并覆盖与所述基板10上，所述有源层22层叠于所述缓冲层21上。所述有缘层22包括沟道层221及分设于所述沟道层221两侧的第一掺杂区222及第二掺杂区223。所述栅极绝缘层23覆盖所述有有缘层22及未被所述有缘层22覆盖的所述缓冲层21。所述栅极24层叠于所述栅极绝缘层23上，且其垂直方向的投影位于所述都到层221内。所述介电层25层叠与所述栅极24上，并覆盖所述栅极24及未被所述栅极24覆盖的栅极绝缘层23。自所述介电层25背向所述栅极绝缘层23的一面向所述有源层22延伸有两个过孔，且两个所述过孔分别位于所述第一掺杂区222及所述第二掺杂区223上。所述源漏极26设于所述介电层25上，且所述源漏极26包括源极及漏极，所述源极与所述漏极分别通过所述过孔与穿过所述介电层25及所述栅极绝缘层23分别与所述第一掺杂区222及所述第二掺杂区223进行电连接。所述阻隔层27层叠于所述源漏极26上并覆盖所述源漏极26及未被所述源漏极26覆盖的所述介电层25。所述平坦层28层叠于所述阻隔层27上。自所述平坦层28背向所述阻隔层27的一面向所述平坦层28内部延伸有一穿孔，所述穿孔延伸至所述源漏极26。可以理解的是，根据实际需要，所述薄膜晶体管20还可以为其它类型的薄膜晶体管，如普通TFT、LTPS-TFT、HTPS-TFT等其它类型的薄膜晶体管。
所述微型发光二极管30包括依次层叠的透明导电层31、P型半导体32、发光层33、N型半导体34。所述P型半导体32与所述N型半导体34相对且平行设置，所述发光层33设于所述P型半导体32与所述N型半导体34之间。所述P型半导体32与所述透明导电层31进行贴合，从而实现所述P型半导体32与所述透明导电层31的电连接。并且，所述P型半导体32通过所述透明导电层31与所述薄膜晶体管20进行电连接。通过所述透明导电层31将所述薄膜晶体管20传输的电流或电压均匀分布于所述P型半导体上，能够促进所 述发光层33各个位置的均匀发光。
所述N型半导体34设于所述P型半导体32背向所述薄膜晶体管20的一侧，且所述N型半导体34背向所述P型半导体32的一面为粗糙面。通过将所述N型半导体34背向所述P型半导体32的一面设置为粗糙面，使得从所述N型半导体与所述P型半导体之间的所述出光层33发光从所述N型半导体侧的出光效率增加。并且，为了尽量减少所述N型半导体34的晶格缺陷，一般所述N型半导体34的厚度会大于所述P型半导体32的厚度，因此，将所述N型半导体34的一面设置为粗糙面，不会影响所述N型半导体34的中的晶体质量，从而不会增加所述Micro LED芯片30的漏电流，实现在增加出光效率的同时，减少所述Micro LED芯片30的漏电流的产生。本发明中，所述N型半导体的厚度大于2μm，所述P型半导体的厚度小于200nm。进一步的，本实施例中，所述N型半导体34背向所述P型半导体32的一面还设置有N型金属电极。
所述显示面板100还包括有机层40、钝化层50、第一电极60及第二电极70。所述有机层40层叠于所述薄膜晶体管20上。所述有机层40上设有开口槽41，且所述微型发光二极管30收容于所述开口槽41内。所述钝化层50层叠于所述有机层40上并覆盖所述微型发光二极管30。所述钝化层50为有机或无机绝缘膜层。
所述第一电极60设于所述薄膜晶体管20的平坦层28上，并内嵌于所述有机层40内，即所述有机层40覆盖所述第一电极60及未被所述第一电极60覆盖的平坦层28。并且，所述开口槽41的底壁为所述第一电极60，即在所述有机层40上设置开口槽41，并露出部分所述第一电极60。所述第一电极60的一端通过所述穿孔与所述薄膜晶体管20的源漏极26进行电连接，另一端与所述P透明导电层31通过键合材料层35进行电连接，从而通过所述第一电极60实现所述微型发光二极管30与所述薄膜晶体管20的电连接。所述第二电极70层叠于所述钝化层40上，所述第二电极70的一端通过设于所述钝化层40上的过孔与所述N型金属电极35进行电连接。本发明中将所述第二电极70设于所述钝化层40上，通过所述钝化层40将所述第一电极60及所述第二电极70隔离开，防止所述第一电极60与所述第二电极70产生短路现象。
本发明中，通过所述第一电极60及所述第二电极70向所述微型发光二极管30加载电流，使得所述微型发光二极管30的所述发光层33进行发光，发出的光线经过所述N型半导体34透出。并且，由于所述N型半导体34背向所述P型半导体32的一面为粗糙面，从而减少所述N型半导体侧对光线的全反射，从而增加所述N型半导体侧的出光效率。并且，由于所述N型半导体34的厚度较大，将所述N型半导体34的一面设置为粗糙面时，不会影响所述N型半导体34的中的晶体质量，从而不会增加所述Micro LED芯片30的漏电流，进而实现在增加出光效率的同时，减少所述Micro LED芯片30的漏电流的产生。
请参阅图2，本发明还所述显示面板100的制作方法，包括：
步骤210、提供一形成有薄膜晶体管20及有机层40的基板10，所述有机层40层叠于所述薄膜晶体管20上，在所述有机层40上形成开口槽41。
具体的，请参阅图3，所述步骤210包括：
步骤211、请参阅图4，提供一基板10，在所述基板10上形成薄膜晶体管20。所述基板10可以为刚性基板或者为柔性基板。本实施例中，所述基板10为刚性的玻璃基板。
本实施例中，所述薄膜晶体管20为LTPS-TFT。所述薄膜晶体管20包括缓冲层21、有缘层22、栅极绝缘层23、栅极24、介电层25、源漏极26、阻隔层27及平坦层28。通过气相沉积、旋涂或喷墨打印等工艺在所述基板10上形成所述缓冲层21，使所述缓冲层21层叠并覆盖与所述基板10上。并在所述缓冲层21上形成有源层22，所述有源层22层叠于所述缓冲层21上。对所述有源层22的两端分别进行N离子掺杂及P离子掺杂，使得所述有源层22形成沟道层221及分设于所述沟道层221两侧的第一掺杂区222及第二掺杂区223。在所述有源层22及未被所述有源层22覆盖的所述缓冲层21上形成所述栅极绝缘层23，所述栅极绝缘层23覆盖所述有源层22及未被所述有源层22覆盖的所述缓冲层21。在所述栅极绝缘层23上形成所述栅极24，所述栅极24垂直方向的投影位于所述沟道层221内。在所述栅极24及未被所述栅极24覆盖的栅极绝缘层23上形成所述介电层25，所述介电层25覆盖所述栅极24及未被所述栅极24覆盖的栅极绝缘层23。自所述介电层25背向所述栅极绝 缘层23的一面向所述有源层22延伸形成两个过孔，且两个所述过孔分别位于所述第一掺杂区222及所述第二掺杂区223上。在所述介电层25上形成所述源漏极26，并使所述源漏极26通过得到过孔穿过所述介电层25及所述栅极绝缘层23分别与所述第一掺杂区222及所述第二掺杂区223进行电连接。在所述源漏极26上形成所述阻隔层27，使所述阻隔层27覆盖所述源漏极26及未被所述源漏极26覆盖的所述介电层25。在所述阻隔层27形成所述平坦层28。自所述平坦层28背向所述阻隔层27的一面向所述源漏极26延伸一穿孔，且所述穿孔位于所述源漏极26上。可以理解的是，根据实际需要，所述薄膜晶体管20还可以为其它类型的薄膜晶体管，如普通TFT、HTPS-TFT等其它类型的薄膜晶体管。
步骤212、请参阅图4，在所述薄膜晶体管20上形成一第一电极60，所述第一电极60与所述薄膜晶体管20进行电连接。
通过电镀、磁控溅射、气相沉积等工艺在所述薄膜晶体管20的所述平坦层26上形成一第一金属层，进一步对所述第一金属层进行图案化得到所述第一电极60。并使所述第一电极60通过所述穿孔与所述源漏极26进行电连接。
步骤213、请参阅图6，在所述第一电极60上及未被所述第一电极60覆盖的所述薄膜晶体管20上沉积有机材料层42。
本实施例中，所述有机材料层42为有机光阻材料。通过旋涂或喷墨打印等工艺沉积形成于所述第一电极60上及未被所述第一电极60覆盖的所述薄膜晶体管20。
步骤214、请参阅图7，图案化所述有机材料层42，得到有机层40，所述有机层40上设有开口槽41。
通过曝光、显影等将所述有机材料层42进行图案化，得到所述有机层40。所述有机层40上包括开口槽41，所述开口槽41为圆台状，其开口方向背离所述薄膜晶体管20，且其开口的大小大于所述底壁的大小。本发明中，对所述有机材料层42进行图案化，除去覆盖在所述第一电极60的所述有机材料层42，露出所述第一电极60并形成所述开口槽41，使得所述开口槽41的底壁为所述第一电极60。
步骤220、请参阅图8，在所述开口槽41内设一微型发光二极管30，并 将所述微型发光二极管30与所述第一电极60键合，所述微型发光二极管30包括P型半导体32、与所述P型半导体32相对设置的N型半导体34及设于所述P型半导体32与所述N型半导体34之间的发光层33。
本发明中，所述N型半导体34设于所述P型半导体32背向所述薄膜晶体管20的一侧，且所述N型半导体34的厚度大于所述P型半导体32。本实施例中，所述P型半导体32背向所述N型半导体34的一侧还设有透明导电层31，并将所述透明导电层31与所述第一电极60通过键合材料层进行键合，以实现所述微型发光二极管30与薄膜晶体管20的电连接。
步骤230、请参阅图9，通过等离子体表面工艺处理所述N型半导体34背向所述P型半导体32的一面，使所述N型半导体34背向所述P型半导体32的一面粗化。
本实施例中，通过所述等离子体表面处理工艺对所述N型半导体34背向所述P型半导体32的一面进行处理。所述等离子体表面处理工艺为将一定的气体进行处理形成等离子体，通过所述等离子体对物体表面进行处理。本发明中，形成所述等离子体的气体还可以为H 2、Ar、N 2或NH 3中任意一种或几种气体。本实施例中，形成所述等离子体的气体为H 2。通过所述等离子体表面处理工艺，使所述N型半导体32背向所述P型半导体的一面粗糙化，从而减少所述N型半导体32对所述发光层33发出光线的全反射，进而增加所述显示面板100的透光率。
步骤240、请参阅图10，在所述有机层40及所述微型发光二极管30上沉积钝化层70。
通过旋涂或喷墨打印等工艺在所述有机层40及所述微型发光二极管30上沉积钝化材料层71，所述钝化材料层71覆盖所述有机层40及所述微型发光二极管30。进一步的，过刻蚀工艺图案化所述钝化材料层71，得到钝化层70。所述钝化层70包括开孔，所述开孔从所述钝化层70背向所述有机层60的一面向所述钝化层70内部延伸至所述N型半导体上。
步骤250、请重新参阅图1，在所述钝化层70上形成第二电极50，且所述第二电极50的一端穿过所述开孔与所述N型半导体34电连接。
通过电镀、磁控溅射、气相沉积等工艺在所述钝化层70上形成一第二金 属层，进一步对所述第二金属层进行图案化得到所述第二电极50。并且，所述第二电极50通过所述开孔与所述N型半导体32进行电连接。本实施例中，所述N型半导体上还层叠并电连接有N型金属电极，通过所述N型金属电极与所述第二电极50实现所述第二电极50与所述N型半导体32的电连接，使得所述第二电极50与所述N型半导体32之间的电连接更加的牢固。
本发明还提供一种显示设备。所述显示设备包括显示设备本体及上述的显示面板，所述显示面板与所述显示设备本体电连接。所述显示设备可以为手机、电脑、平板、电视等电子显示设备。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (16)

  1. 一种显示面板，其中，包括薄膜晶体管，设于所述薄膜晶体管上并与所述薄膜晶体管电连接的微型发光二极管，所述微型发光二极管包括P型半导体、与所述P型半导体相对设置的N型半导体、设于所述P型半导体与所述N型半导体之间的发光层，所述N型半导体设于所述P型半导体背向所述薄膜晶体管的一侧，所述N型半导体的厚度大于所述P型半导体，所述N型半导体背向所述P型半导体的一面为粗糙面。
  2. 如权利要求1所述的显示面板，其中，所述显示面板还包括钝化层及有机层，所述有机层层叠于所述薄膜晶体管上，且所述有机层上设有开口槽，所述微型发光二极管收容所述开口槽内并与所述薄膜晶体管电连接；所述钝化层层叠并覆盖所述有机层及所述微型发光二极管。
  3. 如权利要求2所述的显示面板，其中，所述钝化层为有机或无机绝缘膜层。
  4. 如权利要求2所述的显示面板，其中，所述显示面板还包括第一电极及第二电极，所述第一电极层叠于所述薄膜晶体管上并位于所述有机层的开口槽位置，所述薄膜晶体管包括源漏极，所述第一电极一端与所述源漏极连接，另一端与所述P型半导体进行电连接；所述第二电极层叠于所述钝化层上方，且所述第二电极的一端通过穿过所述钝化层与所述N型半导体进行电连接。
  5. 如权利要求3所述的显示面板，其中，所述P型半导体朝向所述第一电极的一面层叠有透明导电层，所述第一电极通过所述透明导电层与所述P型半导体进行电连接。
  6. 如权利要求3所述的显示面板，其中，所述N型半导体背向所述P型半导体的一侧设有N型金属电极，所述第二电极通过所述N型金属电极与所述N型半导体进行电连接。
  7. 如权利要求1所述的显示面板，其中，所述N型半导体的厚度大于2μm，所述P型半导体的厚度小于200nm。
  8. 一种显示面板的制作方法，其中，包括步骤：
    提供一形成有薄膜晶体管及有机层的基板，所述有机层层叠于所述薄膜晶 体管上，在所述有机层上形成开口槽；
    在所述开口槽内设一微型发光二极管，并将所述微型发光二极管与所述薄膜晶体管电连接，所述微型发光二极管包括P型半导体、与所述P型半导体相对设置的N型半导体及设于所述P型半导体与所述N型半导体之间的发光层，所述N型半导体设于所述P型半导体背向所述薄膜晶体管一侧，且所述N型半导体的厚度大于所述P型半导体；
    通过等离子体表面处理工艺处理所述N型半导体背向所述P型半导体的一面，使所述N型半导体背向所述P型半导体的一面粗化；
    在所述有机层及所述微型发光二极管上形成钝化层；
    在所述钝化层上形成第二电极，且所述第二电极的一端与所述N型半导体电连接。
  9. 如权利要求8所述的显示面板的制作方法，其中，所述等离子体表面处理工艺中的形成等离子体的气体为H 2、Ar、N 2或NH 3中任意一种或几种。
  10. 一种显示设备，其中，包括显示设备本体及显示面板，所述显示面板与所述显示设备本体电连接；所述显示面板包括薄膜晶体管，设于所述薄膜晶体管上并与所述薄膜晶体管电连接的微型发光二极管，所述微型发光二极管包括P型半导体、与所述P型半导体相对设置的N型半导体、设于所述P型半导体与所述N型半导体之间的发光层，所述N型半导体设于所述P型半导体背向所述薄膜晶体管的一侧，所述N型半导体的厚度大于所述P型半导体，所述N型半导体背向所述P型半导体的一面为粗糙面。
  11. 如权利要求10所述的显示设备，其中，所述显示面板还包括钝化层及有机层，所述有机层层叠于所述薄膜晶体管上，且所述有机层上设有开口槽，所述微型发光二极管收容所述开口槽内并与所述薄膜晶体管电连接；所述钝化层层叠并覆盖所述有机层及所述微型发光二极管。
  12. 如权利要求11所述的显示设备，其中，所述钝化层为有机或无机绝缘膜层。
  13. 如权利要求11所述的显示设备，其中，所述显示面板还包括第一电极及第二电极，所述第一电极层叠于所述薄膜晶体管上并位于所述有机层的开口槽位置，所述薄膜晶体管包括源漏极，所述第一电极一端与所述源漏极连接， 另一端与所述P型半导体进行电连接；所述第二电极层叠于所述钝化层上方，且所述第二电极的一端通过穿过所述钝化层与所述N型半导体进行电连接。
  14. 如权利要求12所述的显示设备，其中，所述P型半导体朝向所述第一电极的一面层叠有透明导电层，所述第一电极通过所述透明导电层与所述P型半导体进行电连接。
  15. 如权利要求12所述的显示设备，其中，所述N型半导体背向所述P型半导体的一侧设有N型金属电极，所述第二电极通过所述N型金属电极与所述N型半导体进行电连接。
  16. 如权利要求10所述的显示设备，其中，所述N型半导体的厚度大于2μm，所述P型半导体的厚度小于200nm。
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