WO2018232829A1 - 液晶显示面板及液晶显示设备 - Google Patents

液晶显示面板及液晶显示设备 Download PDF

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Publication number
WO2018232829A1
WO2018232829A1 PCT/CN2017/094412 CN2017094412W WO2018232829A1 WO 2018232829 A1 WO2018232829 A1 WO 2018232829A1 CN 2017094412 W CN2017094412 W CN 2017094412W WO 2018232829 A1 WO2018232829 A1 WO 2018232829A1
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WIPO (PCT)
Prior art keywords
transparent
scan line
liquid crystal
crystal display
light shielding
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PCT/CN2017/094412
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English (en)
French (fr)
Inventor
安立扬
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深圳市华星光电技术有限公司
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Priority to US15/570,323 priority Critical patent/US10416516B2/en
Publication of WO2018232829A1 publication Critical patent/WO2018232829A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a liquid crystal display panel and a liquid crystal display device.
  • the aperture ratio of the liquid crystal panel is an important specification of the liquid crystal panel, which directly determines the maximum brightness that the panel can achieve. Generally, the aperture ratio is maximized at the beginning of product design, because a large aperture ratio means high brightness. When the product specification (brightness specification) is determined, the high aperture ratio can allow the backlight brightness to be appropriately lowered, thereby reducing the power consumption and the target of the backlight. Material consumption, achieving cost reduction.
  • the invention provides an array substrate, which avoids the problem of lowering the aperture ratio of the pixel region and improves the utilization ratio of the backlight.
  • the liquid crystal display panel of the present invention comprises an array substrate, a color filter substrate, and a liquid crystal layer sandwiched between the array substrate and the color filter substrate, wherein the array substrate comprises a plurality of scan lines and a plurality of data lines insulated from the scan lines.
  • the scan line and the data line are arranged perpendicular to each other to define a plurality of pixels arranged in a matrix, each pixel comprising at least one thin film transistor and a pixel electrode connected to the thin film transistor, and the thin film transistor in each pixel Corresponding data lines and scan lines are electrically connected; and a spacer is present between adjacent pixel electrodes, the thin film transistor and the scan line are located in the spacer, and the pixels further include along the scan line a transparent trace of the peripheral setting, the voltage of the transparent trace input is The common voltage of the array substrate.
  • the projection of the edge of the transparent trace on the plane of the scan line coincides with the edge of the scan line; the projection of the transparent trace on the plane of the scan line does not overlap with the scan line .
  • the color film substrate is provided with a light shielding area corresponding to the space, the light shielding area includes a first side and a second side opposite to the first side, and the first side of the light shielding area is located in the transparent Between the line and one of the pixel electrodes or the edge of the transparent trace, the second side of the light-shielding area coincides with or is at a distance from the edge of another adjacent pixel electrode, and the light-shielding area covers the area The scan line and the transparent trace.
  • the light-receiving area includes a first side and a second side opposite to the first side, and the first side of the light-shielding area is located on the scan line. a second side of the light-shielding region adjacent to or at a distance from the pixel electrode, the light-shielding region covering the scan line and the thin film transistor, wherein the light-shielding region is provided with an opening corresponding to the transparent trace The transparent trace is exposed.
  • the pattern of the opening corresponding to the transparent trace on the light shielding area is the same as the transparent trace pattern, and the size of the opening is the same as or slightly smaller than the transparent trace. line.
  • the transparent traces are two, and in the spacer area, the scan line is located between the two transparent traces.
  • the two transparent traces are respectively disposed along two sides of the scan line, and the projections of the two transparent traces on the plane of the scan line do not overlap with the scan line, and the two The projections of the edges of the strips of transparent traces on the plane of the scan lines coincide with the sides of the scan lines, respectively.
  • the liquid crystal display panel includes a display area and an edge area.
  • the two transparent traces in the same interval area are not intersected in the display area, and the two transparent traces are connected in the edge area.
  • the transparent trace is located in the same layer as the pixel electrode and formed by the same process.
  • the liquid crystal display device of the present invention comprises a backlight module and the liquid crystal display panel, and the backlight module provides a light source for the liquid crystal display panel.
  • the liquid crystal display panel of the present invention is provided with a transparent trace on the interval of the TFT position corresponding to the light-shielding area of the array substrate to wrap the entire scan line of the spacer area and the scan line, but does not cover On the scan line; the edge of the light-shielding region (the first side and the second side) is contracted to the edge of the metal (sweep line), and the pixel electrode of the pixel on both sides of the spacer is not blocked, thereby effectively increasing the aperture ratio of the pixel.
  • Figure 1 is a side view of a liquid crystal display panel of the present invention
  • FIG. 2 is a schematic top plan view of an array substrate according to an embodiment of the present invention.
  • FIG. 3 is a partial schematic view of an array substrate according to an embodiment of the present invention.
  • the figure is a perspective view, and the periphery of the light shielding area is indicated by a broken line.
  • the present invention provides a liquid crystal display device and a liquid crystal display device.
  • the liquid crystal display device includes a backlight module and the liquid crystal display panel, and the backlight module provides the liquid crystal display panel. light source.
  • the liquid crystal display panel includes an array substrate 10, a color filter substrate 11, and a liquid crystal layer 12 sandwiched between the array substrate 10 and the color filter substrate 11.
  • the array substrate 10 and the color filter substrate 11 are provided with a plurality of display elements (not shown) for generating an electric field to drive the liquid crystal layer 12 for image display.
  • the array substrate 10 includes a plurality of scanning lines 152 and a plurality of data lines 151 insulated from the scanning lines.
  • the scanning lines 152 and the data lines 151 are arranged perpendicularly to each other to define a plurality of pixels 15 arranged in a matrix.
  • FIG. 2 a schematic diagram of a layout structure of the array substrate 10 is shown.
  • a plurality of scan lines 152 and data lines 151 are arranged in an insulating manner along the mutually perpendicular direction.
  • the pixels 15 are respectively disposed on the adjacent two. Between the data line 151 and the scan line 152, and respectively corresponding to one of the data lines And the scan line is electrically connected.
  • Each of the pixels 15 includes at least one thin film transistor 19 and a pixel electrode 20 connected to the thin film transistor 19.
  • the thin film transistor 19 in each pixel 15 is electrically connected and adjacent to the corresponding data line 151 and the scan line 152.
  • a spacer 16 exists between the pixel electrodes 20 of the two pixels 15, and the thin film transistor 19 and the scan line 152 are located in the spacer 16.
  • the gate of the thin film transistor 19 forms a surface of the substrate, the gate insulating layer covers the surface of the gate, and the active layer is formed on the surface of the gate insulating layer, wherein the gate insulating layer is formed for the source layer and the gate. Electrical insulation.
  • the source and the drain are spaced apart by a predetermined distance on the surface of the active layer, wherein the predetermined distance is a conductive channel between the source and the drain.
  • the substrate may be a transparent quartz substrate, a glass substrate or a plastic substrate.
  • the pixel electrode 20 is made of Indium-Tin-Oxide (ITO).
  • the array substrate is formed using a photolithography process.
  • the thin film transistor 19 is driven to be turned on by the scan signal provided by the gate from the scan line 152.
  • the data signal of the image to be displayed is transmitted from the data line to the source of the thin pixel, and then transmitted to the pixel electrode through the drain, and the pixel electrode 20
  • the electric field is generated by the reference signal voltage driven by the data signal, thereby achieving driving of the liquid crystal layer to perform image display on the data signal.
  • the color filter substrate 11 is provided with the light shielding region 17 facing the surface of the array substrate 10, specifically a black matrix.
  • each of the spacers 16 is provided with a transparent trace 18, and the spacer 16 is partially transparent.
  • a projection of an edge of the transparent trace 18 on a plane of the scan line 152 coincides with an edge of the scan line 152; a projection of the transparent trace 18 on a plane of the scan line 152 and the scan Lines 152 do not overlap.
  • Each of the spacers 16 corresponds to one pixel electrode, and the transparent trace 18 is disposed along a periphery of a scan line of the pixel 15 corresponding to the transparent trace, and the voltage input by the transparent trace is a common voltage of the array substrate. .
  • the thin film transistor 19 includes a source 191 connected to the data line 151, and a drain 192 connected to the pixel through a via provided in the spacer 16. Electrode 20.
  • the light shielding region 17 includes a first side 171 and a second side 172 opposite to the first side 171.
  • the thin film transistor 19 of each pixel and the connected scan line 152 are located in the spacer 16 corresponding to the pixel electrode 20; A transparent trace 18 in the spacer 16 corresponding to one pixel electrode 20 is disposed around the scan line 152 of the pixel 15 and does not cover the scan line 152.
  • the first side 171 of the light shielding area 17 is located between the transparent trace 18 and one of the pixel electrodes 20 or coincides with the edge of the transparent trace 20, and the second side 172 of the light shielding area 17 is different from the other side.
  • An edge of an adjacent pixel electrode 20 coincides or is separated by a distance, and the light shielding region 17 covers the scan line 152 and the transparent trace 18.
  • the first side 171 of the light shielding region 17 of the spacer 16 corresponding to the pixel 15 is located in the outer side of the transparent trace 18 facing the other pixel 15 adjacent thereto, and the other pixel 15 is a pixel corresponding to the spacer 16
  • the other pixel adjacent to the thin film transistor is not the other pixel adjacent to the pixel electrode of the pixel corresponding to the spacer 16.
  • the first side 171 of the light shielding region 17 covering the spacer 16 corresponding to the pixel electrode 20 is located outside the other pixel 15 adjacent to the transparent trace 18, and the pixel electrode of the other pixel Having a gap therebetween increases the transparency of the spacer, and the second side 172 is located at a position where the pixel electrode 20 of the pixel is connected to the spacer 16.
  • a first side of the light shielding region 17 is located at an edge of the scanning line 152, and a second side of the light shielding region 17 is adjacent to or at a distance from the pixel electrode 20, and the light shielding region covers the edge.
  • the scan line 152 and the thin film transistor 15 are provided with an opening corresponding to the transparent trace 18 to expose the transparent trace 18.
  • the pattern of the opening corresponding to the transparent trace 18 on the light-shielding region 17 is the same as the pattern of the transparent trace 18, and the size of the opening is the same as or slightly smaller than the size of the transparent trace 18.
  • each pixel 15 is disposed between two adjacent data lines 151 and two scanning lines 152, and the thin film transistors of each pixel 15 are electrically connected to one of the corresponding data lines 151 and the scanning lines 152, respectively.
  • the transparent traces 18 in each spacer 16 are two and the scan lines 152 in the spacers 16 are located between the two transparent traces 18. Located in the same bay 18, the two transparent traces 18 are disposed along the periphery of the scan line 152 (including the gate below the active layer), and the scan line 152 is surrounded and connected to the scan line 152 and is not covered.
  • the transparent trace 18 is formed in the same layer as the pixel electrode 20 and formed by the same material and the same process. Therefore, the manufacturing process step is not required, and the transparent trace 18 and the pixel electrode 20 are both doped. Indium tin oxide material is formed (ITO). Of course, the transparent trace 18 and the pixel electrode 20 may not be in the same layer.
  • the liquid crystal display panel includes a display area and an edge area (not shown).
  • the two transparent traces 18 in the same spacer 16 are not intersected in the display area, and the two transparent traces are located at the edge. The areas are connected. And the voltage input by the transparent trace 18 is a common voltage of the array substrate 10.
  • the transparent trace is a common potential, which is the same potential as the electrode on the side of the color filter substrate. Therefore, the electric field between the plates is 0, and the liquid crystal molecules do not rotate, which can effectively shield the potential signal of the scan line.
  • the effect of the display area, the liquid crystal above the scan line can be bound to the scan line Fang, to prevent it from affecting the display area, causing the dark state to display an abnormality.
  • the occlusion area does not need to cover the pixel electrode edge beyond the distance of 10-12 um of the scanning line as in the prior art, and is retracted to the scanning line. Occlusion of other non-display areas.
  • the liquid crystal display panel of the present invention is provided with a transparent trace on the interval between the position of the thin film transistor corresponding to the light-shielding region of the array substrate to wrap the entire scan line of the spacer and the scan line, but does not cover the scan line.
  • the edge of the light-shielding region (the first side and the second side) is contracted to the edge of the metal (sweep line), and the pixel electrodes on both sides of the spacer are not blocked, thereby effectively increasing the aperture ratio of the pixel. Since the transparent trace does not cover the scan line, the parasitic capacitance between the transparent trace and the scan line is small, and the load of the scan line is not increased, so that the dark state of the liquid crystal panel is not leaked.
  • the two transparent traces do not intersect within the panel, but are connected together at the periphery of the panel and give a common voltage signal. Therefore, when the transparent trace is short-circuited with the adjacent pixel electrode, it can be detected by the parity row pixel display.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
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Abstract

液晶显示面板，包括阵列基板（10）、彩膜基板（11）及夹持于阵列基板（10）与彩膜基板（11）的液晶层（12），阵列基板（10）包括数条扫描线（152）和与扫描线（152）绝缘的数条数据线（151），扫描线（152）与数据线（151）相互垂直排布限定多个呈矩阵排列的像素（15），每一个像素（15）至少包括一个薄膜晶体管（19）和与薄膜晶体管（19）连接的像素电极（20），每一像素（15）内的薄膜晶体管（19）与对应的数据线（151）以及扫描线（152）电性连接；且相邻像素电极（20）之间存在一间隔区（16），薄膜晶体管（19）和扫描线（152）位于间隔区（16），像素（15）还包括沿着扫描线（152）的外围设置的透明走线（18），透明走线（18）输入的电压为阵列基板（10）的公共电压。

Description

液晶显示面板及液晶显示设备
本发明要求2017年6月20日递交的发明名称为“液晶显示面板及液晶显示设备”的申请号201710471058.8的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种液晶显示面板及液晶显示设备。
背景技术
液晶面板中开口率(Aperture ratio)是液晶面板的一个重要规格，直接决定了面板所能达到的最大亮度。通常在产品设计初期尽量使开口率最大化，因为大的开口率意味着高亮度，在产品规格(亮度规格)确定时，高开口率可以允许背光亮度适当降低，从而减少背光的耗电及靶材消耗，实现成本降低。
因此增大开口率是液晶显示行业的一贯追求，这要求液晶从业者们优化设计，改良结构，提高各层别间设计的合理性，而且要在保证液晶面板暗态显示不漏光的情况下，尽量增大产品的开口率。
发明内容
本发明提供一种阵列基板，规避像素区域的开口率降低问题，提升背光利用率。
本发明所述液晶显示面板，包括阵列基板、彩膜基板及夹持于阵列基板与彩膜基板的液晶层，所述阵列基板包括数条扫描线和与扫描线绝缘的数条数据线，所述扫描线与所述数据线相互垂直排布限定多个呈矩阵排列的像素，每一个像素至少包括一个薄膜晶体管和与所述薄膜晶体管连接的像素电极，每一像素内的所述薄膜晶体管与对应的数据线以及扫描线电性连接；且相邻像素电极之间存在一间隔区，所述薄膜晶体管和所述扫描线位于所述间隔区，所述像素还包括沿着所述扫描线的外围设置的透明走线，所述透明走线输入的电压为所 述阵列基板的公共电压。
其中，所述透明走线的边缘在所述扫描线所在平面上的投影与所述扫描线的边缘重合；所述透明走线在所述扫描线所在平面上的投影与所述扫描线不重叠。
其中，所述彩膜基板上对应所述间隔区设有遮光区，所述遮光区包括第一边及与第一边相对的第二边，所述遮光区的第一边位于所述透明走线与一所述像素电极之间或与所述透明走线的边缘重合，所述遮光区的第二边与另一相邻所述像素电极的边缘重合或相距一定距离，所述遮光区覆盖所述扫描线和所述透明走线。
其中，所述彩膜基板上对应所述间隔区设有遮光区，所述遮光区包括第一边及与第一边相对的第二边，所述遮光区的第一边位于所述扫描线边缘，所述遮光区的第二边与所述像素电极邻接或相距一定距离，所述遮光区覆盖所述扫描线和所述薄膜晶体管，所述遮光区对应所述透明走线设有开口以露出所述透明走线。
其中，所述遮光区上对应所述透明走线开设的所述开口的图案与所述透明走线图案相同，所述开口的尺寸与所述透明走线的尺寸相同或略小于所述透明走线。
其中，其中所述透明走线为两条，在所述间隔区内，所述扫描线位于该两条透明走线之间。
其中，所述两条透明走线分别沿着所述扫描线的两侧设置，所述两条透明走线在所述扫描线所在平面上的投影与所述扫描线不重叠，且所述两条透明走线的边缘在所述扫描线所在平面上的投影分别与所述扫描线的两侧边重合。
其中，所述液晶显示面板包括显示区和边缘区，同一间隔区内的两条所述透明走线位于显示区内不相交，且该两条透明走线位于边缘区内相连接。
其中，所述透明走线与所述像素电极位于同一层并通过同一道工艺形成。
本发明所述的液晶显示设备，包括背光模组及所述的液晶显示面板，所述背光模组为所述液晶显示面板提供光源。
本发明所述的液晶显示面板在阵列基板的与遮光区对应的设置TFT位置的间隔区上设置透明走线来包裹间隔区的整条扫描线与扫描线连接，但不覆盖 在扫描线上；而将遮光区的边缘(第一边和第二边)内缩至金属(扫面线)的边缘，不遮挡间隔区两侧像素的像素电极，有效增加像素的开口率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明液晶显示面板的侧视图；
图2为本发明实施方式的阵列基板俯视结构示意图；
图3为本发明实施方式的阵列基板的局部示意图，本图属于透视图，遮光区外围用虚线表示。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1与图2，本发明提供一种液晶显示面板及液晶显示设备，所述液晶显示设备包括背光模组及所述的液晶显示面板，所述背光模组为所述液晶显示面板提供光源。液晶显示面板包括阵列基板10、彩膜基板11及夹持于阵列基板10与彩膜基板11的液晶层12。其中，阵列基板10、彩膜基板11上设置有多个显示元件(图未示)，所述多个显示元件用于产生电场驱动液晶层12进行图像显示。阵列基板10包括数条扫描线152与扫描线绝缘的数条数据线151，所述扫描线152与所述数据线151相互垂直排布限定多个呈矩阵排列的像素15。
如图2所示，所示阵列基板10的布局结构示意图，沿着相互垂直方向间隔且绝缘排布的多个扫描线152与数据线151，对应地，像素15分别设置于相邻的两条数据线151与扫描线152之间，且分别与对应的其中一条数据线以 及扫描线电性连接。每一像素15至少包括一个薄膜晶体管19和与所述薄膜晶体管19连接的像素电极20，每一像素15内的所述薄膜晶体管19与对应的数据线151以及扫描线152电性连接且相邻两个像素15的像素电极20之间存在一间隔区16，所述薄膜晶体管19和所述扫描线152位于所述间隔区16内。
其中，薄膜晶体管19的栅极形成基板的表面，栅极绝缘层覆盖于栅极表面，有源层形成于栅极绝缘层表面，其中，栅极绝缘层用于针对源极层与栅极形成电性绝缘。源极与漏极间隔预定距离形成于有源层表面，其中，所述预定距离即为源极和漏极之间的导电沟道。其中，基板有可能为透明的石英基板、玻璃基板或是塑胶基板。像素电极20采用氧化铟锡(Indium-Tin-Oxide，ITO)。阵列基板是利用光刻工艺形成。薄膜晶体管19通过栅极自扫描线152提供的扫描信号驱动下处于导通状态，待显示图像的数据信号自数据线传输至薄像素的源极，进而通过漏极传输至像素电极，像素电极20在数据信号驱动下配合参考电压产生电场，从而达成驱动液晶层对数据信号进行图像显示。彩膜基板11朝向所述阵列基板10的表面设有所述遮光区17，具体为黑矩阵。
如图3所示，进一步的，每一所述间隔区16内设有透明走线18，所述间隔区16部分透光。所述透明走线18的边缘在所述扫描线152所在平面上的投影与所述扫描线152的边缘重合；所述透明走线18在所述扫描线152所在平面上的投影与所述扫描线152不重叠。每一所述间隔区16对应一个像素电极，透明走线18沿着与该透明走线对应的像素15的扫描线的外围设置，所述透明走线输入的电压为所述阵列基板的公共电压。
具体的，所述薄膜晶体管19包括源极191和漏极192，所述源极191连接所述数据线151，所述漏极192通过设于所述间隔区16内的过孔连接所述像素电极20。所述遮光区17包括第一边171及与第一边171相对的第二边172，每一个像素的薄膜晶体管19及连接的扫描线152位于与该像素电极20对应的间隔区16内；每一个像素电极20对应的间隔区16内的透明走线18围绕该像素15的扫描线152设置且不覆盖扫描线152。并且所述遮光区17的第一边171位于所述透明走线18与一所述像素电极20之间或与所述透明走线20的边缘重合，所述遮光区17的第二边172与另一相邻所述像素电极20的边缘重合或相距一定距离，所述遮光区17覆盖所述扫描线152和所述透明走线18。遮盖 该像素15对应的间隔区16的遮光区17的第一边171位于该透明走线18朝向与其相邻的另一个像素15的外侧中，另一个像素15是与该间隔区16对应的像素的薄膜晶体管相邻的另一个像素，而不是与该间隔区16对应像素的像素电极相邻的另一个像素。也就是说遮盖该像素电极20对应的间隔区16的遮光区17的第一边171位于该透明走线18朝向与其相邻的另一个像素15的外侧，且与该另一个像素的像素电极之间具有间隙，就增大了间隔区的透明度，而第二边172位于该像素的像素电极20与间隔区16连接位置即可。
另一方式中，所述遮光区17的第一边位于所述扫描线152边缘，所述遮光区17的第二边与所述像素电极20邻接或相距一定距离，所述遮光区覆盖所述扫描线152和所述薄膜晶体管15，所述遮光区17对应所述透明走线18设有开口以露出所述透明走线18。所述遮光区17上对应所述透明走线18开设的所述开口的图案与所述透明走线18图案相同，所述开口的尺寸与所述透明走线18的尺寸相同或略小于所述透明走线18。
对应地，每一像素15设置于相邻的两条数据线151与两个条扫描线152之间，每一像素15的薄膜晶体管分别与对应的其中一条数据线151以及扫描线152电性连接。每一间隔区16内的透明走线18为两条并且该间隔区16内的扫描线152位于该两条透明走线18之间。位于同一间隔区内18，该两条透明走线18沿着所述扫描线152(包括有源层下方的栅极)外围设置，将扫描线152围绕并与扫描线152连接且不覆盖。其中，所述透明走线18与所述像素电极20位于同一层并通过相同的材料及同一道工艺形成，如此不需要增加制造工艺步骤，所述透明走线18与像素电极20均采用为掺锡氧化铟材料形成(ITO)。当然，所述透明走线18与所述像素电极20也可以不在同一层。
进一步的，所述液晶显示面板包括显示区和边缘区(图未示)，同一间隔区16内的两条所述透明走线18位于显示区内不相交，且该两条透明走线位于边缘区内相连接。并且所述透明走线18输入的电压为所述阵列基板10的公共电压。
原理分析：在显示面板显示时，透明走线为公共电位，与彩膜基板侧的电极同电位，所以此处板间电场为0，液晶分子不发生转动，可以有效屏蔽扫描线的电位信号变化对显示区域的影响，可将扫描线上方的液晶束缚在扫描线上 方，防止其影响显示区域，造成暗态显示异常，通过此设计的优化，遮挡区无需向现有技术那样超过扫描线10-12um的距离而覆盖了像素电极边缘，内缩至扫面线处遮挡其他非显示区即可。
本发明所述的液晶显示面板在阵列基板的与遮光区对应的设置薄膜晶体管位置的间隔区上设置透明走线来包裹间隔区的整条扫描线与扫描线连接，但不覆盖在扫描线上；而将遮光区的边缘(第一边和第二边)内缩至金属(扫面线)的边缘，不遮挡间隔区两侧的像素电极，有效增加像素的开口率。由于透明走线并不覆盖在扫描线上，所以透明走线与扫描线间的寄生电容较小，不会增大扫描线的负荷，所以同时保证液晶面板暗态显示不漏光。而且两条透明走线在面板内不相交，但在面板外围连接在一起，并给入公共电压信号。所以当此透明走线与相邻像素电极短接时可以通过奇偶行像素显示进行检测。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (18)

  1. 一种液晶显示面板，包括阵列基板、彩膜基板及夹持于阵列基板与彩膜基板的液晶层，所述阵列基板包括数条扫描线和与所述扫描线绝缘的数条数据线，所述扫描线与所述数据线相互垂直排布以限定多个呈矩阵排列的像素，每一个像素至少包括一个薄膜晶体管和与所述薄膜晶体管连接的像素电极，每一像素内的所述薄膜晶体管与对应的数据线以及扫描线电性连接；且相邻像素电极之间存在一间隔区，所述薄膜晶体管和所述扫描线位于所述间隔区，其中，
    所述像素还包括沿着所述扫描线的外围设置的透明走线，所述透明走线输入的电压为所述阵列基板的公共电压。
  2. 如权利要求1所述的液晶显示面板，其中，所述透明走线的边缘在所述扫描线所在平面上的投影与所述扫描线的边缘重合；所述透明走线在所述扫描线所在平面上的投影与所述扫描线不重叠。
  3. 如权利要求1所述的液晶显示面板，其中，所述彩膜基板上对应所述间隔区设有遮光区，所述遮光区包括第一边及与第一边相对的第二边，所述遮光区的第一边位于所述透明走线与一所述像素电极之间或与所述透明走线的边缘重合，所述遮光区的第二边与另一相邻所述像素电极的边缘重合或相距一定距离，所述遮光区覆盖所述扫描线和所述透明走线。
  4. 如权利要求1所述的液晶显示面板，其中，所述彩膜基板上对应所述间隔区设有遮光区，所述遮光区包括第一边及与第一边相对的第二边，所述遮光区的第一边位于所述扫描线边缘，所述遮光区的第二边与所述像素电极邻接或相距一定距离，所述遮光区覆盖所述扫描线和所述薄膜晶体管，所述遮光区对应所述透明走线设有开口以露出所述透明走线。
  5. 如权利要求4所述的液晶显示面板，其中，所述遮光区上对应所述透明走线开设的所述开口的图案与所述透明走线图案相同，所述开口的尺寸与所述透明走线的尺寸相同或略小于所述透明走线。
  6. 如权利要求1所述的液晶显示面板，其中所述透明走线为两条，在所述间隔区内，所述扫描线位于该两条透明走线之间。
  7. 如权利要求6所述的液晶显示面板，其中，所述两条透明走线分别沿 着所述扫描线的两侧设置，所述两条透明走线在所述扫描线所在平面上的投影与所述扫描线不重叠，且所述两条透明走线的边缘在所述扫描线所在平面上的投影分别与所述扫描线的两侧边重合。
  8. 如权利要求1所述的液晶显示面板，其中，所述液晶显示面板包括显示区和边缘区，同一间隔区内的两条所述透明走线位于显示区内不相交，且该两条透明走线位于边缘区内相连接。
  9. 如权利要求1所述的液晶显示面板，其中，所述透明走线与所述像素电极位于同一层并通过同一道工艺形成。
  10. 一种液晶显示设备，其中，包括背光模组及液晶显示面板，所述背光模组为所述液晶显示面板提供光源；所述液晶显示面板包括阵列基板、彩膜基板及夹持于阵列基板与彩膜基板的液晶层，所述阵列基板包括数条扫描线和与所述扫描线绝缘的数条数据线，所述扫描线与所述数据线相互垂直排布以限定多个呈矩阵排列的像素，每一个像素至少包括一个薄膜晶体管和与所述薄膜晶体管连接的像素电极，每一像素内的所述薄膜晶体管与对应的数据线以及扫描线电性连接；且相邻像素电极之间存在一间隔区，所述薄膜晶体管和所述扫描线位于所述间隔区，其中，
    所述像素还包括沿着所述扫描线的外围设置的透明走线，所述透明走线输入的电压为所述阵列基板的公共电压。
  11. 如权利要求10所述的液晶显示设备，其中，所述透明走线的边缘在所述扫描线所在平面上的投影与所述扫描线的边缘重合；所述透明走线在所述扫描线所在平面上的投影与所述扫描线不重叠。
  12. 如权利要求10所述的液晶显示设备，其中，所述彩膜基板上对应所述间隔区设有遮光区，所述遮光区包括第一边及与第一边相对的第二边，所述遮光区的第一边位于所述透明走线与一所述像素电极之间或与所述透明走线的边缘重合，所述遮光区的第二边与另一相邻所述像素电极的边缘重合或相距一定距离，所述遮光区覆盖所述扫描线和所述透明走线。
  13. 如权利要求10所述的液晶显示设备，其中，所述彩膜基板上对应所述间隔区设有遮光区，所述遮光区包括第一边及与第一边相对的第二边，所述遮光区的第一边位于所述扫描线边缘，所述遮光区的第二边与所述像素电极 邻接或相距一定距离，所述遮光区覆盖所述扫描线和所述薄膜晶体管，所述遮光区对应所述透明走线设有开口以露出所述透明走线。
  14. 如权利要求13所述的液晶显示设备，其中，所述遮光区上对应所述透明走线开设的所述开口的图案与所述透明走线图案相同，所述开口的尺寸与所述透明走线的尺寸相同或略小于所述透明走线。
  15. 如权利要求10所述的液晶显示设备，其中所述透明走线为两条，在所述间隔区内，所述扫描线位于该两条透明走线之间。
  16. 如权利要求15所述的液晶显示设备，其中，所述两条透明走线分别沿着所述扫描线的两侧设置，所述两条透明走线在所述扫描线所在平面上的投影与所述扫描线不重叠，且所述两条透明走线的边缘在所述扫描线所在平面上的投影分别与所述扫描线的两侧边重合。
  17. 如权利要求10所述的液晶显示设备，其中，所述液晶显示面板包括显示区和边缘区，同一间隔区内的两条所述透明走线位于显示区内不相交，且该两条透明走线位于边缘区内相连接。
  18. 如权利要求10所述的液晶显示设备，其中，所述透明走线与所述像素电极位于同一层并通过同一道工艺形成。
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