WO2018229594A1 - 撮像装置、及び電子機器 - Google Patents
撮像装置、及び電子機器 Download PDFInfo
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- WO2018229594A1 WO2018229594A1 PCT/IB2018/053999 IB2018053999W WO2018229594A1 WO 2018229594 A1 WO2018229594 A1 WO 2018229594A1 IB 2018053999 W IB2018053999 W IB 2018053999W WO 2018229594 A1 WO2018229594 A1 WO 2018229594A1
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Definitions
- One embodiment of the present invention relates to an imaging device and an electronic device.
- one embodiment of the present invention is not limited to the above technical field.
- the technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
- one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.
- a semiconductor device refers to an element, circuit, device, or the like that can function by utilizing semiconductor characteristics.
- a semiconductor device such as a transistor or a diode is a semiconductor device.
- the circuit including a semiconductor element is a semiconductor device.
- a device including a circuit including a semiconductor element is a semiconductor device.
- IoT Internet of things
- AI Artificial Intelligence
- Patent Document 1 discloses a technique for adding a calculation function to an imaging apparatus.
- An image pickup apparatus including a solid-state image pickup device such as a CMOS image sensor can easily take high-quality images due to technological development. In the next generation, it is required to mount more intelligent functions in the imaging apparatus.
- Advanced image processing is required to recognize objects from image data.
- various analysis processes for analyzing images such as filter processing and comparison calculation processing are used.
- the calculation amount increases according to the number of pixels to be processed, and the processing time increases according to the calculation amount.
- an in-vehicle image processing system has a problem that an increase in processing time affects safety.
- the image processing system has a problem that power consumption increases due to an increase in the amount of calculation.
- an object of one embodiment of the present invention is to provide an imaging device with a novel structure. Another object of one embodiment of the present invention is to provide an imaging device having a pooling processing function of a neural network. Another object of one embodiment of the present invention is to provide an imaging device with a novel structure that can reduce processing time by reducing the amount of calculation. Another object of one embodiment of the present invention is to provide an imaging device with a novel structure that can reduce power consumption.
- One embodiment of the present invention is an imaging device including a pixel region and a first circuit, and the pixel region includes a pooling module and an output circuit, and the pooling module includes a plurality of pooling circuits;
- a comparison module the pooling circuit includes a plurality of pixels and an arithmetic circuit, the comparison module includes a plurality of comparison circuits and a determination circuit, and the pixels are first converted by photoelectric conversion.
- the pixel has a function of generating a second signal by multiplying the first signal by an arbitrary magnification, and the pooling circuit calculates a plurality of second signals as an arithmetic circuit.
- the comparison module has a function of comparing a plurality of third signals, selecting the largest third signal, and outputting the selected signal to the determination circuit.
- the determination circuit determines the largest third signal.
- the first circuit has a function of generating a fourth signal by binarization, the first circuit controls the timing of outputting the fourth signal to the output circuit, and the pooling module performs a pooling process according to the number of pixels,
- the pooling module is an imaging device that outputs a fourth signal generated by the pooling process.
- the imaging device further includes a second circuit, a third circuit, a first wiring, a second wiring, and a third wiring
- the pixel includes the first circuit
- the arithmetic circuit includes a first transistor, a second transistor, and a third transistor, and the second circuit extends in the row direction through the first wiring.
- the third circuit is electrically connected to the plurality of pixels, and the third circuit is electrically connected to the plurality of pixels extending in the column direction via the second wiring, and the third wiring is connected to the first transistor.
- One of the source and the drain, the one of the source and the drain of the second transistor, and the one of the source and the drain of the third transistor are electrically connected, and the gate of the first transistor is connected to the first transistor The other of the source or drain and the gate of the second transistor And the gate of the third transistor and the first output terminal of the pixel included in the pooling circuit, and the third circuit has a function of outputting a selection signal to the second wiring,
- the second circuit has a function of setting an arbitrary magnification for the pixel through the first wiring, and the first transistor has the same channel length as the second transistor and the third transistor.
- the second transistor has a function of outputting a third signal obtained by adding a plurality of second signals because the channel width of the first transistor is the same, and the third transistor A function of outputting a fifth signal having a size obtained by dividing the size of the third signal by the number of pixels by making the channel width of one transistor the length obtained by dividing the channel width by the number of pixels of the pooling circuit.
- An imaging device is preferred.
- the comparison module includes a first comparison circuit, a second comparison circuit, and a current mirror circuit
- the first comparison circuit includes the fourth transistor to the ninth transistor, the first transistor, Input terminal, second input terminal, second output terminal, and fourth wiring, and the second output terminal of the first comparison circuit is connected to the second comparison circuit via the current mirror circuit.
- the first input terminal is electrically connected to the first input terminal.
- the first input terminal includes one of a source and a drain of the fifth transistor, one of a source and a drain of the seventh transistor, and a gate of the fourth transistor.
- the second input terminal has one of the source or the drain of the eighth transistor and the source of the sixth transistor or Do One of the transistors, the gate of the seventh transistor, the gate of the eighth transistor, and the gate of the ninth transistor, and the second output terminal is the source or drain of the fourth transistor.
- the fourth transistor to the ninth transistor have the same channel length, and the channel of the fourth transistor
- the width is preferably the same as the channel width of the fifth transistor, the channel width of the sixth transistor is preferably twice the channel width of the fifth transistor, and the fourth to sixth transistors.
- the channel width of the ninth transistor is the same as the channel width of the eighth transistor.
- the channel width of the seventh transistor is preferably twice the channel width of the eighth transistor, and the seventh to ninth transistors form a second current mirror circuit, and A sixth signal is supplied to the first input terminal of the comparison circuit, a seventh signal is supplied to the second input terminal of the first comparison circuit, and a second signal of the first comparison circuit is supplied.
- the output terminal outputs the larger signal of the sixth signal or the seventh signal as the eighth signal, the eighth signal is given to the first input terminal of the second comparison circuit,
- the second input terminal of the second comparison circuit is supplied with a ninth signal, and the second output terminal of the second comparison circuit receives a signal that is larger of the eighth signal or the ninth signal than the second signal.
- 10 signal is output to the determination circuit, and the determination circuit determines the 10th signal and binarizes it.
- the imaging device has a function of generating a fourth signal
- the first circuit has a function of controlling the timing of outputting the fourth signal to the output circuit.
- the plurality of pixels be arranged in a matrix and have an area that is shielded from light between adjacent pixels.
- the pixel further includes a photoelectric conversion element, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a first capacitor element.
- One electrode of the element is electrically connected to one of a source and a drain of the tenth transistor, and the other of the source and the drain of the tenth transistor is electrically connected to one of the source and the drain of the eleventh transistor.
- One of the source and the drain of the eleventh transistor is electrically connected to the gate of the twelfth transistor, the gate of the twelfth transistor is electrically connected to one electrode of the first capacitor, One of a source and a drain of the twelfth transistor is electrically connected to the first output terminal, and the other electrode of the first capacitor is The one of the source and the drain of the thirteenth transistor is electrically connected, the other of the source and the drain of the thirteenth transistor is electrically connected to the first wiring, and the gate of the thirteenth transistor is connected to the second An imaging device in which the tenth transistor and the twelfth transistor have metal oxide in a channel formation region is preferably connected.
- an imaging device in which the metal oxide includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) is preferable.
- the photoelectric conversion element is preferably an imaging device having selenium or a compound containing selenium.
- one embodiment of the present invention can provide an imaging device with a novel structure.
- one embodiment of the present invention can provide an imaging device having a pooling processing function of a neural network.
- an imaging device with a novel structure that can reduce power consumption can be provided.
- the effects of one embodiment of the present invention are not limited to the effects listed above.
- the effects listed above do not preclude the existence of other effects.
- the other effects are effects not mentioned in this item described in the following description. Effects not mentioned in this item can be derived from the description of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions.
- one embodiment of the present invention has at least one of the above effects and / or other effects. Therefore, one embodiment of the present invention may not have the above-described effects depending on circumstances.
- FIG. 11 is a block diagram illustrating an imaging device.
- FIG. 11 is a block diagram illustrating an imaging device.
- FIG. 4A is a block diagram illustrating an imaging device.
- FIG. 10 is a circuit diagram illustrating a pixel.
- FIG. 4A is a block diagram illustrating an imaging device.
- B A timing chart illustrating the operation of the imaging device.
- FIG. 11 is a block diagram illustrating an imaging device.
- FIG. 10 is a circuit diagram illustrating a pixel.
- 3A and 3B illustrate a structure of a pixel of an imaging device.
- 3A and 3B illustrate a structure of a pixel of an imaging device.
- 3A and 3B illustrate a structure of a pixel of an imaging device.
- FIG. 3A and 3B illustrate a structure of a pixel of an imaging device.
- FIG. 5A illustrates a structure of an imaging device.
- FIG. 4B is a cross-sectional view illustrating a structure of an imaging device.
- 3A and 3B illustrate a structure of a pixel of an imaging device.
- 3A and 3B illustrate a structure of a pixel of an imaging device.
- FIG. 9 illustrates a configuration example of an electronic device.
- the imaging device 10 includes a pixel region, a driver 11, a driver 12, a driver 13, a plurality of wirings 111, a plurality of wirings 112 (not shown), and a plurality of wirings 113a (not shown).
- the pixel area has a plurality of pooling modules 200, a plurality of analog-digital conversion circuits 250, and an output circuit 251.
- the pooling module 200 includes a plurality of pooling circuits 210 and a comparison module 220.
- the pooling circuit 210 includes a plurality of pixels 100 and an arithmetic circuit 212 (not shown).
- the comparison module 220 includes a plurality of comparison circuits 230 (not shown) and a determination circuit 221 (not shown).
- the pixel 100 can acquire a first signal by converting light into an electrical signal, and the pixel 100 can multiply the first signal by an arbitrary magnification to generate a second signal. Can do.
- the first signal and the second signal are output as currents.
- the arbitrary magnification indicates the value of weight data used for the pooling processing of the neural network.
- the pooling circuit 210 can add a plurality of second signals by the arithmetic circuit 212 to generate a third signal. Furthermore, the arithmetic circuit 212 can average the plurality of second signals to generate the fifth signal.
- the comparison module 220 can compare a plurality of third signals, select the largest third signal, and output it to the determination circuit 221.
- the determination circuit 221 can determine and binarize the largest third signal to generate a fourth signal.
- the pooling module 200 can perform a pooling process according to the number of pixels that the pooling module 200 has. That is, the pooling module 200 can output the fourth signal generated by performing the pooling process on the first signal acquired from the plurality of pixels included in the pooling module 200.
- the driver 11 can control the timing of outputting the fourth signal to the output circuit 251 by the selection signal given to the wiring 111.
- the output circuit 251 can output a fourth signal to the neural network that controls the imaging device 10.
- the first data is pooled by the imaging device 10 to the neural network, and the data features are input as extracted data. Therefore, since the neural network only needs to process the extracted data features, the amount of data to be processed can be reduced. Therefore, the data transfer time from the image sensor to the neural network can be shortened, and the calculation amount of the neural network can be further reduced. By reducing the calculation amount of the neural network, the power consumption can be reduced.
- the pooling module 200 preferably has a plurality of pooling circuits 210.
- FIG. 1 shows an example in which the pooling module 200 includes four pooling circuits 210.
- the number of pooling circuits 210 included in the pooling module 200 can be 1 or more and n or less (n is a natural number of 2 or more).
- n is a natural number of 2 or more.
- the pooling circuit 210 includes a plurality of pixels 100, an arithmetic circuit 212, a switch 203, a switch 204, a plurality of wirings 112, a plurality of wirings 113a, a wiring 114, a wiring 115, and a wiring 210a.
- the pixel 100 includes a first output terminal
- the arithmetic circuit 212 includes a transistor 212a, a transistor 212b, and a transistor 212c. Note that an example in which the pooling circuit 210 illustrated in FIG. 2 includes four pixels will be described.
- the driver 12 is electrically connected to the plurality of pixels 100 extending in the row direction via the wiring 112, and the driver 13 is electrically connected to the plurality of pixels 100 extending in the column direction via the wiring 113a. Has been.
- the wiring 114 is electrically connected to one of a source and a drain of the transistor 212a, one of a source and a drain of the transistor 212b, and one of a source and a drain of the transistor 212c.
- the gate of the transistor 212a is electrically connected to the other of the source and the drain of the transistor 212a, the gate of the transistor 212b, and the gate of the transistor 212c.
- the gate of the transistor 212 a is further electrically connected to the output terminals 100 a of the plurality of pixels 100 included in the pooling circuit 210.
- the other of the source and the drain of the transistor 212b is electrically connected to one of the electrodes of the switch 203, and the other of the source and the drain of the transistor 212c is electrically connected to one of the electrodes of the switch 204.
- the other electrode of the switch 203 is electrically connected to the other of the electrodes of the switch 204 and the comparison module 220 through the wiring 210a.
- the driver 13 can output a selection signal to the wiring 113a.
- the driver 12 can set an arbitrary magnification as weight data to the pixel 100 via the wiring 112.
- the transistor 212a has the same channel length as the transistor 212b and the transistor 212c, and the transistor 212b has the same channel width as the transistor 212a, so that a third signal obtained by adding a plurality of second signals is output. Can do.
- the transistor 212c has a channel width obtained by dividing the channel width of the transistor 212a by the number of the pixels 100 included in the pooling circuit 210, so that a fifth signal having a size obtained by dividing the magnitude of the third signal by the number of pixels 100 is provided. A signal can be output.
- the third signal and the fifth signal are controlled by current.
- the switch 203 and the switch 204 are preferably in a complementary relationship.
- FIG. 2 shows an example in which a p-channel transistor is applied to the switch 203 and an n-channel transistor is applied to the switch 204.
- the pooling circuit 210 can output a third signal to the comparison module 220 via the wiring 210a when the first switching signal is “L”.
- the pooling circuit 210 can output the fifth signal to the comparison module 220 via the wiring 210a when the first switching signal is “H”.
- the imaging apparatus 10 having the pooling module 200 specializes in detecting features from the imaging data, thereby reducing the amount of computation and shortening the processing time.
- FIG. 2 shows an example in which different weight data is given to each pixel 100 included in the pooling circuit 210.
- the same weight data may be given using the pooling circuit 210 or the pooling module 200 as one unit. Therefore, the wiring 112 and the wiring 113a may be electrically connected using the pooling circuit 210 or the pooling module 200 as one unit.
- the imaging device 10 can increase the degree of integration by reducing the wiring 112 and the wiring 113a.
- the comparison module 220 includes a plurality of comparison circuits 230, a plurality of current mirror circuits 222, and a determination circuit 221.
- Each comparison circuit 230 has an input terminal 231a, an input terminal 231b, and an output terminal 231c.
- the determination circuit 221 includes an input terminal 221a, an input terminal 221b, and an output terminal 221c.
- the current mirror circuit 222 has an input terminal 224a and an output terminal 224b.
- FIG. 3A illustrates an example in which output signals from the four pooling circuits 210 are given to the comparison module 220.
- the comparison module 220 is electrically connected to four different pooling circuits 210 via wiring 210a (i, j) to wiring 210a (i + 1, j + 1). It is preferable to provide a number of comparison circuits 230 corresponding to the number of input signals.
- the comparison module 220 includes a comparison circuit 230a, a comparison circuit 230b, a comparison circuit 230c, a current mirror circuit 222a, a current mirror circuit 222b, and a determination circuit 221.
- the wiring 210a (i, j) is electrically connected to the input terminal 231a of the comparison circuit 230a
- the wiring 210a (i + 1, j) is electrically connected to the input terminal 231b
- the output terminal 231c is connected to the output terminal 231c.
- the input terminal 224a of the current mirror circuit 222a is electrically connected
- the input terminal 231a of the comparison circuit 230b is electrically connected to the output terminal 224b of the current mirror circuit 222a.
- the wiring 210a (i, j + 1) is electrically connected to the input terminal 231b of the comparison circuit 230b, the input terminal 224a of the current mirror circuit 222b is electrically connected to the output terminal 231c, and the current mirror circuit 222b The output terminal 224b is electrically connected to the input terminal 231a of the comparison circuit 230c.
- a wiring 210a (i + 1, j + 1) is electrically connected to the input terminal 231b of the comparison circuit 230c, and an input terminal 221a of the determination circuit 221 is electrically connected to the output terminal 231c.
- the current mirror circuit 222 includes a transistor 223a and a transistor 223b.
- the transistors 223a and 223b are preferably p-channel transistors.
- One of a source and a drain of the transistor 223a is electrically connected to one of a source and a drain of the transistor 223b and the wiring 114.
- the gate of the transistor 223a is electrically connected to the other of the source and the drain of the transistor 223a and the gate of the transistor 223b.
- the signal a1 is given to the input terminal 231a of the comparison circuit 230a through the wiring 210a (i, j).
- a signal a2 is supplied to the input terminal 231b through the wiring 210a (i + 1, j).
- a larger signal of the signal a1 or the signal a2 is output as the signal a3, and is given to the input terminal 224a of the current mirror circuit 222a.
- the signal a3 becomes a signal b1 having the same magnitude as the signal a3 through the current mirror circuit 222a, and is given to the output terminal 224b of the current mirror circuit. Therefore, the signal b1 having the same magnitude as the signal a3 is supplied to the input terminal 231a of the comparison circuit 230b.
- the signal a3 and the signal b1 have different signal directions.
- the signal b2 is given to the input terminal 231b of the comparison circuit 230b via the wiring 210a (i, j + 1), and a signal larger than the signal b1 or the signal b2 is output as the signal b3 from the output terminal 231c.
- a signal c1 is applied to the input terminal 231a of the comparison circuit 230c through the current mirror circuit 222b, a signal c2 is applied to the input terminal 231b through the wiring 210a (i + 1, j + 1), and the output terminal 231c
- the larger of the signal c1 and the signal c2 is output to the determination circuit 221 as the signal c3.
- the signals a1, a2, a3, b1, b2, b3, c1, c2, and c3 are all preferably analog signals.
- the determination circuit 221 can determine the signal c3 input to the input terminal 221a, binarize it, generate a fourth signal, and output the fourth signal to the output terminal 221c.
- the timing at which the fourth signal is output to the output circuit 251 through the wiring 211 can be controlled by the selection signal given to the wiring 111 by the driver 11.
- the comparison circuit 230 includes transistors 241 to 246, an input terminal 231a, an input terminal 231b, an output terminal 231c, and a wiring 232.
- the input terminal 231a is electrically connected to one of a source and a drain of the transistor 242, one of a source and a drain of the transistor 244, a gate of the transistor 241, a gate of the transistor 242, and a gate of the transistor 243.
- the input terminal 231b is electrically connected to one of a source and a drain of the transistor 245, one of a source and a drain of the transistor 243, a gate of the transistor 244, a gate of the transistor 245, and a gate of the transistor 246.
- the output terminal 231 c is electrically connected to one of the source and the drain of the transistor 241 and one of the source and the drain of the transistor 246.
- the wiring 232 is electrically connected to the other of the source and the drain of the transistors 241 to 246.
- transistors 241 to 246 have the same channel length.
- the channel width of the transistor 241 is preferably the same as the channel width of the transistor 242, and the channel width of the transistor 243 is preferably twice the channel width of the transistor 242.
- the transistors 241 to 243 form a first current mirror circuit.
- the channel width of the transistor 246 is preferably the same as the channel width of the transistor 245, and the channel width of the transistor 244 is preferably twice the channel width of the transistor 245.
- the transistors 244 to 246 form a second current mirror circuit.
- a current is supplied as an analog signal to the input terminal 231a and the input terminal 231b, and a current is sucked in as an analog signal from the output terminal 231c.
- the signal supplied to the input terminal 231b is sucked into the transistor 243.
- the signal supplied to the input terminal 231a is sucked into the transistor 244. Therefore, the output terminal 231c outputs a signal having the same magnitude as the larger one of the signals input to the input terminal 231a or the input terminal 231b by either the first current mirror circuit or the second current mirror circuit. Can be inhaled.
- the output terminal 231 c absorbs a signal having a combined magnitude of the transistor 241 and the transistor 246. Therefore, the output terminal 231c can absorb a signal having the same magnitude as the input terminal 231a and the input terminal 231b.
- the wiring 232 preferably has a low potential that can absorb a signal.
- the largest signal among the signals a1, a2, b2, and c2 given to the comparison module 220 is given as the signal c3 to the determination circuit 221 in FIG.
- the determination circuit 221 can determine the signal c3 and binarize it to generate a fourth signal.
- the driver 11 can supply a selection signal to the determination circuit 221 via the wiring 111 and cause the output circuit 251 to output the determination result.
- the pixel 100 includes a photoelectric conversion element 101, a transistor 102, a transistor 103, a capacitor 104, a transistor 105, a transistor 106, and an output terminal 100a.
- the pixel 100 is electrically connected to the wiring 112, the wiring 113a, the wiring 113b, the wiring 117, the wiring 118, and the wiring 119.
- One electrode of the photoelectric conversion element 101 is electrically connected to one of a source and a drain of the transistor 102.
- the other of the source and the drain of the transistor 102 is electrically connected to one of the source and the drain of the transistor 103, the gate of the transistor 105, and one electrode of the capacitor 104.
- One of a source and a drain of the transistor 105 is electrically connected to the output terminal 100 a, and the other electrode of the capacitor 104 is electrically connected to one of the source and the drain of the transistor 106.
- the other of the source and the drain of the transistor 106 is electrically connected to the wiring 112, and the gate of the transistor 106 is electrically connected to the wiring 113a.
- a gate of the transistor 102 is electrically connected to the wiring 113b.
- a gate of the transistor 103 is electrically connected to the wiring 113c.
- the other of the source and the drain of the transistor 103 is electrically connected to the wiring 118.
- the other electrode of the photoelectric conversion element 101 is electrically connected to the wiring 117.
- the other of the source and the drain of the transistor 105 is electrically connected to the wiring 119.
- the node FN is formed by being connected to the other of the source and the drain of the transistor 102, one of the source and the drain of the transistor 103, the gate of the transistor 105, and one electrode of the capacitor 104. Note that a structure in which the capacitor 104 is not provided may be employed.
- the transistor 103 can be turned on by a signal supplied to the wiring 113c. Therefore, the node FN can be initialized by the reset potential applied to the wiring 118.
- the transistor 102 can be turned on by a signal supplied to the wiring 113b. Therefore, the photoelectric conversion element 101 can update the data of the node FN with the imaging data subjected to photoelectric conversion through the transistor 102.
- the transistor 102 can be turned off by a signal supplied to the wiring 113b.
- the node FN can hold imaging data when the transistor 102 is turned off. Therefore, the first signal indicates a current that flows when imaging data is supplied to the gate of the transistor 105.
- FIG. 4 shows an example in which an n-channel transistor is applied to the transistor 105, but a p-channel transistor may be applied. Note that in the case where the transistor 105 is an n-channel transistor, the potential applied to the wiring 119 is preferably a low potential. Even in the case where the transistor 105 is a p-channel transistor, the potential applied to the wiring 119 is low. Is preferred.
- the transistor 106 can be turned on by a signal supplied to the wiring 113a. Weight data can be supplied to the capacitor 104 from the wiring 112 through the transistor 106.
- the node FN is preferably a floating node when the transistor 102 and the transistor 103 are off. Therefore, it is preferable to use transistors with low off-state current as the transistors 102 and 103.
- a transistor including a metal oxide (OS transistor) in a channel formation region is preferably used as the transistor with low off-state current.
- the OS transistor will be described in detail in Embodiment Mode 2.
- Weighting data is added to the imaging data held in the node FN via the capacitive element 104. That is, a data voltage obtained by adding weight data to imaging data is applied to the gate of the transistor 105. Therefore, the transistor 105 can be multiplied by an arbitrary weight data magnification using the conductance of the transistor 105. Therefore, the second signal indicates a current that flows when a data voltage obtained by adding weight data to imaging data is supplied to the gate of the transistor 105.
- FIG. 5 illustrates an example of an operation method of the pooling module 200.
- the pooling module 200 includes four pooling circuits 210 and the comparison module 220 will be described in order to simplify the description.
- the example in which the pooling circuit 210 has four pixels is shown.
- the number of pooling modules 200 included in the imaging apparatus 10 is not limited.
- FIG. 5B shows an example of an operation method of the pooling module 200 of FIG. 5A with a timing chart. Although the timing chart shown in FIG. 5B is not shown in the drawing, an L signal is given to the wiring 115, and the pooling circuit 210 adds the first signals of the plurality of pixels 100. Is shown.
- the transistor 103 included in each pixel 100 is turned on by applying an H signal to the wiring 113c. Therefore, the node FN is reset with the potential applied to the wiring 118. Further, a selection signal is given to the wiring 113 a and an initial value Res of weight data is given via the wiring 112.
- each pixel 100 performs photoelectric conversion by the photoelectric conversion element 101, and updates the node FN with the imaging data.
- an L signal is given to the wiring 113b and the imaging data of the node FN is determined. Further, a selection signal is supplied to the wiring 113a (1), and the pixels 100 (1), 100 (2), 100 (5), and 100 (6) are connected through the wirings 112 (1) to 112 (4). ) Weight data is set.
- a selection signal is supplied to the wiring 113a (2), and the pixel 100 (3), the pixel 100 (4), the pixel 100 (7), and the pixel 100 ( 8)
- the weight data is set.
- a selection signal is supplied to the wiring 113a (3), and the pixel 100 (9), the pixel 100 (10), the pixel 100 (13), and the pixel 100 (through the wirings 112 (1) to 112 (4) are connected. 14) weight data is set. Further, the pooling circuit 210 (1, 1) outputs a data signal a1 obtained by adding weight data to the imaging data to the wiring 210a (1, 1). Further, the pooling circuit 210 (2, 1) outputs a signal a2 obtained by adding weight data to the imaging data to the wiring 210a (2, 1).
- a selection signal is supplied to the wiring 113a (4), and the pixel 100 (11), the pixel 100 (12), the pixel 100 (15), and the pixel 100 (through the wirings 112 (1) to 112 (4) are connected. 16) Weight data is set.
- the pooling circuit 210 (1,1) outputs the data signal b2 obtained by adding the weight data to the imaging data to the wiring 210a (1,2). Further, the pooling circuit 210 (2, 2) outputs a signal c2 obtained by adding weight data to the imaging data to the wiring 210a (2, 2).
- the comparison module 220 detects the maximum signal from a1, a2, b2, and c2.
- the determination circuit 221 included in the comparison module 220 determines the detected maximum signal, binarizes it, and outputs the digital signal out to the wiring 211.
- the digital signal out is supplied to the output circuit 251.
- the output circuit 251 combines the digital signals out so as to be easily handled by the neural network, and outputs them as digital data having an arbitrary data width.
- FIG. 6 illustrates an example of the pooling circuit 210 having a configuration different from that of FIG. 2 using a block diagram. 6 is different from FIG. 2 in that the pooling circuit 210 includes a plurality of wirings 113d, a wiring 211a, and a wiring 211b, and the pixel 100 includes an output terminal 100b.
- the wiring 113d is electrically connected to a plurality of pixels extending in the column direction.
- the wiring 211a is electrically connected to the output terminal 100b of the pixel 100 extending in the row direction.
- Imaging data is output to the wiring 211a or the wiring 211b.
- the imaging data is output to the analog / digital conversion circuit 250 through the wiring 211a and the wiring 211b.
- FIG. 7 illustrates an example of the pixel 100 having a configuration different from that in FIG. 7 is different from FIG. 4 in that the transistor 107 and the transistor 108 are included.
- the gate of the transistor 107 is electrically connected to the node FN.
- One of the source and the drain of the transistor 107 is electrically connected to one of the source and the drain of the transistor 108.
- the other of the source and the drain of the transistor 108 is electrically connected to the output terminal 100b.
- a gate of the transistor 108 is electrically connected to the wiring 113d.
- the other of the source and the drain of the transistor 107 is electrically connected to the wiring 119.
- the transistor 107 can pass a current corresponding to the potential of the imaging data held in the node FN.
- the transistor 108 can output imaging data to the output terminal 100b by a selection signal supplied to the wiring 113d. Note that when weight data is set in the capacitor 104, the weight data is added to the imaging data, and a multiplication result corresponding to the conductance of the transistor 105 is output.
- the imaging apparatus 10 can easily perform the pooling process by including the pooling module 200. Therefore, it is possible to reduce power consumption by reducing the amount of data transferred to the neural network and further reducing the amount of calculation.
- FIG. 8A illustrates the structure of a pixel including the above pixel circuit.
- a pixel illustrated in FIG. 8A is an example having a stacked structure of a layer 61 and a layer 62.
- the layer 61 includes the photoelectric conversion element 101.
- the photoelectric conversion element 101 can be a stack of a layer 65a, a layer 65b, and a layer 65c as illustrated in FIG.
- a photoelectric conversion element 101 illustrated in FIG. 8C is a pn junction photodiode, and for example, a p + type semiconductor can be used for the layer 65a, an n type semiconductor can be used for the layer 65b, and an n + type semiconductor can be used for the layer 65c.
- a p + type semiconductor may be used for the layer 65a
- a p type semiconductor may be used for the layer 65b
- a p + type semiconductor may be used for the layer 65c.
- a pin junction photodiode in which the layer 65b is an i-type semiconductor may be used.
- the pn junction photodiode or the pin junction photodiode can be formed using single crystal silicon. Further, the pin junction photodiode can be formed using a thin film such as amorphous silicon, microcrystalline silicon, or polycrystalline silicon.
- the photoelectric conversion element 101 included in the layer 61 may be a stack of a layer 66a, a layer 66b, a layer 66c, and a layer 66d as illustrated in FIG.
- a photoelectric conversion element 101 illustrated in FIG. 8D is an example of an avalanche photodiode, and the layers 66a and 66d correspond to electrodes, and the layers 66b and 66c correspond to photoelectric conversion portions.
- the layer 66a is preferably a low-resistance metal layer or the like.
- a low-resistance metal layer or the like aluminum, titanium, tungsten, tantalum, silver, or a stacked layer thereof can be used.
- the layer 66d is preferably a conductive layer having a high light-transmitting property with respect to visible light (Light).
- indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, graphene, or the like can be used. Note that the layer 66d may be omitted.
- the layers 66b and 66c of the photoelectric conversion part can be configured as a pn junction type photodiode using a selenium-based material as a photoelectric conversion layer, for example.
- the layer 66b is preferably formed using a selenium-based material that is a p-type semiconductor, and the layer 66c is preferably formed using gallium oxide that is an n-type semiconductor.
- a photoelectric conversion element using a selenium material has a high external quantum efficiency with respect to visible light.
- amplification of electrons with respect to the amount of incident light can be increased by using avalanche multiplication.
- the selenium-based material has a high light absorption coefficient, it has production advantages such that the photoelectric conversion layer can be formed as a thin film.
- a thin film of a selenium-based material can be formed using a vacuum evaporation method, a sputtering method, or the like.
- Selenium-based materials include crystalline selenium such as single crystal selenium and polycrystalline selenium, amorphous selenium, copper, indium, selenium compound (CIS), or copper, indium, gallium, selenium compound (CIGS), etc. Can be used.
- the n-type semiconductor is preferably formed of a material having a wide band gap and a light-transmitting property with respect to visible light.
- a material having a wide band gap and a light-transmitting property with respect to visible light For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or an oxide in which they are mixed can be used. These materials also have a function as a hole injection blocking layer, and can reduce the dark current.
- a silicon substrate can be used as the layer 62 shown in FIG. 8A.
- the silicon substrate is provided with an Si transistor and the like, and in addition to the above-described pixel circuit, a circuit for driving the pixel circuit, an image signal reading circuit, an image processing circuit, and the like can be provided.
- the pixel may have a stacked structure of a layer 61, a layer 63, and a layer 62 as shown in FIG.
- the layer 63 can include an OS transistor (for example, the transistors 102 and 103 of the pixel circuit).
- the layer 62 preferably includes Si transistors (for example, the transistors 107 and 108 of the pixel circuit).
- the layer 62 may be used as a supporting substrate, and the pixel 100 and the peripheral circuit may be provided in the layer 61 and the layer 63.
- ⁇ OS transistor> As a semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used.
- a typical example is an oxide semiconductor containing indium.
- a CAC-OS described later can be used.
- the semiconductor layer is represented by an In-M-Zn-based oxide containing, for example, indium, zinc, and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). It can be a membrane.
- M a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium.
- the atomic ratio of the metal elements of the sputtering target used for forming the In-M-Zn oxide is In ⁇ M, Zn It is preferable to satisfy ⁇ M.
- the atomic ratio of the semiconductor layer to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target.
- the semiconductor layer an oxide semiconductor with low carrier density is used.
- the semiconductor layer has a carrier density of 1 ⁇ 10 17 / cm 3 or less, preferably 1 ⁇ 10 15 / cm 3 or less, more preferably 1 ⁇ 10 13 / cm 3 or less, more preferably 1 ⁇ 10 11 / cm 3. 3 or less, more preferably less than 1 ⁇ 10 10 / cm 3 , and an oxide semiconductor having a carrier density of 1 ⁇ 10 ⁇ 9 / cm 3 or more can be used.
- Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Accordingly, it can be said that the oxide semiconductor has stable characteristics because the impurity concentration is low and the defect state density is low.
- the composition is not limited thereto, and a transistor having an appropriate composition may be used depending on required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, and the like) of the transistor.
- the semiconductor layer in order to obtain the required semiconductor characteristics of the transistor, it is preferable that the semiconductor layer have appropriate carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like. .
- the concentration of silicon or carbon in the semiconductor layer is 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
- the concentration of alkali metal or alkaline earth metal (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
- the nitrogen concentration (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is preferably 5 ⁇ 10 18 atoms / cm 3 or less.
- Non-single-crystal structures include, for example, CAAC-OS (C-Axis Crystalline Oxide Semiconductor, C-Axis Aligned and A-B-Plane Ancillary Crystal Oxide Crystal Structure, C-Axis Crystalline Oxide Crystal Structure, C-Axis Aligned Crystalline Crystal Structure, Includes a microcrystalline structure or an amorphous structure.
- CAAC-OS C-Axis Crystalline Oxide Semiconductor, C-Axis Aligned and A-B-Plane Ancillary Crystal Oxide Crystal Structure
- C-Axis Crystalline Oxide Crystal Structure C-Axis Aligned Crystalline Crystal Structure
- the amorphous structure has the highest density of defect states
- the CAAC-OS has the lowest density of defect states.
- An amorphous oxide semiconductor film has, for example, disordered atomic arrangement and no crystal component.
- the oxide film having an amorphous structure has, for example, a completely amorphous structure and does not have a crystal part.
- the semiconductor layer may be a mixed film including two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region.
- the mixed film may have a single-layer structure or a stacked structure including any two or more of the above-described regions.
- CAC Cloud-Aligned Composite
- the CAC-OS is one structure of a material in which elements forming an oxide semiconductor are unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. Note that in the following, in an oxide semiconductor, one or more metal elements are unevenly distributed, and a region including the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof.
- the state mixed with is also referred to as mosaic or patch.
- the oxide semiconductor preferably contains at least indium.
- One kind selected from the above or a plurality of kinds may be included.
- a CAC-OS in In-Ga-Zn oxide is an indium oxide (hereinafter referred to as InO).
- X1 (X1 is greater real than 0) and.), or indium zinc oxide (hereinafter, in X2 Zn Y2 O Z2 ( X2, Y2, and Z2 is larger real than 0) and a.), gallium An oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0)) or a gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (where X4, Y4, and Z4 are greater than 0)) to.) and the like, the material becomes mosaic by separate into, mosaic InO X1, or in X2 Zn Y2 O Z2 is configured uniformly distributed in the film (hereinafter, Kura Also referred to as a de-like.) A.
- CAC-OS includes a region GaO X3 is the main component, In X2 Zn Y2 O Z2, or InO X1 there is a region which is a main component, a composite oxide semiconductor having a structure that is mixed.
- the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.
- IGZO is a common name and may refer to one compound of In, Ga, Zn, and O.
- ZnO ZnO
- the crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure.
- the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.
- CAC-OS relates to a material structure of an oxide semiconductor.
- CAC-OS refers to a region observed in the form of nanoparticles mainly composed of Ga in a material structure including In, Ga, Zn and O, and nanoparticles mainly composed of In.
- the region observed in a shape is a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in the CAC-OS, the crystal structure is a secondary element.
- the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions.
- a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.
- a region GaO X3 is the main component, In X2 Zn Y2 O Z2, or the region InO X1 is the main component, it may clear boundary can not be observed.
- the CAC-OS includes a region observed in a part of a nanoparticle mainly including the metal element and a nano part mainly including In.
- the region observed in the form of particles refers to a configuration in which each region is randomly dispersed in a mosaic shape.
- the CAC-OS can be formed by a sputtering method, for example, under conditions where the substrate is not intentionally heated.
- a sputtering method any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. Good.
- the flow rate ratio of the oxygen gas to the total flow rate of the deposition gas during film formation is preferably as low as possible. .
- the CAC-OS has a feature that a clear peak is not observed when measurement is performed using a ⁇ / 2 ⁇ scan by an out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods. Have. That is, it can be seen from X-ray diffraction that no orientation in the ab plane direction and c-axis direction of the measurement region is observed.
- XRD X-ray diffraction
- the CAC-OS in an electron beam diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam), a ring-shaped high luminance region and a plurality of regions in the ring region are provided. A bright spot is observed. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.
- nc nano-crystal
- GaO X3 is a main component by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region and the region mainly composed of In X2 Zn Y2 O Z2 or InO X1 are unevenly distributed and mixed.
- the CAC-OS has a structure different from that of the IGZO compound in which the metal element is uniformly distributed, and has a property different from that of the IGZO compound. That is, in the CAC-OS, a region in which GaO X3 or the like is a main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component are phase-separated from each other, and a region in which each element is a main component. Has a mosaic structure.
- the region containing In X2 Zn Y2 O Z2 or InO X1 as a main component is a region having higher conductivity than a region containing GaO X3 or the like as a main component. That, In X2 Zn Y2 O Z2, or InO X1 is a region which is a main component, by carriers flow, expressed the conductivity of the oxide semiconductor. Therefore, a region where In X2 Zn Y2 O Z2 or InO X1 is a main component is distributed in a cloud shape in the oxide semiconductor, whereby high field-effect mobility ( ⁇ ) can be realized.
- areas such as GaO X3 is the main component, In X2 Zn Y2 O Z2, or InO X1 is compared to region which is a main component, has a high area insulation. That is, a region containing GaO X3 or the like as a main component is distributed in the oxide semiconductor, whereby leakage current can be suppressed and good switching operation can be realized.
- CAC-OS when CAC-OS is used for a semiconductor element, high insulation is achieved by the complementary action of the insulating properties caused by GaO X3 and the like and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1.
- An on-current (I on ) and high field effect mobility ( ⁇ ) can be realized.
- CAC-OS is suitable as a constituent material for various semiconductor devices.
- FIG. 9A illustrates an example of a cross section of the pixel illustrated in FIG.
- the layer 61 has a pn junction type photodiode using silicon as a photoelectric conversion layer as the photoelectric conversion element 101.
- the layer 62 includes a Si transistor or the like that forms a pixel circuit.
- the layer 65a can be a p + -type region
- the layer 65b can be an n-type region
- the layer 65c can be an n + -type region.
- the layer 65b is provided with a region 36 for connecting the power supply line and the layer 65c.
- region 36 can be a p + type region.
- the Si transistor has a planar structure having a channel formation region in the silicon substrate 40. As shown in FIGS. 12A and 12B, the Si transistor has a fin type structure. The structure which has a semiconductor layer may be sufficient. 12A corresponds to a cross section in the channel length direction, and FIG. 12B corresponds to a cross section in the channel width direction.
- a transistor having a silicon thin film semiconductor layer 45 may be used.
- the semiconductor layer 45 can be, for example, single crystal silicon (SOI (Silicon on Insulator)) formed on the insulating layer 46 on the silicon substrate 40.
- SOI Silicon on Insulator
- FIG. 9A shows a configuration example in which an electrical connection between an element included in the layer 61 and an element included in the layer 62 is obtained by a bonding technique.
- the layer 61 is provided with an insulating layer 42, a conductive layer 33, and a conductive layer 34.
- the conductive layer 33 and the conductive layer 34 have a region embedded in the insulating layer 42.
- the conductive layer 33 is electrically connected to the layer 65a.
- Conductive layer 34 is electrically connected to region 36.
- the surfaces of the insulating layer 42, the conductive layer 33, and the conductive layer 34 are flattened so that their heights coincide with each other.
- an insulating layer 41, a conductive layer 31, and a conductive layer 32 are provided in the layer 62.
- the conductive layer 31 and the conductive layer 32 have a region embedded in the insulating layer 41.
- the conductive layer 32 is electrically connected to the power supply line.
- the conductive layer 31 is electrically connected to the source or drain of the transistor 102.
- the surfaces of the insulating layer 41, the conductive layer 31, and the conductive layer 32 are flattened so that their heights coincide with each other.
- the conductive layer 31 and the conductive layer 33 are preferably composed of the same metal element as the main component.
- the conductive layer 32 and the conductive layer 34 are preferably composed of the same metal element as the main component.
- the insulating layer 41 and the insulating layer 42 are comprised with the same component.
- Cu, Al, Sn, Zn, W, Mo, Ag, Pt, or Au can be used for the conductive layers 31, 32, 33, and 34.
- Cu, Al, W, or Au is preferably used.
- silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like can be used.
- the electrical connection of the combination of the conductive layer 31 and the conductive layer 33 and the combination of the conductive layer 32 and the conductive layer 34 can be obtained by the bonding. Moreover, the connection which has the mechanical strength of the insulating layer 41 and the insulating layer 42 can be obtained.
- a surface activated bonding method in which the oxide film on the surface, the adsorption layer of impurities, and the like are removed by sputtering, and the cleaned and activated surfaces are brought into contact with each other to be bonded can be used.
- a diffusion bonding method in which the surfaces are bonded to each other using both temperature and pressure can be used. In both cases, bonding at the atomic level occurs, so that excellent bonding not only electrically but also mechanically can be obtained.
- the insulating layers can be bonded to each other after high flatness is obtained by polishing or the like, and then the surfaces that have been subjected to hydrophilic treatment with oxygen plasma or the like are brought into contact with each other for temporary bonding, followed by dehydration by heat treatment to perform the main bonding.
- a bonding method or the like can be used. Since the bonding at the atomic level also occurs in the hydrophilic bonding method, a mechanically excellent bonding can be obtained.
- an insulating layer and a metal layer are mixed on each bonding surface.
- a surface activated bonding method and a hydrophilic bonding method may be combined.
- the surface of the metal layer is subjected to an antioxidant treatment and then subjected to a hydrophilic treatment and bonded.
- the surface of the metal layer may be made of a hardly oxidizable metal such as Au and subjected to a hydrophilic treatment. Note that a bonding method other than the method described above may be used.
- FIG. 9B is a cross-sectional view in the case where a pn junction type photodiode using a selenium-based material as a photoelectric conversion layer is used for the pixel layer 61 shown in FIG. 8A.
- a layer 66a is provided as one electrode, layers 66b and 66c as photoelectric conversion layers, and a layer 66d as the other electrode.
- the layer 61 can be formed directly on the layer 62.
- the layer 66a is electrically connected to the source or the drain of the transistor 102.
- the layer 66d is electrically connected to the power supply line through the conductive layer 37.
- FIG. 10A illustrates an example of a cross section of the pixel illustrated in FIG.
- the layer 61 has, as the photoelectric conversion element 101, a pn junction type photodiode having silicon as a photoelectric conversion layer.
- the layer 62 includes a Si transistor or the like.
- the layer 63 includes an OS transistor or the like.
- the layer 61 and the layer 63 illustrate a configuration example in which electrical connection is obtained by bonding.
- the OS transistor has a self-aligned structure, but may be a non-self-aligned top gate transistor as shown in FIG. 12D.
- the transistor 102 may have no back gate.
- the back gate 35 may be electrically connected to a front gate of a transistor provided to face the back gate 35. Or the structure which can supply the fixed electric potential different from a front gate to the back gate 35 may be sufficient.
- An insulating layer 43 having a function of preventing hydrogen diffusion is provided between the region where the OS transistor is formed and the region where the Si transistor is formed. Hydrogen in the insulating layer provided in the vicinity of the channel formation regions of the transistors 107 and 108 terminates dangling bonds of silicon. On the other hand, hydrogen in the insulating layer provided in the vicinity of the channel formation region of the transistor 102 is one of the factors that generate carriers in the oxide semiconductor layer.
- the reliability of the transistors 107 and 108 can be improved by confining hydrogen in one layer by the insulating layer 43.
- the reliability of the transistor 102 can be improved by suppressing the diffusion of hydrogen from one layer to the other layer.
- the insulating layer 43 for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria stabilized zirconia (YSZ), or the like can be used.
- aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria stabilized zirconia (YSZ), or the like can be used.
- FIG. 10B is a cross-sectional view in the case where a pn junction type photodiode using a selenium-based material as a photoelectric conversion layer is used for the pixel layer 61 shown in FIG. 8B.
- the layer 61 can be formed directly on the layer 63.
- the above description can be referred to.
- FIG. 11A is a diagram illustrating the configuration of FIG.
- the sensor region includes a layer 61 having a photoelectric conversion element 101 and a layer 63 having an OS transistor.
- the calculation area is composed of a layer 63 having a Si transistor or the like.
- the calculation area includes the transistors 107 and 108 in the pixel, the pooling circuit of the first embodiment, and the drivers 11, 12, and 13.
- the circuit area can be reduced by forming the sensor region and the calculation region in a stacked structure.
- FIG. 11B is a cross-sectional photograph of the sensor area and a cross-sectional photograph of the calculation area.
- the sensor region is constituted by a pn junction type photodiode using a selenium-based material as a photoelectric conversion layer and an OS transistor (OSFET), and the calculation region is constituted by various circuits by Si transistors (SiFET).
- OSFET OS transistor
- FIG. 13A is a perspective view illustrating an example in which a color filter or the like is added to a pixel of the imaging device of one embodiment of the present invention. In the perspective view, cross sections of a plurality of pixels are also shown.
- An insulating layer 80 is formed over the layer 61 where the photoelectric conversion element 101 is formed.
- the insulating layer 80 can be formed using a silicon oxide film having high light-transmitting property with respect to visible light.
- a silicon nitride film may be stacked as a passivation film.
- a dielectric film such as hafnium oxide may be laminated as the antireflection film.
- a light shielding layer 81 may be formed on the insulating layer 80.
- the light shielding layer 81 has a function of preventing color mixture of light passing through the upper color filter.
- a metal layer such as aluminum or tungsten can be used for the light shielding layer 81. Further, the metal layer and a dielectric film having a function as an antireflection film may be stacked.
- an organic resin layer 82 can be provided as a planarizing film. Further, a color filter 83 (color filters 83a, 83b, 83c) is formed for each pixel. For example, color images such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) are assigned to the color filters 83a, 83b, and 83c. Can be obtained.
- an insulating layer 86 having a light-transmitting property with respect to visible light can be provided.
- an optical conversion layer 85 may be used instead of the color filter 83.
- an infrared imaging device can be obtained. If a filter that blocks light having a wavelength shorter than or equal to the near infrared wavelength is used for the optical conversion layer 85, a far infrared imaging device can be obtained. Further, if a filter that blocks light having a wavelength longer than or equal to that of visible light is used for the optical conversion layer 85, an ultraviolet imaging device can be obtained. A visible color filter and an infrared or ultraviolet filter may be combined.
- a scintillator is used for the optical conversion layer 85, an imaging device that obtains an image that visualizes the intensity of radiation used in an X-ray imaging device or the like can be obtained.
- radiation such as X-rays transmitted through the subject
- the scintillator it is converted into light (fluorescence) such as visible light or ultraviolet light by a photoluminescence phenomenon.
- the photoelectric conversion element 101 detects the light and acquires image data.
- the imaging device having the configuration may be used for a radiation detector or the like.
- a scintillator contains a substance that emits visible light or ultraviolet light by absorbing energy when irradiated with radiation such as X-rays or gamma rays.
- Gd 2 O 2 S Tb
- Gd 2 O 2 S Pr
- Gd 2 O 2 S Eu
- BaFCl Eu
- distributed to resin or ceramics can be used.
- the photoelectric conversion element 101 using a selenium-based material can directly convert radiation such as X-rays into electric charges, and thus can be configured to eliminate a scintillator.
- a microlens array 84 may be provided on the color filter 83. Light passing through the individual lenses of the microlens array 84 passes through the color filter 83 directly below and is irradiated to the photoelectric conversion element 101. Alternatively, the microlens array 84 may be provided over the optical conversion layer 85 illustrated in FIG.
- FIG. 14A1 is an external perspective view of the upper surface side of the package containing the image sensor chip.
- the package includes a package substrate 410 for fixing the image sensor chip 450, a cover glass 420, and an adhesive 430 for bonding the two.
- FIG. 14 (A2) is an external perspective view of the lower surface side of the package.
- BGA Ball grid array
- solder balls as bumps 440.
- FIG. 14 (A3) is a perspective view of the package shown with the cover glass 420 and part of the adhesive 430 omitted.
- An electrode pad 460 is formed on the package substrate 410, and the electrode pad 460 and the bump 440 are electrically connected through a through hole.
- the electrode pad 460 is electrically connected to the image sensor chip 450 by a wire 470.
- FIG. 14B1 is an external perspective view of the upper surface side of the camera module in which the image sensor chip is housed in a lens-integrated package.
- the camera module includes a package substrate 411 for fixing the image sensor chip 451, a lens cover 421, a lens 435, and the like. Further, an IC chip 490 having functions such as a drive circuit and a signal conversion circuit of the imaging device is also provided between the package substrate 411 and the image sensor chip 451, and has a configuration as a SiP (System in package). Yes.
- SiP System in package
- FIG. 14 (B2) is an external perspective view of the lower surface side of the camera module.
- the package substrate 411 has a QFN (Quad Flat No-Lead Package) configuration in which mounting lands 441 are provided on a lower surface and a side surface. Note that this configuration is an example, and a QFP (Quad Flat Package) or the above-described BGA may be provided.
- QFN Quad Flat No-Lead Package
- FIG. 14 (B3) is a perspective view of the module shown with a part of the lens cover 421 and the lens 435 omitted.
- the land 441 is electrically connected to the electrode pad 461, and the electrode pad 461 is electrically connected to the image sensor chip 451 or the IC chip 490 by a wire 471.
- the image sensor chip can be mounted on a printed circuit board or the like by housing the image sensor chip in a package having the above-described form, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.
- Electronic devices that can use the imaging device according to one embodiment of the present invention include a display device, a personal computer, an image storage device or an image playback device including a recording medium, a mobile phone, a portable game machine, and a portable data terminal , Digital book terminals, video cameras, digital still cameras and other cameras, goggles-type displays (head-mounted displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction devices Automatic teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIGS.
- FIG. 15A shows a monitoring camera, which includes a support base 951, a camera unit 952, a protective cover 953, and the like.
- the camera unit 952 is provided with a rotation mechanism and the like, and can be imaged all around by being installed on the ceiling.
- the imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the camera unit.
- the surveillance camera is an idiomatic name and does not limit the application.
- a device having a function as a surveillance camera is also called a camera or a video camera.
- FIG. 15B illustrates a video camera, which includes a first housing 971, a second housing 972, a display portion 973, operation keys 974, a lens 975, a connection portion 976, and the like.
- the operation key 974 and the lens 975 are provided in the first housing 971, and the display portion 973 is provided in the second housing 972.
- the imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the video camera.
- FIG. 15C illustrates a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light-emitting portion 967, a lens 965, and the like.
- the imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the digital camera.
- FIG. 15D illustrates a wristwatch-type information terminal, which includes a display portion 932, a housing / wristband 933, a camera 939, and the like.
- Display unit 932 includes a touch panel for operating the information terminal.
- the display portion 932 and the casing / wristband 933 are flexible and have excellent wearability to the body.
- the imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the information terminal.
- FIG. 15E illustrates an example of a mobile phone, which includes a housing 981, a display portion 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like.
- the mobile phone includes a touch sensor in the display portion 982. All operations such as making a call or inputting characters can be performed by touching the display portion 982 with a finger, a stylus, or the like.
- the imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the mobile phone.
- FIG. 15F illustrates a portable data terminal, which includes a housing 911, a display portion 912, a camera 919, and the like. Information can be input and output by a touch panel function of the display portion 912.
- the imaging device of one embodiment of the present invention can be provided as one of the components for acquiring an image in the portable data terminal.
- This embodiment mode can be combined with any of the other embodiment modes as appropriate.
- a display element, a display device which is a device including a display element, a light-emitting element, and a light-emitting device which is a device including a light-emitting element have various forms or have various elements. Can do.
- a display element, a display device, a light emitting element, or a light emitting device includes, for example, an EL (electroluminescence) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element), an LED chip (a white LED chip, a red LED chip, Green LED chip, blue LED chip, etc.), transistor (transistor that emits light in response to current), plasma display panel (PDP), electron-emitting device, display device using carbon nanotube, liquid crystal device, electronic ink, electrowetting device , Electrophoretic elements, display elements using MEMS (micro electro mechanical system) (for example, grating light valve (GLV), digital micromirror device (DMD), DMS (digital micro shutter), MIRASOL R), IMOD (interferometric modulation) elements, MEMS display element shutter method, MEMS display element employing optical interferometry, such as a piezoelectric ceramic display), or has at least one and quantum dots.
- the display element, the display device, the light-emitting element, or the light-emitting device may include a display medium whose contrast, luminance, reflectance, transmittance, and the like change due to an electrical or magnetic action.
- An example of a display device using an EL element is an EL display.
- As an example of a display device using an electron-emitting device there is a field emission display (FED), a SED type flat display (SED: Surface-conduction Electron-emitter Display), or the like.
- a display device using a liquid crystal element there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like.
- a display device using electronic ink, electronic powder fluid (registered trademark), or an electrophoretic element is electronic paper.
- An example of a display device using a quantum dot for each pixel is a quantum dot display. Note that the quantum dots may be provided not in the display element but in part of the backlight. By using quantum dots, display with high color purity can be performed.
- part or all of the pixel electrode may have a function as a reflective electrode.
- part or all of the pixel electrode may have aluminum, silver, or the like.
- a memory circuit such as an SRAM can be provided under the reflective electrode.
- power consumption can be further reduced.
- Graphene or graphite may be a multilayer film in which a plurality of layers are stacked.
- a nitride semiconductor for example, an n-type GaN semiconductor layer having a crystal can be easily formed thereon.
- a p-type GaN semiconductor layer having a crystal or the like can be provided thereon to form an LED chip.
- an AlN layer may be provided between graphene or graphite and an n-type GaN semiconductor layer having a crystal.
- the GaN semiconductor layer of the LED chip may be formed by MOCVD.
- the GaN semiconductor layer of the LED chip can be formed by a sputtering method.
- a space in which the display element is sealed (for example, an element substrate on which the display element is arranged, and an element substrate facing the element substrate)
- a desiccant may be disposed between the opposite substrate).
- the content described in one embodiment (may be a part of content) is different from the other content described in the embodiment (may be a part of content) and one or more other implementations.
- Application, combination, replacement, or the like can be performed on at least one of the contents described in the form (may be part of the contents).
- a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, another drawing (may be a part) described in the embodiment, or one or more different drawings.
- more drawings can be formed.
- the terms “upper” and “lower” do not limit that the positional relationship between the constituent elements is directly above or directly below and in direct contact with each other.
- the expression “electrode B on the insulating layer A” does not require the electrode B to be formed in direct contact with the insulating layer A, and another configuration between the insulating layer A and the electrode B. Do not exclude things that contain elements.
- the size, the layer thickness, or the region is shown in an arbitrary size for the purpose of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematically shown for the sake of clarity, and are not limited to the shapes or values shown in the drawings. For example, variation in signal, voltage, or current due to noise, variation in signal, voltage, or current due to timing shift can be included.
- one of a source and a drain is referred to as “one of a source and a drain” (or a first electrode or a first terminal), and the source and the drain The other is referred to as “the other of the source and the drain” (or the second electrode or the second terminal).
- the source and drain of a transistor vary depending on the structure or operating conditions of the transistor.
- the names of the source and the drain of the transistor can be appropriately rephrased depending on the situation, such as a source (drain) terminal or a source (drain) electrode.
- two terminals other than the gate may be referred to as a first terminal and a second terminal, or may be referred to as a third terminal and a fourth terminal.
- these gates may be referred to as a first gate and a second gate, , Sometimes called back gate.
- the phrase “front gate” can be rephrased as simply the phrase “gate”.
- the phrase “back gate” can be rephrased simply as the phrase “gate”.
- a bottom gate refers to a terminal formed before a channel formation region when a transistor is manufactured, and a “top gate” is formed after a channel formation region when a transistor is manufactured. Terminal.
- the transistor has three terminals called gate, source, and drain.
- the gate is a terminal that functions as a control terminal for controlling the conduction state of the transistor.
- One of the two input / output terminals functioning as a source or drain serves as a source and the other serves as a drain depending on the type of the transistor and the potential applied to each terminal. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.
- Electrode and “wiring” do not functionally limit these components.
- an “electrode” may be used as part of a “wiring” and vice versa.
- the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.
- the voltage is a potential difference from a reference potential.
- the reference potential is a ground potential (ground potential)
- the voltage can be rephrased as a potential.
- the ground potential does not necessarily mean 0V. Note that the potential is relative, and the potential applied to the wiring or the like may be changed depending on the reference potential.
- conductive layer may be changed to the term “conductive film”.
- insulating film may be changed to the term “insulating layer”.
- the term “conductive layer” or “conductive film” may be changed to the term “conductor” in some cases.
- the terms “insulating layer” and “insulating film” may be changed to the term “insulator”.
- wiring can be interchanged with each other depending on circumstances or circumstances.
- the term “wiring” may be changed to a term such as “power supply line”.
- the term “wiring” may be changed to a term such as “power supply line”.
- a term such as “power line” may be changed to a term such as “signal line”.
- a term such as “signal line” may be changed to a term such as “power line”.
- the term “potential” applied to the wiring may be changed to a term “signal” or the like depending on circumstances or circumstances. The reverse is also true, and a term such as “signal” may be changed to a term “potential”.
- the semiconductor impurity means, for example, a component other than the main component constituting the semiconductor layer.
- an element having a concentration of less than 0.1 atomic% is an impurity.
- the impurities are included, for example, DOS (Density of States) may be formed in the semiconductor, carrier mobility may be reduced, or crystallinity may be reduced.
- examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and components other than main components Examples include transition metals, and in particular, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like.
- oxygen vacancies may be formed by mixing impurities such as hydrogen, for example.
- impurities such as hydrogen, for example.
- examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.
- a transistor is an element having at least three terminals including a gate, a drain, and a source.
- a channel formation region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode).
- the functions of the source and drain may be switched when transistors with different polarities are used or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.
- a switch refers to a switch that is in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether or not to pass current.
- the switch refers to a switch having a function of selecting and switching a current flow path.
- an electrical switch or a mechanical switch can be used. That is, the switch is not limited to a specific one as long as it can control the current.
- Examples of electrical switches include transistors (eg, bipolar transistors, MOS transistors, etc.), diodes (eg, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.), or a logic circuit combining these.
- transistors eg, bipolar transistors, MOS transistors, etc.
- diodes eg, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.
- diodes eg, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes. , Dio
- the “conducting state” of the transistor means a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited.
- the “non-conducting state” of a transistor refers to a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically disconnected. Note that when a transistor is operated as a simple switch, the polarity (conductivity type) of the transistor is not particularly limited.
- a mechanical switch is a switch using MEMS (micro electro mechanical system) technology such as a digital micromirror device (DMD).
- MEMS micro electro mechanical system
- DMD digital micromirror device
- the switch has an electrode that can be moved mechanically, and operates by controlling conduction and non-conduction by moving the electrode.
- connection relation ⁇ About connection
- X and Y when X and Y are described as being connected, when X and Y are electrically connected, and when X and Y are functionally connected And the case where X and Y are directly connected. Therefore, it is not limited to a predetermined connection relation, for example, the connection relation shown in the figure or text, and includes things other than the connection relation shown in the figure or text.
- X and Y used here are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
- an element for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.
- the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current.
- a circuit for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc.
- Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.)
- One or more can be connected between them.
- a circuit for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc.
- Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power
- the source (or the first terminal) of the transistor is electrically connected to X through (or not through) Z1, and the drain (or the second terminal or the like) of the transistor is connected to Z2.
- Y is electrically connected, or the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, and another part of Z1 Is directly connected to X, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y.
- X and Y, and the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor are electrically connected to each other.
- the drain of the transistor (or the second terminal, etc.) and the Y are electrically connected in this order.
- the source (or the first terminal, etc.) of the transistor is electrically connected to X
- the drain (or the second terminal, etc.) of the transistor is electrically connected to Y
- X, the source of the transistor ( Or the first terminal or the like, the drain of the transistor (or the second terminal, or the like) and Y are electrically connected in this order.
- X is electrically connected to Y through the source (or the first terminal) and the drain (or the second terminal) of the transistor, and X is the source of the transistor (or the first terminal). Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order.
- the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are separated. Apart from that, the technical scope can be determined.
- these expression methods are examples, and are not limited to these expression methods.
- X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).
- the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.
- parallel refers to a state in which two straight lines are arranged at an angle of ⁇ 10 ° to 10 °. Therefore, the case of ⁇ 5 ° to 5 ° is also included.
- substantially parallel means a state in which two straight lines are arranged at an angle of ⁇ 30 ° to 30 °.
- Vertical refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.
- substantially vertical means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.
Abstract
Description
本実施の形態では、ニューラルネットワークのプーリング処理を効率的に行う撮像装置について、図1乃至図7を用いて説明する。
本実施の形態では、撮像装置10に用いられる光電変換素子101について、図8乃至図14を用いて説明する。
図8(A)に、上述した画素回路を有する画素の構成を例示する。図8(A)に示す画素は、層61及び層62の積層構成を有する例である。
OSトランジスタに用いる半導体材料としては、エネルギーギャップが2eV以上、好ましくは2.5eV以上、より好ましくは3eV以上である金属酸化物を用いることができる。代表的には、インジウムを含む酸化物半導体などであり、例えば、後述するCAC−OSなどを用いることができる。
図13(A)は、本発明の一態様の撮像装置の画素にカラーフィルタ等を付加した例を示す斜視図である。当該斜視図では、複数の画素の断面もあわせて図示している。光電変換素子101が形成される層61上には、絶縁層80が形成される。絶縁層80は可視光に対して透光性の高い酸化シリコン膜などを用いることができる。また、パッシベーション膜として窒化シリコン膜を積層してもよい。また、反射防止膜として、酸化ハフニウムなどの誘電体膜を積層してもよい。
以下では、イメージセンサチップを収めたパッケージ及びカメラモジュールの一例について説明する。当該イメージセンサチップには、上記撮像装置の構成を用いることができる。
本発明の一態様に係る撮像装置を用いることができる電子機器として、表示機器、パーソナルコンピュータ、記録媒体を備えた画像記憶装置又は画像再生装置、携帯電話、携帯型を含むゲーム機、携帯データ端末、電子書籍端末、ビデオカメラ、デジタルスチルカメラ等のカメラ、ゴーグル型ディスプレイ(ヘッドマウントディスプレイ)、ナビゲーションシステム、音響再生装置(カーオーディオ、デジタルオーディオプレイヤー等)、複写機、ファクシミリ、プリンタ、プリンタ複合機、現金自動預け入れ払い機(ATM)、自動販売機などが挙げられる。これら電子機器の具体例を図15に示す。
以上の実施の形態における各構成の説明について、以下に付記する。
各実施の形態に示す構成は、他の実施の形態に示す構成と適宜組み合わせて、本発明の一態様とすることができる。また、1つの実施の形態の中に、複数の構成例が示される場合は、互いに構成例を適宜組み合わせることが可能である。
本明細書等において、「第1」、「第2」、「第3」という序数詞は、構成要素の混同を避けるために付したものである。したがって、構成要素の数を限定するものではない。また、構成要素の順序を限定するものではない。また例えば、本明細書等の実施の形態の一において「第1」に言及された構成要素が、他の実施の形態、あるいは特許請求の範囲において「第2」に言及された構成要素とすることもありうる。また例えば、本明細書等の実施の形態の一において「第1」に言及された構成要素を、他の実施の形態、あるいは特許請求の範囲において省略することもありうる。
実施の形態について図面を参照しながら説明している。ただし、実施の形態は多くの異なる態様で実施することが可能であり、趣旨及びその範囲から逸脱することなく、その形態及び詳細を様々に変更し得ることは当業者であれば容易に理解される。したがって、本発明は、実施の形態の記載内容に限定して解釈されるものではない。なお、実施の形態の発明の構成において、同一部分又は同様な機能を有する部分には同一の符号を異なる図面間で共通して用い、その繰り返しの説明は省略する。
本明細書等において、トランジスタの接続関係を説明する際、ソースとドレインとの一方を、「ソース又はドレインの一方」(又は第1電極、又は第1端子)と表記し、ソースとドレインとの他方を「ソース又はドレインの他方」(又は第2電極、又は第2端子)と表記している。これは、トランジスタのソースとドレインは、トランジスタの構造又は動作条件等によって変わるためである。なおトランジスタのソースとドレインの呼称については、ソース(ドレイン)端子や、ソース(ドレイン)電極等、状況に応じて適切に言い換えることができる。また、本明細書等では、ゲート以外の2つの端子を第1端子、第2端子と呼ぶ場合や、第3端子、第4端子と呼ぶ場合がある。また、本明細書等に記載するトランジスタが2つ以上のゲートを有するとき(この構成をデュアルゲート構造という場合がある)、それらのゲートを第1ゲート、第2ゲートと呼ぶ場合や、フロントゲート、バックゲートと呼ぶ場合がある。特に、「フロントゲート」という語句は、単に「ゲート」という語句に互いに言い換えることができる。また、「バックゲート」という語句は、単に「ゲート」という語句に互いに言い換えることができる。なお、ボトムゲートとは、トランジスタの作製時において、チャネル形成領域よりも先に形成される端子のことをいい、「トップゲート」とは、トランジスタの作製時において、チャネル形成領域よりも後に形成される端子のことをいう。
以下では、上記実施の形態中で言及した語句の定義について説明する。
半導体の不純物とは、例えば、半導体層を構成する主成分以外をいう。例えば、濃度が0.1原子%未満の元素は不純物である。不純物が含まれることにより、例えば、半導体にDOS(Density of States)が形成されることや、キャリア移動度が低下することや、結晶性が低下することなどが起こる場合がある。半導体が酸化物半導体である場合、半導体の特性を変化させる不純物としては、例えば、第1族元素、第2族元素、第13族元素、第14族元素、第15族元素、主成分以外の遷移金属などがあり、特に、例えば、水素(水にも含まれる)、リチウム、ナトリウム、シリコン、ホウ素、リン、炭素、窒素などがある。酸化物半導体の場合、例えば水素などの不純物の混入によって酸素欠損を形成する場合がある。また、半導体がシリコン層である場合、半導体の特性を変化させる不純物としては、例えば、酸素、水素を除く第1族元素、第2族元素、第13族元素、第15族元素などがある。
本明細書において、トランジスタとは、ゲートと、ドレインと、ソースとを含む少なくとも三つの端子を有する素子である。そして、ドレイン(ドレイン端子、ドレイン領域又はドレイン電極)とソース(ソース端子、ソース領域又はソース電極)の間にチャネル形成領域を有する。ゲート−ソース間にしきい値電圧を超える電圧を与えることによって、チャネル形成領域にチャネルが形成され、ソース‐ドレイン間に電流を流すことができる。
本明細書等において、スイッチとは、導通状態(オン状態)、又は、非導通状態(オフ状態)になり、電流を流すか流さないかを制御する機能を有するものをいう。又は、スイッチとは、電流を流す経路を選択して切り替える機能を有するものをいう。
本明細書等において、XとYとが接続されている、と記載する場合は、XとYとが電気的に接続されている場合と、XとYとが機能的に接続されている場合と、XとYとが直接接続されている場合とを含むものとする。したがって、所定の接続関係、例えば、図又は文章に示された接続関係に限定されず、図又は文章に示された接続関係以外のものも含むものとする。
本明細書において、「平行」とは、二つの直線が−10°以上10°以下の角度で配置されている状態をいう。したがって、−5°以上5°以下の場合も含まれる。また、「略平行」とは、二つの直線が−30°以上30°以下の角度で配置されている状態をいう。また、「垂直」とは、二つの直線が80°以上100°以下の角度で配置されている状態をいう。したがって、85°以上95°以下の場合も含まれる。また、「略垂直」とは、二つの直線が60°以上120°以下の角度で配置されている状態をいう。
Claims (8)
- 画素領域と、第1の回路と、を有する撮像装置であって、
前記画素領域は、プーリングモジュールと、出力回路とを有し、
前記プーリングモジュールは、複数のプーリング回路と、比較モジュールと、を有し、
前記プーリング回路は、複数の画素と、演算回路と、を有し、
前記比較モジュールは、複数の比較回路と、判定回路とを有し、
前記画素は、光電変換により第1の信号を取得する機能を有し、
前記画素は、前記第1の信号を任意の倍率で乗算して第2の信号を生成する機能を有し、
前記プーリング回路は、複数の前記第2の信号を前記演算回路によって加算して第3の信号を生成する機能を有し、
前記比較モジュールは、複数の前記第3の信号を比較し、最も大きな前記第3の信号を選択し、前記判定回路に出力する機能を有し、
前記判定回路は、最も大きな前記第3の信号を判定し2値化して第4の信号を生成する機能を有し、
前記第1の回路は、前記第4の信号を前記出力回路に出力するタイミングを制御し、
前記プーリングモジュールは、前記画素の数に応じてプーリング処理し、
前記プーリングモジュールは、前記プーリング処理により生成された前記第4の信号を出力する撮像装置。 - 請求項1において、
前記撮像装置は、さらに、第2の回路と、第3の回路と、第1の配線と、第2の配線と、第3の配線と、を有し、
前記画素は、第1の出力端子を有し、
前記演算回路は、第1のトランジスタと、第2のトランジスタと、第3のトランジスタとを有し、
前記第2の回路は、前記第1の配線を介して行方向に延在する複数の前記画素と電気的に接続され、
前記第3の回路は、前記第2の配線を介して列方向に延在する複数の前記画素と電気的に接続され、
前記第3の配線は、前記第1のトランジスタのソース又はドレインの一方と、前記第2のトランジスタのソース又はドレインの一方と、前記第3のトランジスタのソース又はドレインの一方とに電気的に接続され、
前記第1のトランジスタのゲートは、前記第1のトランジスタのソース又はドレインの他方と、前記第2のトランジスタのゲートと、前記第3のトランジスタのゲートと、前記プーリング回路が有する前記画素の前記第1の出力端子とに電気的に接続され、
前記第3の回路は、前記第2の配線に選択信号を出力する機能を有し、
前記第2の回路は、前記第1の配線を介して前記画素に任意の倍率を設定する機能を有し、
前記第1のトランジスタは、前記第2のトランジスタと、前記第3のトランジスタと同じチャネル長を有し、
前記第2のトランジスタは、前記第1のトランジスタのチャネル幅と同じ幅を有することで、複数の前記第2の信号を加算した前記第3の信号を出力する機能を有し、
前記第3のトランジスタは、前記第1のトランジスタのチャネル幅を前記プーリング回路が有する前記画素の数で割った長さにすることで、前記第3の信号の大きさを前記画素の数で割った大きさの前記第5の信号を出力する機能を有する撮像装置。 - 請求項1において、
前記比較モジュールは、第1の比較回路と、第2の比較回路と、カレントミラー回路と、を有し、
前記第1の比較回路は、第4のトランジスタ、第5のトランジスタ、第6のトランジスタ、第7のトランジスタ、第8のトランジスタ、第9のトランジスタ、第1の入力端子、第2の入力端子、第2の出力端子、及び第4の配線を有し、
前記第1の比較回路の前記第2の出力端子は、前記カレントミラー回路を介して前記第2の比較回路の前記第1の入力端子と電気的に接続され、
前記第1の入力端子は、前記第5のトランジスタのソース又はドレインの一方と、前記第7のトランジスタのソース又はドレインの一方と、前記第4のトランジスタのゲートと、前記第5のトランジスタのゲートと、前記第6のトランジスタのゲートとに電気的に接続され、
前記第2の入力端子は、前記第8のトランジスタのソース又はドレインの一方と、前記第6のトランジスタのソース又はドレインの一方と、前記第7のトランジスタのゲートと、前記第8のトランジスタのゲートと、前記第9のトランジスタのゲートとに電気的に接続され、
前記第2の出力端子は、前記第4のトランジスタのソース又はドレインの一方と、前記第9のトランジスタのソース又はトレインの一方とに電気的に接続され、
前記第4のトランジスタ乃至前記第9のトランジスタは、同じ大きさのチャネル長を有し、
前記第4のトランジスタのチャネル幅は、前記第5のトランジスタのチャネル幅と同じであることが好ましく、
前記第6のトランジスタのチャネル幅は、前記第5のトランジスタのチャネル幅の2倍が好ましく、
前記第4のトランジスタ乃至前記第6のトランジスタは、第1のカレントミラー回路を形成し、
前記第9のトランジスタのチャネル幅は、前記第8のトランジスタのチャネル幅と同じであることが好ましく、
前記第7のトランジスタのチャネル幅は、前記第8のトランジスタのチャネル幅の2倍が好ましく、
前記第7のトランジスタ乃至前記第9のトランジスタは、第2のカレントミラー回路を形成し、
前記第1の比較回路の前記第1の入力端子には、第6の信号が与えられ、
前記第1の比較回路の前記第2の入力端子には、第7の信号が与えられ、
前記第1の比較回路の前記第2の出力端子は、前記第6の信号又は前記第7の信号のいずれか大きい信号を第8の信号として出力し、
前記第2の比較回路の前記第1の入力端子には、前記第8の信号が与えられ、
前記第2の比較回路の前記第2の入力端子には、第9の信号が与えられ、
前記第2の比較回路の前記第2の出力端子は、前記第8の信号又は前記第9の信号のいずれか大きい信号を第10の信号として前記判定回路に出力し、
前記判定回路は、前記第10の信号を判定し、2値化して前記第4の信号を生成する機能を有し
前記第1の回路は、前記第4の信号を前記出力回路に出力するタイミングを制御する機能を有する撮像装置。 - 請求項1又は請求項2において、
前記複数の前記画素はマトリクス状に配置され、隣り合う画素の間に遮光されている領域を有する撮像装置。 - 請求項1又は請求項2において、
前記画素は、さらに、光電変換素子、第10のトランジスタ、第11のトランジスタ、第12のトランジスタ、第13のトランジスタ、第14のトランジスタ、及び第1の容量素子を有し、
前記光電変換素子の一方の電極は、前記第10のトランジスタのソース又はドレインの一方と電気的に接続され、
前記第10のトランジスタのソース又はドレインの他方は、前記第11のトランジスタのソース又はドレインの一方と電気的に接続され、
前記第11のトランジスタのソース又はドレインの一方は、前記第12のトランジスタのゲートと電気的に接続され、
前記第12のトランジスタのゲートは、前記第1の容量素子の一方の電極と電気的に接続され、
前記第12のトランジスタのソース又はドレインの一方は、前記第1の出力端子と電気的に接続され、
前記第1の容量素子の他方の電極は、前記第13のトランジスタのソース又はドレインの一方と電気的に接続され、
前記第13のトランジスタのソース又はドレインの他方は、前記第1の配線と電気的に接続され、
前記第13のトランジスタのゲートは、前記第2の配線と電気的に接続され、
前記第10のトランジスタ及び前記第12のトランジスタは、チャネル形成領域に金属酸化物を有する撮像装置。 - 請求項5において、
前記金属酸化物は、Inと、Znと、M(MはAl、Ti、Ga、Sn、Y、Zr、La、Ce、Nd又はHf)と、を有する撮像装置。 - 請求項5において、
前記光電変換素子は、セレン又はセレンを含む化合物を有する撮像装置。 - 請求項1乃至3のいずれか一に記載の撮像装置と、表示装置と、を有する電子機器。
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US20240048868A1 (en) | 2024-02-08 |
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