WO2018224051A1 - 一种防电磁干扰的射频模块及其实现方法 - Google Patents

一种防电磁干扰的射频模块及其实现方法 Download PDF

Info

Publication number
WO2018224051A1
WO2018224051A1 PCT/CN2018/093940 CN2018093940W WO2018224051A1 WO 2018224051 A1 WO2018224051 A1 WO 2018224051A1 CN 2018093940 W CN2018093940 W CN 2018093940W WO 2018224051 A1 WO2018224051 A1 WO 2018224051A1
Authority
WO
WIPO (PCT)
Prior art keywords
radio frequency
frequency module
electromagnetic interference
substrate
conductive material
Prior art date
Application number
PCT/CN2018/093940
Other languages
English (en)
French (fr)
Inventor
金福娟
白云芳
Original Assignee
唯捷创芯(天津)电子技术股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 唯捷创芯(天津)电子技术股份有限公司 filed Critical 唯捷创芯(天津)电子技术股份有限公司
Priority to US16/620,457 priority Critical patent/US11264335B2/en
Publication of WO2018224051A1 publication Critical patent/WO2018224051A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0215—Grounding of printed circuits by connection to external grounding means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0007—Casings
    • H05K9/002—Casings with localised screening
    • H05K9/0022—Casings with localised screening of components mounted on printed circuit boards [PCB]
    • H05K9/0024—Shield cases mounted on a PCB, e.g. cans or caps or conformal shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the invention relates to a radio frequency module, in particular to a radio frequency signal product, a radio frequency module with anti-electromagnetic interference function, and a method for realizing the radio frequency module, and belongs to the technical field of integrated circuit manufacturing.
  • RF signal products are currently widely used in consumer electronics.
  • the integration of various functional modules is getting higher and higher.
  • the RF module determines whether the signal reception of the mobile phone is good or bad.
  • the degree of integration is higher, the electromagnetic interference generated by it is stronger, which makes the performance of the RF module itself greatly reduced.
  • it is necessary to effectively isolate the electromagnetic interference generated around.
  • it is also necessary to reduce or effectively isolate the surrounding electromagnetic interference, thereby enhancing the strength of the effective signal received/output by the RF module and improving the performance of the RF module.
  • an electromagnetic shielding structure is generally used to reduce or effectively isolate electromagnetic interference around the radio frequency module.
  • the conventional electromagnetic shielding structure generally covers the periphery of the RF module with a metal cover.
  • the metal cover body is connected to the circuit board by soldering, and the product may have hidden damage due to the high temperature reflow step. For example, a short circuit is caused by the turbulence of the solder due to the fall of the solder resist.
  • the above-mentioned high-temperature reflow step also causes problems such as an increase in man-hours at the production end and an increase in cost.
  • it is necessary to increase the space occupied by the product resulting in an increase in the size of the product.
  • the primary technical problem to be solved by the present invention is to provide an RF module that prevents electromagnetic interference.
  • Another technical problem to be solved by the present invention is to provide a method for implementing the above radio frequency module.
  • a radio frequency module for preventing electromagnetic interference includes: a radio frequency module body, wherein the radio frequency module body is internally provided with an electrical connection region and a grounding region, and an upper surface of the radio frequency module body is The metal film structure is attached to the side surface, and the metal film structure is electrically connected to the grounding region to form an anti-electromagnetic interference shielding layer structure integrated with the body of the radio frequency module.
  • one or more sides of the radio frequency module body are exposed with a first conductive material cross section, and the first conductive material end surface is connected to the metal thin film structure, and the opposite ends of the first conductive material cross section are The grounding region is connected to electrically connect the metal thin film structure and the grounding region to form an anti-electromagnetic interference shielding layer structure of the radio frequency module body.
  • the radio frequency module body comprises a substrate, the electrical connection region and the grounding region are disposed on the substrate, and the electrical connection region is provided with a single chip radio frequency module or a multi-chip radio frequency module.
  • the single-chip radio frequency module or the multi-chip radio frequency module and the corresponding first conductive material and the second conductive material are wrapped in the epoxy resin filler to form an inseparable integral sealing structure.
  • the substrate includes, but is not limited to, a single layer circuit board, a single layer circuit frame, a multi-layer integrated circuit board, and a multi-layer integrated circuit frame.
  • the multi-chip radio frequency module is composed of a plurality of functional chips and components
  • the single-chip radio frequency module is composed of a single-function chip or a single-function chip and components, and the functional chip and the component respectively Electrically connected to the substrate.
  • the first conductive material, the second conductive material, and the metal thin film structure are metal materials having a single conductive property or alloy materials having conductive properties mixed with the plurality of metal materials, and the A conductive material and the second conductive material have a shape of a line or a strip.
  • a method for implementing an anti-electromagnetic interference radio frequency module includes the following steps:
  • Step S1 preparing a substrate and dividing different regions on the substrate
  • Step S2 setting each component of the radio frequency module in an electrical connection region of the substrate
  • Step S3 electrically connecting the corresponding chip and the substrate, the grounding area and the corresponding wire-bonding area in the dicing area by using a conductive material;
  • Step S4 filling the plastic sealing material to each corner of the radio frequency body, so that the components of the radio frequency module and the conductive material are wrapped in the molding compound;
  • Step S5 cutting the whole sealing structure into a separate packaged finished product according to the finished product size of the single RF module by using a finished cutting process
  • Step S6 converting the RF module body to the coating film on the coating fixture to form an RF module for preventing electromagnetic interference.
  • step S1 at least one grounding area is disposed on the substrate, the wire-bonding areas are respectively grounded, and the outer circumference of the substrate is provided with a dicing area, which is located on either side of the substrate or more A wire bonding region is disposed on the side of the scribe line.
  • step S2 when the component is included in the radio frequency module, the component is attached to the substrate by a surface mount process, so that the component is electrically connected to the substrate respectively. connection.
  • step S2 when the function chip is included in the radio frequency module, the function chip is attached to the substrate by using a mounting process, or the function chip adopts a flip chip process to make the The functional chip is directly electrically connected to the substrate.
  • step S3 when the functional chip is attached to the substrate by using a mounting process, the functional chip passes the second conductive material and utilizes a wire bonding process and the substrate electrical property. Connecting; the grounding area of the ground is electrically connected to the wire bonding area in the area of the scribe line by the first conductive material and by a wire bonding process.
  • step S5 the scribe line region is cut off, and the first conductive material respectively connected to the corresponding grounded wire bonding region is cut to form a cross section, so that the cross section of the first conductive material is separately exposed to The corresponding surface of the body of the radio frequency module on which it is located.
  • a plurality of independent radio frequency module bodies are converted onto the coating fixture, such that each of the independent radio frequency module bodies has an upper surface facing upward, and each of the independent a predetermined gap is formed between the main body of the radio frequency module, such that a side surface of each of the radio frequency module bodies is exposed to air, and a lower surface of the substrate is completely covered by the coating fixture, and an upper surface of the radio frequency module body is
  • the metal film structure is directly connected to the side surface of the first conductive material exposed on the side of the radio frequency body to electrically connect the metal film structure and the grounding area inside the radio frequency module body.
  • the electrical connection forms an anti-electromagnetic interference shielding layer integrated with the radio frequency body.
  • the anti-electromagnetic interference radio frequency module integrates the radio frequency module body and the metal thin film structure, and connects the metal thin film structure and the grounding area inside the radio frequency body through the first conductive material to form a body with the radio frequency module body.
  • An integrated anti-electromagnetic interference shielding structure integrated with the anti-electromagnetic interference shielding layer structure, so that the electromagnetic interference generated around the radio frequency module is effectively isolated, thereby improving the performance of the radio frequency module.
  • the RF module combines the original RF module production process with the metal film sputtering process, and can form an anti-electromagnetic interference shielding layer required for the RF module in a simpler, more efficient, and more cost-effective manner.
  • FIG. 1 is a schematic structural diagram of an anti-electromagnetic interference radio frequency module according to the present invention.
  • FIG. 2 is a schematic structural diagram of a radio frequency module body using a multi-chip radio frequency module in an anti-electromagnetic interference radio frequency module provided by the present invention
  • FIG. 3 and FIG. 4 are schematic diagrams showing the structure of a radio frequency module body using a single-chip radio frequency module in an anti-electromagnetic interference radio frequency module according to the present invention
  • FIG. 5 is a flow chart of a method for implementing an anti-electromagnetic interference radio frequency module according to the present invention
  • FIG. 6 to FIG. 14 are schematic diagrams showing the working process of the method for implementing the radio frequency module shown in FIG. 5.
  • the anti-electromagnetic interference radio frequency module includes a radio frequency module body, and an electrical connection region 1 and a grounding region 2 are disposed inside the radio frequency module body; and one or more sides of the radio frequency module body are exposed.
  • a first conductive material cross section (the first conductive material cross section 301 shown in FIG. 12), the opposite end of the first conductive material cross section is connected to the grounding area 2, and the metal thin film structure 4 is attached to the upper surface and the side surface of the radio frequency module body,
  • the metal thin film structure 4 is connected to the end surface of the first conductive material to electrically connect the metal thin film structure 4 and the grounding region 2 to form an electromagnetic interference shielding layer structure.
  • the electromagnetic interference generated around the radio frequency module is effectively isolated by the anti-electromagnetic interference shielding layer structure, thereby improving the performance of the radio frequency module.
  • the radio frequency module body refers to an independent packaged product with radio frequency function.
  • the RF module body includes a base plate 5 (referred to as a substrate), and the substrate 5 may be a single-layer circuit board or a frame, or may be a multi-layer integrated circuit board or frame.
  • An electrical connection region 1 and a ground region 2 are provided on the substrate.
  • a multi-chip radio frequency module composed of a plurality of functional chips 6 and components 7 may be disposed in the electrical connection region 1; a single-chip radio frequency composed of the single-function chip 6 may also be disposed in the electrical connection region 1.
  • Module (not shown); as shown in FIG. 3 and FIG.
  • a single-chip RF module composed of a single-function chip 6 and a component 7 can also be disposed in the electrical connection region 1.
  • the function chip 6 can be a single RF function chip, and the function chip can also be a combination of multiple function chips.
  • the function chip can be a radio frequency component, a power amplifier chip, a switch chip, a low noise amplifier chip, and a filter. Any one or more of the chips having radio frequency functions.
  • the function chip 6 can be attached to the substrate by using a mounting process, and the functional chip 6 is electrically connected to the substrate 5 by a wire bonding process by using one or more second conductive materials 11; the functional chip 6 can also be flipped. The process electrically connects the functional chip directly to the substrate 5.
  • the component 7 may be any one of a component such as a capacitor, a resistor, an inductor, a filter, or the like which is attached to the substrate 5 by a package surface mounting process (such a component is also referred to as an SMT component). kind or more.
  • the position of the grounding area 2 can be set according to the design requirements of the product and the packaging process capability, and the size thereof is not limited.
  • the ground region 2 is connected to one or more first conductive materials 3 (opposite ends of the first conductive material section).
  • the first conductive material 3 and the second conductive material 11 may be a metal material having a single conductive property, such as a metal material such as gold, silver, copper, aluminum, etc.; the first conductive material 3 and the second conductive material 11 may also be a plurality of metals.
  • the shapes of the first conductive material 3 and the second conductive material 11 may be linear or strip-shaped, and the first conductive material 3 and the second conductive material 11 are mainly conductive materials that can be connected by a wire bonding process.
  • the RF module body can cover the surface of each space on the substrate 5 by using an encapsulation process to cover the epoxy resin filling material 8 (also referred to as a molding compound).
  • the electrical connection region 1 and the grounding region 2 are all wrapped in the epoxy resin filling 8 so that the components of the RF module (single-chip RF module or multi-chip RF module) on the electrical connection region 1 are closely related to the substrate 5.
  • the integral sealing structure can be used to cut and separate the whole sealing structure into a separate packaged product according to the finished product size of the single RF module, and the packaged product is the RF module body, and one or more of the RF module body The side of the first conductive material is exposed on the side.
  • the metal thin film structure 4 may be a conductive metal composed of a single conductive material, such as a conductive metal such as gold, silver or copper; and the metal thin film structure 4 may also be a mixture of various conductive materials. Conductive alloys, such as alloys of gold and nickel, alloys of stainless steel and copper, and conductive alloys such as nickel and copper alloys.
  • the metal thin film structure 4 can be firmly adhered to the upper surface and the side surface of the radio frequency module body by using a metal film sputtering process of the package to form a metal thin film structure 4 (ie, a metal plating layer) having a thickness generally between 2 and 15 ⁇ m.
  • the metal film structure 4 does not significantly change the thickness and quality of the RF module body itself, and is integrated with the RF module body to form an inseparable integral structure, that is, the RF module for preventing electromagnetic interference provided by the present invention.
  • the method for implementing the anti-electromagnetic interference radio frequency module provided by the present invention is specifically described below with reference to FIG. 5 to FIG. 14 and a multi-chip radio frequency module disposed on the substrate 5 of the radio frequency module body.
  • Step S1 preparing a substrate and dividing different regions on the substrate
  • the substrate 5 may be a multi-layer circuit board, and the substrate 5 is provided with an electrical connection region 1, a ground region 2, and a dicing region 9. Specifically, as shown in FIG. 6 , three grounding regions may be disposed on the substrate 5, which are a wire bonding region 2a, a wire bonding region 2b, and a wire bonding region 2c, a wire bonding region 2a, a wire bonding region 2b, and The wire bonding regions 2c are grounded to form a ground region 2.
  • a scribe line region 9 for cutting and separating the independent RF module body is disposed at a periphery of the substrate 5, and a Threading region is disposed on the scribe channel region 9 located on either or more sides of the substrate 5, and the scribe line region 9 is disposed At least one wire area.
  • the wire bonding region 10a, the wire bonding region 10b, and the wire bonding region 10c may be respectively disposed on the dicing street region 9 on the left side, the right side, and the front side of the substrate 5.
  • the wire bonding area 2a, the wire bonding area 2b, and the wire bonding area 2c may be disposed at a position adjacent to the corresponding cutting track area 9, and preferably correspond to the position of the corresponding wire-bonding area in the cutting track area 9 to save conductive material.
  • the position, the number and the size of the grounding area and the wiring area provided in the dicing area 9 can be set according to the design requirements of the product and the packaging process capability.
  • Step S2 setting each component of the radio frequency module in an electrical connection region of the substrate
  • two different specifications of components can be disposed in the electrical connection region 1 of the substrate 5, wherein the first component is a component 7a-7e, and the second component is a component 7f. ⁇ h.
  • the first components 7a to 7e and the second components 7f to h are attached to the substrate 5 by a surface mounting process in a package, and the components 7a to 7e are electrically connected to the substrate 5, respectively.
  • two different functions of the chip may be provided.
  • the first functional chip is the chip 6a and the chip 6b
  • the second functional chip is the chip 6c.
  • the mounting process of the chip 6a and the chip 6b is attached to the substrate 5, and the chip 6c is flip-chip mounted to electrically connect the functional chip 6c directly to the substrate 5.
  • Step S3 electrically connecting the corresponding chip and the substrate, the grounding area and the corresponding wire-bonding area in the dicing area by using a conductive material;
  • the conductive material includes a first conductive material 3 and a second conductive material 11, and the first conductive material 3 and the second conductive material 11 may be made of a conductive line of a copper alloy.
  • the chip 6a and the chip 6b are electrically connected to the substrate 5 by using a plurality of second conductive materials 11 and using a wire bonding process.
  • the grounding regions 2a to 2c are electrically connected to the bonding regions 10a to 10c in the dicing region 9 by using one or more first conductive materials 3 and by a wire bonding process.
  • a plurality of electrical materials are electrically connected between the wire bonding area 2a and the wire bonding area 10a, the wire bonding area 2b and the wire bonding area 10b, and the wire bonding area 2c and the wire bonding area 10c are electrically connected.
  • the material is electrically connected. It should be emphasized that the shape and height of the line arc of the first conductive material 3 are not particularly required, and the connection direction of the first conductive material 3 may be from the grounding line area to the line area in the dicing area 9, or may be cut from The wire bonding area in the track area 9 goes to the grounding wire area, and the others follow the wire bonding process.
  • Step S4 filling the plastic sealing material to each corner of the radio frequency body, so that the components of the radio frequency module and the conductive material are wrapped in the molding compound;
  • a molding material 8 epoxy resin filler
  • a molding material 8 epoxy resin filler
  • the components 7a located on the substrate 5 are electrically connected to each other.
  • the chips 6a-6c and the first conductive material 3 and the second conductive material 11 are all wrapped in the molding compound, and the components 7a-7h and the chips 6a-6c are closely adhered to the substrate 5 to form an inseparable integral seal. structure.
  • Step S5 cutting the whole sealing structure into independent packaged products according to the finished product size of the single RF module by using a finished cutting process
  • the overall sealing structure in step S4 can be cut into individual packaged products according to the finished product size of the single RF module by using a finished cutting process, and the packaged product is the RF module body.
  • the scribe line region 9 is cut away, and the first conductive material 3 respectively connected to the corresponding grounded wire bonding region is cut to form a section 301 (as shown in FIG. 12), so that the first conductive material 3 Sections 301 are respectively exposed to respective faces of the body of the RF module on which they are located.
  • the three sides of the radio frequency module body provided in this embodiment respectively expose the cross section 301 of the first conductive material 3, and the cross section of the first conductive material 3 is used for electrically connecting with the metal thin film structure 4 to make the metal
  • the film structure 4 is electrically connected to the grounding region 2. It should be emphasized that the radio frequency module body is a completely independent individual separated by one-time cutting, and there is no connection of any form or part after cutting between the single radio frequency module bodies.
  • Step S6 converting the RF module body to the coating film on the coating fixture to form an RF module for preventing electromagnetic interference.
  • the independent radio frequency module body in the plurality of steps S5 is converted to the jig 12 for metal thin film sputtering (referred to as a coating jig) by using an adapter device, by making each of the independent
  • the upper surface of the RF module body (the side filled with the molding compound 8) faces upward, and there is a certain gap between each of the independent RF module bodies, so that the sides (four sides) of each RF module body are exposed.
  • the lower surface of the substrate 5 (the surface through which the components and the chip leads are pierced) is completely covered by the coating fixture 12.
  • the metal thin film structure 4 During the sputtering (coating) process of the metal thin film structure 4, only the five surfaces (the upper surface and the four sides) of the radio frequency module body exposed to the air are adhered by a conductive metal or a conductive alloy to form a metal of 2 to 15 ⁇ m thick.
  • the film structure 4, the lower surface of the covered substrate 5 is free from any conductive metal or conductive alloy.
  • the metal film structure 4 does not significantly change the thickness and quality of the RF module body itself, and is integrated with the RF module body to form an inseparable structure, that is, the RF module for preventing electromagnetic interference provided by the present invention. As shown in FIG.
  • the upper surface and the side metal film structure 4 of the radio frequency module body are directly electrically connected to the cross section 301 of the first conductive material 3 exposed on the side of the radio frequency body, so that the metal thin film structure 4 and the ground inside the radio frequency module body are grounded.
  • the area 2 is electrically connected to form an anti-electromagnetic interference shielding layer of the radio frequency body. That is, the cross section 301 of the first conductive material 3 exposed by the three sides of the radio frequency module body provided by the embodiment is electrically connected to the metal thin film structure 4, so that the metal thin film structure 4 and the grounding region 2 are electrically connected.
  • the metal thin film structure 4 is electrically connected to the grounding region 2 inside the radio frequency module body.
  • the anti-electromagnetic interference shielding layer of the radio frequency body can realize the function of anti-electromagnetic interference, thereby effectively isolating the electromagnetic interference generated around the radio frequency module, thereby improving the radio frequency module. Performance.
  • the anti-electromagnetic interference radio frequency module provided by the invention is provided with a grounding area and a dicing area on the substrate of the radio frequency body, and electrically connects the grounding area and the splicing area of the dicing area by the first conductive material, and is plastically sealed.
  • the material fill covers each space corner of the RF body to form an inseparable integral sealing structure.
  • One or more sides of the RF module body are exposed with a cross-section of the first conductive material by cutting the integral sealing structure into individual packaged products at the finished dimensions of the single RF module.
  • the metal film structure is directly connected to the grounding area inside the radio frequency body by providing a metal thin film structure on the upper surface and the side surface of the radio frequency body, thereby forming an anti-electromagnetic interference radio frequency module in which the metal thin film structure and the radio frequency module body are integrated.
  • the RF module combines the original RF module production process with the metal film sputtering process, and can form an anti-electromagnetic interference shielding layer required for the RF module in a simpler, more efficient, and more cost-effective manner.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种防电磁干扰的射频模块及其实现方法。该防电磁干扰的射频模块包括射频模块本体，射频模块本体内部设置有电性连接区域（1）与接地区域（2），射频模块本体的上表面与侧面附着金属薄膜结构（4），金属薄膜结构与接地区域导通，形成与射频模块本体融为一体的防电磁干扰屏蔽层结构。本射频模块通过防电磁干扰屏蔽层结构实现防电磁干扰的作用，使射频模块周围生成的电磁干扰被有效地隔离，从而提高射频模块的性能。同时，本射频模块将原有的射频模块生产过程与金属薄膜溅镀工艺组合，可以更简单高效和更具有制造成本优势地形成射频模块所需的防电磁干扰屏蔽层。

Description

一种防电磁干扰的射频模块及其实现方法 技术领域
本发明涉及一种射频模块，尤其涉及一种用于射频信号类产品、具有防电磁干扰功能的射频模块，同时也涉及该射频模块的实现方法，属于集成电路制造技术领域。
背景技术
射频信号类产品目前被广泛应用在消费类电子产品中。在不断更新换代的消费类电子产品中，各个功能模块的集成度越来越高。例如在手机中不可或缺的射频模块，该射频模块决定着手机信号接收的好坏。当集成度越高，周围对它产生的电磁干扰也越强，使射频模块本身的性能大打折扣。为了保证射频模块所需的性能匹配，需要使周围生成的电磁干扰能够被有效隔离。同时，在射频模块接收和输出信号的过程中，也需要让周围的电磁干扰降低或被有效隔离，从而增强射频模块接收/输出的有效信号的强度，提高射频模块的性能。
在现有技术中，通常采用电磁屏蔽结构使射频模块周围的电磁干扰降低或被有效隔离。传统的电磁屏蔽结构一般采用金属盖体罩盖于射频模块外围。在该电磁屏蔽结构的制备工艺中，金属盖体是以焊接方式连接于电路板，由于产品必须经过高温回焊步骤，有可能造成产品的隐藏性破坏。例如，由于防焊漆胶脱落造成锡窜流而短路。再者，上述高温回焊步骤也会造成生产端的工时增加、成本上升等问题。并且，为了组装上述金属盖体，必须加大产品占据的空间，从而导致产品尺寸会增加。
所以，鉴于上述传统的电磁屏蔽结构在实际使用时的缺点，需要提供一种设计合理且有效改善上述问题的屏蔽结构。
发明内容
本发明所要解决的首要技术问题在于提供一种防电磁干扰的射频模块。
本发明所要解决的另一技术问题在于提供一种上述射频模块的实现方法。
为了实现上述发明目的，本发明采用下述的技术方案：
根据本发明实施例的第一方面，提供一种防电磁干扰的射频模块，包括射频模块本体，所述射频模块本体内部设置有电性连接区域与接地区域，所述射频模块本体的上表面与侧面附着金属薄膜结构，所述金属薄膜结构与所述接地区域导通，形成与所述射频模块本体融为一体的防电磁干扰屏蔽层结构。
其中较优地，所述射频模块本体的一个或多个侧面暴露有第一导电材料断面，所述第一导电材料端面与所述金属薄膜结构连接，所述第一导电材料断面的相对端与所述接地区域连接，使所述金属薄膜结构与所述接地区域导通，形成所述射频模块本体的防电磁干扰屏蔽层结构。
其中较优地，所述射频模块本体包括基板，所述基板上设置有所述电性连接区域与所述接地区域，所述电性连接区域设置有单芯片射频模块或多芯片射频模块，所述单芯片射频模块或多芯片射频模块及相应的所述第一导电材料与第二导电材料包裹于所述环氧树脂填充物内，形成不可分割的整体密封结构。
其中较优地，所述基板包括但不限于单层电路板材、单层电路框架、多层集成的电路板材、多层集成的电路框架中的任意一种。
其中较优地，所述多芯片射频模块由多种功能芯片与元器件组成，所述单芯片射频模块由单功能芯片或者单功能芯片与元器件组成，所述功能芯片、所述元器件分别与所述基板电性连接。
其中较优地，所述第一导电材料、所述第二导电材料以及金属薄膜结构为具有单一导电特性的金属材料或者多种所述金属材料混合的具有导电特性的合金材料，并且所述第一导电材料与所述第二导电材料的形状为线状或条状。
根据本发明实施例的第二方面，提供一种防电磁干扰的射频模块的实现方法，包括如下步骤：
步骤S1：准备基板，并在基板上划分不同的区域；
步骤S2：在基板的电性连接区域设置射频模块的各组成部分；
步骤S3：采用导电材料使相应的芯片与基板、接地区域与切割道区域内相应的打线区域的电性连接；
步骤S4：将塑封料填充覆盖到射频本体的每个空间角落，使射频模块的各组成部分及导电材料包裹于塑封料内；
步骤S5：采用成品切割工艺将整体密封结构按单颗射频模块的成品尺寸切割出独立的封装成品；
步骤S6：将射频模块本体转换到镀膜治具上镀膜，形成防电磁干扰的射频模块。
其中较优地，步骤S1中，所述基板上设置至少一个接地的打线区域，所述打线区域分别接地，所述基板的外周设置有切割道区域，位于所述基板任意一侧或多侧的所述切割道区域上设置有打线区域。
其中较优地，步骤S2中，当所述射频模块中含有所述元器件时，所述元器件采用表面贴装工艺贴附所述基板上，使所述元器件分别与所述基板电性连接。
其中较优地，步骤S2中，当所述射频模块中含有所述功能芯片时，所述功能芯片采用贴装工艺贴附于所述基板上，或者所述功能芯片采用倒装工艺使所述功能芯片直接与所述基板电性连接。
其中较优地，步骤S3中，当所述功能芯片采用贴装工艺贴附于所述基板上时，所述功能芯片通过所述第二导电材料并利用引线键合工艺与所述基板电性连接；接地的打线区域通过所述第一导电材料并利用引线键合工艺分别对应与切割道区域内的打线区域电性连接。
其中较优地，步骤S5中，切割道区域被切除，分别与相应的接地的打线区域相连接的所述第一导电材料被切断形成断面，使所述第一导电材料的断面分别暴露于其所在的所述射频模块本体的相应面上。
其中较优地，步骤S6中，将多颗独立的所述射频模块本体转换到所述镀膜治具上，通过使每颗独立的所述射频模块本体的上表面朝上，且每颗独立的所述射频模块本体之间有预定间隙，使每颗所述射频模块本体的侧面暴露在空气中，而所述基板的下表面被所述镀膜治具完全遮盖，所述射频模块本体的上表面与侧面被金属薄膜结构附着，所述金属薄膜结构直接与所述射频本体侧面暴露的所述第一导电材料的断面电性连接，使所述金属薄膜结构与所述射频模块本体内部的接地区域电性连接，形成与所述射频本体融为一体的防电磁干扰屏蔽层。
本发明所提供的防电磁干扰的射频模块通过将射频模块本体与金 属薄膜结构融为一体，并且将金属薄膜结构与射频本体内部的接地区域通过第一导电材料导通，形成与射频模块本体融为一体的防电磁干扰屏蔽层结构。通过防电磁干扰屏蔽层结构实现防电磁干扰的作用，使射频模块周围生成的电磁干扰被有效隔离，从而提高射频模块的性能。同时，该射频模块将原有的射频模块生产过程与金属薄膜溅镀工艺组合，可以更简单高效和更具有制造成本优势地形成射频模块所需的防电磁干扰屏蔽层。
附图说明
图1为本发明所提供的防电磁干扰的射频模块的结构示意图；
图2为本发明所提供的防电磁干扰的射频模块中，采用多芯片射频模块的射频模块本体的结构示意图；
图3和图4为本发明所提供的防电磁干扰的射频模块中，采用单芯片射频模块的射频模块本体的结构示意图；
图5为本发明所提供的防电磁干扰的射频模块的实现方法流程图；
图6～图14为图5中所示的射频模块实现方法的工作过程示意图。
具体实施方式
下面结合附图和具体实施例对本发明的技术内容做进一步的详细说明。
如图1所示，本发明所提供的防电磁干扰的射频模块包括射频模块本体，在射频模块本体内部设置有电性连接区域1与接地区域2；在射频模块本体一个或多个侧面暴露有第一导电材料断面(如图12所示的第一导电材料断面301)，该第一导电材料断面的相对端与接地区域2连接，在射频模块本体的上表面与侧面附着金属薄膜结构4，使金属薄膜结构4与第一导电材料端面连接，实现将金属薄膜结构4与接地区域2导通，形成防电磁干扰屏蔽层结构。通过防电磁干扰屏蔽层结构实现将射频模块周围生成的电磁干扰被有效的隔离，从而提高射频模块的性能。
其中，射频模块本体是指具有射频功能的独立的封装成品。如图2～图4所示，该射频模块本体包括基底板材5(简称基板)，该基板5 可以是单层电路板材或框架，也可以是多层集成的电路板材或框架。在基板上设置有电性连接区域1与接地区域2。如图2所示，在电性连接区域1可以设置由多种功能芯片6、元器件7组成的多芯片射频模块；在电性连接区域1还可以设置由单功能芯片6组成的单芯片射频模块(图中未示出)；如图3和图4所示，在电性连接区域1还可以设置由单功能芯片6与元器件7组成的单芯片射频模块。其中，功能芯片6可以是单颗射频功能芯片，功能芯片也可以是多颗多种功能芯片的组合，例如，功能芯片可以是射频元件、功率放大器芯片、开关芯片、低噪声放大器芯片、滤波器等具有射频功能的芯片中的任意一种或多种。功能芯片6可以采用贴装工艺贴附在基板上，并采用一根或多根第二导电材料11通过引线键合工艺使功能芯片6与基板5电性连接；功能芯片6还可以采用倒装工艺使功能芯片直接与基板5电性连接。元器件7可以是电容、电阻、电感、滤波器等此类用封装表面贴装工艺使其贴附于基板5上的元器件(此种元器件也被称为SMT元器件)中的任意一种或多种。接地区域2的位置可以根据产品的设计需要和封装工艺能力进行设置，其大小也不受限制。该接地区域2与一根或多根第一导电材料3(第一导电材料断面的相对端)连接。第一导电材料3与第二导电材料11可以是具有单一导电特性的金属材料，如金、银、铜、铝等金属材料；第一导电材料3与第二导电材料11还可以是多种金属材料混合的具有导电特性的合金材料，如铜合金，银合金等合金材料。并且，第一导电材料3与第二导电材料11的形状可以是线状或条状，第一导电材料3与第二导电材料11主要是可以采用引线键合工艺进行连接的导电材料。
如图2～图4所示，射频模块本体通过采用包封工艺，可以将环氧树脂填充物8(也被称为塑封料)覆盖在基板5上的每一个空间角落上，使基板5上的电性连接区域1与接地区域2全部包裹于环氧树脂填充物8内，使电性连接区域1上的射频模块(单芯片射频模块或多芯片射频模块)的各组成部分与基板5紧密贴合，并使电性连接区域1上的射频模块的各个组成部分(单芯片射频模块或多芯片射频模块)及导电材料(第一导电材料3与第二导电材料11)全部包裹于环氧树脂填充物8内，形成不可分割的整体密封结构。该整体密封结构 可以采用封装中成品切割工艺将整体密封结构按单颗射频模块的成品尺寸切割分离出独立的封装成品，该封装成品即为射频模块本体，并且该射频模块本体的一个或多个侧面暴露有第一导电材料断面。
在本发明所提供的防电磁干扰的射频模块中，金属薄膜结构4可以是单一导电材料构成的导电金属，如金、银、铜等导电金属；金属薄膜结构4还可以是多种导电材料混合成的导电合金，如金与镍的合金、不锈钢与铜的合金、镍与铜合金等导电性合金。通过采用封装的金属薄膜溅镀工艺可以使金属薄膜结构4牢牢附着在射频模块本体的上表面与侧面，形成厚度一般在2～15um之间的金属薄膜结构4(即金属镀层)。该金属薄膜结构4对射频模块本体本身的厚度和质量不会产生明显的改变，且与射频模块本体融为一体，形成不可分离的整体结构，即本发明所提供的防电磁干扰的射频模块。
下面结合图5～图14，并以射频模块本体的基板5上设置有多芯片射频模块为典型实施例，具体说明本发明所提供的防电磁干扰的射频模块的实现方法。
步骤S1：准备基板，并在基板上划分不同的区域；
在本实施例所提供的防电磁干扰的射频模块中，基板5可以选用多层电路板，在基板5上设置有电性连接区域1、接地区域2以及切割道区域9。具体地，如图6所示，可以在基板5上设置三个接地的打线区域，分别为打线区域2a、打线区域2b以及打线区域2c，打线区域2a、打线区域2b以及打线区域2c分别接地，形成接地区域2。在基板5的外围设置有用于切割分离出独立的射频模块本体的切割道区域9，在位于基板5任意一侧或多侧的切割道区域9上设置有打线区域，切割道区域9上设置至少一个打线区域。例如，可以在位于基板5左侧、右侧及前侧的切割道区域9上分别设置打线区域10a、打线区域10b以及打线区域10c。打线区域2a、打线区域2b以及打线区域2c可以设置在临近相应的切割道区域9的位置上，并优选与切割道区域9内的相应的打线区域的位置对应，以节约导电材料的用量。其中，接地的打线区域与切割道区域9内设置的打线区域的位置、数量及大小可以根据产品的设计需要和封装工艺能力进行设置。
步骤S2：在基板的电性连接区域设置射频模块的各组成部分；
如图7所示，可以在基板5的电性连接区域1设置两种不同规格的元器件，其中，第一种元器件分别为元器件7a～7e，第二种元器件分别为元器件7f～h。将第一种元器件7a～7e与第二种元器件7f～h分别采用封装中的表面贴装工艺贴附于基板5上，使元器件7a～7e分别与基板5电性连接。在基板5的电性连接区域1设置完元器件后，还可以设置两种不同功能的芯片，第一种功能芯片分别为芯片6a和芯片6b，第二种功能芯片为芯片6c。其中，芯片6a和芯片6b贴装工艺贴附在基板5上，芯片6c采用倒装工艺使功能芯片6c直接与基板5电性连接。
步骤S3：采用导电材料使相应的芯片与基板、接地区域与切割道区域内相应的打线区域的电性连接；
如图8和图9所示，导电材料包括第一导电材料3与第二导电材料11，第一导电材料3与第二导电材料11可以采用铜合金的导电线。通过采用多根第二导电材料11并利用引线键合工艺可以实现将芯片6a和芯片6b与基板5电性连接。通过采用一根或多根第一导电材料3并利用引线键合工艺可以实现将接地的打线区域2a～2c分别对应与切割道区域9内的打线区域10a～10c电性连接。其中，打线区域2a和打线区域10a之间、打线区域2b和打线区域10b之间分别采用多根电性材料实现电性连接，打线区域2c和打线区域10c采用一根电性材料实现电性连接。需要强调的是，第一导电材料3的线弧形状及高度无特殊要求，第一导电材料3的连接方向可以从接地的打线区域到切割道区域9内的打线区域，也可从切割道区域9内的打线区域到接地的打线区域，其它遵循引线键合工艺即可。
步骤S4：将塑封料填充覆盖到射频本体的每个空间角落，使射频模块的各组成部分及导电材料包裹于塑封料内；
如图10所示，可以采用包封工艺将塑封料8(环氧树脂填充物)填充覆盖在基板5上的每一个空间角落上，使位于基板5上电性连接区域1的元器件7a～7h、芯片6a～6c以及第一导电材料3与第二导电材料11全部包裹于塑封料内，并使元器件7a～7h、芯片6a～6c与基板5紧密贴合，形成不可分割的整体密封结构。
步骤S5：采用成品切割工艺将整体密封结构按单颗射频模块的成 品尺寸切割出独立的封装成品；
如图11所示，可以采用成品切割工艺将步骤S4中的整体密封结构按单颗射频模块的成品尺寸切割出独立的封装成品，该封装成品即为射频模块本体。在此切割过程中，切割道区域9被切除，分别与相应的接地的打线区域相连接的第一导电材料3被切断形成断面301(如图12所示)，使第一导电材料3的断面301分别暴露于其所在的射频模块本体的相应面上。也就是在本实施例所提供的射频模块本体的三个侧面的会分别暴露出第一导电材料3的断面301，第一导电材料3的断面用于与金属薄膜结构4电性连接，使金属薄膜结构4与接地区域2电性连接。需要强调的是，此射频模块本体为一次性切割分离成的完整独立的个体，并且单颗射频模块本体之间切割后不存在任何形式、部位的连接。
步骤S6：将射频模块本体转换到镀膜治具上镀膜，形成防电磁干扰的射频模块。
如图13和图14所示，通过将多颗步骤S5中独立的射频模块本体使用转接装置转换到金属薄膜溅射用的治具12(简称镀膜治具)上，通过使每颗独立的射频模块本体的上表面(填充有塑封料8的一面)朝上，并且每颗独立的射频模块本体之间有一定的间隙，这样使得每颗射频模块本体的侧面(四个侧面)会暴露在空气中，而基板5的下表面(元器件、芯片引脚穿出的一面)被镀膜治具12完全遮盖。在进行金属薄膜结构4的溅镀(镀膜)过程中，只有射频模块本体暴露在空气中的五个表面(上表面及四个侧面)被导电金属或导电合金附着，形成2～15um厚的金属薄膜结构4，被遮盖住的基板5的下表面无任何导电金属或导电合金附着。该金属薄膜结构4对射频模块本体本身的厚度和质量不会产生明显的改变，且与射频模块本体融为一体，形成不可分离的结构，即本发明所提供的防电磁干扰的射频模块。如图14所示，位于射频模块本体的上表面及侧面金属薄膜结构4与射频本体侧面暴露的第一导电材料3的断面301直接电性连接，使金属薄膜结构4与射频模块本体内部的接地区域2电性连接，形成射频本体的防电磁干扰屏蔽层。也就是本实施例所提供的射频模块本体的三个侧面暴露出的第一导电材料3的断面301分别与金属薄膜结构4电性连 接，使金属薄膜结构4与接地区域2电性连接，使金属薄膜结构4与射频模块本体内部的接地区域2电性连接。当本发明所提供的防电磁干扰的射频模块工作时，通过射频本体的防电磁干扰屏蔽层可以实现防电磁干扰的作用，从而将射频模块周围生成的电磁干扰被有效的隔离，从而提高射频模块的性能。
本发明所提供的防电磁干扰的射频模块通过在射频本体的基板上分别设置接地区域及切割道区域，通过第一导电材料将接地区域与切割道区域的打线区域电性连接，并通过塑封料填充覆盖到射频本体的每个空间角落，形成不可分割的整体密封结构。通过将整体密封结构按单颗射频模块的成品尺寸切割出独立的封装成品，使射频模块本体的一个或多个侧面暴露有第一导电材料的断面。通过在射频本体的上表面及侧面设置金属薄膜结构，使金属薄膜结构直接与射频本体内部的接地区域电性连接，形成金属薄膜结构与射频模块本体融为一体的防电磁干扰的射频模块。同时，本射频模块将原有的射频模块生产过程与金属薄膜溅镀工艺组合，可以更简单高效和更具有制造成本优势地形成射频模块所需的防电磁干扰屏蔽层。
以上对本发明所提供的防电磁干扰的射频模块及其实现方法进行了详细的说明。对本领域的一般技术人员而言，在不背离本发明实质精神的前提下对它所做的任何显而易见的改动，都将属于本发明专利权的保护范围。

Claims (13)

  1. 一种防电磁干扰的射频模块，其特征在于包括射频模块本体，所述射频模块本体内部设置有电性连接区域与接地区域，所述射频模块本体的上表面与侧面附着金属薄膜结构，所述金属薄膜结构与所述接地区域导通，形成与所述射频模块本体融为一体的防电磁干扰屏蔽层结构。
  2. 如权利要求1所述的防电磁干扰的射频模块，其特征在于：
    所述射频模块本体的一个或多个侧面暴露有第一导电材料断面，所述第一导电材料端面与所述金属薄膜结构连接，所述第一导电材料断面的相对端与所述接地区域连接，使所述金属薄膜结构与所述接地区域导通，形成所述射频模块本体的防电磁干扰屏蔽层结构。
  3. 如权利要求1所述的防电磁干扰的射频模块，其特征在于：
    所述射频模块本体包括基板，所述基板上设置有所述电性连接区域与所述接地区域，所述电性连接区域设置有单芯片射频模块或多芯片射频模块，所述单芯片射频模块或多芯片射频模块及相应的所述第一导电材料与第二导电材料包裹于所述环氧树脂填充物内，形成不可分割的整体密封结构。
  4. 如权利要求3所述的防电磁干扰的射频模块，其特征在于：
    所述基板包括但不限于单层电路板材、单层电路框架、多层集成的电路板材、多层集成的电路框架中的任意一种。
  5. 如权利要求3所述的防电磁干扰的射频模块，其特征在于：
    所述多芯片射频模块由多种功能芯片与元器件组成，所述单芯片射频模块由单功能芯片或者单功能芯片与元器件组成，所述功能芯片、所述元器件分别与所述基板电性连接。
  6. 如权利要求3所述的防电磁干扰的射频模块，其特征在于：
    所述第一导电材料、所述第二导电材料以及金属薄膜结构为具有单一导电特性的金属材料或者多种所述金属材料混合的具有导电特性的合金材料，并且所述第一导电材料与所述第二导电材料的形状为线状或条状。
  7. 一种如权利要求1～6中任意一项所述的防电磁干扰的射频模 块的实现方法，包括如下步骤：
    步骤S1：准备基板，并在基板上划分不同的区域；
    步骤S2：在基板的电性连接区域设置射频模块的各组成部分；
    步骤S3：采用导电材料使相应的芯片与基板、接地区域与切割道区域内相应的打线区域的电性连接；
    步骤S4：将塑封料填充覆盖到射频本体的每个空间角落，使射频模块的各组成部分及导电材料包裹于塑封料内；
    步骤S5：采用成品切割工艺将整体密封结构按单颗射频模块的成品尺寸切割出独立的封装成品；
    步骤S6：将射频模块本体转换到镀膜治具上镀膜，形成防电磁干扰的射频模块。
  8. 如权利要求7所述的防电磁干扰的射频模块的实现方法，其特征在于：
    步骤S1中，所述基板上设置至少一个接地的打线区域，所述打线区域分别接地，所述基板的外周设置有切割道区域，位于所述基板任意一侧或多侧的所述切割道区域上设置有打线区域。
  9. 如权利要求7所述的防电磁干扰的射频模块的实现方法，其特征在于：
    步骤S2中，当所述射频模块中含有所述元器件时，所述元器件采用表面贴装工艺贴附所述基板上，使所述元器件分别与所述基板电性连接。
  10. 如权利要求7所述的防电磁干扰的射频模块的实现方法，其特征在于：
    步骤S2中，当所述射频模块中含有所述功能芯片时，所述功能芯片采用贴装工艺贴附于所述基板上，或者所述功能芯片采用倒装工艺使所述功能芯片直接与所述基板电性连接。
  11. 如权利要求7所述的防电磁干扰的射频模块的实现方法，其特征在于：
    步骤S3中，当所述功能芯片采用贴装工艺贴附于所述基板上时，所述功能芯片通过所述第二导电材料并利用引线键合工艺与所述基板电性连接；接地的打线区域通过所述第一导电材料并利用引线键合工 艺分别对应与切割道区域内的打线区域电性连接。
  12. 如权利要求7所述的防电磁干扰的射频模块的实现方法，其特征在于：
    步骤S5中，切割道区域被切除，分别与相应的接地的打线区域相连接的所述第一导电材料被切断形成断面，使所述第一导电材料的断面分别暴露于其所在的所述射频模块本体的相应面上。
  13. 如权利要求7所述的防电磁干扰的射频模块的实现方法，其特征在于：
    步骤S6中，将多颗独立的所述射频模块本体转换到所述镀膜治具上，通过使每颗独立的所述射频模块本体的上表面朝上，且每颗独立的所述射频模块本体之间有预定间隙，使每颗所述射频模块本体的侧面暴露在空气中，而所述基板的下表面被所述镀膜治具完全遮盖，所述射频模块本体的上表面与侧面被金属薄膜结构附着，所述金属薄膜结构直接与所述射频本体侧面暴露的所述第一导电材料的断面电性连接，使所述金属薄膜结构与所述射频模块本体内部的接地区域电性连接，形成与所述射频本体融为一体的防电磁干扰屏蔽层。
PCT/CN2018/093940 2017-06-08 2018-07-01 一种防电磁干扰的射频模块及其实现方法 WO2018224051A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/620,457 US11264335B2 (en) 2017-06-08 2018-07-01 Anti-electromagnetic interference radio frequency module and implementation method therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710429562.1 2017-06-08
CN201710429562.1A CN107342279A (zh) 2017-06-08 2017-06-08 一种防电磁干扰的射频模块及其实现方法

Publications (1)

Publication Number Publication Date
WO2018224051A1 true WO2018224051A1 (zh) 2018-12-13

Family

ID=60220590

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/093940 WO2018224051A1 (zh) 2017-06-08 2018-07-01 一种防电磁干扰的射频模块及其实现方法

Country Status (3)

Country Link
US (1) US11264335B2 (zh)
CN (1) CN107342279A (zh)
WO (1) WO2018224051A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107342279A (zh) * 2017-06-08 2017-11-10 唯捷创芯(天津)电子技术股份有限公司 一种防电磁干扰的射频模块及其实现方法
US10134687B1 (en) 2017-12-14 2018-11-20 Amkor Technology, Inc. Semiconductor device and method of manufacturing a semiconductor device
CN114615874A (zh) * 2018-04-13 2022-06-10 乾坤科技股份有限公司 屏蔽磁性装置
CN108417555A (zh) * 2018-04-28 2018-08-17 上海飞骧电子科技有限公司 一种防电磁干扰的射频模块结构及实现方法
KR101961316B1 (ko) * 2018-05-16 2019-03-25 썬시스템(주) 솔리드 스테이트 드라이브의 전자파 차폐 구조
CN110767630A (zh) * 2019-10-31 2020-02-07 中电海康无锡科技有限公司 SiP模块电磁屏蔽方法
CN113204936B (zh) * 2021-07-02 2021-09-17 苏州贝克微电子有限公司 一种自动添加环境稳定系统的芯片设计方法
CN114823651B (zh) * 2022-04-06 2023-04-07 杭州道铭微电子有限公司 一种带有滤波器的射频系统模块封装结构及方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105990317A (zh) * 2015-02-25 2016-10-05 晟碟信息科技（上海）有限公司 具有电磁干扰屏蔽层和半导体装置和其制造方法
CN106409781A (zh) * 2015-07-31 2017-02-15 株式会社东芝 半导体装置及其制造方法
CN106711124A (zh) * 2015-11-18 2017-05-24 艾马克科技公司 具有电磁干扰遮蔽的半导体装置
CN107342279A (zh) * 2017-06-08 2017-11-10 唯捷创芯(天津)电子技术股份有限公司 一种防电磁干扰的射频模块及其实现方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211898A (zh) * 2006-12-25 2008-07-02 郭士迪 具有静电防护、电磁隔离以及抗氧化的封装结构及其制造方法
TWI349357B (en) * 2007-05-30 2011-09-21 Advanced Semiconductor Eng Emi shielded semiconductor package and method for manufacturing the same
JP2010010441A (ja) * 2008-06-27 2010-01-14 Murata Mfg Co Ltd 回路モジュールの製造方法および回路モジュール
CN102376628A (zh) * 2010-08-17 2012-03-14 环旭电子股份有限公司 系统封装模块的制造方法及其封装结构
CN102655096A (zh) * 2011-03-03 2012-09-05 力成科技股份有限公司 芯片封装方法
US8987872B2 (en) * 2013-03-11 2015-03-24 Qualcomm Incorporated Electromagnetic interference enclosure for radio frequency multi-chip integrated circuit packages
CN104409446A (zh) * 2014-10-24 2015-03-11 苏州日月新半导体有限公司 采用引线键合的仿形屏蔽结构及其制作工艺
US10477687B2 (en) * 2016-08-04 2019-11-12 Samsung Electronics Co., Ltd. Manufacturing method for EMI shielding structure
KR102572559B1 (ko) * 2017-01-25 2023-09-01 삼성전자주식회사 전자파 차폐구조

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105990317A (zh) * 2015-02-25 2016-10-05 晟碟信息科技（上海）有限公司 具有电磁干扰屏蔽层和半导体装置和其制造方法
CN106409781A (zh) * 2015-07-31 2017-02-15 株式会社东芝 半导体装置及其制造方法
CN106711124A (zh) * 2015-11-18 2017-05-24 艾马克科技公司 具有电磁干扰遮蔽的半导体装置
CN107342279A (zh) * 2017-06-08 2017-11-10 唯捷创芯(天津)电子技术股份有限公司 一种防电磁干扰的射频模块及其实现方法

Also Published As

Publication number Publication date
CN107342279A (zh) 2017-11-10
US11264335B2 (en) 2022-03-01
US20210082833A1 (en) 2021-03-18

Similar Documents

Publication Publication Date Title
WO2018224051A1 (zh) 一种防电磁干扰的射频模块及其实现方法
US20230020310A1 (en) Impedance Controlled Electrical Interconnection Employing Meta-Materials
TWI438885B (zh) 半導體封裝件及其製法
US20180096967A1 (en) Electronic package structure and method for fabricating the same
CN101800215B (zh) 无线通讯模组封装构造
CN102543937B (zh) 一种芯片上倒装芯片封装及制造方法
JPH0817964A (ja) 半導体装置及びその製造方法及び基板
CN101998213B (zh) 一种mems麦克风的封装结构及晶圆级封装方法
US10854560B2 (en) Semiconductor device and semiconductor device manufacturing method
CN112234048B (zh) 电磁屏蔽模组封装结构和电磁屏蔽模组封装方法
KR20110020548A (ko) 반도체 패키지 및 그의 제조방법
US10923444B1 (en) Semiconductor device
JPH07307413A (ja) 半導体装置
JP3417388B2 (ja) 半導体装置
CN102403236B (zh) 芯片外露的半导体器件及其生产方法
US20030071332A1 (en) Semiconductor packaging structure
CN102709199B (zh) 包覆基板侧边的模封阵列处理方法
US9704812B1 (en) Double-sided electronic package
US20030151123A1 (en) Semiconductor die package having two die paddles
CN114337587A (zh) 一种滤波器系统级混合封装模组及封装方式
TWI467729B (zh) 射頻模組之封裝結構及其製造方法
CN104681544A (zh) 多芯片qfn封装结构
JP2003179181A (ja) 樹脂製配線基板
JP3446695B2 (ja) 半導体装置
CN106298749B (zh) 发光二极管、电子器件及其制作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18813232

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18813232

Country of ref document: EP

Kind code of ref document: A1