WO2018223767A1 - 像素电路及其驱动方法、显示面板 - Google Patents

像素电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2018223767A1
WO2018223767A1 PCT/CN2018/082632 CN2018082632W WO2018223767A1 WO 2018223767 A1 WO2018223767 A1 WO 2018223767A1 CN 2018082632 W CN2018082632 W CN 2018082632W WO 2018223767 A1 WO2018223767 A1 WO 2018223767A1
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Prior art keywords
voltage
transistor
node
scan signal
driver
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PCT/CN2018/082632
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English (en)
French (fr)
Inventor
玄明花
陈小川
杨盛际
卢鹏程
王磊
付杰
肖丽
Original Assignee
京东方科技集团股份有限公司
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Priority to EP18814246.7A priority Critical patent/EP3637405B1/en
Priority to US16/330,639 priority patent/US10937367B2/en
Publication of WO2018223767A1 publication Critical patent/WO2018223767A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0238—Improving the black level

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display panel.
  • the organic electroluminescent display (English name: Organic Light-Emitting Diode, OLED) is made of low temperature polysilicon (English name: Low Temperature Poly Silicon, LTPS). Because the LTPS crystal particles are irregular, It is necessary to perform pixel compensation for each pixel in the OLED, thereby eliminating unevenness of the LTPS crystal particles on the channel of each driving thin film transistor (English name: Driving Thin Film Transistor, DTFT), and thus uneven brightness of each pixel. The problem.
  • OLED Organic Light-Emitting Diode
  • LTPS Low Temperature Poly Silicon
  • an embodiment of the present disclosure provides a pixel circuit, including: a node control circuit, a driver, a display sub-circuit, a threshold compensator, and a resetter;
  • the node control circuit is configured to receive a first scan signal, a second scan signal, a third scan signal, a reference voltage, and a data voltage, the node control circuit further configured to be at a voltage or a second scan of the first scan signal Outputting the reference voltage to the first node under control of a voltage of the signal, or outputting the data voltage to the first node under control of a voltage of the third scan signal;
  • An input of the driver is configured to receive a first level signal, and the driver is further configured to output a driving current at an output of the driver under control of a voltage of the first level signal and a voltage of a second node ;
  • the display subcircuit is coupled to the resetter and an output of the driver, the display subcircuit is configured to receive a second level signal and the second scan signal, and the display subcircuit is further configured to be in the Displaying the gray scale by the driving current under the control of the voltage of the second scan signal;
  • the threshold compensator connects the first node, an output of the driver, and a second node, the threshold compensator is configured to receive the third scan signal and a fourth scan signal, and the threshold compensator is further configured Adjusting a voltage of the second node to a sum of a voltage of the first level signal and a threshold voltage of the driver under control of a voltage of the third scan signal or a voltage of the fourth scan signal, and Adjusting a voltage of the second node to a voltage of the first level signal, a threshold voltage of the driver, and the reference voltage under control of a voltage of the first node and a voltage of an output of the driver And the difference from the data voltage;
  • the resetter is coupled to the second node and the display sub-circuit, the resetter is configured to receive a reset voltage signal, the first scan signal, and the third scan signal, the resetter further configured to The second node is reset by the voltage of the reset voltage signal under the control of the voltage of the first scan signal, and the voltage pair of the reset voltage signal is controlled under the control of the voltage of the third scan signal
  • the display sub-circuit is reset;
  • the first node is an intersection between an output end of the node control circuit and an input end of the threshold compensator
  • the second node is an intersection between an output of the threshold compensator, an input of the driver, and an output of the resetter.
  • the node control circuit includes: a first transistor, a second transistor, and a third transistor;
  • a first pole of the first transistor is configured to receive the reference voltage
  • a second pole of the first transistor is connected to the first node
  • a gate of the first transistor is configured to receive the first scan signal
  • a first pole of the second transistor is configured to receive the reference voltage
  • a second pole of the second transistor is coupled to the first node
  • a gate of the second transistor is configured to receive the second scan signal
  • a first pole of the third transistor is configured to receive the data voltage
  • a second pole of the third transistor is coupled to the first node
  • a gate of the third transistor is configured to receive the third scan signal .
  • the threshold compensator includes: a fourth transistor, a fifth transistor, and a first capacitor;
  • a first pole of the fourth transistor is connected to an output end of the driver, a second pole of the fourth transistor is connected to the second node, and a gate of the fourth transistor is configured to receive the third scan signal ;
  • a first pole of the fifth transistor is connected to an output end of the driver, a second pole of the fifth transistor is connected to the second node, and a gate of the fifth transistor is configured to receive the fourth scan signal ;
  • the first pole of the first capacitor is connected to the first node, and the second pole of the first capacitor is connected to the second node.
  • the fourth transistor and the fifth transistor share a source, a drain, and an active layer
  • a gate of the fourth transistor and a gate of the fifth transistor are respectively located on both sides of the active layer.
  • the gate of the fourth transistor and the gate of the fifth transistor coincide in a projection in a direction perpendicular to the active layer.
  • a first insulating layer is further disposed between the gate of the fifth transistor and the active layer; and a second insulating layer is further disposed between the gate of the fourth transistor and the active layer a third insulating layer is further disposed between the gate and the source and the drain of the fourth transistor; and the source and the drain pass through the second insulating layer and the third insulating layer A hole is in contact with the active layer.
  • the first pole of the first capacitor and the gate of the fourth transistor are formed by the same patterning process, and the second pole of the first capacitor is the same as the gate of the fifth transistor Sub-patterning process is formed;
  • first pole of the first capacitor and the gate of the fifth transistor are formed by the same patterning process, and the second pole of the first capacitor and the gate of the fourth transistor pass the same patterning Process production is formed.
  • the resetter includes: a sixth transistor and a seventh transistor;
  • a first pole of the sixth transistor is configured to receive the reset voltage signal
  • a second pole of the sixth transistor is coupled to the second node
  • a gate of the sixth transistor is configured to receive the first scan signal
  • the first pole of the seventh transistor is configured to receive the reset voltage signal
  • the second pole of the seventh transistor is connected to the display sub-circuit
  • the gate of the seventh transistor is configured to receive the third scan signal
  • the driver is a driving transistor, an input end of the driver is a source of the driving transistor, a control end of the driver is a gate of the driving transistor, and an output end of the driver is a drain of the driving transistor.
  • the display subcircuit includes: an eighth transistor and a light emitting diode;
  • a first pole of the eighth body tube is connected to an output end of the driver, a second pole of the eighth transistor is connected to an anode of the light emitting diode, and a gate of the eighth transistor is configured to receive the second Scanning signal
  • a cathode of the light emitting diode is configured to receive the second level signal.
  • the third scan signal is an output signal of the nth stage shift register in the shift register circuit; and the fourth scan signal is an output signal of the n+1th stage shift register in the shift register circuit; n is a positive integer.
  • a second aspect provides a driving method of a pixel circuit for driving the pixel circuit according to any one of the first aspects, the method comprising:
  • the node control circuit outputs the reference voltage to the first node under control of a voltage of the first scan signal;
  • the resetter is under the control of a voltage of the first scan signal Resetting the second node by a voltage of the reset voltage signal;
  • the node control circuit outputs the data voltage to the first node under control of a voltage of the third scan signal; and controlling the voltage of the third scan signal by the threshold compensator And adjusting a voltage of the second node to a sum of a voltage of the first level signal and a threshold voltage of the driver; and the reset module passes the reset voltage signal under the control of a voltage of the third scan signal The voltage resets the display sub-circuit;
  • the threshold compensator adjusts a voltage of the second node to a sum of a voltage of the first level signal and a threshold voltage of the driver under the control of a voltage of the fourth scan signal;
  • the node control circuit outputs the reference voltage to the first node under control of a voltage of the second scan signal; the voltage of the threshold compensator at the first node and the The voltage of the second node is adjusted to a voltage of the first level signal, a threshold voltage of the driver, and a difference between a sum of the reference voltage and the data voltage under control of a voltage at an output of the driver;
  • the driver outputs a driving current at an output of the driver under the control of a voltage of the first level signal and a voltage of the second node; control of a voltage of the display sub-circuit at the second scan signal
  • the display gray scale is driven by the drive current.
  • a display panel including the pixel circuit described above.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 3 is a flow chart of steps of a method for driving a pixel circuit according to an embodiment of the present disclosure
  • FIG. 4 is a signal timing state diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a fourth and fifth transistor according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a fourth and fifth transistor according to an embodiment of the present disclosure.
  • FIG. 7 is a flow chart of steps of a method for fabricating a pixel circuit according to an embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices having the same characteristics.
  • the transistors employed in the embodiments of the present disclosure mainly include switching transistors and driving transistors according to the functions in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable. In the embodiment of the present disclosure, in order to distinguish the two poles of the transistor except the gate, one of the poles is referred to as a source and the other pole is referred to as a drain. According to the form in the drawing, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistor used in the embodiment of the present disclosure includes a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level, and the N-type switching transistor is turned off. It is turned on when the gate is high and turned off when the gate is low.
  • the driving transistor includes a P-type and an N-type, wherein the P-type driving transistor is in an amplified state when the gate voltage is low (the gate voltage is less than the source voltage), and the absolute value of the gate-source voltage difference is greater than the threshold voltage Or saturated state.
  • the gate voltage of the N-type driving transistor is at a high level (the gate voltage is greater than the source voltage), and the absolute value of the gate-source voltage difference is greater than the threshold voltage, and is in an amplified state or a saturated state.
  • the pixel circuit includes a node control circuit node control circuit 11 , a driver 12 , a display sub-circuit 13 , a threshold compensator 14 , and a resetter 15 .
  • the node control circuit node control circuit 11 is configured to receive the first scan signal S1, the second scan signal S2, the third scan signal S3, the reference voltage Vref, and the data voltage Vdata, and the node control circuit node control circuit 11 is further configured to be at the first
  • the reference voltage Vref is output to the first node N1 under the control of the voltage of the scan signal S1 or the voltage of the second scan signal S2, or the data voltage Vdata is output to the first node N1 under the control of the voltage of the third scan signal S3.
  • the input terminal I of the driver 12 is configured to receive the first level signal V1, the control terminal Q of the driver 12 is connected to the second node N2, and the driver 12 is further configured to be at the voltage of the first level signal V1 and the voltage of the second node N2.
  • the drive current is output at the output O of the driver 12 under control.
  • the display sub-circuit 13 is connected to the resetter 15 and the output terminal O of the driver 12.
  • the display sub-circuit 13 is configured to receive the second level signal V2 and the second scan signal S2, and the display sub-circuit 13 is further configured to be in the second scan signal S2. Under the control of the voltage, the display gray scale is driven by the drive current.
  • the threshold compensator 14 is connected to the first node N1, the output terminal O of the driver 12, and the second node N2, and the threshold compensator 14 is configured to receive the third scan signal S3 and the fourth scan signal S4.
  • the threshold compensator 14 is further configured to be in the third
  • the voltage of the second node N2 is adjusted to the sum of the voltage of the first level signal V1 and the threshold voltage of the driver 12 under the control of the voltage of the scan signal S3 or the voltage of the fourth scan signal S4, and the voltage at the first node N1.
  • the voltage of the second node N2 is adjusted to the difference between the sum of the voltage of the first level signal V1, the threshold voltage of the driver 12, and the reference voltage Vref and the data voltage Vdata under the control of the voltage of the output terminal O of the driver 12.
  • the resetter 15 is connected to the second node N2 and the display sub-circuit 13.
  • the resetter 15 is configured to receive the reset voltage signal Vinit, the first scan signal S1 and the third scan signal S3, and the resetter 15 is further configured to be at the first scan signal S1.
  • the second node N2 is reset by the voltage of the reset voltage signal Vinit and the display sub-circuit 13 is reset by the voltage of the reset voltage signal Vinit under the control of the voltage of the third scan signal S3.
  • first node N1 is an intersection between the output end of the node control circuit 11 and the input end of the threshold compensator 14, and the second node N2 is an output end of the threshold compensator 14, an input end of the driver 21, and The intersection between the outputs of the resetter 15.
  • the pixel circuit provided by the embodiment of the present disclosure includes a node control circuit 11, a threshold compensator 14, a resetter 15, a driver 21, and a display sub-circuit 13. Since the threshold compensator 14 can adjust the voltage of the second node N2 to the sum of the voltage of the first level signal V1 and the threshold voltage of the driver 12 under the control of the voltage of the third scan signal S3 or the voltage of the fourth scan signal S4. That is, the pixel circuit provided by the embodiment of the present disclosure may read the threshold voltage of the driver 12 when the third level signal or the fourth level signal is a valid signal, and thus embodiments of the present disclosure may increase the threshold of the prime circuit read driver. The length of the voltage, which in turn solves the problem that the pixel circuit cannot read the threshold voltage of the driver.
  • the node control circuit 11 includes a first transistor T1, a second transistor T2, and a third transistor T3.
  • the first pole of the first transistor T1 is configured to receive the reference voltage Vref
  • the second pole of the first transistor T1 is coupled to the first node N1
  • the gate of the first transistor T1 is configured to receive the first scan signal S1.
  • the first pole of the second transistor T2 is configured to receive the reference voltage Vref
  • the second pole of the second transistor T2 is coupled to the first node N1
  • the gate of the second transistor T2 is configured to receive the second scan signal S2.
  • the first pole of the third transistor T3 is configured to receive the data voltage Vdata
  • the second pole of the third transistor T3 is coupled to the first node N1
  • the gate of the third transistor T3 is configured to receive the third scan signal S3.
  • the threshold compensator 14 includes a fourth transistor T4, a fifth transistor T5, and a first capacitor C1.
  • the first transistor of the fourth transistor T4 is connected to the output terminal O of the driver 12, the second electrode of the fourth transistor T4 is connected to the second node N2, and the gate of the fourth transistor T4 is configured to receive the third scan signal S3.
  • the first terminal of the fifth transistor T5 is connected to the output terminal O of the driver 12, the second electrode of the fifth transistor T5 is connected to the second node N2, and the gate of the fifth transistor T5 is configured to receive the fourth scan signal S4.
  • the first pole of the first capacitor C1 is connected to the first node N1, and the second pole of the first capacitor C1 is connected to the second node N2.
  • the resetter 15 includes a sixth transistor T6 and a seventh transistor T7.
  • the first pole of the sixth transistor T6 is configured to receive the reset voltage signal Vinit
  • the second pole of the sixth transistor T6 is coupled to the second node N2
  • the gate of the sixth transistor T6 is configured to receive the first scan signal S1.
  • the first pole of the seventh transistor T7 is configured to receive the reset voltage signal Vinit
  • the second pole of the seventh transistor T7 is coupled to the display sub-circuit 13
  • the gate of the seventh transistor T7 is configured to receive the third scan signal S3.
  • the driver 12 is a driving transistor DTFT
  • the input terminal I of the driver 12 is the source of the driving transistor DTFT
  • the control terminal Q of the driver 12 is the gate of the driving transistor DTFT
  • the output terminal O of the driver 12 is the drain of the driving transistor DTFT.
  • the display sub-circuit 13 includes an eighth transistor T8 and a light emitting diode D1.
  • the first pole of the eighth body tube T8 is connected to the output terminal O of the driver 12
  • the second pole of the eighth transistor T8 is connected to the anode of the light emitting diode D1
  • the gate of the eighth transistor T8 is configured to receive the second scan signal S2.
  • the cathode of the light emitting diode D1 is configured to receive the second level signal V2.
  • An embodiment of the present disclosure further provides a driving method of the above pixel circuit. Specifically, referring to FIG. 3, the method includes the following steps:
  • the first stage, the node control circuit outputs the reference voltage to the first node under the control of the voltage of the first scan signal; the resetter passes the voltage of the reset voltage signal to the second node under the control of the voltage of the first scan signal Reset.
  • the node control circuit outputs the data voltage to the first node under the control of the voltage of the third scan signal; and the threshold compensator adjusts the voltage of the second node to the first control under the control of the voltage of the third scan signal.
  • the third stage, the threshold compensator adjusts the voltage of the second node to a sum of a voltage of the first level signal and a threshold voltage of the driver under the control of the voltage of the fourth scan signal.
  • the fourth stage, the node control circuit outputs the reference voltage to the first node under the control of the voltage of the second scan signal; the threshold compensator controls the second node under the control of the voltage of the first node and the voltage of the output of the driver
  • the voltage is adjusted to the voltage of the first level signal, the threshold voltage of the driver, and the difference between the sum of the reference voltage and the data voltage; the driver is at the output of the driver under the control of the voltage of the first level signal and the voltage of the second node
  • the driving current is output; the display sub-circuit drives the display gray scale by the driving current under the control of the voltage of the second scanning signal.
  • FIG. 4 includes signal timing states of the first scan signal S1, the second scan signal S2, the third scan signal S3, and the fourth scan signal S4. Further, the first level signal V1 provides a high level Vdd, and the second level signal V2 is grounded to provide Vss. Illustratively, the second level signal V2 can be grounded.
  • t1 first phase
  • t2 second phase
  • t3 third phase
  • t4 fourth phase
  • the first scan signal S1 is low level
  • the second scan signal S2, the third scan signal S3, and the fourth scan signal S4 are high level, so the first transistor T1 and the sixth transistor T6 are turned on, and the remaining transistors are cutoff.
  • the reference voltage Vref is connected to the first node N1 through the first transistor T1, so the voltage of the first node N1 at this stage is the reference voltage Vref.
  • the reset voltage signal Vinit is connected to the second node N2 through the sixth transistor T6, so the voltage of the second node N2 is the voltage of the reset voltage signal Vinit at this stage, and the first pole and the second pole of the first capacitor C1 are respectively connected to the first The node N1 and the second node N2, so the voltages of the first pole and the second pole of the first capacitor C1 are also the voltages of the reference voltage Vref and the reset voltage signal Vinit, respectively. Since this phase resets the voltages of the first phase N1 and the second phase N2 to a constant voltage, the first phase is also referred to as a reset phase.
  • the third scan signal S3 is low level, and the first scan signal S1, the second scan signal S2, and the fourth scan signal S4 are at a high level, so the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are led. Pass, the rest of the transistors are turned off.
  • the data voltage Vdata is connected to the first node N1 through the third transistor T3, and the voltage of the first node N1 is jumped from the reference voltage Vref of the first stage to the data voltage Vdata.
  • the fourth transistor T4 since the fourth transistor T4 is turned on, the gate of the driving transistor DTFT is connected to the drain, and the gate-source voltage difference of the driving transistor DTFT is equal to the threshold voltage of the driving transistor, so the voltage of the second node N2 jumps to the first level signal.
  • the seventh transistor T7 since the seventh transistor T7 is turned on, the reset voltage signal Vinit at this stage also resets the voltage of the anode of the light-emitting diode D1 to the voltage of the reset voltage signal Vinit through the seventh transistor T7.
  • the threshold read time of the driving transistor DTFT of each pixel is less than 5 us, and the higher the resolution, the shorter the threshold voltage reading time of the driving transistor DTFT of each pixel.
  • This phase mainly functions to read the threshold voltage of the driving transistor, so this phase is also called the threshold reading phase.
  • the fourth scan signal S4 is low level, and the first scan signal S1, the second scan signal S2, and the third scan signal S3 are at a high level, so the fifth transistor T5 is turned on, and the remaining transistors are turned off. Since the first transistor T1, the second transistor T2, and the third transistor T3 are both turned off, the first pole of the first capacitor C1 has no discharge path, and the voltage remains the data voltage of the previous stage. Similar to the second phase, and because the fifth transistor T5 is turned on, the gate of the driving transistor DTFT is connected to the drain, and the gate-source voltage difference of the driving transistor DTFT is equal to the threshold voltage of the driving transistor DTFT, so the voltage of the second node N2 is jumped. The sum of the voltage of the first level signal V1 and the threshold voltage of the driving transistor DTFT.
  • This phase mainly serves to supplement the threshold voltage of the read drive transistor DTFT, also known as the threshold complementary read phase.
  • the embodiment of the present disclosure can increase the length of time during which the pixel circuit reads the threshold voltage of the driver, thereby solving the problem that the pixel circuit may not be able to read the threshold voltage of the driver.
  • the second scan signal S2 is low level, the first scan signal S1, the third scan signal S3, and the fourth scan signal S4 are at a high level, so the second transistor T2 and the eighth transistor T8 are turned on, and the remaining transistors are cutoff.
  • the reference voltage Vref is connected to the first node through the second transistor T2, and thus the voltage of the first node N1 becomes the reference voltage Vref.
  • the voltage of the second node N2 becomes the voltage of the first level signal, the threshold voltage of the driver, and the difference between the sum of the reference voltage and the data voltage.
  • the current flowing into the OLED can be obtained from the TFT saturation current formula:
  • I OLED K(V gs -V th ) 2
  • W is the channel width of the driving transistor DTFT.
  • L is the channel length of the driving transistor DTFT.
  • V gs is the voltage difference between the gate voltage and the source voltage of the driving transistor DTFT.
  • Vth drives the threshold voltage of the transistor DTFT.
  • the gate voltage of the driving transistor DTFT is equal to the voltage of the second node N2, the gate voltage of the driving transistor DTFT is:
  • V g V1+V th +Vref-Vdata
  • V1 is the voltage of the first level signal.
  • Vref is the reference voltage terminal.
  • Vdata is the data voltage.
  • the voltage difference between the gate voltage and the source voltage of the driving transistor DTFT is:
  • the operating current of the OLED is not affected by the threshold voltage of the driving transistor DTFT, and is only related to the data voltage and the reference voltage, so that the threshold voltage drift of the driving transistor due to the process process and long-time operation can be solved.
  • the problem is to eliminate its influence on the current flowing into the OLED and ensure the normal operation of the OLED.
  • all the transistors in the pixel circuit in the above embodiment may also be N-type transistors whose gates are turned on at a high level. If all the transistors are N-type transistors, only the timing of each scanning signal of the pixel circuit needs to be re-adjusted.
  • the state can be, for example, adjusting the first clock signal signal of the t1 phase in FIG. 4 to be adjusted to a high level, adjusting the second clock signal signal of the t1 phase to a low level, and adjusting other signals to a timing signal having opposite phases.
  • an N-type transistor and a P-type transistor can also be used at the same time.
  • Reasonable variations that can be made by the skilled person in accordance with the embodiments of the present disclosure are therefore intended to be the scope of protection of the present disclosure.
  • the active layer doping materials of different types of transistors are different, The use of a uniform type of transistor in the pixel circuit is more conducive to simplifying the process of the pixel circuit.
  • the fourth transistor T4 and the fifth transistor T5 in the pixel circuit shown in FIG. 2 may further share the source 51, the drain 52, and the active layer 53.
  • the gate G4 of the fourth transistor T4 and the gate G5 of the fifth transistor T5 are respectively located on both sides of the active layer 53.
  • the active layer 53 may be a polysilicon layer.
  • the gate of the fourth transistor T4 is located on the upper side of the active layer 53 and the gate of the fifth transistor T5 is located on the lower side of the active layer 53 in FIG. 5 , but the embodiment of the present disclosure is described. It is not limited to this. In some embodiments of the present disclosure, the gate of the fourth transistor T4 may also be located on the lower side of the active layer 53, and the gate of the fifth transistor T5 may also be located on the upper side of the active layer 53.
  • the gate G4 of the fourth transistor T4 and the gate G5 of the fifth transistor T5 coincide in a projection in a direction perpendicular to the active layer 53.
  • the fourth transistor T4 and the fifth transistor T5 Since the active layer 53 is sensitive to light intensity, when the inside of the display panel or external light is irradiated on the active layer 53, the fourth transistor T4 and the fifth transistor T5 generate leakage current. Since the gate G4 of the fourth transistor T4 and the gate G5 of the fifth transistor T5 coincide with the projection in the direction perpendicular to the active layer 53 in the embodiment of the present disclosure, the gate G4 and the fifth transistor of the fourth transistor are The gates G5 can serve as a light blocking layer for each other, thereby reducing leakage currents of the fourth transistor T4 and the fifth transistor T5, and ensuring accurate compensation of the threshold voltage of the driving transistor.
  • a first insulating layer GI1 is further disposed between the gate G5 of the fifth transistor T5 and the active layer 53.
  • a second insulating layer GI2 is further disposed between the gate G4 of the fourth transistor T4 and the active layer 53.
  • a third insulating layer GI3 is further disposed between the gate G4 of the fourth transistor T4 and the source 51 and the drain 52. The source 51 and the drain 52 are in contact with the active layer 53 through through holes penetrating the second insulating layer GI2 and the third insulating layer GI3.
  • the gate G4 of the fourth transistor T4 and the gate G5 of the fifth transistor T5 are not in the same gate metal layer, the gate G4 of the fourth transistor T4 and the gate G5 of the fifth transistor T5 are formed. It needs to be made separately by one patterning process. This will increase the process flow of the pixel circuit, thereby increasing the manufacturing cost of the pixel circuit.
  • the capacitor medium needs to be disposed between the two stages of the first capacitor C1, the first pole and the second pole of the first capacitor C1 also need to be fabricated by one patterning process.
  • the first and second poles of the first capacitor C1 are formed by the same patterning process as the gate G4 of the fourth transistor T4 and the gate G5 of the fifth transistor T5, respectively.
  • the first pole of the first capacitor C1 and the gate G4 of the fourth transistor T4 may be formed by the same patterning process, and the second pole of the first capacitor C1 and the gate G5 of the fifth transistor T5 pass the same patterning.
  • Process production is formed.
  • the second pole of the first capacitor C1 and the gate G4 of the fourth transistor T4 may be formed by the same patterning process, and the first pole of the first capacitor C1 and the gate G5 of the fifth transistor T5 pass the same patterning process. Production formation.
  • the manufacturing process of the pixel circuit can be reduced. In turn, the manufacturing cost of the pixel circuit is reduced.
  • the third scan signal in the foregoing embodiment is an output signal of the nth stage shift register in the shift register circuit.
  • the fourth scan signal is an output signal of the n+1th stage shift register in the shift register circuit.
  • n is a positive integer.
  • the third scan signal is substantially a signal received by the third scan end
  • the output signal of the fourth scan end is substantially a signal received by the fourth scan end.
  • the nth stage shift register in the shift register circuit is connected to the third scan terminal in the nth row of pixel circuits in the display panel, that is, the nth shift in the shift register circuit
  • the output signal of the bit register is a signal received by the third scan terminal in the nth row of pixel circuits in the display panel.
  • the n+1th stage shift register in the shift register circuit is connected to the fourth scan end of the nth row pixel circuit in the display panel, that is, the output signal of the n+1th stage shift register in the shift register circuit is a display panel. a signal received by a fourth scan end of the nth row of pixel circuits.
  • the process and cost of separately manufacturing the drive circuits of the third scan terminal S3 and the fourth scan terminal S4 are eliminated, thereby further simplifying the pixel.
  • the manufacturing process of the circuit reduces the manufacturing cost of the pixel circuit.
  • an embodiment of the present disclosure further provides a method for fabricating a pixel circuit for fabricating a fourth transistor T4 and a fifth transistor T5 in any of the above pixel circuits. Specifically, referring to Figure 7, the method includes:
  • the primary patterning process mainly includes the steps of film formation, glue coating, exposure, development, etching, and stripping.
  • Film formation refers to a process of forming a thin film of a base material on a substrate by magnetron sputtering, evaporation, chemical deposition, or the like.
  • Gluing refers to the process of applying a photoresist on a film of a formed base material.
  • Exposure refers to the process of exposing a specified location of a photoresist using a mask.
  • Development refers to the process of removing the photoresist that has undergone a chemical reaction to produce a desired film pattern on the glass.
  • Etching refers to the process of etching away a thin film of a base material that is not covered by a photoresist. Peeling refers to the process of removing the etched photoresist film.
  • a process including a substrate cleaning, a pattern inspection, and the like may be required.
  • the steps included in the patterning process and the order of the processes are not limited, so that the first gate can be formed.
  • a third insulating layer covering the second gate is formed.
  • an embodiment of the present disclosure further provides a method for fabricating a pixel circuit for fabricating the first to third transistors T1 to T3 and the sixth to eighth transistors T1 to T8 of any one of the above pixel circuits. . Specifically, the method includes:
  • Step S81 forming first gates T1 to third transistors T3 and gates of sixth transistors T6 to eighth transistors T8 while forming a first gate on the substrate by the first patterning process.
  • Step S82 When the first insulating layer covering the first gate is formed, the first insulating layer covers the first transistor T1 to the third transistor T3 and the gates of the sixth transistor T6 to the eighth transistor T8.
  • Step S83 when the active layer is formed on the first insulating layer, the active layers of the first transistor T1 to the third transistor T3 and the sixth transistor T6 to the eighth transistor T8 are simultaneously formed.
  • Step S84 When the second insulating layer covering the active layer is formed, the second insulating layer covers the first to third transistors T1 to T3 and the respective active layers of the sixth to eighth transistors T6 to T8.
  • the second gate is formed only at the position corresponding to the first gate on the second insulating layer, for the first transistor T1 to the third transistor T3.
  • the second gate is not formed.
  • Step S85 when forming the third insulating layer covering the second gate, the third insulating layer covers only the second gate, or the third insulating layer covers the first transistor T1 to the third transistor T3 at the same time. And a second insulating layer of the sixth transistor T6 to the eighth transistor T8.
  • Step S86 forming a source and a drain of the first transistor T1 to the third transistor T3 and the sixth transistor T6 to the eighth transistor T8 simultaneously with the source and the drain on the third insulating layer.
  • step S85 covers only the second gate
  • step S86 a source and a source are formed on the third insulating layer.
  • the first transistor T1 to the third transistor T3 can be simultaneously formed on the second insulating layer covering the first transistor T1 to the third transistor T3 and covering the sixth transistor T6 to the eighth transistor T8, and the sixth The source and the drain of the transistor T6 to the eighth transistor T8, wherein each of the source and the drain are in contact with the active layers through a via hole penetrating the second insulating layer.
  • the third insulating layer formed in step S85 covers both the first transistor T1 to the third transistor T3 and the second insulating layer of the sixth transistor T6 to the eighth transistor T8.
  • a second insulating layer covering the first transistor T1 to the third transistor T3 and the sixth transistor T6 to the eighth transistor T8 is formed on the third insulating layer simultaneously with the source and the drain.
  • the first transistor T1 to the third transistor T3 and the source and the drain of the sixth transistor T6 to the eighth transistor T8 may be simultaneously formed on the third insulating layer, wherein the source and the drain pass through the second insulation
  • the via holes of the layer and the third insulating layer are in contact with the active layers.
  • the first gate may be the gate G4 of the fourth transistor T4 or the gate G5 of the fifth transistor T5.
  • the manufacturing method of the foregoing pixel circuit further includes:
  • the second pole of the first capacitor is formed by the first patterning process, and the first pole of the first capacitor is formed by the second patterning process.
  • An embodiment of the present disclosure provides a display panel including any of the pixel circuits of the above embodiments.
  • the display panel can be: electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator and the like with any display product or component.

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Abstract

一种像素电路及其驱动方法、显示面板。该电路包括：节点控制电路（11）、驱动器（12）、显示子电路（13）、阈值补偿器（14）以及复位器（15）。节点控制电路（11）配置为将参考电压端的电压（Vref）输出至第一节点（N1），或将数据电压端的电压（Vdata）输出至第一节点（N1）；驱动器（12）配置为输出驱动电流；显示子电路（13）配置为显示灰阶；阈值补偿器（14）配置为将第二节点（N2）的电压调节为第一电平端的电压（V1）与驱动器（12）的阈值电压之和以及将第二节点（N2）的电压调节为第一电平端的电压（V1）、驱动器（12）的阈值电压以及参考电压端的电压（Vref）的和与数据电压端的电压（Vdata）的差；复位器（15）配置为对第二节点（N2）和显示子电路（13）复位。

Description

像素电路及其驱动方法、显示面板
本申请要求于2017年6月8日提交中国专利局、申请号为201710428659.0、发明名称为“一种像素电路及其驱动方法、显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、显示面板。
背景技术
以低温多晶硅(英文名称：Low Temperature Poly Silicon，英文简称：LTPS)为衬底制作的有机电致发光显示(英文名称：Organic Light-Emitting Diode,简称：OLED)面板因为LTPS晶体颗粒不规则，所以需要对OLED中的每个像素进行像素补偿，从而消除由于每个驱动薄膜晶体管(英文名称：Driving Thin Film Transistor，英文简称：DTFT)沟道上LTPS晶体颗粒不均匀，进而导致的各像素亮度不均匀的问题。
发明内容
第一方面，本公开的实施例提供一种像素电路，包括：节点控制电路、驱动器、显示子电路、阈值补偿器以及复位器；
所述节点控制电路配置为接收第一扫描信号、第二扫描信号、第三扫描信号、参考电压以及数据电压，所述节点控制电路还配置为在所述第一扫描信号的电压或第二扫描信号的电压的控制下将所述参考电压输出至第一节点，或者在所述第三扫描信号的电压的控制下将所述数据电压输出至所述第一节点；
所述驱动器的输入端配置为接收第一电平信号，所述驱动器还配置为在所述第一电平信号的电压和第二节点的电压的控制下在所述驱动器的输出端输出驱动电流；
所述显示子电路连接所述复位器以及所述驱动器的输出端，所 述显示子电路配置为接收第二电平信号和所述第二扫描信号，所述显示子电路还配置为在所述第二扫描信号的电压的控制下通过所述驱动电流驱动显示灰阶；
所述阈值补偿器连接所述第一节点、所述驱动器的输出端以及第二节点，所述阈值补偿器配置为接收所述第三扫描信号和第四扫描信号，所述阈值补偿器还配置为在所述第三扫描信号的电压或所述第四扫描信号的电压的控制下将所述第二节点的电压调节为第一电平信号的电压与所述驱动器的阈值电压之和，以及在所述第一节点的电压和所述驱动器的输出端的电压的控制下将所述第二节点的电压调节为所述第一电平信号的电压、所述驱动器的阈值电压以及所述参考电压的和与所述数据电压的差；
所述复位器连接所述第二节点以及所述显示子电路，所述复位器配置为接收复位电压信号、所述第一扫描信号和所述第三扫描信号，所述复位器还配置为在所述第一扫描信号的电压的控制下通过所述复位电压信号的电压对所述第二节点进行复位以及在所述第三扫描信号的电压的控制下通过所述复位电压信号的电压对所述显示子电路进行复位；
所述第一节点为所述节点控制电路的输出端与所述阈值补偿器的输入端之间的交点；
所述第二节点为所述阈值补偿器的输出端、所述驱动器的输入端以及所述复位器的输出端之间的交点。
可选的，所述节点控制电路包括：第一晶体管、第二晶体管以及第三晶体管；
所述第一晶体管的第一极配置为接收所述参考电压，所述第一晶体管的第二极连接所述第一节点，所述第一晶体管的栅极配置为接收所述第一扫描信号；
所述第二晶体管的第一极配置为接收所述参考电压，所述第二晶体管的第二极连接所述第一节点，所述第二晶体管的栅极配置为接收所述第二扫描信号；
所述第三晶体管的第一极配置为接收所述数据电压，所述第三晶体管的第二极连接所述第一节点，所述第三晶体管的栅极配置为接收所述第三扫描信号。
可选的，所述阈值补偿器包括：第四晶体管、第五晶体管以及第一电容；
所述第四晶体管的第一极连接所述驱动器的输出端，所述第四晶体管的第二极连接所述第二节点，所述第四晶体管的栅极配置为接收所述第三扫描信号；
所述第五晶体管的第一极连接所述驱动器的输出端，所述第五晶体管的第二极连接所述第二节点，所述第五晶体管的栅极配置为接收所述第四扫描信号；
所述第一电容的第一极连接所述第一节点，所述第一电容的第二极连接所述第二节点。
可选的，所述第四晶体管和所述第五晶体管共用源极、漏极以及有源层；
所述第四晶体管的栅极和所述第五晶体管的栅极分别位于所述有源层的两侧。
可选的，所述第四晶体管的栅极和所述第五晶体管的栅极在与所述有源层垂直方向上的投影重合。
可选的，所述第五晶体管的栅极与所述有源层之间还设置有第一绝缘层；所述第四晶体管的栅极与所述有源层之间还设置有第二绝缘层；所述第四晶体管的栅极与源极、漏极之间还设置有第三绝缘层；所述源极、漏极通过贯穿所述第二绝缘层和所述第三绝缘层的通孔与所述有源层接触。
可选的，所述第一电容的第一极与所述第四晶体管的栅极通过同一次构图工艺制作形成，所述第一电容的第二极与所述第五晶体管的栅极通过同一次构图工艺制作形成；
或，所述第一电容的第一极与所述第五晶体管的栅极通过同一次构图工艺制作形成，所述第一电容的第二极与所述第四晶体管的栅 极通过同一次构图工艺制作形成。
可选的，所述复位器包括：第六晶体管和第七晶体管；
所述第六晶体管的第一极配置为接收所述复位电压信号，所述第六晶体管的第二极连接所述第二节点，所述第六晶体管的栅极配置为接收所述第一扫描信号；
所述第七晶体管的第一极配置为接收所述复位电压信号，所述第七晶体管的第二极连接所述显示子电路，所述第七晶体管的栅极配置为接收所述第三扫描信号。
可选的，所述驱动器为驱动晶体管，所述驱动器的输入端为驱动晶体管的源极，所述驱动器的控制端为驱动晶体管的栅极，所述驱动器的输出端为驱动晶体管的漏极。
可选的，所述显示子电路包括：第八晶体管和发光二极管；
所述第八体管的第一极连接所述驱动器的输出端，所述第八晶体管的第二极连接所述发光二极管的阳极，所述第八晶体管的栅极配置为接收所述第二扫描信号；
所述发光二极管的阴极配置为接收所述第二电平信号。
可选的，所述第三扫描信号为移位寄存电路中第n级移位寄存器的输出信号；所述第四扫描信号为移位寄存电路中第n+1级移位寄存器的输出信号；n为正整数。
第二方面，提供一种像素电路的驱动方法，用于驱动第一方面任一项所述的像素电路，所述方法包括：
第一阶段，所述节点控制电路在所述第一扫描信号的电压的控制下将所述参考电压输出至所述第一节点；所述复位器在所述第一扫描信号的电压的控制下通过所述复位电压信号的电压对所述第二节点进行复位；
第二阶段，所述节点控制电路在所述第三扫描信号的电压的控制下将所述数据电压输出至所述第一节点；所述阈值补偿器在所述第三扫描信号的电压的控制下将所述第二节点的电压调节为第一电平信号的电压与所述驱动器的阈值电压之和；所述复位模块在所述第三 扫描信号的电压的控制下通过所述复位电压信号的电压对所述显示子电路进行复位；
第三阶段，所述阈值补偿器在所述第四扫描信号的电压的控制下将所述第二节点的电压调节为第一电平信号的电压与所述驱动器的阈值电压之和；
第四阶段，所述节点控制电路在所述第二扫描信号的电压的控制下将所述参考电压输出至所述第一节点；所述阈值补偿器在所述第一节点的电压和所述驱动器的输出端的电压的控制下将所述第二节点的电压调节为所述第一电平信号的电压、所述驱动器的阈值电压以及所述参考电压的和与所述数据电压的差；所述驱动器在所述第一电平信号的电压和所述第二节点的电压的控制下在所述驱动器的输出端输出驱动电流；所述显示子电路在所述第二扫描信号的电压的控制下通过所述驱动电流驱动显示灰阶。
第三方面，提供一种显示面板，包括上述的像素电路。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本公开实施例提供的像素电路的示意性结构图；
图2为本公开实施例提供的像素电路的电路图；
图3为本公开实施例提供的像素电路的驱动方法的步骤流程图；
图4为本公开实施例提供的像素电路的信号时序状态图；
图5为本公开实施例提供的第四、五晶体管的示意性结构图之一；
图6为本公开实施例提供的第四、五晶体管的示意性结构图之二；
图7为本公开实施例提供的像素电路的制造方法的步骤流程图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本公开的实施例所采用的晶体管主要包括开关晶体管、驱动晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外本公开实施例所采用的开关晶体管包括P型开关晶体管和N型开关晶体管两种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管为在栅极为高电平时导通，在栅极为低电平时截止。驱动晶体管包括P型和N型，其中P型驱动晶体管在栅极电压为低电平(栅极电压小于源极电压)，且栅极源极的压差的绝对值大于阈值电压时处于放大状态或饱和状态。N型驱动晶体管的栅极电压为高电平(栅极电压大于源极电压)，且栅极源极的压差的绝对值大于阈值电压时处于放大状态或饱和状态。
还需要说明的是，为了便于清楚描述本公开实施例的技术方案，在本公开的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分，本领域技术人员可以理解“第一”、“第二”等字样并不是在对数量和执行次序进行限定。
发明人了解到，随着OLED显示面板分辨率的提高，分摊到每个像素的DTFT的阈值电压读取时间不断缩短。例如：显示面板的分 辨率为1440*2560、频率为60HZ时，每个像素的DTFT的阈值电压读取时间为1s÷60HZ÷2560＝6.5us。此外。除去波形的上升、下降时间，每个像素的DTFT的阈值读取时间不足5us，并且分辨率越高，每个像素的DTFT的阈值电压读取时间越短。由于分摊到每个像素的DTFT的阈值电压读取时间不断缩短，所以可能导致像素电路无法读取DTFT的阈值电压，进而导致显示画面不均匀，出现水波纹(mura)的现象。
本公开的实施例提供一种像素电路，具体的，参照图1所示，该像素电路包括：节点控制电路节点控制电路11、驱动器12、显示子电路13、阈值补偿器14以及复位器15。
节点控制电路节点控制电路11配置为接收第一扫描信号S1、第二扫描信号S2、第三扫描信号S3、参考电压Vref以及数据电压Vdata，该节点控制电路节点控制电路11还配置为在第一扫描信号S1的电压或第二扫描信号S2的电压的控制下将参考电压Vref输出至第一节点N1，或者在第三扫描信号S3的电压的控制下将数据电压Vdata输出至第一节点N1。
驱动器12的输入端I配置为接收第一电平信号V1，驱动器12的控制端Q连接第二节点N2，驱动器12还配置为在第一电平信号V1的电压和第二节点N2的电压的控制下在驱动器12的输出端O输出驱动电流。
显示子电路13连接复位器15以及驱动器12的输出端O，显示子电路13配置为接收第二电平信号V2和第二扫描信号S2，显示子电路13还配置为在第二扫描信号S2的电压的控制下通过驱动电流驱动显示灰阶。
阈值补偿器14连接第一节点N1、驱动器12的输出端O以及第二节点N2，阈值补偿器14配置为接收第三扫描信号S3和第四扫描信号S4阈值补偿器14还配置为在第三扫描信号S3的电压或第四扫描信号S4的电压的控制下将第二节点N2的电压调节为第一电平信号V1的电压与驱动器12的阈值电压之和，以及在第一节点N1的电 压和驱动器12的输出端O的电压的控制下将第二节点N2的电压调节为第一电平信号V1的电压、驱动器12的阈值电压以及参考电压Vref的和与数据电压Vdata的差。
复位器15连接第二节点N2以及显示子电路13，复位器15配置为接收复位电压信号Vinit、第一扫描信号S1和第三扫描信号S3，复位器15还配置为在第一扫描信号S1的电压的控制下通过复位电压信号Vinit的电压对第二节点N2进行复位以及在第三扫描信号S3的电压的控制下通过复位电压信号Vinit的电压对显示子电路13进行复位。
需要说明的是，上述第一节点N1为节点控制电路11的输出端与阈值补偿器14的输入端之间的交点，第二节点N2为阈值补偿器14的输出端、驱动器21的输入端以及复位器15的输出端之间的交点。
本公开实施例提供的像素电路包括：节点控制电路11、阈值补偿器14、复位器15、驱动器21以及显示子电路13。由于阈值补偿器14可以在第三扫描信号S3的电压或第四扫描信号S4的电压的控制下将第二节点N2的电压调节为第一电平信号V1的电压与驱动器12的阈值电压之和，即本公开实施例提供的像素电路可以在第三电平信号或第四电平信号为有效信号时读取驱动器12的阈值电压，因此本公开的实施例可以增加素电路读取驱动器的阈值电压的时间长度，进而解决像素电路无法读取驱动器的阈值电压的问题。
进一步的，本公开的实施例还提供了一种上述图1所示像素电路的具体电路结构。具体的，参照图2所示，节点控制电路11包括：第一晶体管T1、第二晶体管T2以及第三晶体管T3。
第一晶体管T1的第一极配置为接收参考电压Vref，第一晶体管T1的第二极连接第一节点N1，第一晶体管T1的栅极配置为接收第一扫描信号S1。
第二晶体管T2的第一极配置为接收参考电压Vref，第二晶体管T2的第二极连接第一节点N1，第二晶体管T2的栅极配置为接收第二扫描信号S2。
第三晶体管T3的第一极配置为接收数据电压Vdata，第三晶体管T3的第二极连接第一节点N1，第三晶体管T3的栅极配置为接收第三扫描信号S3。
阈值补偿器14包括：第四晶体管T4、第五晶体管T5以及第一电容C1。
第四晶体管T4的第一极连接驱动器12的输出端O，第四晶体管T4的第二极连接第二节点N2，第四晶体管T4的栅极配置为接收第三扫描信号S3。
第五晶体管T5的第一极连接驱动器12的输出端O，第五晶体管T5的第二极连接第二节点N2，第五晶体管T5的栅极配置为接收第四扫描信号S4。
第一电容C1的第一极连接第一节点N1，第一电容C1的第二极连接第二节点N2。
复位器15包括：第六晶体管T6和第七晶体管T7。
第六晶体管T6的第一极配置为接收复位电压信号Vinit，第六晶体管T6的第二极连接第二节点N2，第六晶体管T6的栅极配置为接收第一扫描信号S1。
第七晶体管T7的第一极配置为接收复位电压信号Vinit，第七晶体管T7的第二极连接显示子电路13，第七晶体管T7的栅极配置为接收第三扫描信号S3。
驱动器12为驱动晶体管DTFT，驱动器12的输入端I为驱动晶体管DTFT的源极，驱动器12的控制端Q为驱动晶体管DTFT的栅极，驱动器12的输出端O为驱动晶体管DTFT的漏极。
显示子电路13包括：第八晶体管T8和发光二极管D1。
第八体管T8的第一极连接驱动器12的输出端O，第八晶体管T8的第二极连接发光二极管D1的阳极，第八晶体管T8的栅极配置为接收第二扫描信号S2。
发光二极管D1的阴极配置为接收第二电平信号V2。
本公开的实施例还提供了一种上述像素电路的驱动方法，具体 的，参照图3所示，该方法包括如下步骤：
S31、第一阶段，节点控制电路在第一扫描信号的电压的控制下将参考电压输出至第一节点；复位器在第一扫描信号的电压的控制下通过复位电压信号的电压对第二节点进行复位。
S32、第二阶段，节点控制电路在第三扫描信号的电压的控制下将数据电压输出至第一节点；阈值补偿器在第三扫描信号的电压的控制下将第二节点的电压调节为第一电平信号的电压与驱动器的阈值电压之和；复位模块在第三扫描信号的电压的控制下通过复位电压信号的电压对显示子电路进行复位。
S33、第三阶段，阈值补偿器在第四扫描信号的电压的控制下将第二节点的电压调节为第一电平信号的电压与驱动器的阈值电压之和。
S34、第四阶段，节点控制电路在第二扫描信号的电压的控制下将参考电压输出至第一节点；阈值补偿器在第一节点的电压和驱动器的输出端的电压的控制下将第二节点的电压调节为第一电平信号的电压、驱动器的阈值电压以及参考电压的和与数据电压的差；驱动器在第一电平信号的电压和第二节点的电压的控制下在驱动器的输出端输出驱动电流；显示子电路在第二扫描信号的电压的控制下通过驱动电流驱动显示灰阶。
以下参照图4所示的信号时序状态示意图，对图2所示的像素电路以及图3所示像素电路的驱动方法的工作原理进行说明。以图2中所有开关晶体管均为栅极低电平时导通的P型晶体管为例进行说明。图4中包含第一扫描信号S1、第二扫描信号S2、第三扫描信号S3以及第四扫描信号S4的信号时序状态。此外，第一电平信号V1提供高电平Vdd，第二电平信号V2接地提供Vss。示例性的，第二电平信号V2可以接地。如图4所示提供四个时序阶段，包括：t1(第一阶段)、t2(第二阶段)、t3(第三阶段)和t4(第四阶段)。
第一阶段，第一扫描信号S1低电平，第二扫描信号S2、第三扫描信号S3以及第四扫描信号S4高电平，因此第一晶体管T1和第 六晶体管T6导通，其余晶体管均截止。参考电压Vref通过第一晶体管T1连接第一节点N1,所以此阶段第一节点N1的电压为参考电压Vref。复位电压信号Vinit通过第六晶体管T6连接第二节点N2，所以此阶段第二节点N2的电压为复位电压信号Vinit的电压，同时由于第一电容C1的第一极和第二极分别连接第一节点N1和第二节点N2，所以第一电容C1的第一极和第二极的电压也分别为参考电压Vref和复位电压信号Vinit的电压。由于此阶段将第一阶段N1和第二阶段N2的电压复位为常数电压，因此第一阶段又称为复位阶段。
第二阶段，第三扫描信号S3低电平，第一扫描信号S1、第二扫描信号S2以及第四扫描信号S4高电平，因此第三晶体管T3、第四晶体管T4以及第七晶体管T7导通，其余晶体管均截止。数据电压Vdata通过第三晶体管T3连接第一节点N1，第一节点N1的电压由第一阶段的参考电压Vref跳变为数据电压Vdata。又由于第四晶体管T4导通，所以驱动晶体管DTFT的栅极与漏极连接，驱动晶体管DTFT栅源电压差等于驱动晶体管的阈值电压，因此第二节点N2的电压跳变为第一电平信号V1的电压与驱动晶体管DTFT的阈值电压之和。此外，由于第七晶体管T7导通，所以此阶段复位电压信号Vinit还通过第七晶体管T7将发光二极管D1的阳极的电压复位为复位电压信号Vinit的电压。
需要说明的是，虽然理论上可以通过第二阶段使第二节点N2的电压跳变为第一电平信号V1的电压与驱动晶体管DTFT的阈值电压之和(即，可以读取驱动晶体管DTFT的阈值电压)。但是在一些高分辨率的应用场景中，由于第二阶段的时间长度过小，可能会导致无法读取驱动晶体管的阈值电压。例如：显示面板的分辨率为1440*2560、频率为60HZ时，每个像素的驱动晶体管DTFT的阈值电压读取时间为1s÷60HZ÷2560＝6.5us。此外。除去波形的上升、下降时间，每个像素的驱动晶体管DTFT的阈值读取时间不足5us，并且分辨率越高，每个像素的驱动晶体管DTFT的阈值电压读取时间越短。此阶段主要作用为读取驱动晶体管的阈值电压，所以此阶段又称 为阈值读取阶段。
第三阶段，第四扫描信号S4低电平，第一扫描信号S1、第二扫描信号S2以及第三扫描信号S3高电平，因此第五晶体管T5导通，其余晶体管均截止。由于第一晶体管T1、第二晶体管T2以及第三晶体管T3均截止，所以第一电容C1的第一极没有放电路径，电压仍保持为上一阶段的数据电压。与第二阶段类似，又由于第五晶体管T5导通，所以驱动晶体管DTFT的栅极与漏极连接，驱动晶体管DTFT栅源电压差等于驱动晶体管DTFT的阈值电压，因此第二节点N2的电压跳变为第一电平信号V1的电压与驱动晶体管DTFT的阈值电压之和。此阶段主要作用为补充读取驱动晶体管DTFT的阈值电压，又称为阈值补充读取阶段。
由于本公开实施例中增加了上述第三阶段，因此本公开的实施例可以增加像素电路读取驱动器的阈值电压的时间长度，进而解决像素电路可能无法读取驱动器的阈值电压的问题。
第四阶段，第二扫描信号S2低电平，第一扫描信号S1、第三扫描信号S3以及第四扫描信号S4高电平，因此第二晶体管T2和第八晶体管T8导通，其余晶体管均截止。参考电压Vref通过第二晶体管T2连接第一节点，因此第一节点N1的电压变为参考电压Vref。同时根据第二节点N2上的电荷守恒定律，第二节点N2的电压变为第一电平信号的电压、驱动器的阈值电压以及参考电压的和与数据电压的差。
由TFT饱和电流公式可以得到流入OLED的电流为：
I OLED＝K(V gs-V th) 2
Figure PCTCN2018082632-appb-000001
μ、C ox为工艺常数。W为驱动晶体管DTFT的沟道宽度。L为驱动晶体管DTFT的沟道长度。V gs为驱动晶体管DTFT的栅极电压与源极电压的电压差。V th驱动晶体管DTFT的阈值电压。
由于驱动晶体管DTFT的栅极电压等于第二节点N2的电压，因此，驱动晶体管DTFT的栅极电压为：
V g＝V1+V th+Vref-Vdata、
V1为第一电平信号的电压。Vref为参考电压端。Vdata为数据电压。
驱动晶体管DTFT的源极电压为：V S＝V1。
所以驱动晶体管DTFT的栅极电压与源极电压的电压差为：
V gs＝(V1+V th+Vref-Vdata)-V1＝V th+Vref-Vdata
I OLED＝K(V gs-V th) 2＝K[(V th+Vref-Vdata)-V th] 2＝K(Vref-Vdata) 2
由上式中可以看到OLED的工作电流已经不受驱动晶体管DTFT的阈值电压的影响，只与数据电压和参考电压有关，因此可以解决驱动晶体管由于工艺制程及长时间的操作造成阈值电压漂移的问题，消除其对流入OLED的电流的影响，保证OLED的正常工作。
进一步的，上述实施例中的像素电路中所有晶体管还可以均为栅极高电平导通的N型晶体管，若所有晶体管均为N型晶体管，则只需要重新调整像素电路各个扫描信号的时序状态即可，例如：调整图4中t1阶段第一时钟信号信号调整为高电平，调整t1阶段第二时钟信号信号调整为低电平，其他信号也调整为相位相反的时序信号。
再进一步的，上述像素电路中也可以同时采用N型晶体管和P型晶体管，此时需保证像素电路中通过同一个时序信号或电压控制的晶体管需要采用相同的类型，当然这都是本领域的技术人员依据本公开的实施例可以做出的合理变通方案，因此均应为本公开的保护范围，然而考虑到晶体管的制程工艺，由于不同类型的晶体管的有源层掺杂材料不相同，因此像素电路中采用统一类型的晶体管更有利于简化像素电路的制程工艺。
进一步的，参照图5所示，上述图2所示像素电路中的第四晶体管T4和第五晶体管T5还可以共用源极51、漏极52以及有源层53。
第四晶体管T4的栅极G4和第五晶体管T5的栅极G5分别位于有源层53的两侧。
示例性的，上述有源层53具体可以为多晶硅层。
需要说明的是，图5中以第四晶体管T4的栅极位于有源层53的上侧，第五晶体管T5的栅极位于有源层53的下侧为例进行说明， 但本公开实施例并不限定于此。在本公开的一些实施例中，第四晶体管T4的栅极也可以位于有源层53的下侧，第五晶体管T5的栅极也可以位于有源层53的上侧。
通过使第四晶体管T4和第五晶体管T5共用源极51、漏极52以及有源层53，可以节省晶体管占用显示面板的面积，进而提高显示面板的开口率。
可选的，如图5所示，第四晶体管T4的栅极G4和第五晶体管T5的栅极G5在与有源层53垂直方向上的投影重合。
由于有源层53对光线强度较为敏感，因此当显示面板内部或者外界光线照射在有源层53上时，会使第四晶体管T4和第五晶体管T5产生漏电流。因为本公开实施例中使第四晶体管T4的栅极G4和第五晶体管T5的栅极G5在与有源层53垂直方向上的投影重合，所以第四晶体管的栅极G4和第五晶体管的栅极G5可以相互作为光阻挡层，进而减小第四晶体管T4和第五晶体管T5的漏电流，保证对驱动晶体管阈值电压进行准确的补偿。
进一步的，以下参照图6所示，对第四晶体管T4和第五晶体管T5的结构进行详细说明。
参照图6所示，第五晶体管T5的栅极G5与有源层53之间还设置有第一绝缘层GI1。第四晶体管T4的栅极G4与有源层53之间还设置有第二绝缘层GI2。第四晶体管T4的栅极G4与源极51、漏极52之间还设置有第三绝缘层GI3。源极51、漏极52通过贯穿第二绝缘层GI2和第三绝缘层GI3的通孔与有源层53接触。
在上述实施例中，由于第四晶体管T4的栅极G4与第五晶体管T5的栅极G5不在同一栅金属层，因此在制作第四晶体管T4的栅极G4和第五晶体管T5的栅极G5需要分别通过一次构图工艺来制作。这样会增加像素电路的工艺流程，进而增加像素电路的制造成本。此外，由于第一电容C1的两级间需要设置电容介质，所以第一电容C1的第一极和第二极也需要分别通过一次构图工艺来制作。
基于上述制程工艺，本公开实施例中使第一电容C1的第一极 和第二极分别与第四晶体管T4的栅极G4和第五晶体管T5的栅极G5通过同一次构图工艺制作形成。
即，可以为第一电容C1的第一极与第四晶体管T4的栅极G4通过同一次构图工艺制作形成，第一电容C1的第二极与第五晶体管T5的栅极G5通过同一次构图工艺制作形成。也可以为第一电容C1的第二极与第四晶体管T4的栅极G4通过同一次构图工艺制作形成，第一电容C1的第一极与第五晶体管T5的栅极G5通过同一次构图工艺制作形成。
通过使使第一电容C1的第一极和第二极分别与第四晶体管T4的栅极G4和第五晶体管T5的栅极G5通过同一次构图工艺制作形成，可以减少像素电路的制造工序，进而减少像素电路的制造成本。
可选的，上述实施例中的第三扫描信号为移位寄存电路中第n级移位寄存器的输出信号。第四扫描信号为移位寄存电路中第n+1级移位寄存器的输出信号。n为正整数。
在本公开的实施例中，上述第三扫描信号实质为第三扫描端接收到的信号，上述第四扫描端的输出信号实质为第四扫描端接收到的信号。在任一具有多行像素电路的显示面板中，移位寄存电路中第n级移位寄存器与显示面板中第n行像素电路中的第三扫描端相连，即移位寄存电路中第n级移位寄存器的输出信号为显示面板中第n行像素电路中的第三扫描端接收到的信号。移位寄存电路中第n+1级移位寄存器与显示面板中第n行像素电路中的第四扫描端相连，即移位寄存电路中第n+1级移位寄存器的输出信号为显示面板中第n行像素电路中的第四扫描端接收到的信号。
通过将移位寄存电路的输出信号作为第三扫描信号S3和第四扫描信号S4，省去了单独制作第三扫描端S3和第四扫描端S4的驱动电路的工艺和成本，进而进一步简化像素电路的制作工序，降低像素电路的制造成本。
进一步的，本公开的实施例还提供了一种像素电路的制造方法，用于制作上述任一像素电路中的第四晶体管T4和第五晶体管T5。具 体的，参照图7所示，该方法包括：
S71、通过第一次构图工艺在基板上形成第一栅极。
具体的，一次构图工艺主要包括：成膜、涂胶、曝光、显影、刻蚀、剥离等工序。成膜是指通过磁控溅射、蒸镀、化学沉积等方式在基板上形成一层基础材料的薄膜的过程。涂胶是指在形成的基础材料的薄膜上涂覆光刻胶的过程。曝光是指利用掩膜板对光刻胶的指定位置进行曝光的过程。显影是指将发生化学反应的光刻胶清除干净，使玻璃上产生想要得到的胶膜图形的过程。刻蚀是指将未被光刻胶覆盖住的基础材料的薄膜腐蚀掉的过程。剥离是指将刻蚀后的光刻胶膜去除的过程。当然，在构图工艺还可能需要包括基板清洗、图案检查等过程，本公开实施例中对构图工艺包括的工序以及各工序的顺序不做限定，以能够形成第一栅极为准。
S72、制作覆盖第一栅极的第一绝缘层。
S73、在第一绝缘层上制作有源层。
S74、制作覆盖有源层的第二绝缘层。
S75、通过第二次构图工艺在第二绝缘层上形成第二栅极。
S76、制作覆盖第二栅极的第三绝缘层。
S77、通过第三次构图工艺在第三绝缘层上形成源极和漏极；其中，源极和漏极通过贯穿第二绝缘层和第三绝缘层的通孔与有源层相接触。
示例性的，本公开的实施例还提供了一种像素电路的制造方法，用于制作上述任一像素电路中的第一晶体管T1～第三晶体管T3，以及第六晶体管T6～第八晶体管T8。具体的，该方法包括：
步骤S81、通过第一次构图工艺在基板上形成第一栅极的同时，形成第一晶体管T1～第三晶体管T3，以及第六晶体管T6～第八晶体管T8的栅极。
步骤S82、制作覆盖第一栅极的第一绝缘层时，使该第一绝缘层同时覆盖第一晶体管T1～第三晶体管T3，以及第六晶体管T6～第八晶体管T8的栅极。
步骤S83、在第一绝缘层上制作有源层时，同时制作第一晶体管T1～第三晶体管T3，以及第六晶体管T6～第八晶体管T8的各自的有源层。
步骤S84、制作覆盖有源层的第二绝缘层时，使该第二绝缘层同时覆盖第一晶体管T1～第三晶体管T3，以及第六晶体管T6～第八晶体管T8的各自的有源层。
需要说明的是，在本公开的实施例中，在步骤S75中，只在第二绝缘层上对应第一栅极的位置上形成有第二栅极，对于第一晶体管T1～第三晶体管T3的栅极对应的第二绝缘层上，以及第六晶体管T6～第八晶体管T8的栅极对应的第二绝缘层上，并不形成第二栅极。
步骤S85、在形成覆盖第二栅极的第三绝缘层时，使该第三绝缘层只覆盖第二栅极，或，使该第三绝缘层同时覆盖第一晶体管T1～第三晶体管T3，以及第六晶体管T6～第八晶体管T8的第二绝缘层。
步骤S86、在第三绝缘层上形成与源极和漏极的同时，形成第一晶体管T1～第三晶体管T3，以及第六晶体管T6～第八晶体管T8的源极和漏极。
需要补充的是，在本公开的一些实施例中，若在步骤S85中形成的第三绝缘层只覆盖了第二栅极，则在步骤S86中，在第三绝缘层上形成与源极和漏极的同时，在覆盖第一晶体管T1～第三晶体管T3，以及覆盖第六晶体管T6～第八晶体管T8的第二绝缘层上可同时形成第一晶体管T1～第三晶体管T3，以及第六晶体管T6～第八晶体管T8的源极和漏极，其中，各源极和漏极通过贯穿第二绝缘层的通孔与各有源层相接触。
在本公开的另外一些实施例中，若在步骤S85中形成的第三绝缘层同时覆盖在第一晶体管T1～第三晶体管T3，以及第六晶体管T6～第八晶体管T8的第二绝缘层上，则在步骤S86中，在第三绝缘层上形成与源极和漏极的同时，在覆盖第一晶体管T1～第三晶体管T3，以及第六晶体管T6～第八晶体管T8的第二绝缘层的第三绝缘层上也可同时形成第一晶体管T1～第三晶体管T3，以及第六晶体管T6～第八晶 体管T8的源极和漏极，其中，各源极和漏极通过贯穿第二绝缘层和第三绝缘层的通孔与各有源层相接触。
在本公开的实施例中，第一栅极可以为第四晶体管T4的栅极G4也可以为第五晶体管T5的栅极G5。
可选的，上述像素电路的制造方法还包括：
通过第一次构图工艺形成第一电容的第一极，通过第二次构图工艺形成第一电容的第二极；
或者；
通过第一次构图工艺形成第一电容的第二极，通过第二次构图工艺形成第一电容的第一极。
本公开一实施例提供一种显示面板，包括上述实施例中任一种像素电路。
另外，显示面板可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (14)

  1. 一种像素电路，包括：节点控制电路、驱动器、显示子电路、阈值补偿器以及复位器；
    所述节点控制电路配置为接收第一扫描信号、第二扫描信号、第三扫描信号、参考电压以及数据电压，所述节点控制电路还配置为在所述第一扫描信号的电压或第二扫描信号的电压的控制下将所述参考电压输出至第一节点，或者在所述第三扫描信号的电压的控制下将所述数据电压输出至所述第一节点；
    所述驱动器的输入端配置为接收第一电平信号，所述驱动器的控制端连接第二节点，所述驱动器还配置为在所述第一电平信号的电压和第二节点的电压的控制下在所述驱动器的输出端输出驱动电流；
    所述显示子电路连接所述复位器以及所述驱动器的输出端，所述显示子电路配置为接收第二电平信号和所述第二扫描信号，所述显示子电路还配置为在所述第二扫描信号的电压的控制下通过所述驱动电流驱动显示灰阶；
    所述阈值补偿器连接所述第一节点、所述驱动器的输出端以及第二节点，所述阈值补偿器配置为接收所述第三扫描信号和第四扫描信号，所述阈值补偿器还配置为在所述第三扫描信号的电压或所述第四扫描信号的电压的控制下将所述第二节点的电压调节为第一电平信号的电压与所述驱动器的阈值电压之和，以及在所述第一节点的电压和所述驱动器的输出端的电压的控制下将所述第二节点的电压调节为所述第一电平信号的电压、所述驱动器的阈值电压以及所述参考电压的和与所述数据电压的差；
    所述复位器连接所述第二节点以及所述显示子电路，所述复位器配置为接收复位电压信号、所述第一扫描信号和所述第三扫描信号，所述复位器还配置为在所述第一扫描信号的电压的控制下通过所述复位电压信号的电压对所述第二节点进行复位以及在所述第三扫描信号的电压的控制下通过所述复位电压信号的电压对所述显示子电路进行复位；
    所述第一节点为所述节点控制电路的输出端与所述阈值补偿器的输入端之间的交点；
    所述第二节点为所述阈值补偿器的输出端、所述驱动器的输入端以及所述复位器的输出端之间的交点。
  2. 根据权利要求1所述的像素电路，其中，所述节点控制电路包括：第一晶体管、第二晶体管以及第三晶体管；
    所述第一晶体管的第一极配置为接收所述参考电压，所述第一晶体管的第二极连接所述第一节点，所述第一晶体管的栅极配置为接收所述第一扫描信号；
    所述第二晶体管的第一极配置为接收所述参考电压，所述第二晶体管的第二极连接所述第一节点，所述第二晶体管的栅极配置为接收所述第二扫描信号；
    所述第三晶体管的第一极配置为接收所述数据电压，所述第三晶体管的第二极连接所述第一节点，所述第三晶体管的栅极配置为接收所述第三扫描信号。
  3. 根据权利要求1所述的像素电路，其中，所述阈值补偿器包括：第四晶体管、第五晶体管以及第一电容；
    所述第四晶体管的第一极连接所述驱动器的输出端，所述第四晶体管的第二极连接所述第二节点，所述第四晶体管的栅极配置为接收所述第三扫描信号；
    所述第五晶体管的第一极连接所述驱动器的输出端，所述第五晶体管的第二极连接所述第二节点，所述第五晶体管的栅极配置为接收所述第四扫描信号；
    所述第一电容的第一极连接所述第一节点，所述第一电容的第二极连接所述第二节点。
  4. 根据权利要求3所述的像素电路，其中，所述第四晶体管和所述第五晶体管共用源极、漏极以及有源层；
    所述第四晶体管的栅极和所述第五晶体管的栅极分别位于所述有源层的两侧。
  5. 根据权利要求4所述的像素电路，其中，所述第四晶体管的栅极和所述第五晶体管的栅极在与所述有源层垂直方向上的投影重合。
  6. 根据权利要求4所述的像素电路，其中，所述第五晶体管的栅极与所述有源层之间还设置有第一绝缘层；所述第四晶体管的栅极与所述有源层之间还设置有第二绝缘层；所述第四晶体管的栅极与源极、漏极之间还设置有第三绝缘层；所述源极、漏极通过贯穿所述第二绝缘层和所述第三绝缘层的通孔与所述有源层接触。
  7. 根据权利要求4所述的像素电路，其中，所述第一电容的第一极与所述第四晶体管的栅极通过同一次构图工艺制作形成，所述第一电容的第二极与所述第五晶体管的栅极通过同一次构图工艺制作形成。
  8. 根据权利要求4所述的像素电路，其中，所述第一电容的第一极与所述第五晶体管的栅极通过同一次构图工艺制作形成，所述第一电容的第二极与所述第四晶体管的栅极通过同一次构图工艺制作形成。
  9. 根据权利要求1所述的像素电路，其中，所述复位器包括：第六晶体管和第七晶体管；
    所述第六晶体管的第一极配置为接收所述复位电压信号，所述第六晶体管的第二极连接所述第二节点，所述第六晶体管的栅极配置为接收所述第一扫描信号；
    所述第七晶体管的第一极配置为接收所述复位电压信号，所述第七晶体管的第二极连接所述显示子电路，所述第七晶体管的栅极配置为接收所述第三扫描信号。
  10. 根据权利要求1所述的像素电路，其中，所述驱动器为驱动晶体管，所述驱动器的输入端为驱动晶体管的源极，所述驱动器的控制端为驱动晶体管的栅极，所述驱动器的输出端为驱动晶体管的漏极。
  11. 根据权利要求1所述的像素电路，其中，所述显示子电路包括： 第八晶体管和发光二极管；
    所述第八体管的第一极连接所述驱动器的输出端，所述第八晶体管的第二极连接所述发光二极管的阳极，所述第八晶体管的栅极配置为接收所述第二扫描信号；
    所述发光二极管的阴极配置为接收所述第二电平信号。
  12. 根据权利要求1所述的像素电路，其中，所述第三扫描信号为移位寄存电路中第n级移位寄存器的输出信号；所述第四扫描信号为移位寄存电路中第n+1级移位寄存器的输出信号；n为正整数。
  13. 一种像素电路的驱动方法，用于驱动权利要求1-12任一项所述的像素电路，所述方法包括：
    第一阶段，所述节点控制电路在所述第一扫描信号的电压的控制下将所述参考电压输出至所述第一节点；所述复位器在所述第一扫描信号的电压的控制下通过所述复位电压信号的电压对所述第二节点进行复位；
    第二阶段，所述节点控制电路在所述第三扫描信号的电压的控制下将所述数据电压输出至所述第一节点；所述阈值补偿器在所述第三扫描信号的电压的控制下将所述第二节点的电压调节为第一电平信号的电压与所述驱动器的阈值电压之和；所述复位模块在所述第三扫描信号的电压的控制下通过所述复位电压信号的电压对所述显示子电路进行复位；
    第三阶段，所述阈值补偿器在所述第四扫描信号的电压的控制下将所述第二节点的电压调节为第一电平信号的电压与所述驱动器的阈值电压之和；
    第四阶段，所述节点控制电路在所述第二扫描信号的电压的控制下将所述参考电压输出至所述第一节点；所述阈值补偿器在所述第一节点的电压和所述驱动器的输出端的电压的控制下将所述第二节点的电压调节为所述第一电平信号的电压、所述驱动器的阈值电压以及所述参考电压的和与所述数据电压的差；所述驱动器在所述第一电平信号的电压和所述第二节点的电压的控制下在所述驱动器的输出端输出驱动电流；所述显示子电 路在所述第二扫描信号的电压的控制下通过所述驱动电流驱动显示灰阶。
  14. 一种显示面板，包括权利要求1-12任一项所述的像素电路。
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