WO2018223699A1 - 显示面板及其制备方法、显示装置以及显示方法 - Google Patents

显示面板及其制备方法、显示装置以及显示方法 Download PDF

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Publication number
WO2018223699A1
WO2018223699A1 PCT/CN2018/072049 CN2018072049W WO2018223699A1 WO 2018223699 A1 WO2018223699 A1 WO 2018223699A1 CN 2018072049 W CN2018072049 W CN 2018072049W WO 2018223699 A1 WO2018223699 A1 WO 2018223699A1
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Prior art keywords
electrode
pixel
substrate
display
orthographic projection
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2018/072049
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English (en)
French (fr)
Inventor
邹清华
朱儒晖
姚固
郭书鹏
屈丽桃
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US16/075,001 priority Critical patent/US10763319B2/en
Publication of WO2018223699A1 publication Critical patent/WO2018223699A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G09G3/342—Control of illumination source using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/826—Multilayers, e.g. opaque multilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/02—Composition of display devices
    • G09G2300/023—Display panel composed of stacked panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures
    • H10K2102/3023—Direction of light emission
    • H10K2102/3026—Top emission
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures
    • H10K2102/3023—Direction of light emission
    • H10K2102/3031—Two-side emission, e.g. transparent OLEDs [TOLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/11—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
    • H10K50/115—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers comprising active inorganic nanostructures, e.g. luminescent quantum dots
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80524—Transparent cathodes, e.g. comprising thin metal layers

Definitions

  • Embodiments of the present disclosure relate to the field of display technologies, and in particular, to a display panel, a method for fabricating the same, a display device, and a display method.
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diode
  • Embodiments of the present disclosure provide a display panel, a method of fabricating the same, a display device, and a display method.
  • a display panel includes: a substrate; a thin film transistor on the substrate; an insulating layer covering the substrate and the thin film transistor; and first and second electrodes electrically insulating on the insulating layer, wherein An orthographic projection of the first electrode on the substrate does not overlap with an orthographic projection of the thin film transistor on the substrate, an orthographic projection of the second electrode on the substrate and the thin film transistor are in the An orthographic projection on the substrate overlap; a light emitting layer on the first electrode and the second electrode; and a third electrode and a fourth electrode on the light emitting layer, wherein the third electrode is in the An orthographic projection on the substrate overlaps with an orthographic projection of the first electrode on the substrate, and an orthographic projection of the fourth electrode on the substrate overlaps with an orthographic projection of the second electrode on the substrate.
  • the first electrode, the third electrode, and the first portion of the light emitting layer between the first electrode and the third electrode constitute a first pixel
  • a second portion of the light emitting layer between the second electrode and the fourth electrode constitutes a second pixel
  • the first electrode is connected to a source/drain electrode of the thin film transistor via a via hole passing through the insulating layer, thereby using the first pixel as a display pixel and the first Two pixels are used as illumination pixels.
  • the second electrode is connected to a source/drain electrode of the thin film transistor via a via hole passing through the insulating layer, thereby using the first pixel as an illumination pixel and the first Two pixels are used as display pixels.
  • the first electrode, the third electrode, and the fourth electrode are transparent electrodes, and the second electrode is a non-transparent electrode.
  • the transparent electrode includes a transparent conductive material
  • the non-transparent electrode includes a metal
  • the third electrode and the fourth electrode are formed in one body.
  • the display panel further includes a pixel defining layer between the first electrode and the second electrode.
  • a method of preparing a display panel includes: forming a thin film transistor on a substrate; forming an insulating layer to cover the substrate and the thin film transistor; forming an electrically insulating first electrode and a second electrode on the insulating layer, wherein the first An orthographic projection of an electrode on the substrate does not overlap with an orthographic projection of the thin film transistor on the substrate, an orthographic projection of the second electrode on the substrate and a positive of the thin film transistor on the substrate Projection overlap; forming a light-emitting layer on the first electrode and the second electrode; and forming a third electrode and a fourth electrode on the light-emitting layer, wherein the third electrode is positive on the substrate A projection overlaps an orthographic projection of the first electrode on the substrate, and an orthographic projection of the fourth electrode on the substrate overlaps with an orthographic projection of the second electrode on the substrate.
  • the first electrode, the third electrode, and the first portion of the light emitting layer between the first electrode and the third electrode constitute a first pixel
  • a second portion of the light emitting layer between the second electrode and the fourth electrode constitutes a second pixel
  • forming the insulating layer further includes patterning the insulating layer to form a via hole through the insulating layer.
  • the first electrode is connected to a source/drain electrode of the thin film transistor via the via, thereby using the first pixel as a display pixel and the second pixel as an illumination pixel .
  • the second electrode is connected to source/drain electrodes of the thin film transistor via the via, thereby using the first pixel as an illumination pixel and the second pixel as a display pixel .
  • the first electrode, the third electrode, and the fourth electrode are transparent electrodes, and the second electrode is a non-transparent electrode.
  • the transparent electrode includes a transparent conductive material
  • the non-transparent electrode includes a metal
  • the third electrode and the fourth electrode are formed in one body.
  • the light emitting layer before forming the light emitting layer, further comprising forming a pixel defining layer between the first electrode and the second electrode.
  • a display device including the display panel described in the first aspect of the present disclosure.
  • a display method using the display panel described in the first aspect of the present disclosure controls the display panel in one of the following modes: a first mode, wherein the first pixel is a display pixel, the second pixel is an illumination pixel, the first pixel is illuminated, and the second a second mode, wherein the first pixel is a display pixel, the second pixel is an illumination pixel, the first pixel and the second pixel are simultaneously illuminated; and a third mode, wherein the a first pixel as a display pixel, the second pixel as an illumination pixel, the first pixel does not emit light, the second pixel emits light, and a fourth mode, wherein the first pixel serves as an illumination pixel, and the second a pixel as a display pixel, the first pixel does not emit light, the second pixel emits light, and a fifth mode, wherein the first pixel is an illumination pixel, and the second pixel is a display pixel, the
  • FIG. 1 is a schematic view of a cross section of a display panel in accordance with an embodiment of the present disclosure
  • FIG. 2 is a schematic view of a cross section of a display panel according to another embodiment of the present disclosure.
  • FIG. 3 is a plan view of a display panel in accordance with an embodiment of the present disclosure.
  • FIG. 4 is a flow chart of a method of preparing a display panel in accordance with an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of forming a thin film transistor of a method of fabricating a display panel according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of forming an insulating layer of a method of fabricating a display panel according to an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of forming a first electrode and a second electrode in a method of fabricating a display panel according to an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of forming a pixel defining layer of a method of fabricating a display panel according to an embodiment of the present disclosure
  • FIG. 9 is a schematic view of forming a light-emitting layer of a method of fabricating a display panel according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of forming an electrode layer of a method of fabricating a display panel according to an embodiment of the present disclosure
  • FIG. 11 is a schematic diagram of a first mode of a display panel in accordance with an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a second mode of a display panel in accordance with an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a third mode of a display panel according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of a fourth mode of a display panel according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of a fifth mode of a display panel in accordance with an embodiment of the present disclosure.
  • an element or layer when an element or layer is referred to as being “on” another element or layer, it may be directly on the other element or layer, or an element or layer may be present; likewise, when the element or layer is When the other element or layer is "under”, it may be directly under the other element or layer, or there may be at least one intermediate element or layer; when the element or layer is referred to as being between the two or two layers It may be a single element or layer between two or two layers, or more than one intermediate element or layer may be present.
  • a display panel is provided.
  • the display panel can be an OLED display panel or a QLED display panel.
  • An anode is disposed between the thin film transistor of the display panel and the light emitting layer to utilize the light emitting layer corresponding to the anode, thereby improving the aperture ratio of the display panel, and enabling the display panel to perform both display and illumination functions.
  • FIG. 1 is a schematic view of a cross section of a display panel 10 in accordance with an embodiment of the present disclosure.
  • the display panel 10 includes: a substrate 1; a thin film transistor 2 on the substrate 1; an insulating layer 3 covering the substrate 1 and the thin film transistor 2, wherein the insulating layer 3 includes a via 31 penetrating the insulating layer 3.
  • the electrode layer 7 includes a third electrode 71 and a fourth electrode 72.
  • the orthographic projection of the third electrode 71 on the substrate 1 overlaps with the orthographic projection of the first electrode 41 on the substrate 1, and the orthographic projection of the fourth electrode 72 on the substrate 1 overlaps with the orthographic projection of the second electrode 42 on the substrate 1.
  • the third electrode 71 and the fourth electrode 72 may be formed in one body.
  • the first electrode 41, the third electrode 71, and the first portion 61 of the light-emitting layer 6 located between the first electrode 41 and the third electrode 71 constitute a first pixel 81
  • the fourth electrode 72 and the second portion 62 of the light-emitting layer 6 between the second electrode 42 and the fourth electrode 72 constitute a second pixel 82.
  • the first electrode 41 is connected to the source/drain electrodes of the thin film transistor 2 via the via 31, thereby using the first pixel 81 as a display pixel and the second pixel 82 as an illumination pixel.
  • FIG. 2 is a schematic view of a cross section of a display panel 20 in accordance with another embodiment of the present disclosure. 2 is different from FIG. 1 in that, as shown in FIG. 2, the second electrode 42 is connected to the source/drain electrodes of the thin film transistor 2 via the via 31, thereby using the first pixel 81 as an illumination pixel and the second pixel 82 as Display pixels.
  • the other parts of FIG. 2 are similar to FIG. 1 and will not be described again.
  • the first electrode 41, the third electrode 71, and the fourth electrode 72 are transparent electrodes
  • the second electrode 42 is a non-transparent electrode
  • the transparent electrode may include a transparent conductive material such as a transparent conductive oxide such as indium tin oxide, indium tin zinc oxide, and tin oxide.
  • the non-transparent electrode may include a metal such as silver or aluminum.
  • an oxidation resistant layer such as indium tin oxide may also be formed on the metal surface.
  • the non-transparent electrode may be a stack of indium tin oxide/silver/indium tin oxide, as shown by the second electrode 42 in FIG.
  • the substrate 1 is transparent.
  • the substrate 1 may be a glass substrate.
  • the thin film transistor 2 may be a top gate thin film transistor or a bottom gate thin film transistor, which is not specifically limited herein.
  • the insulating layer 3 may be a laminate including a passivation layer and a protective layer.
  • the pixel area of the display panel includes display pixels and illumination pixels.
  • the display pixels in FIG. 3 correspond to the first pixels 81
  • the illumination pixels correspond to the second pixels 82
  • the display pixels in FIG. 3 correspond to the second pixels 82
  • the illumination pixels correspond to the first pixels 81.
  • a black matrix may be included between display pixels to prevent crosstalk of light.
  • a method of preparing the above display panel is also provided.
  • the prepared display panel is capable of both display and illumination functions.
  • FIG. 4 is a flow chart of a method of preparing a display panel in accordance with an embodiment of the present disclosure. As shown in Fig. 4, in step 401, a thin film transistor is formed on a substrate. FIG. 5 further shows a schematic diagram of forming the thin film transistor 2.
  • the thin film transistor 2 is formed on the substrate 1.
  • the substrate 1 may be a transparent substrate such as a glass substrate.
  • the method of forming the thin film transistor 2 is not particularly limited, and the thin film transistor 2 can be formed using a method known to those skilled in the art.
  • the thin film transistor 2 may be a top gate thin film transistor or a bottom gate thin film transistor.
  • step S402 an insulating layer is formed to cover the substrate and the thin film transistor.
  • FIG. 6 further shows a schematic view of forming the insulating layer 3.
  • step S402 further includes patterning the insulating layer 3 to form a via 31 through the insulating layer 3 and exposing the source/drain electrodes of the thin film transistor 2.
  • the insulating layer 3 may be a laminate including a passivation layer and a protective layer.
  • step S403 a first electrode and a second electrode are formed on the insulating layer.
  • FIG. 7 further shows a schematic view of forming the first electrode 41 and the second electrode 42.
  • the patterned first electrode 41 and second electrode 42 are formed on the insulating layer 3.
  • the orthographic projection of the first electrode 41 on the substrate 1 does not overlap with the orthographic projection of the thin film transistor 2 on the substrate 1, and the orthographic projection of the second electrode 42 on the substrate 1 overlaps with the orthographic projection of the thin film transistor 2 on the substrate 1.
  • the first electrode 41 is a transparent electrode.
  • the second electrode 42 is a non-transparent electrode.
  • step S404 a pixel defining layer is formed between the first electrode and the second electrode.
  • FIG. 8 further shows a schematic diagram of forming the pixel definition layer 5.
  • a patterned pixel defining layer 5 is formed between the first electrode 41 and the second electrode 42.
  • the pixel defining layer 5 encloses a pixel opening, thereby forming a plurality of sub-pixel units.
  • step S405 a light-emitting layer is formed on the first electrode, the second electrode, and the pixel defining layer.
  • FIG. 9 further shows a schematic view of the formation of the light-emitting layer 6.
  • the light emitting layer 6 is formed to cover the first electrode 41, the second electrode 42, and the pixel defining layer 5.
  • the light-emitting layer 5 may be an OLED light-emitting layer or a QLED light-emitting layer. Those skilled in the art can make a selection according to actual needs.
  • step S406 an electrode layer is formed on the light-emitting layer.
  • FIG. 10 further shows a schematic view of forming the electrode layer 7.
  • the electrode layer 7 is formed on the light-emitting layer 6.
  • the electrode layer 7 may include a third electrode 71 and a fourth electrode 72.
  • the orthographic projection of the third electrode 71 on the substrate 1 overlaps with the orthographic projection of the first electrode 41 on the substrate 1, and the orthographic projection of the fourth electrode 72 on the substrate 1 overlaps with the orthographic projection of the second electrode 42 on the substrate 1.
  • the first electrode 41 and the second electrode 42 are anodes.
  • the third electrode 71 and the fourth electrode 72 are cathodes.
  • the first electrode 41, the third electrode 71, and the first portion 61 of the light emitting layer 6 may constitute the first pixel 81.
  • the second electrode 42, the fourth electrode 72, and the second portion 62 of the light emitting layer 6 may constitute the second pixel 82.
  • the first electrode 41 is connected to the source/drain electrodes of the thin film transistor 2 via the via 31 so that the first pixel 81 serves as a display pixel and the second pixel 82 serves as an illumination pixel.
  • the second electrode 42 may also be connected to the source/drain electrodes of the thin film transistor 2 via the via 31, so that the first pixel 81 serves as an illumination pixel and the second pixel 82 serves as a display pixel, as shown in FIG.
  • a display method for displaying using the above display panel which enables the display panel to perform both display and illumination functions.
  • FIG. 11 is a schematic diagram of a first mode of a display panel in accordance with an embodiment of the present disclosure.
  • the first electrode 41 is connected to the source/drain electrodes of the thin film transistor 2 via the via 31, with the first pixel 81 serving as a display pixel and the second pixel 82 as an illumination pixel.
  • the first pixel 81 emits light
  • the second pixel 82 does not emit light, thereby achieving double-sided display. That is to say, the first mode can be referred to as a double-sided display mode.
  • FIG. 12 is a schematic diagram of a second mode of a display panel in accordance with an embodiment of the present disclosure.
  • the first electrode 41 is connected to the source/drain electrodes of the thin film transistor 2 via the via 31, with the first pixel 81 serving as a display pixel and the second pixel 82 as an illumination pixel.
  • the first pixel 81 and the second pixel 82 are simultaneously illuminated, thereby achieving both-sided display and illumination. Since the second pixel 82 emits light for illumination, the brightness of the illumination affects the display effect of the ipsilateral display area to form a secret display, thereby enabling one side to display the other side of the illumination. That is to say, the second mode can be referred to as a secret display mode.
  • FIG. 13 is a schematic diagram of a third mode of a display panel according to an embodiment of the present disclosure.
  • the first electrode 41 is connected to the source/drain electrodes of the thin film transistor 2 via the via 31, with the first pixel 81 serving as a display pixel and the second pixel 82 as an illumination pixel.
  • the first pixel 81 does not emit light
  • the second pixel 82 emits light, thereby achieving single-sided illumination. That is to say, the third mode can be a single-sided illumination mode.
  • FIG. 14 is a schematic diagram of a fourth mode of a display panel according to an embodiment of the present disclosure.
  • the second electrode 42 is connected to the source/drain electrodes of the thin film transistor 2 via the via 31, with the first pixel 81 serving as an illumination pixel and the second pixel 82 as a display pixel.
  • the first pixel 81 does not emit light
  • the second pixel 82 emits light, thereby achieving single-sided display. That is to say, the third mode can be referred to as a single-sided display mode.
  • FIG. 15 is a schematic diagram of a fifth mode of a display panel in accordance with an embodiment of the present disclosure.
  • the second electrode 42 is connected to the source/drain electrodes of the thin film transistor 2 via the via 31, with the first pixel 81 serving as an illumination pixel and the second pixel 82 as a display pixel.
  • the first pixel 81 emits light
  • the second pixel 82 does not emit light, thereby achieving double-sided illumination. That is to say, the fifth mode can be referred to as a double-sided illumination mode.
  • a display device including the above display panel, which is capable of performing both display and illumination functions.
  • an anode is disposed between the thin film transistor of the display panel and the light emitting layer to utilize the light emitting layer corresponding to the anode, thereby improving the aperture ratio of the display panel and enabling the display panel to be realized. Display and lighting two functions.

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Abstract

一种显示面板(10)及其制备方法、显示装置以及显示方法。该显示面板(10)包括：基板(1)；位于基板(1)上的薄膜晶体管(2)；覆盖基板(1)和薄膜晶体管(2)的绝缘层(3)；位于绝缘层(3)上且电绝缘的第一电极(41)和第二电极(42)，其中，第一电极(41)在基板(1)上的正投影与薄膜晶体管(2)在所述基板(1)上的正投影不重叠，第二电极(42)在基板(1)上的正投影与薄膜晶体管(2)在所述基板(1)上的正投影重叠；位于第一电极(41)和第二电极(42)上的发光层(6)；以及位于发光层(6)上的第三电极(71)和第四电极(72)，其中，第三电极(71)在基板(1)上的正投影与第一电极(41)在所述基板(1)上的正投影重叠，第四电极(72)在基板(1)上的正投影与第二电极(42)在所述基板(1)上的正投影重叠。

Description

显示面板及其制备方法、显示装置以及显示方法
相关申请的交叉引用
本申请要求于2017年6月8日递交的中国专利申请第201710427338.9号优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及显示技术领域，尤其涉及一种显示面板及其制备方法、显示装置以及显示方法。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum Dot Light Emitting Diode，简称QLED)显示器件由于具备自发光、不需要背光源、对比度高、厚度薄、视角广、反应速度快、可用于柔性面板、使用温度范围广等优异特性，被公认为是下一代显示的主流技术，得到了各大显示器制造商的青睐。
发明内容
本公开的实施例提供了一种显示面板及其制备方法、显示装置以及显示方法。
根据本公开的第一方面，提供一种显示面板。所述显示面板包括：基板；位于所述基板上的薄膜晶体管；覆盖所述基板和所述薄膜晶体管的绝缘层；位于所述绝缘层上且电绝缘的第一电极和第二电极，其中，所述第一电极在所述基板上的正投影与所述薄膜晶体管在所述基板上的正投影不重叠，所述第二电极在所述基板上的正投影与所述薄膜晶体管在所述基板上的正投影重叠；位于所述第一电极和所述第二电极上的发光层；以及位于所述发光层上的第三电极和第四电极，其中，所述第三电极在所述基板 上的正投影与所述第一电极在所述基板上的正投影重叠，所述第四电极在所述基板上的正投影与所述第二电极在所述基板上的正投影重叠。所述第一电极、所述第三电极以及位于所述第一电极与所述第三电极之间的所述发光层的第一部分构成第一像素，所述第二电极、所述第四电极以及位于所述第二电极与所述第四电极之间的所述发光层的第二部分构成第二像素。
在本公开的实施例中，所述第一电极经由穿过所述绝缘层的过孔连接到所述薄膜晶体管的源/漏电极，从而将所述第一像素作为显示像素以及将所述第二像素作为照明像素。
在本公开的实施例中，所述第二电极经由穿过所述绝缘层的过孔连接到所述薄膜晶体管的源/漏电极，从而将所述第一像素作为照明像素以及将所述第二像素作为显示像素。
在本公开的实施例中，所述第一电极、所述第三电极以及所述第四电极为透明电极，所述第二电极为非透明电极。
在本公开的实施例中，所述透明电极包括透明导电材料，所述非透明电极包括金属。
在本公开的实施例中，所述第三电极与所述第四电极被形成为一体。
在本公开的实施例中，所述显示面板还包括位于所述第一电极与所述第二电极之间的像素定义层。
根据本公开的第二方面，提供一种制备显示面板的方法。所述方法包括：在基板上形成薄膜晶体管；形成绝缘层以覆盖所述基板和所述薄膜晶体管；在所述绝缘层上形成电绝缘的第一电极和第二电极，其中，所述第一电极在所述基板上的正投影与所述薄膜晶体管在所述基板上的正投影不重叠，所述第二电极在所述基板上的正投影与所述薄膜晶体管在所述基板上的正投影重叠；在所述第一电极和所述第二电极上形成发光层；以及在所述发光层上形成第三电极和第四电极，其中，所述第三电极在所述基板上的正投影与所述第一电极在所述基板上的正投影重叠，所述第四电极在 所述基板上的正投影与所述第二电极在所述基板上的正投影重叠。所述第一电极、所述第三电极以及位于所述第一电极与所述第三电极之间的所述发光层的第一部分构成第一像素，所述第二电极、所述第四电极以及位于所述第二电极与所述第四电极之间的所述发光层的第二部分构成第二像素。
在本公开的实施例中，形成所述绝缘层还包括：构图所述绝缘层以形成穿过所述绝缘层的过孔。
在本公开的实施例中，所述第一电极经由所述过孔连接到所述薄膜晶体管的源/漏电极，从而将所述第一像素作为显示像素以及将所述第二像素作为照明像素。
在本公开的实施例中，所述第二电极经由所述过孔连接到所述薄膜晶体管的源/漏电极，从而将所述第一像素作为照明像素以及将所述第二像素作为显示像素。
在本公开的实施例中，所述第一电极、所述第三电极以及所述第四电极为透明电极，所述第二电极为非透明电极。
在本公开的实施例中，所述透明电极包括透明导电材料，所述非透明电极包括金属。
在本公开的实施例中，所述第三电极与所述第四电极被形成为一体。
在本公开的实施例中，在形成所述发光层之前还包括在所述第一电极与所述第二电极之间形成像素定义层。
根据本公开的第三方面，提供一种包括在本公开的第一方面中描述的显示面板的显示装置。
根据本公开的第四方面，提供一种使用在本公开的第一方面中描述的显示面板的显示方法。该方法以下列模式中的一种来控制上述显示面板：第一模式，其中，所述第一像素作为显示像素，所述第二像素作为照明像素，所述第一像素发光，所述第二像素不发光；第二模式，其中，所述第一像素作为显示像素，所述第二像素作为照明像素，所述第一像素和所述 第二像素同时发光；第三模式，其中，所述第一像素作为显示像素，所述第二像素作为照明像素，所述第一像素不发光，所述第二像素发光；第四模式，其中，所述第一像素作为照明像素，所述第二像素作为显示像素，所述第一像素不发光，所述第二像素发光；以及第五模式，其中，所述第一像素作为照明像素，所述第二像素作为显示像素，所述第一像素发光，所述第二像素不发光。
适应性的进一步的方面和范围从本文中提供的描述变得明显。应当理解，本申请的各个方面可以单独或者与一个或多个其他方面组合实施。还应当理解，本文中的描述和特定实施例旨在仅说明的目的并不旨在限制本申请的范围。
附图说明
本文中描述的附图用于仅对所选择的实施例的说明的目的，并不是所有可能的实施方式，并且不旨在限制本申请的范围，其中：
图1是根据本公开实施例的显示面板的截面的示意图；
图2是根据本公开另一实施例的显示面板的截面的示意图；
图3是根据本公开实施例的显示面板的平面示意图；
图4是根据本公开实施例的制备显示面板的方法的流程图；
图5是根据本公开实施例的显示面板的制备方法的形成薄膜晶体管的示意图；
图6是根据本公开实施例的显示面板的制备方法的形成绝缘层的示意图；
图7是根据本公开实施例的显示面板的制备方法的形成第一电极和第二电极的示意图；
图8是根据本公开实施例的显示面板的制备方法的形成像素定义层的示意图；
图9是根据本公开实施例的显示面板的制备方法的形成发光层的示意 图；
图10是根据本公开实施例的显示面板的制备方法的形成电极层的示意图；
图11是根据本公开实施例的显示面板的第一模式的示意图；
图12是根据本公开实施例的显示面板的第二模式的示意图；
图13是根据本公开实施例的显示面板的第三模式的示意图；
图14是根据本公开实施例的显示面板的第四模式的示意图；以及
图15是根据本公开实施例的显示面板的第五模式的示意图。
贯穿这些附图的各个视图，相应的参考编号指示相应的部件或特征。
具体实施方式
首先，需要说明的是，除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。相似地，措辞“包含”和“包括”将解释为包含在内而不是独占性地。同样地，术语“包括”和“或”应当解释为包括在内的，除非本文中另有说明。在本文中使用术语“实例”之处，特别是当其位于一组术语之后时，所述“实例”仅仅是示例性的和阐述性的，且不应当被认为是独占性的或广泛性的。
另外，还需要说明的是，在本公开的描述中，术语“上”、“之上”、“下”、“之下”、“顶”、“底”、“之间”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。此外，当元件或层被称为在另一元件或层“上”时，它可以直接在该另一元件或层上，或者可以存在中间的元件或层；同样，当元件或层被称为在另一元件或层“下”时，它可以直接在该另一元件或层下，或者可以存在至少一个中间的元件或层；当元件或层被称为在两元件或两层“之间”时，其可以为该两元件或两层之间的唯一的元件或层，或者可以存在一个以上的中间元件或层。
此外，还需要说明的是，当介绍本申请的元素及其实施例时，冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素；除非另有说明，“多个”的 含义是两个或两个以上；用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素；术语“第一”、“第二”、“第三”等仅用于描述的目的，而不能理解为指示或暗示相对重要性及形成顺序。
本公开中描绘的流程图仅仅是一个例子。在不脱离本公开精神的情况下，可以存在该流程图或其中描述的步骤的很多变型。例如，所述步骤可以以不同的顺序进行，或者可以添加、删除或者修改步骤。这些变型都被认为是所要求保护的方面的一部分。
现将参照附图更全面地描述示例性的实施例。
在本公开的实施例中，提供了一种显示面板。该显示面板可以为OLED显示面板或QLED显示面板。在该显示面板的薄膜晶体管与发光层之间设置一个阳极，以将与该阳极对应的发光层利用起来，从而提高了显示面板的开口率，并且使显示面板能够实现显示和照明两种功能。
图1是根据本公开实施例的显示面板10的截面的示意图。如图1所示，显示面板10包括：基板1；位于基板1上的薄膜晶体管2；覆盖基板1和薄膜晶体管2的绝缘层3，其中，绝缘层3中包括贯穿绝缘层3的过孔31；位于绝缘层3上且电绝缘的第一电极41和第二电极42，其中，第一电极41在基板1上的正投影与薄膜晶体管2在基板1上的正投影不重叠，第二电极42在基板1上的正投影与薄膜晶体管2在基板1上的正投影重叠；位于第一电极41与第二电极42之间的像素定义层5；位于第一电极41、第二电极42和像素定义层5上的发光层6；以及位于发光层6上的电极层7。电极层7包括第三电极71和第四电极72。第三电极71在基板1上的正投影与第一电极41在基板1上的正投影重叠，第四电极72在基板1上的正投影与第二电极42在基板1上的正投影重叠。根据本公开的实施例，第三电极71和第四电极72可以被形成为一体。
在本公开的实施例中，第一电极41、第三电极71以及位于第一电极41与第三电极71之间的发光层6的第一部分61构成第一像素81，第二电极42、第四电极72以及位于第二电极42与第四电极72之间的发光层6 的第二部分62构成第二像素82。
如图1所示，第一电极41经由过孔31连接到薄膜晶体管2的源/漏电极，从而将第一像素81作为显示像素以及将第二像素82作为照明像素。
图2是根据本公开另一实施例的显示面板20的截面的示意图。图2与图1的区别在于，如图2所示，第二电极42经由过孔31连接到薄膜晶体管2的源/漏电极，从而将第一像素81作为照明像素以及将第二像素82作为显示像素。图2的其他部分与图1类似，在此不再赘述。
在本公开的实施例中，第一电极41、第三电极71和第四电极72为透明电极，第二电极42为非透明电极。作为一个示例，透明电极可以包括透明导电材料，例如，诸如铟锡氧化物、铟锡锌氧化物以及氧化锡等的透明导电氧化物。非透明电极可以包括诸如银或铝等的金属。根据本公开的实施例，当金属为银或铝等易于氧化的金属时，还可以在金属表面上形成抗氧化层，例如，铟锡氧化物。在本公开的实施例中，非透明电极可以为铟锡氧化物/银/铟锡氧化物的叠层，如图1中的第二电极42所示。
在本公开的实施例中，基板1为透明的。基板1可以为玻璃基板。
在本公开的实施例中，薄膜晶体管2可以是顶栅型薄膜晶体管，也可以是底栅型薄膜晶体管，在此不作具体限定。
在本公开的实施例中，绝缘层3可以为包括钝化层和保护层的叠层。
图3是根据本公开实施例的显示面板的平面示意图。如图3所示，显示面板的像素区包括显示像素和照明像素。其中，在如图1所示的实施例中，图3中的显示像素对应于第一像素81，照明像素对应于第二像素82。在如图2所示的实施例中，图3中的显示像素对应于第二像素82，照明像素对应于第一像素81。另外，显示像素之间还可以包括黑矩阵，以防止光的串扰。
在本公开的实施例中，还提供了一种制备上述显示面板的方法。制备出的显示面板能够实现显示和照明两种功能。
图4是根据本公开实施例的制备显示面板的方法的流程图。如图4所 示，在步骤401中，在基板上形成薄膜晶体管。图5进一步示出了形成薄膜晶体管2的示意图。
在本公开的实施例中，如图5所示，在基板1上形成薄膜晶体管2。基板1可以为诸如玻璃基板等的透明基板。在本公开的实施例中，对形成薄膜晶体管2的方法不作具体限定，可以使用本领域技术人员公知的方法形成薄膜晶体管2。另外，薄膜晶体管2可以为顶栅型薄膜晶体管或底栅型薄膜晶体管。
如图4所示，在步骤S402中，形成绝缘层以覆盖基板和薄膜晶体管。图6进一步示出了形成绝缘层3的示意图。
在本公开的实施例中，如图6所示，形成绝缘层3以覆盖基板1和薄膜晶体管2。另外，步骤S402还包括构图绝缘层3以形成穿过绝缘层3且暴露薄膜晶体管2的源/漏电极的过孔31。
在本公开的实施例中，绝缘层3可以为包括钝化层和保护层的叠层。
如图4所示，在步骤S403中，在绝缘层上形成第一电极和第二电极。图7进一步示出了形成第一电极41和第二电极42的示意图。
在本公开的实施例中，如图7所示，在绝缘层3上形成图案化的第一电极41和第二电极42。第一电极41在基板1上的正投影与薄膜晶体管2在基板1上的正投影不重叠，第二电极42在基板1上的正投影与薄膜晶体管2在基板1上的正投影重叠。第一电极41为透明电极。第二电极42为非透明电极。
如图4所示，在步骤S404中，在第一电极与第二电极之间形成像素定义层。图8进一步示出了形成像素定义层5的示意图。
在本公开的实施例中，如图8所示，在第一电极41与第二电极42之间形成图案化的像素定义层5。像素定义层5围成像素开口，从而形成多个子像素单元。
如图4所示，在步骤S405中，在第一电极、第二电极和像素定义层上形成发光层。图9进一步示出了形成发光层6的示意图。
在本公开的实施例中，如图9所示，形成发光层6以覆盖第一电极41、第二电极42和像素定义层5。在此，发光层5可以是OLED发光层或QLED发光层。本领域的技术人员可以根据实际需要而进行选择。
如图4所示，在步骤S406中，在发光层上形成电极层。图10进一步示出了形成电极层7的示意图。
在本公开的实施例中，如图10所示，在发光层6上形成电极层7。电极层7可以包括第三电极71和第四电极72。第三电极71在基板1上的正投影与第一电极41在基板1上的正投影重叠，第四电极72在基板1上的正投影与第二电极42在基板1上的正投影重叠。第一电极41和第二电极42为阳极。第三电极71和第四电极72为阴极。第一电极41、第三电极71和发光层6的第一部分61可以构成第一像素81。第二电极42、第四电极72和发光层6的第二部分62可以构成第二像素82。
在图10中，第一电极41经由过孔31连接到薄膜晶体管2的源/漏电极，以使第一像素81作为显示像素以及使第二像素82作为照明像素。此外，第二电极42也可以经由过孔31连接到薄膜晶体管2的源/漏电极，从而使第一像素81作为照明像素以及使第二像素82作为显示像素，如图2所示。
在本公开的实施例中，还提供了一种使用上述显示面板进行显示的显示方法，使显示面板实现显示和照明两种功能。
图11是根据本公开实施例的显示面板的第一模式的示意图。如图11所示，在第一模式下，第一电极41经由过孔31连接到薄膜晶体管2的源/漏电极，使第一像素81作为显示像素，第二像素82作为照明像素。在第一模式下，第一像素81发光，第二像素82不发光，从而实现双面显示。也就是说，第一模式可以称为双面显示模式。
图12是根据本公开实施例的显示面板的第二模式的示意图。如图12所示，在第二模式下，第一电极41经由过孔31连接到薄膜晶体管2的源/漏电极，使第一像素81作为显示像素，第二像素82作为照明像素。在第 二模式下，第一像素81和第二像素82同时发光，从而同时实现双面显示和照明。由于第二像素82发光以用于照明，照明的亮度会影响同侧显示区域的显示效果，以形成保密显示，从而实现一面显示另一面照明。也就是说，第二模式可以称为保密显示模式。
图13是根据本公开实施例的显示面板的第三模式的示意图。如图13所示，在第三模式下，第一电极41经由过孔31连接到薄膜晶体管2的源/漏电极，使第一像素81作为显示像素，第二像素82作为照明像素。在第三模式下，第一像素81不发光，第二像素82发光，从而实现单面照明。也就是说，第三模式可以成为单面照明模式。
图14是根据本公开实施例的显示面板的第四模式的示意图。如图14所示，第二电极42经由过孔31连接到薄膜晶体管2的源/漏电极，使第一像素81作为照明像素，第二像素82作为显示像素。在第四模式下，第一像素81不发光，第二像素82发光，从而实现单面显示。也就是说，第三模式可以称为单面显示模式。
图15是根据本公开实施例的显示面板的第五模式的示意图。如图15所示，在第五模式下，第二电极42经由过孔31连接到薄膜晶体管2的源/漏电极，使第一像素81作为照明像素，第二像素82作为显示像素。在第五模式下，第一像素81发光，第二像素82不发光，从而实现双面照明。也就是说，第五模式可以称为双面照明模式。
在本公开的实施例中，还提供了一种包括上述显示面板的显示装置，该显示装置能够实现显示和照明两种功能。
在本公开的实施例中，在显示面板的薄膜晶体管与发光层之间设置一个阳极，以将与该阳极对应的发光层利用起来，从而提高了显示面板的开口率，并且使显示面板能够实现显示和照明两种功能。
以上为了说明和描述的目的提供了实施例的前述描述。其并不旨在是穷举的或者限制本申请。特定实施例的各个元件或特征通常不限于特定的实施例，但是，在合适的情况下，这些元件和特征是可互换的并且可用在 所选择的实施例中，即使没有具体示出或描述。同样也可以以许多方式来改变。这种改变不能被认为脱离了本申请，并且所有这些修改都包含在本申请的范围内。

Claims (15)

  1. 一种显示面板，包括：
    基板；
    位于所述基板上的薄膜晶体管；
    覆盖所述基板和所述薄膜晶体管的绝缘层；
    位于所述绝缘层上且电绝缘的第一电极和第二电极，其中，所述第一电极在所述基板上的正投影与所述薄膜晶体管在所述基板上的正投影不重叠，所述第二电极在所述基板上的正投影与所述薄膜晶体管在所述基板上的正投影重叠；
    位于所述第一电极和所述第二电极上的发光层；以及
    位于所述发光层上的第三电极和第四电极，其中，所述第三电极在所述基板上的正投影与所述第一电极在所述基板上的正投影重叠，所述第四电极在所述基板上的正投影与所述第二电极在所述基板上的正投影重叠，
    其中，所述第一电极、所述第三电极以及位于所述第一电极与所述第三电极之间的所述发光层的第一部分构成第一像素，所述第二电极、所述第四电极以及位于所述第二电极与所述第四电极之间的所述发光层的第二部分构成第二像素。
  2. 根据权利要求1所述的显示面板，其中，所述第一电极经由穿过所述绝缘层的过孔连接到所述薄膜晶体管的源/漏电极，从而将所述第一像素作为显示像素以及将所述第二像素作为照明像素。
  3. 根据权利要求1所述的显示面板，其中，所述第二电极经由穿过所述绝缘层的过孔连接到所述薄膜晶体管的源/漏电极，从而将所述第一像素作为照明像素以及将所述第二像素作为显示像素。
  4. 根据权利要求2或3所述的显示面板，其中，所述第一电极、所述第三电极以及所述第四电极为透明电极，所述第二电极为非透明电极。
  5. 根据权利要求4所述的显示面板，其中，所述透明电极包括透明导电材料，所述非透明电极包括金属。
  6. 根据权利要求1所述的显示面板，其中，还包括位于所述第一电极 与所述第二电极之间的像素定义层。
  7. 一种制备显示面板的方法，包括：
    在基板上形成薄膜晶体管；
    形成绝缘层以覆盖所述基板和所述薄膜晶体管；
    在所述绝缘层上形成电绝缘的第一电极和第二电极，其中，所述第一电极在所述基板上的正投影与所述薄膜晶体管在所述基板上的正投影不重叠，所述第二电极在所述基板上的正投影与所述薄膜晶体管在所述基板上的正投影重叠；
    在所述第一电极和所述第二电极上形成发光层；以及
    在所述发光层上形成第三电极和第四电极，其中，所述第三电极在所述基板上的正投影与所述第一电极在所述基板上的正投影重叠，所述第四电极在所述基板上的正投影与所述第二电极在所述基板上的正投影重叠，
    其中，所述第一电极、所述第三电极以及位于所述第一电极与所述第三电极之间的所述发光层的第一部分构成第一像素，所述第二电极、所述第四电极以及位于所述第二电极与所述第四电极之间的所述发光层的第二部分构成第二像素。
  8. 根据权利要求7所述的方法，其中，形成所述绝缘层还包括：构图所述绝缘层以形成穿过所述绝缘层的过孔。
  9. 根据权利要求8所述的方法，其中，所述第一电极经由所述过孔连接到所述薄膜晶体管的源/漏电极，从而将所述第一像素作为显示像素以及将所述第二像素作为照明像素。
  10. 根据权利要求8所述的方法，其中，所述第二电极经由所述过孔连接到所述薄膜晶体管的源/漏电极，从而将所述第一像素作为照明像素以及将所述第二像素作为显示像素。
  11. 根据权利要求9或10所述的方法，其中，所述第一电极、所述第三电极以及所述第四电极为透明电极，所述第二电极为非透明电极。
  12. 根据权利要求11所述的方法，其中，所述透明电极包括透明导电 材料，所述非透明电极包括金属。
  13. 根据权利要求7所述的方法，其中，在形成所述发光层之前还包括在所述第一电极与所述第二电极之间的形成像素定义层。
  14. 一种包括根据权利要求1至6中任一项所述的显示面板的显示装置。
  15. 一种使用根据权利要求1至6中任一项所述的显示面板的显示方法，所述方法以下列模式中的一种来控制所述显示面板：
    第一模式，其中，所述第一像素作为显示像素，所述第二像素作为照明像素，所述第一像素发光，所述第二像素不发光；
    第二模式，其中，所述第一像素作为显示像素，所述第二像素作为照明像素，所述第一像素和所述第二像素同时发光；
    第三模式，其中，所述第一像素作为显示像素，所述第二像素作为照明像素，所述第一像素不发光，所述第二像素发光
    第四模式，其中，所述第一像素作为照明像素，所述第二像素作为显示像素，所述第一像素不发光，所述第二像素发光；以及
    第五模式，其中，所述第一像素作为照明像素，所述第二像素作为显示像素，所述第一像素发光，所述第二像素不发光。
PCT/CN2018/072049 2017-06-08 2018-01-10 显示面板及其制备方法、显示装置以及显示方法 Ceased WO2018223699A1 (zh)

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