WO2018214635A1 - 阵列基板、显示装置以及制备阵列基板的方法 - Google Patents
阵列基板、显示装置以及制备阵列基板的方法 Download PDFInfo
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- WO2018214635A1 WO2018214635A1 PCT/CN2018/080425 CN2018080425W WO2018214635A1 WO 2018214635 A1 WO2018214635 A1 WO 2018214635A1 CN 2018080425 W CN2018080425 W CN 2018080425W WO 2018214635 A1 WO2018214635 A1 WO 2018214635A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 143
- 238000000034 method Methods 0.000 title claims abstract description 60
- 239000010409 thin film Substances 0.000 claims abstract description 47
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 38
- 238000000206 photolithography Methods 0.000 claims description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 238000001459 lithography Methods 0.000 claims description 8
- 239000002210 silicon-based material Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 6
- 239000010408 film Substances 0.000 claims description 3
- 238000005224 laser annealing Methods 0.000 claims description 3
- 238000009825 accumulation Methods 0.000 description 10
- 239000004973 liquid crystal related substance Substances 0.000 description 10
- 230000000694 effects Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 239000007769 metal material Substances 0.000 description 8
- 238000005286 illumination Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- H01L27/1214—
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- H01L27/1259—
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- H01L2021/775—
Definitions
- the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a display device, and a method of fabricating an array substrate.
- Low Temperature Poly-Silicon has received extensive attention in recent years due to its high electron mobility.
- Low-temperature polysilicon technology is a branch of multi-product silicon technology, which has significant advantages in miniaturizing components, increasing panel aperture ratio, and improving picture quality and clarity.
- the low-temperature multi-silicon material can have a faster reaction speed when preparing the thin film transistor, thereby facilitating the control of the liquid crystal molecules of the thin film transistor.
- the smaller thin film circuit is advantageous for increasing the aperture ratio of the liquid crystal display, so that better display brightness and better color output can be obtained under the premise that the output power of the backlight module is constant.
- an array substrate including:
- the thin film transistor being located on the substrate and comprising:
- a light shielding layer on the substrate and including an amorphous silicon material
- An active layer located on a side of the light shielding layer away from the substrate.
- the array substrate includes a display area, and the thin film transistor is disposed in the display area.
- the array substrate includes at least one of an array substrate row driving region and a multiplexing region, and the thin film transistor is disposed in the array substrate row driving region and the multiplexing region. Said at least one.
- the active layer is an active layer formed of polysilicon.
- the active layer covers only a portion of the surface of the light shielding layer.
- the surface of the light shielding layer that is not covered by the active layer has a width of 0.2 to 0.3 microns.
- a display device including:
- a color filter substrate the color film substrate and the array substrate are disposed on a box.
- a method for preparing an array substrate including:
- a thin film transistor is disposed on the substrate, and the step of disposing the thin film transistor on the substrate comprises:
- the light shielding layer being formed of amorphous silicon
- An active layer is disposed on a side of the light shielding layer away from the substrate.
- the array substrate includes a display area
- the step of disposing the thin film transistor on the substrate further includes disposing the thin film transistor in the display area.
- the array substrate includes at least one of an array substrate row driving region and a multiplexing region
- the disposing the thin film transistor on the substrate includes disposing the thin film transistor in the at least one of the array substrate row driving region and the multiplexing region.
- the step of disposing the light shielding layer on the substrate comprises forming the light shielding layer by using a first photolithography process
- the step of disposing an active layer on a side of the light shielding layer away from the substrate includes forming the active layer by using a second photolithography process
- the first lithography process and the second lithography process share one lithography mask.
- the exposure amount of the first photolithography process is 70-90% of the exposure amount of the second photolithography process.
- the step of forming the light shielding layer by using the first photolithography process comprises:
- the first amorphous silicon layer is subjected to a first photolithography process to form the light shielding layer.
- the step of forming the active layer by using a second photolithography process comprises:
- the second amorphous silicon layer subjected to the second photolithography process is subjected to laser annealing treatment to convert amorphous silicon into polycrystalline silicon to form the active layer.
- FIG. 1 shows a schematic structural view of an array substrate according to an embodiment of the present disclosure
- FIG. 2 is a schematic structural view of an array substrate according to another embodiment of the present disclosure.
- FIG. 3 is a schematic structural view of an array substrate according to still another embodiment of the present disclosure.
- FIG. 5 shows a partial structural diagram of a thin film transistor according to an embodiment of the present disclosure
- FIG. 6 shows a schematic structural view of a display device according to an embodiment of the present disclosure
- FIG. 7 is a schematic cross-sectional view showing a display device according to an embodiment of the present disclosure.
- FIG. 8 shows a schematic flow chart of preparing an array substrate according to an embodiment of the present disclosure.
- a display device based on low-temperature polysilicon has at least one of the problems that the switching ratio of the thin film transistor on the array substrate is not ideal, and the production process is complicated. This is mainly due to the fact that low-temperature polysilicon is sensitive to light, and under the illumination of the backlight, photo-generated leakage current is generated. In general, the photo-induced leakage current of low-temperature polysilicon is ten to 100 times that of amorphous silicon. Therefore, if the photo-generated leakage current cannot be effectively controlled, the array substrate cannot effectively control the deflection of the liquid crystal molecules, thereby affecting the display effect.
- Both light and temperature cause low-temperature polysilicon to generate photo-generated leakage current.
- a metal material is generally used to form a light-shielding structure.
- the light-shielding structure described above can be applied only to the display area, and cannot be applied to the array substrate row driving region and the multiplexing region. This is mainly because the light-shielding structure formed of the metal material easily forms charge accumulation, and thus cannot be applied to the array substrate row driving and multiplexing regions.
- the introduction of the light-shielding structure of the metal material also complicates the preparation process of the low-temperature polysilicon field effect transistor.
- At least one embodiment of the present disclosure provides an array substrate, a display device, and a method of fabricating an array substrate that can at least partially address or alleviate the above problems.
- an array substrate is provided.
- the array substrate 900 includes a substrate 100 and a thin film transistor 200.
- the thin film transistor 200 is located on the substrate 100.
- the thin film transistor 200 includes a light shielding layer 210 and an active layer 220.
- the light shielding layer 210 is on the substrate 100 and is formed of amorphous silicon.
- the active layer 220 is disposed on a side of the light shielding layer 210 away from the substrate 100.
- the thin film transistor may also have a structure such as a source, a drain, a gate, etc., in order to realize that the thin film transistor functions normally.
- the array substrate 900 includes a display area 300.
- the array substrate 900 may further include at least one of an array substrate row drive region (GOA) 400 and a multiplex region (MUX) 500.
- the thin film transistor 200 is located in the display area 300.
- the thin film transistor 200 may also be disposed in at least one of the array substrate row driving region 400 and the multiplexing region 500.
- the active layer can be at least partially reduced to generate photo-generated leakage current under illumination conditions without generating charge accumulation, and further, the photo-generated leakage current of the display region, the array substrate row driving region and the multiplexing region can be made. Effective control is achieved so that the performance of the array substrate can be improved.
- the material constituting the active layer 220 is not particularly limited as long as the function of using the thin film transistor can be realized, and those skilled in the art can design according to the needs of actual use.
- the active layer 220 may be formed of polysilicon. More specifically, the active layer 220 may be formed using low temperature polysilicon. Thereby, the performance of the array substrate can be further improved by utilizing the excellent performance of the low temperature polysilicon material.
- the polycrystalline silicon generates light-generated carriers by illumination, thereby forming a photo-generated leakage current, thereby affecting the performance of the array substrate.
- the photo-generated leakage current of the active layer 220 under illumination is ten to 100 times that of the active layer formed of amorphous silicon.
- the light generated by the backlight module needs to penetrate the array substrate, be irradiated to the liquid crystal layer and deflected, and finally emitted from the side of the color filter substrate to realize the function of using the display device. Therefore, the active layer of the array substrate is inevitably exposed to light during use.
- the backlight generated by the backlight module can be first penetrated through the substrate 100 and then irradiated onto the light shielding layer 220.
- the active layer 220 of the array substrate can be prevented from being exposed to the backlight environment during use, thereby alleviating the generation of photo-generated leakage current.
- Amorphous silicon is significantly less sensitive to light than polysilicon. That is to say, under the illumination condition, the amorphous silicon material does not generate photogenerated carriers. Also, the amorphous silicon material has a good absorption ability for visible light, and thus can be used to form the light shielding layer 210 of the array substrate according to an embodiment of the present disclosure.
- the light-shielding layer formed using amorphous silicon can be prepared by a process similar to that of the active layer 220 formed of polycrystalline silicon, as compared with the light-shielding layer prepared using a metal material, thereby facilitating the simplification of the production process.
- the light-shielding layer 210 formed of amorphous silicon does not cause accumulation of electric charges, and thus can be more widely applied to the array substrate, and at least to some extent, does not affect the electrical properties of the thin film transistor.
- the specific size and shape of the light shielding layer 210 are not particularly limited, and those skilled in the art may select according to actual conditions.
- the size of the light shielding layer 210 may be slightly larger than the size of the active layer 220 to achieve a better light shielding effect.
- the backlight emitted by the backlight module firstly illuminates the light shielding layer 210. Therefore, when the size of the light shielding layer 210 is larger than the size of the active layer 220, the backlight can be more fully shielded to prevent the backlight from being illuminated.
- Layer 220 produces a photo-generated leakage current.
- the size of the light shielding layer 210 is larger than the size of the active layer 220 means that the cross-sectional area of the light shielding layer 210 is larger than the area of the cross section of the active layer 220.
- the active layer 220 covers a portion of the surface of the light shielding layer 210, and a portion of the surface of the light shielding layer 210 that is in contact with the active layer 220 is partially covered by the active layer 220. That is, the active layer 220 is close to the surface on the side of the light shielding layer 210, and is entirely covered by the light shielding layer 210.
- the width of the surface of the light shielding layer 210 that is not covered by the active layer 220 may be 0.2-0.3 microns. Thereby, a better shading effect can be achieved.
- a person skilled in the art can set the cross-sectional ratio between the active layer 220 and the light shielding layer 210 as needed.
- the cross-sectional dimension of the light shielding layer 210 may also be set to be the same as or smaller than the cross-sectional dimension of the active layer 220.
- the thin film transistor 200 is also disposed in at least one of the array substrate row driving region 400 and the multiplexing region 500 of the array substrate 900. That is, a light shielding layer 210 composed of amorphous silicon is also provided in at least one of the array substrate row driving region 400 and the multiplexing region 500. Thereby, the leakage currents of the display region 300, the array substrate row driving region 400, and the multiplexing region 500 can be effectively controlled to at least further improve the performance of the array substrate 900.
- the light shielding layer 210 is formed of an amorphous silicon material, the light shielding layer 210 according to an embodiment of the present disclosure does not generate charge accumulation as compared with the light shielding layer formed of the metal material.
- an array substrate in which an active layer is formed using low-temperature polysilicon is generally designed using a top gate type TFT. That is, a light shielding layer 210 made of a metal material is formed under the active layer 220 (TFT channel region). Since the large-area metal structure causes the accumulation of electric charges, when the light-shielding layer 210' is formed of a metal material, the light-shielding layer 210' is disposed only at the active layer 220 corresponding to the gate electrode 230, and both sides of the light-shielding layer 210' are controlled. Longer than the channel to achieve a shading effect.
- the light shielding layer 210' formed by the metal structure can block the doped region of the light doping drain process (LDD) of the TFT, but in order to avoid charge accumulation, the active layer 220 at the source terminal 250, the drain terminal 240, and the like is not Shading treatment.
- LDD light doping drain process
- a large area of metal material is placed in the row driving and multiplexing regions of the array substrate, which tends to cause charge accumulation. Therefore, with the light shielding layer formed of metal, the metal light shielding layer is formed only under the TFT channel of the display region, and the TFT in the row driving and multiplexing region of the array substrate is not subjected to any processing.
- the light shielding layer 210 since the light shielding layer 210 is formed of non-silicon, the light shielding layer 210 does not cause accumulation of charges, so that the light shielding layer 210 may be disposed on all lower surfaces of the active layer 220. This can significantly reduce the photo-generated leakage current generated by the illumination. Further, since it is not necessary to consider the influence of charge accumulation on the electrical performance of the TFT, the structure can be applied to the display region of the array substrate, the array substrate row driving and the multiplex region. The photo-generated leakage current can be effectively controlled to a certain extent to further improve the performance of the array substrate.
- the display device 1000 includes the aforementioned array substrate 900.
- the display device has all the features and advantages of the foregoing array substrate, and details are not described herein again.
- the array substrate of the display device can at least partially prevent the generation of light leakage current, and the light shielding layer does not generate charge accumulation, and further, the light leakage current of the display region, the array substrate row driving region and the multiplexing region can be obtained. At least partially effective control, so that the performance of the display device can be improved.
- the display device 1000 further includes a color film substrate 700 and a liquid crystal layer 800.
- the color filter substrate 700 and the array substrate 900 are disposed in a box, and the liquid crystal layer 800 is packaged between the color filter substrate 700 and the array substrate 900.
- the liquid crystal molecules 10 are encapsulated in the liquid crystal layer 800, whereby the display function of the display device can be realized.
- the array substrate prepared by the method may be the aforementioned array substrate.
- the method includes disposing a thin film transistor on a substrate.
- the step of setting the thin film transistor may specifically include the following steps:
- the light shielding layer is disposed on the substrate.
- a light shielding layer is formed on the substrate.
- the light shielding layer formed in this step may have the same features and advantages as the light shielding layer of the array substrate described above.
- the material, shape and the like of the light shielding layer have been described in detail above and will not be described again.
- the light shielding layer is formed of amorphous silicon, whereby the photo-generated leakage current can be at least partially effectively controlled.
- the specific manner in which the light shielding layer is provided is not particularly limited.
- disposing the light shielding layer on the substrate includes forming the light shielding layer by a first photolithography process.
- the step of forming a light shielding layer by using the first photolithography process comprises: first depositing an amorphous silicon material on the substrate to form a first amorphous silicon layer, and then performing the first amorphous silicon layer by using a mask; A photolithography process removes the first amorphous silicon layer at a region where the light shielding layer is not required to be provided, thereby obtaining a light shielding layer according to an embodiment of the present disclosure.
- an active layer is disposed on a side of the light shielding layer away from the substrate.
- the active layer formed in this step may have the same features and advantages as the active layer of the array substrate described above.
- the material of the active layer has been described in detail above and will not be described herein.
- the active layer may be formed of polysilicon, whereby the performance of the array substrate can be further improved.
- the specific manner of setting the active layer is not particularly limited.
- the active layer is formed by a second photolithography process, which comprises: first depositing a second non-silicon layer on the light-shielding layer prepared previously and on the substrate not covered by the light-shielding layer, and then The second amorphous silicon layer is subjected to a second photolithography process, and finally the second amorphous silicon layer subjected to the second photolithography process is subjected to laser annealing treatment to convert amorphous silicon into polycrystalline silicon to form an active layer.
- the first photolithography process and the second photolithography process may employ the same mask.
- the size of the light shielding layer may be slightly larger than the size of the active layer. Photolithography processing using the same mask requires only adjustment of the exposure amount of the two photolithography processes, that is, a light shielding layer having a size slightly larger than that of the active layer can be obtained.
- the exposure amount of the first photolithography process may be 70-90% of the exposure amount of the second photolithography process. In one example, the exposure amount of the first photolithography process may be 15% smaller than the exposure amount of the second photolithography process. Since the exposure amount of the first photolithography process is small, the size of the finally obtained light shielding layer is slightly larger than the size of the mask. That is, the first photolithography process employs an underexposure process, and the first amorphous silicon layer is not completely etched. When the second photolithography process is performed, the second amorphous silicon layer is etched strictly in accordance with the shape of the mask by increasing the exposure amount, whereby the finally obtained light shielding layer can be made larger than the active layer. Thereby, a light-shielding layer having a size larger than that of the active layer can be obtained by a simple process, and a good shading effect is achieved while saving cost.
- the first lithography process and the second lithography process order or the exposure mode described above may also be adjusted or modified, and the cross-sectional dimension of the light shielding layer 210 is set to be opposite to the active layer 220.
- the cross-sectional dimensions are the same or smaller than their cross-sectional dimensions. Therefore, the specific preparation steps thereof will not be described in detail herein.
- the prepared thin film transistor may be disposed in a display region of the array substrate, and the thin film transistor may be disposed in at least one of the row substrate driving region and the multiplexing region.
- the leakage currents of the display region, the array substrate row driving region, and the multiplexing region can be effectively controlled, so that the performance of the array substrate can be further improved.
- the description of the terms “one embodiment”, “another embodiment” or the like means that the specific features, structures, materials or characteristics described in connection with the embodiments are included in at least one embodiment of the present disclosure. .
- the schematic representation of the above terms is not necessarily directed to the same embodiment or example.
- the particular features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.
- various embodiments or examples described in the specification, as well as features of various embodiments or examples may be combined and combined.
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Abstract
公开了阵列基板、显示装置以及制备阵列基板的方法。该阵列基板（900）包括基板（100）和薄膜晶体管（200）。薄膜晶体管位于基板上。薄膜晶体管包括遮光层（210）和有源层（220）。遮光层位于基板上并由非晶硅形成。有源层设置在遮光层远离基板的一侧。
Description
交叉引用：
本申请要求于2017年5月24日递交的、申请号为201710375611.8、发明名称为“阵列基板、显示装置以及制备阵列基板的方法”的中国专利申请的优先权，其全部内容通过引用并入本申请中。
本公开涉及显示技术领域，尤其涉及阵列基板、显示装置以及制备阵列基板的方法。
低温多晶硅(Low Temperature Poly-Silicon，LTPS)由于具有较高的电子迁移率，近年来受到了广泛的关注。低温多晶硅技术是多品硅技术的一个分支，其在元件小型化、提高面板开口率、提升画面品质与清晰度上具有显著的优势。与传统的非晶硅材料形成的薄膜晶体管液晶显示器(TFT-LCD)相比，低温多品硅材料在制备薄膜晶体管时可以具有更快的反应速度，从而有利于提高薄膜晶体管对于液晶分子的控制能力，并可以缩小薄膜电路的尺寸。因此，一方面可以使得形成的薄膜晶体管小型化，另一方面也可以降低薄膜电路的功耗。并且，较小的薄膜电路有利于提高液晶显示器的开口率，因此在背光模块输出功率不变的前提下，可以获得更好的显示亮度以及更好的色彩输出。
发明内容
根据本公开的一个方面，提供了一种阵列基板，包括：
基板；
薄膜晶体管，所述薄膜晶体管位于所述基板上并且包括：
遮光层，所述遮光层位于所述基板上并包括非晶硅材料；和
有源层，所述有源层位于所述遮光层远离所述基板的一侧。
在一个实施例，所述阵列基板包括显示区，所述薄膜晶体管设置在所述显示区。
在一个实施例，所述阵列基板包括阵列基板行驱动区和多路复用区中的至少一个，所述薄膜晶体管设置在所述阵列基板行驱动区和所述多路复用区中的所述至少一个中。
在一个实施例，所述有源层为由多晶硅形成的有源层。
在一个实施例，所述有源层仅覆盖所述遮光层的部分表面。
在一个实施例，所述遮光层未被所述有源层覆盖的表面的宽度为0.2-0.3微米。
根据本公开的另一实施例，提供了一种显示装置，包括：
如前述的阵列基板；
彩膜基板，所述彩膜基板与所述阵列基板对盒设置。
根据本公开的还一实施例，提供了一种制备阵列基板的方法，包括：
在基板上设置薄膜晶体管，所述在基板上设置所述薄膜晶体管的步骤包括：
在所述基板上设置遮光层，所述遮光层由非晶硅形成；和
在所述遮光层远离所述基板的一侧设置有源层。
在一个实施例，所述阵列基板包括显示区，
所述在基板上设置所述薄膜晶体管的步骤还包括将所述薄膜晶体管设置在所述显示区。
在一个实施例，所述阵列基板包括阵列基板行驱动区和多路复用区中的至少一个，
所述在基板上设置所述薄膜晶体管的步骤包括：将所述薄膜晶体管设置在所述阵列基板行驱动区和所述多路复用区中的所述至少一个中。
在一个实施例，所述在基板上设置所述遮光层的步骤包括利用第一光刻处理形成所述遮光层；
所述在遮光层远离所述基板的一侧设置有源层的步骤包括利用第二光刻处理形成所述有源层，
其中，所述第一光刻处理和所述第二光刻处理共用一个光刻掩膜。
在一个实施例，所述第一光刻处理的曝光量为所述第二光刻处理的曝光量的70-90％。
在一个实施例，所述利用第一光刻处理形成所述遮光层的步骤包括：
在所述基板上沉积第一非晶硅层；
对所述第一非晶硅层进行第一光刻处理，以便形成所述遮光层。
在一个实施例，所述利用第二光刻处理形成所述有源层的步骤包括：
在所述遮光层和所述基板上沉积第二非晶硅层，对所述第二非晶硅层进行第二光刻处理；
对经过所述第二光刻处理的所述第二非晶硅层进行激光退火处理，以便将非晶硅转化为多晶硅，从而形成所述有源层。
本公开的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解，其中：
图1显示了根据本公开一个实施例的阵列基板的结构示意图；
图2显示了根据本公开另一个实施例的阵列基板的结构示意图；
图3显示了根据本公开又一个实施例的阵列基板的结构示意图；
图4显示了一种薄膜晶体管的部分结构示意图；
图5显示了根据本公开一个实施例的薄膜晶体管的部分结构示意图；
图6显示了根据本公开一个实施例的显示装置的结构示意图；
图7显示了根据本公开一个实施例的显示装置的横截面结构示意图；以及
图8显示了根据本公开一个实施例的制备阵列基板的流程示意图。
下面详细描述本公开的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本公开，而不能理解为对本公开的限制。
在本公开的描述中，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开而不是要求本公开必须以特定的方位构造和操作，因此不能理解为对本公开的限制。
目前，基于低温多晶硅的显示装置存在阵列基板上的薄膜晶体管的开关比不够理想、生产工艺较为复杂等问题中的至少一个。这主要是由于低温多晶硅对光照较为敏感，在背光照射下，会产生光生漏电流。一般而言，低温多晶硅的光生漏电流为非晶硅的十至百倍。因此，如果无法有效控制光生漏电流，则阵列基板无法有效控制液晶分子的偏转，进而影响显示效果。
光照和温度均会引发低温多晶硅生成光生漏电流。抑制漏电流的方法主要有以下三种：第一，通过降低热载流子效应，抑制光生漏电流；第二，制备遮光结构，通过避免背光照射到有源层的低温多晶硅材料，抑制光生漏电流的产生；第三，使用双栅场效应晶体管设计，控制光生漏电流。
然而，经过研究发现，光照对漏电流的影响，远比温度的影响严重。10000nit的光照足以使漏电流升高1-2个数量级。因此，单纯依靠降低热载流子效应，难以真正 实现光生漏电流的抑制。而双栅型场效应晶体管的设计，无疑将使得阵列基板的制备复杂化。因此，目前采用低温多晶硅材料的显示装置，多通过设置遮光结构抑制光生漏电流。
但是，在相关的产品中，普遍采用金属材料形成遮光结构。上述遮光结构仅能够应用于显示区，而无法应用在阵列基板行驱动区域和多路复用区域。这主要是由于金属材料形成的遮光结构容易形成电荷累积，因此无法应用于阵列基板行驱动和多路复用区域。并且，引入金属材料的遮光结构，也使得低温多晶硅场效应晶体管的制备工艺复杂化。
本公开的至少一个实施例，提供了一种可以至少部分地解决或缓解上述问题的阵列基板、显示装置以及制备阵列基板的方法。
在本公开的一个实施例中，提供了一种阵列基板。参考图1，该阵列基板900包括基板100和薄膜晶体管200。该薄膜晶体管200位于基板100上。薄膜晶体管200包括遮光层210和有源层220。遮光层210位于基板100上并由非晶硅形成。有源层220设置在遮光层210远离基板100的一侧。
应当理解，薄膜晶体管还可以具有诸如源极、漏极、栅极等结构，以便实现该薄膜晶体管正常发挥功能。
参考图3，该阵列基板900包括显示区300。在一个示例中，该阵列基板900还可以包括阵列基板行驱动区(GOA)400和多路复用区(MUX)500中的至少一个。薄膜晶体管200位于显示区300中。当然，阵列基板行驱动区400和多路复用区500中的至少一个中也可以设置所述薄膜晶体管200。由此，可以至少部分地降低有源层在光照条件下产生光生漏电流，且不会产生电荷积累，进一步地可以使显示区、阵列基板行驱动区以及多路复用区的光生漏电流均得到有效控制，从而可以提高该阵列基板的性能。
下面，根据本公开的具体实施例，对该阵列基板的各个结构进行详细说明：
构成有源层220的材料不受特别限制，只要能够实现薄膜晶体管的使用功能即可，本领域技术人员可以根据实际使用的需求进行设计。例如，有源层220可以由多晶硅形成。更具体地，可以采用低温多晶硅形成有源层220。由此，可以利用低温多晶硅材料的优异性能，进一步提高该阵列基板的性能。
下面首先对遮光层210的工作原理进行简单说明：如前所述，多晶硅经过光照会产生光生载流子，从而形成光生漏电流，进而影响阵列基板的性能。特别是采用低温多晶硅形成有源层220时，有源层220在光照下的光生漏电流为非晶硅形成的有源 层的十至百倍。而在液晶显示装置中，背光模组产生的光需要穿透阵列基板，照射至液晶层并发生偏转，最终由彩膜基板一侧射出，以便来实现显示装置的使用功能。因此，阵列基板的有源层在使用过程中，必然会暴露在光照条件下。
通过在基板100和有源层220之间设置遮光层210，可以使得背光模组产生的背光，首先穿透基板100，之后照射至遮光层220上。由此，可以避免该阵列基板的有源层220在使用过程中暴露在背光环境中，从而缓解光生漏电流的产生。与多晶硅相比，非晶硅对于光照的敏感程度大幅降低。也就是说，在光照条件下，非晶硅材料不会产生光生载流子。并且，非晶硅材料对于可见光具有较好的吸收能力，因此可以用于形成根据本公开实施例的阵列基板的遮光层210。
与利用金属材料制备的遮光层相比，采用非晶硅形成的遮光层可以采用与制备多晶硅形成的有源层220类似的工艺进行制备，从而有利于简化生产流程。此外，非晶硅形成的遮光层210不会造成电荷的累积，从而可以更加广泛地应用于阵列基板上，且至少在一定程度上不会影响薄膜晶体管的电学性能。
在本公开的实施例中，遮光层210的具体尺寸以及形状不受特别限制，本领域技术人员可以根据实际情况进行选择。例如，参考图2，遮光层210的尺寸可以略微大于有源层220的尺寸，以达到较好的遮光效果。如前所述，背光模组发出的背光首先照射到遮光层210上，因此当遮光层210的尺寸大于有源层220的尺寸时，可以对背光进行较为全面的遮挡，防止背光照射至有源层220而产生光生漏电流。
需要说明的是，在本公开中，“遮光层210的尺寸大于有源层220的尺寸”，是指遮光层210的横截面面积大于有源层220的横截面的面积。换句话说，有源层220覆盖遮光层210的部分表面，遮光层210与有源层220相接触的一侧，有部分表面未被有源层220覆盖。也就是说，有源层220靠近遮光层210一侧的表面，全部被遮光层210覆盖。
在一些实施例中，未被有源层220覆盖的遮光层210的表面的宽度(如图中所示出的D)可以为0.2-0.3微米。由此，可以达到较好的遮光效果。本领域技术人员可以根据需要设置有源层220和遮光层210之间的横截面比例。
可以理解，在本公开的一些实施例中，还可以将遮光层210的横截面尺寸设置成与有源层220的横截面尺寸相同或比其的横截面尺寸小。
参考图3，该阵列基板900的阵列基板行驱动区400和多路复用区500中的至少一个中也设置有所述薄膜晶体管200。也就是说，在阵列基板行驱动区400和多路复用区500中的至少一个中也设置有由非晶硅构成的遮光层210。由此，可以使显示区 300、阵列基板行驱动区400以及多路复用区500的漏电流均得到有效控制，至少进一步提高该阵列基板900的性能。
如前所述，由于遮光层210由非晶硅材料形成，因此，与金属材料形成的遮光层相比，根据本公开实施例的遮光层210不会产生电荷累积。
具体地，参考图4，采用低温多晶硅形成有源层的一种阵列基板，通常采用顶栅型TFT设计。也就是在有源层220(TFT沟道区)下形成金属材料构成的遮光层210。由于大面积金属结构会引起电荷的累积，因此，采用金属材料形成遮光层210’时，仅在与栅极230对应的有源层220处设置遮光层210’，控制遮光层210’两侧均比沟道长，从而实现遮光效果。采用金属结构形成的遮光层210’，可以遮挡TFT的轻掺杂漏工艺(LDD)的掺杂区域，但为了避免电荷累积，源极端250、漏极端240等位置的有源层220，并未进行遮光处理。另外，大面积的金属材料放置于阵列基板行驱动和多路复用区域，易引起电荷累积。因此，采用金属形成的遮光层，只在显示区的TFT沟道下形成金属遮光层，而未对阵列基板行驱动和多路复用区域中的TFT进行任何处理。
参考图5，由于遮光层210由非品硅形成，因此，遮光层210不会造成电荷的累积，从而可以在有源层220的全部下表面设置遮光层210。由此可以显著降低由光照产生的光生漏电流。进一步地，由于无需考虑电荷累积对TFT电学性能的影响，因此，该结构可以应用于阵列基板的显示区、阵列基板行驱动和多路复用区域。可以在一定程度上有效地控制光生漏电流，进一步提高该阵列基板的性能。
本公开的另一实施例提供了一种显示装置。参考图6，该显示装置1000包括前述的阵列基板900。该显示装置具有前述的阵列基板的全部特征以及优点，在此不再赘述。该显示装置的阵列基板可以至少部分地防止光生漏电流的产生，且遮光层不会产生电荷积累，进一步地其显示区、阵列基板行驱动区以及多路复用区的光生漏电流均可以得到至少部分地有效控制，从而可以提高该显示装置的性能。
参考图7，该显示装置1000还包括彩膜基板700和液晶层800。彩膜基板700与阵列基板900对盒设置，液晶层800封装在彩膜基板700以及阵列基板900之间。液晶层800中封装有液晶分子10，由此，可以实现该显示装置的显示功能。
本公开的又一实施例提供了一种制备阵列基板的方法。该方法制备的阵列基板可以为前述的阵列基板。该方法包括在基板上设置薄膜晶体管。参考图8，所述设置该薄膜晶体管的步骤可以具体包括以下步骤：
S100：将遮光层设置在基板上。
在该步骤S100中，在基板上形成遮光层。在该步骤中形成的遮光层，可以具有与前面描述的阵列基板的遮光层相同的特征以及优点。关于遮光层的材料、形状等等，前面已经进行了详细的描述，在此不再赘述。
例如，遮光层由非晶硅形成，由此可以使光生漏电流得到至少部分地有效地控制。设置遮光层的具体方式不受特别限制。例如，在所述基板上设置所述遮光层包括利用第一光刻处理形成所述遮光层。所述利用第一光刻处理形成遮光层的步骤包括：可以首先在基板上沉积一层非晶硅材料，形成第一非晶硅层，然后利用掩膜对该第一非晶硅层进行第一光刻处理，去除不需要设置遮光层的区域处的第一非晶硅层，从而获得根据本公开实施例的遮光层。
S200：在遮光层上形成有源层。
在该步骤S200中，在遮光层远离基板的一侧设置有源层。在该步骤中形成的有源层，可以具有与前面描述的阵列基板的有源层相同的特征以及优点。关于有源层的材料前面已经进行了详细描述，在此不再赘述。
例如，有源层可以由多晶硅形成，由此，可以进一步提高阵列基板的性能。设置有源层的具体方式不受特别限制。例如，利用第二光刻处理形成所述有源层，其的步骤包括：可以首先在前面制备的遮光层，以及未被遮光层覆盖的基板上沉积一层第二非品硅层，然后对第二非晶硅层进行第二光刻处理，最后对经过第二光刻处理的第二非晶硅层进行激光退火处理，以便将非晶硅转化为多晶硅，形成有源层。
根据本公开的具体实施例，为了进一步简化生产流程，降低生产成本，上述第一光刻处理以及第二光刻处理可以采用同一个掩膜。根据本公开的实施例，遮光层的尺寸可以略大于有源层的尺寸。采用同一个掩膜进行光刻处理，仅需要对两次光刻处理的曝光量进行调节，即可以获得尺寸略大于有源层的遮光层。
具体的，第一光刻处理的曝光量，可以为第二光刻处理的曝光量的70-90％。在一个示例中，第一光刻处理的曝光量，可以比第二光刻处理的曝光量小15％。由于第一光刻处理的曝光量较小，因此，最终获得的遮光层的尺寸，略大于掩膜的尺寸。也就是说，第一光刻处理采用欠曝光处理，第一非晶硅层没有刻蚀完全。在进行第二光刻处理时，通过增大曝光量，使得第二非晶硅层严格按照掩膜的形状进行刻蚀，由此，可以使最终获得的遮光层比有源层大。由此，可以利用简便的工艺便获得尺寸大于有源层的遮光层，在达到较好遮光效果的同时还节省了成本。
可以理解，在本公开的一些实施例中，还可以调整或修改上述的第一光刻处理和第二光刻处理次序或曝光方式，将遮光层210的横截面尺寸设置成与有源层220的 横截面尺寸相同或比其的横截面尺寸小。因此，其具体制备步骤在此不再详述。
在该方法中，可以将制备的薄膜晶体管设置在该阵列基板的显示区中，同时在阵列基板行驱动区和多路复用区中的至少一个中也可以设置上述薄膜晶体管。由此，可以使显示区、阵列基板行驱动区以及多路复用区的漏电流均得到有效控制，从而可以进一步提高该阵列基板的性能。
在本说明书的描述中，参考术语“一个实施例”、“另一个实施例”等的描述意指结合该实施例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例中。在本说明书中，对上述术语的示意性表述不必须针对的是同一实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。
Claims (14)
- 一种阵列基板，包括：基板；薄膜晶体管，所述薄膜晶体管位于所述基板上并且包括：遮光层，所述遮光层位于所述基板上并包括非晶硅材料；和有源层，所述有源层位于所述遮光层远离所述基板的一侧。
- 根据权利要求1所述的阵列基板，其中，所述阵列基板包括显示区，所述薄膜晶体管设置在所述显示区。
- 根据权利要求1或2所述的阵列基板，其中，所述阵列基板包括阵列基板行驱动区和多路复用区中的至少一个，所述薄膜晶体管设置在所述阵列基板行驱动区和所述多路复用区中的所述至少一个中。
- 根据权利要求1-3中任一项所述的阵列基板，其中，所述有源层为由多晶硅形成的有源层。
- 根据权利要求1-4中任一项所述的阵列基板，其中，所述有源层仅覆盖所述遮光层的部分表面。
- 根据权利要求5所述的阵列基板，其中，所述遮光层未被所述有源层覆盖的表面的宽度为0.2-0.3微米。
- 一种显示装置，包括：如权利要求1-6中任一项所述的阵列基板；彩膜基板，所述彩膜基板与所述阵列基板对盒设置。
- 一种制备阵列基板的方法，包括：在基板上设置薄膜晶体管，所述在基板上设置所述薄膜晶体管的步骤包括：在所述基板上设置遮光层，所述遮光层由非晶硅形成；和在所述遮光层远离所述基板的一侧设置有源层。
- 根据权利要求8所述的方法，其中，所述阵列基板包括显示区，所述在基板上设置所述薄膜晶体管的步骤还包括将所述薄膜晶体管设置在所述显示区。
- 根据权利要求8或9所述的方法，其中，所述阵列基板包括阵列基板行驱动区和多路复用区中的至少一个，所述在基板上设置所述薄膜晶体管的步骤包括：将所述薄膜晶体管设置在所述阵列基板行驱动区和所述多路复用区中的所述至少一个中。
- 根据权利要求8-10中任一项所述的方法，其中，所述在基板上设置所述遮光层的步骤包括利用第一光刻处理形成所述遮光层；所述在遮光层远离所述基板的一侧设置有源层的步骤包括利用第二光刻处理形成所述有源层，其中，所述第一光刻处理和所述第二光刻处理共用一个光刻掩膜。
- 根据权利要求11所述的方法，其中，所述第一光刻处理的曝光量为所述第二光刻处理的曝光量的70-90％。
- 根据权利要求11或12所述的方法，其中，所述利用第一光刻处理形成所述遮光层的步骤包括：在所述基板上沉积第一非晶硅层；对所述第一非晶硅层进行第一光刻处理，以便形成所述遮光层。
- 根据权利要求11-13中任一项所述的方法，其中，所述利用第二光刻处理形成所述有源层的步骤包括：在所述遮光层和所述基板上沉积第二非晶硅层，对所述第二非晶硅层进行第二光刻处理；对经过所述第二光刻处理的所述第二非晶硅层进行激光退火处理，以便将非晶硅转化为多晶硅，从而形成所述有源层。
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| CN108227268B (zh) * | 2018-01-31 | 2020-12-22 | 武汉华星光电技术有限公司 | 液晶显示装置的制作方法及液晶显示装置 |
| CN111640706A (zh) * | 2020-06-28 | 2020-09-08 | 武汉华星光电技术有限公司 | 阵列基板制备方法和阵列基板 |
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