WO2018205655A1 - 栅极驱动电路及其驱动方法、栅极驱动器、显示面板和显示装置 - Google Patents

栅极驱动电路及其驱动方法、栅极驱动器、显示面板和显示装置 Download PDF

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Publication number
WO2018205655A1
WO2018205655A1 PCT/CN2018/070785 CN2018070785W WO2018205655A1 WO 2018205655 A1 WO2018205655 A1 WO 2018205655A1 CN 2018070785 W CN2018070785 W CN 2018070785W WO 2018205655 A1 WO2018205655 A1 WO 2018205655A1
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Prior art keywords
transistor
pull
signal
terminal
node
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PCT/CN2018/070785
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English (en)
French (fr)
Inventor
李艳
徐成福
时凌云
孙伟
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US16/066,749 priority Critical patent/US11170681B2/en
Publication of WO2018205655A1 publication Critical patent/WO2018205655A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a gate driving circuit and a driving method thereof, a gate driver, a display panel, and a display device.
  • a typical HIC (Hybrid In Cell) touch display panel adopts a time-sharing driving mode, that is, the HIC touch display panel performs display scanning and touch scanning in different time periods of one frame.
  • the potential of the pull-up node in the Gate Driver on Array (GOA) cannot be normally pulled down to an inactive level, thereby interfering with the gate line signal. causes the screen to display an abnormality.
  • GOA Gate Driver on Array
  • An object of the present disclosure is to provide an improved gate drive circuit, a method of driving the gate drive circuit, a gate driver including the gate drive circuit, a display panel, and a display device.
  • a gate driving circuit includes: a first signal terminal, a second signal terminal, a third signal terminal, a fourth signal terminal, a fifth signal terminal, a reset terminal, and a first voltage terminal. a second voltage terminal, an output terminal, a pull-up sub-circuit, a reset sub-circuit, a pull-down sub-circuit, and an output sub-circuit.
  • the pull-up sub-circuit is respectively connected to the first signal end, the second signal end, the third signal end, the fourth signal end, the fifth signal end, the first voltage end, the pull-down node, and the pull-up node PU, and is configured to The potential of the pull-up node is controlled according to the signals input from the first signal terminal, the second signal terminal, the third signal terminal, the fourth signal terminal, and the fifth signal terminal, and the potential of the pull-down node.
  • the reset sub-circuit is respectively connected to the reset terminal, the second voltage terminal, and the pull-up node, and is configured to reset the potential of the pull-up node according to a signal input from the reset terminal.
  • the pull-down sub-circuit is respectively connected to the fourth signal end, the first voltage end, the output end, the pull-up node and the pull-down node, and is configured to be based on a signal input from the fourth signal end, a signal output from the output end, and a pull-up
  • the potential of the node controls the potential of the pull-down node.
  • the output sub-circuit is respectively connected to the third signal end, the first voltage end, the output end, the pull-up node, and the pull-down node, and is configured to be based on a signal input from the third signal end, a potential of the pull-down node, and a pull-up node The potential controls the signal output from the output.
  • the pull-up sub-circuit includes a first transistor, a fifth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor.
  • a control electrode of the first transistor is coupled to the second signal terminal, a first pole of the first transistor is coupled to the first signal terminal, and a second pole of the first transistor is coupled to the pullup Node connection.
  • a control electrode of the fifth transistor is connected to the pull-down node, a first pole of the fifth transistor is connected to the first voltage terminal, and a second pole of the fifth transistor is connected to the pull-up node .
  • a control electrode of the ninth transistor is connected to the fifth signal terminal, a first pole of the ninth transistor is connected to a second pole of the tenth transistor, and a second pole of the ninth transistor is The first voltage terminal is connected.
  • the control electrode of the tenth transistor is connected to the fourth signal terminal, and the first pole of the tenth transistor is connected to the second electrode of the eleventh transistor.
  • a control electrode of the eleventh transistor is connected to the third signal terminal, and a first pole of the eleventh transistor is connected to the pull-up node.
  • the reset subcircuit comprises a second transistor. a control electrode of the second transistor is connected to the reset terminal, a first pole of the second transistor is connected to the pull-up node, and a second pole of the second transistor is connected to the second voltage terminal .
  • the pull-down sub-circuit includes a sixth transistor, a seventh transistor, an eighth transistor, and a capacitor.
  • a control electrode of the sixth transistor is connected to the pull-up node, a first pole of the sixth transistor is connected to the first voltage terminal, and a second pole of the sixth transistor is connected to the pull-down node .
  • a control electrode of the seventh transistor is connected to the output terminal, a first pole of the seventh transistor is connected to the pull-down node, and a second pole of the seventh transistor is connected to the first voltage terminal.
  • a control electrode of the eighth transistor is connected to the fourth signal terminal, a first pole of the eighth transistor is connected to the fourth signal terminal, and a second pole of the eighth transistor is connected to the pull-down node connection.
  • a first pole of the capacitor is coupled to the pull up node and a second pole of the capacitor is coupled to the output.
  • the output subcircuit includes a third transistor and a fourth transistor.
  • a control electrode of the third transistor is connected to the pull-up node, a first pole of the third transistor is connected to the third signal terminal, and a second pole of the third transistor is connected to the output terminal .
  • a control electrode of the fourth transistor is connected to the pull-down node, a first pole of the fourth transistor is connected to the output terminal, and a second pole of the fourth transistor is connected to the first voltage terminal.
  • the tenth transistor and the eleventh transistor are P-type transistors
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth The transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are N-type transistors.
  • the tenth transistor and the eleventh transistor are N-type transistors
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth The transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are P-type transistors.
  • a driving method of any of the above-described gate driving circuits includes a reset phase, a charging phase, a display phase, and a discharging phase.
  • the reset phase an active level is input from the reset terminal, and an inactive level is input from the second voltage terminal, and the inactive level input from the second voltage terminal VGL is transmitted to the pull-up node.
  • the charging phase an active level is input from the second signal terminal, and an active level is input from the first signal terminal, and the active level input from the first signal terminal is transmitted to the pull-up node.
  • an active level is input from the third signal terminal, and an active level input from the third signal terminal is transmitted to the input terminal.
  • an inactive level is input from the second voltage terminal, an active level is input from the third signal terminal, an active level is input from the fourth signal terminal, and an active level is input from the fifth signal terminal, and the second voltage is input from the second voltage.
  • the invalid level of the terminal input is transmitted to the pull-up node.
  • a gate driver includes a plurality of cascaded gate drive circuits of any of the above.
  • the first voltage terminal is connected to the first voltage line
  • the second voltage terminal is connected to the second voltage line
  • the first signal terminal is connected to the first signal line
  • the second signal terminal is connected to the previous signal line.
  • the output end of the gate driving circuit is connected, the third signal end is connected to the third signal line, the fourth signal end is connected to the fourth signal line, and the fifth signal end is connected to the pull-up node of the second-stage gate driving circuit, and is reset.
  • the terminal is connected to the output end of the gate driving circuit of the latter stage, and the output terminal is connected to the reset end of the previous stage gate driving circuit and the second signal end of the gate driving circuit of the subsequent stage.
  • a display panel including the above-described gate driver is provided.
  • a display device including the above display panel is provided.
  • FIG. 1 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram showing a specific structure of the gate driving circuit shown in FIG. 1 according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a gate driver according to an embodiment of the present disclosure.
  • FIG. 4 is an operational timing diagram of the gate driving circuit shown in FIG. 2 according to an embodiment of the present disclosure
  • FIG. 5 is a flowchart of a driving method of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the gate driving circuit includes a first signal terminal CN, a second signal terminal STV, a third signal terminal CK, a fourth signal terminal CKB, a fifth signal terminal PU[N+1], and a reset terminal RESET.
  • the PD and the pull-up node PU are connected, and are configured to input signals according to the first signal terminal CN, the second signal terminal STV, the third signal terminal CK, the fourth signal terminal CKB, and the fifth signal terminal PU[N+1].
  • the potential of the pull-down node PD controls the potential of the pull-up node PU.
  • the reset sub-circuit 102 is connected to the reset terminal RESET, the second voltage terminal CNB, and the pull-up node PU, respectively, and is configured to reset the potential of the pull-up node PU according to a signal input from the reset terminal RESET.
  • the pull-down sub-circuit 103 is respectively connected to the fourth signal terminal CKB, the first voltage terminal VGL, the output terminal OUT, the pull-up node PU, and the pull-down node PD, and is configured to be based on the signal input from the fourth signal terminal CKB, from the output terminal OUT.
  • the output signal and the potential of the pull-up node PU control the potential of the pull-down node PD.
  • the output sub-circuit 104 is respectively connected to the third signal terminal CK, the first voltage terminal VGL, the output terminal OUT, the pull-up node PU, and the pull-down node PD, and is configured to be based on the signal input from the third signal terminal CK, the pull-down node PD
  • the potential and the potential of the pull-up node PU control the signal output from the output terminal OUT.
  • the potential of the pull-up node PU can be normally pulled low by the cooperation between the pull-up sub-circuit, the reset sub-circuit, the pull-down sub-circuit, and the output sub-circuit, thereby preventing the gate line signal from being subjected to other Signal interference, thus improving the uniformity and display quality of the display.
  • the pull-up sub-circuit 101 may include a first transistor M1, a fifth transistor M5, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11.
  • the control electrode of the first transistor M1 is connected to the second signal terminal STV
  • the first pole of the first transistor M1 is connected to the first signal terminal CN
  • the second pole of the first transistor M1 is connected to the pull-up node PU.
  • the gate of the fifth transistor M5 is connected to the pull-down node PD, the first pole of the fifth transistor M5 is connected to the first voltage terminal VGL, and the second pole of the fifth transistor M5 is connected to the pull-up node PU.
  • the control electrode of the ninth transistor M9 is connected to the fifth signal terminal PU[N+1], the first pole of the ninth transistor M9 is connected to the second pole of the tenth transistor M10, and the second pole of the ninth transistor M9 is A voltage terminal VGL is connected.
  • the gate of the tenth transistor M10 is connected to the fourth signal terminal CKB, and the first pole of the tenth transistor M10 is connected to the second electrode of the eleventh transistor M11.
  • the control electrode of the eleventh transistor M11 is connected to the third signal terminal CK, and the first pole of the eleventh transistor M11 is connected to the pull-up node PU.
  • the reset sub-circuit 102 may include a second transistor M2.
  • the control electrode of the second transistor M2 is connected to the reset terminal RESET, the first electrode of the second transistor M2 is connected to the pull-up node PU, and the second electrode of the second transistor M2 is connected to the second voltage terminal CNB.
  • the pull-down sub-circuit 103 may include a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a capacitor C.
  • the gate of the sixth transistor M6 is connected to the pull-up node PU, the first pole of the sixth transistor M6 is connected to the first voltage terminal VGL, and the second pole of the sixth transistor M6 is connected to the pull-down node PD.
  • the control electrode of the seventh transistor M7 is connected to the output terminal OUT, the first electrode of the seventh transistor M7 is connected to the pull-down node PD, and the second electrode of the seventh transistor M7 is connected to the first voltage terminal VGL.
  • the control electrode and the first pole of the eighth transistor M8 are both connected to the fourth signal terminal CKB, and the second pole of the eighth transistor M8 is connected to the pull-down node PD.
  • the first pole of the capacitor C is connected to the pull-up node PU, and the second pole of the capacitor C is connected to the output terminal OUT.
  • the output sub-circuit 104 may include a third transistor M3 and a fourth transistor M4.
  • the control electrode of the third transistor M3 is connected to the pull-up node PU, the first electrode of the third transistor M3 is connected to the third signal terminal CK, and the second electrode of the third transistor M3 is connected to the output terminal OUT.
  • the control electrode of the fourth transistor M4 is connected to the pull-down node PD, the first electrode of the fourth transistor M4 is connected to the output terminal OUT, and the second electrode of the fourth transistor M4 is connected to the first voltage terminal VGL.
  • the tenth transistor M10 and the eleventh transistor M11 may be P-type transistors, and the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the The five transistors M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 may be N-type transistors.
  • the tenth transistor M10 and the eleventh transistor M11 may be N-type transistors, and the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth The transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are P-type transistors.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices having the same characteristics. Since the source and drain of the transistor are interchangeable under certain conditions, there is no essential difference in the description of the source and drain connections.
  • one of the poles is referred to as a first pole
  • the other pole is referred to as a second pole
  • the gate is referred to as a gate.
  • Transistors can be classified into N-type and P-type according to their characteristics. When a P-type transistor is used, the source of the first extreme P-type transistor, the second is the drain of the P-type transistor, and when the gate is input low, the P-type transistor is turned on. The opposite is true for N-type transistors.
  • the gate driver includes a plurality of cascaded gate drive circuits G[N-1], G[N], G[N+1], G[N+2]. .
  • the first voltage terminal VGL of each gate driving circuit (taking the Nth gate driving circuit G[N] as an example) is connected to the first voltage line Vgl, and the second voltage terminal CNB is connected to the second voltage line Cnb,
  • a signal terminal CN is connected to the first signal line Cn
  • the second signal terminal STV is connected to the output terminal OUT of the previous stage gate driving circuit G[N-1]
  • the third signal terminal CK is connected to the third signal line Ck.
  • the fourth signal terminal CKB is connected to the fourth signal line Ckb, and the fifth signal terminal PU[N+1] is connected to the pull-up node PU of the subsequent-stage gate driving circuit G[N+1], and the reset terminal RESET and the latter
  • the output terminal OUT of the gate drive circuit G[N+1] is connected, and the output terminal OUT and the reset terminal RESET of the previous stage gate drive circuit G[N-1] and the gate drive circuit G[N of the subsequent stage
  • the second signal terminal STV of +1] is connected.
  • an active level is input from the reset terminal RESET, and an inactive level is input from the second voltage terminal VGL, so that the second transistor M2 is turned on, thereby input from the second voltage terminal VGL.
  • the invalid level is transmitted to the pull-up node PU, that is, the potential of the pull-up node PU is reset to an inactive level.
  • the third transistor M3 is turned off, thereby isolating the interference of other signals with the output signal of the gate driving circuit G[N].
  • an active level is input from the second signal terminal STV, and an active level is input from the first signal terminal CN, so that the first transistor M1 is turned on, thereby transmitting the active level input from the first signal terminal CN.
  • Up to the pull-up node PU that is, pull up the potential of the pull-up node PU to an active level.
  • the active level transmitted to the pull-up node PU is stored in capacitor C.
  • the first active level is input from the third signal terminal CK, and since the capacitor C holds the potential of the pull-up node PU at the active level, the third transistor M3 is turned on, so that the third signal terminal CK will be turned on.
  • the active level of the input is transmitted to the input terminal OUT, that is, the gate drive circuit outputs an active level.
  • an inactive level is input from the second voltage terminal VGL
  • a second active level is input from the third signal terminal CK
  • an active level is input from the fourth signal terminal CKB, from the fifth signal terminal PU[N+ 1] inputting an active level such that the eleventh transistor M11, the tenth transistor M10, and the ninth transistor M9 are turned on, thereby transmitting an inactive level input from the second voltage terminal VGL to the pull-up node PU, that is, pulling up The potential of the node PU is pulled down to an inactive level.
  • an "active level" of an input signal refers to a level at which an element controlled by the signal takes a corresponding action.
  • the tenth transistor M10 and the eleventh transistor M11 are P-type transistors, and the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the The five transistors M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are exemplified as N-type transistors.
  • the active level input from the reset terminal RESET is a high level at which the second transistor M2 is turned on, and the inactive level input from the second voltage terminal VGL is at a low level.
  • the active level input from the second signal terminal STV is a high level at which the first transistor M1 is turned on, and the active level is input from the first signal terminal CN to a high level.
  • the inactive level input from the second voltage terminal VGL is a low level
  • the first active level input from the third signal terminal CK is a high level that causes the gate driving circuit to generate an effective output.
  • the second active level input from the third signal terminal CK is a low level that turns on the eleventh transistor M11
  • the effective level input from the fourth signal terminal CKB is such that the tenth transistor M10 is turned on.
  • the low level, the active level input from the fifth signal terminal PU[N+1] is a high level that causes the ninth transistor M9 to be turned on.
  • the potential of the pull-up node PU of the next-stage gate drive circuit G[N+1] is passed through the current-stage gate drive circuit G in the discharge phase.
  • the fifth signal terminal PU[N+1] of [N] is fed back to the current stage gate driving circuit G[N], and the ninth transistor M9 and the tenth transistor M10 of the current stage gate driving circuit G[N] can be made.
  • the eleventh transistor M11 is in the charging phase and the display phase of the next-stage gate driving circuit G[N+1] (wherein the potential of the pull-up node PU of the next-stage gate driving circuit G[N+1] is The active level is turned on, thereby pulling down the potential of the pull-up node PU of the current-stage gate driving circuit G[N] to an inactive level, thereby effectively ensuring the pull-up node of the current-stage gate driving circuit G[N]
  • the PU maintains an inactive level in the charging phase and the display phase of the next-stage gate driving circuit G[N+1].
  • the inactive level of the pull-up node PU causes the third transistor M3 to be turned off, thereby preventing the output signal of the output terminal OUT from being interfered by other signals, thereby ensuring the uniformity of the display picture and ultimately improving the quality of the display picture.
  • the current-stage gate driving circuit When the current-stage gate driving circuit is the last-stage gate driving circuit in the display scanning period, the current-stage gate driving circuit outputs a touch signal, and the pull-up node PU of the current-stage gate driving circuit G[N] is under The inactive level is still maintained in the charging phase and the display phase of the primary gate drive circuit G[N+1].
  • embodiments of the present disclosure provide a driving method of a gate driving circuit.
  • a gate driving circuit As shown in FIG. 5, in the reset phase 501, an active level is input from the reset terminal, and an inactive level is input from the second voltage terminal, and the inactive level input from the second voltage terminal VGL is transmitted to the pull-up node.
  • an active level is input from the second signal terminal, and an active level is input from the first signal terminal, and the active level input from the first signal terminal is transmitted to the pull-up node.
  • an active level is input from the third signal terminal, and an active level input from the third signal terminal is transmitted to the input terminal.
  • an inactive level is input from the second voltage terminal, an active level is input from the third signal terminal, an active level is input from the fourth signal terminal, and an active level is input from the fifth signal terminal, and the second level is input from the second signal terminal.
  • the inactive level of the voltage terminal input is transferred to the pull-up node.
  • a further aspect of the present disclosure provides a display panel including the above-described gate driver.
  • the pull-up of the current-stage gate drive circuit G[N] is performed in the charge phase and the display phase of the next-stage gate drive circuit G[N+1]
  • the potential of the node PU is pulled down to an inactive level, which can effectively ensure the charging phase and display of the pull-up node PU of the current-stage gate driving circuit G[N] in the next-stage gate driving circuit G[N+1]
  • the level is kept inactive during the phase.
  • the inactive level of the pull-up node PU causes the third transistor M3 to be turned off, thereby preventing the output signal of the output terminal OUT from being interfered by other signals, thereby ensuring the uniformity of the display picture and ultimately improving the quality of the display picture.
  • a further aspect of the present disclosure also provides a display device including the above display panel.
  • the potential of the pull-up node PU of the current-stage gate drive circuit G[N] is pulled down by the charge phase and the display phase of the next-stage gate drive circuit G[N+1].
  • the level can effectively ensure that the pull-up node PU of the current stage gate driving circuit G[N] maintains an inactive level in the charging phase and the display phase of the next-stage gate driving circuit G[N+1].
  • the inactive level of the pull-up node PU causes the third transistor M3 to be turned off, thereby preventing the output signal of the output terminal OUT from being interfered by other signals, thereby ensuring the uniformity of the display picture and ultimately improving the quality of the display picture.

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种栅极驱动电路（G[N-1]、G[N]、G[N+1]、G[N+2]）及其驱动方法、栅极驱动器、显示面板和显示装置。在栅极驱动电路（G[N-1]、G[N]、G[N+1]、G[N+2]）中，上拉子电路（101）配置成根据从第一信号端（CN）、第二信号端（STV）、第三信号端（CK）、第四信号端（CKB）和第五信号端（PU[N+1]）输入的信号以及下拉节点（PD）的电位控制上拉节点（PU）的电位；复位子电路（102）配置成根据从复位端（RESET）输入的信号对上拉节点（PU）的电位进行复位；下拉子电路（103）配置成根据从第四信号端（CKB）输入的信号、从输出端（OUT）输出的信号以及上拉节点（PU）的电位控制下拉节点（PD）的电位；输出子电路（104）配置成根据从第三信号端（CK）输入的信号、下拉节点（PD）的电位和上拉节点（PU）的电位控制从输出端（OUT）输出的信号。

Description

栅极驱动电路及其驱动方法、栅极驱动器、显示面板和显示装置
相关申请的交叉引用
本申请要求享有2017年5月9日提交的中国专利申请No.201710322409.9的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开涉及显示技术领域，尤其涉及一种栅极驱动电路及其驱动方法、栅极驱动器、显示面板和显示装置。
背景技术
典型的HIC(Hybrid In Cell)触控显示面板采用分时驱动模式，也就是说，HIC触控显示面板在一帧的不同时段内分别进行显示扫描和触控扫描。在常规的触控显示面板中，经常出现的情况是，栅极驱动电路(Gate Driver on Array，GOA)之中的上拉节点的电位无法被正常下拉至无效电平，从而干扰栅线信号，导致画面显示异常。
发明内容
栅极驱动电路栅极驱动电路本公开的目的是提供一种改进的栅极驱动电路、该栅极驱动电路的驱动方法、包括该栅极驱动电路的栅极驱动器、显示面板和显示装置。
根据本公开的一方面，提供了一种栅极驱动电路，包括：第一信号端、第二信号端、第三信号端、第四信号端、第五信号端、复位端、第一电压端、第二电压端、输出端、上拉子电路、复位子电路、下拉子电路以及输出子电路。所述上拉子电路分别与第一信号端、第二信号端、第三信号端、第四信号端、第五信号端、第一电压端、下拉节点以及上拉节点PU连接，并且配置成根据从第一信号端、第二信号端、第三信号端、第四信号端和第五信号端输入的信号以及下拉节点的电位控制上拉节点的电位。所述复位子电路分别与复位端、第二电压端以及上拉节点连接，并且配置成根据从复位端输入的信号对上拉节点的电位进行复位。所述下拉子电路分别与第四信号端、第一电压端、输出端、上拉节点以及下拉节点连接，并且配置成根据从第四信号端 输入的信号、从输出端输出的信号以及上拉节点的电位控制下拉节点的电位。所述输出子电路分别与第三信号端、第一电压端、输出端、上拉节点以及下拉节点连接，并且配置成根据从第三信号端输入的信号、下拉节点的电位和上拉节点的电位控制从输出端输出的信号。
根据一些实施例，所述上拉子电路包括第一晶体管、第五晶体管、第九晶体管、第十晶体管以及第十一晶体管。所述第一晶体管的控制极与所述第二信号端连接，所述第一晶体管的第一极与所述第一信号端连接，并且所述第一晶体管的第二极与所述上拉节点连接。所述第五晶体管的控制极与所述下拉节点连接，所述第五晶体管的第一极与所述第一电压端连接，并且所述第五晶体管的第二极与所述上拉节点连接。所述第九晶体管的控制极与所述第五信号端连接，所述第九晶体管的第一极与所述第十晶体管的第二极连接，并且所述第九晶体管的第二极与所述第一电压端连接。所述第十晶体管的控制极与所述第四信号端连接，并且所述第十晶体管的第一极与所述第十一晶体管的第二极连接。所述第十一晶体管的控制极与所述第三信号端连接，并且所述第十一晶体管的第一极与所述上拉节点连接。
根据一些实施例，所述复位子电路包括第二晶体管。所述第二晶体管的控制极与所述复位端连接，所述第二晶体管的第一极与所述上拉节点连接，并且所述第二晶体管的第二极与所述第二电压端连接。
根据一些实施例，所述下拉子电路包括第六晶体管、第七晶体管、第八晶体管以及电容器。所述第六晶体管的控制极与所述上拉节点连接，所述第六晶体管的第一极与所述第一电压端连接，并且所述第六晶体管的第二极与所述下拉节点连接。所述第七晶体管的控制极与所述输出端连接，所述第七晶体管的第一极与所述下拉节点连接，并且所述第七晶体管的第二极与所述第一电压端连接。所述第八晶体管的控制极与所述第四信号端连接，所述第八晶体管的第一极与所述第四信号端连接，并且所述第八晶体管的第二极与所述下拉节点连接。所述电容器的第一极与所述上拉节点连接，并且所述电容器的第二极与所述输出端连接。
根据一些实施例，所述输出子电路包括第三晶体管和第四晶体管。所述第三晶体管的控制极与所述上拉节点连接，所述第三晶体管的第一极与所述第三信号端连接，并且所述第三晶体管的第二极与所述输 出端连接。所述第四晶体管的控制极与所述下拉节点连接，所述第四晶体管的第一极与所述输出端连接，并且所述第四晶体管的第二极与所述第一电压端连接。
根据一些实施例，所述第十晶体管和所述第十一晶体管为P型晶体管，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管以及所述第九晶体管为N型晶体管。
根据一些实施例，所述第十晶体管和所述第十一晶体管为N型晶体管，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管以及所述第九晶体管为P型晶体管。
根据本公开的另一方面，提供了上述任一种栅极驱动电路的驱动方法。所述驱动方法包括：复位阶段、充电阶段、显示阶段和放电阶段。在复位阶段中，从复位端输入有效电平，从第二电压端输入无效电平，将从第二电压端VGL输入的无效电平传输至上拉节点。在充电阶段中，从第二信号端输入有效电平，从第一信号端输入有效电平，将从第一信号端输入的有效电平传输至上拉节点。在显示阶段中，从第三信号端输入有效电平，将从第三信号端输入的有效电平传输至输入端。在放电阶段中，从第二电压端输入无效电平，从第三信号端输入有效电平，从第四信号端输入有效电平，从第五信号端输入有效电平，将从第二电压端输入的无效电平传输至上拉节点。
根据本公开的又一方面，提供了一种栅极驱动器，包括多个级联的上述任一种栅极驱动电路。对于每一级栅极驱动电路，第一电压端与第一电压线连接，第二电压端与第二电压线连接，第一信号端与第一信号线连接，第二信号端与前一级栅极驱动电路的输出端连接，第三信号端与第三信号线连接，第四信号端与第四信号线连接，第五信号端与后一级栅极驱动电路的上拉节点连接，复位端与后一级栅极驱动电路的输出端连接，并且输出端与前一级栅极驱动电路的复位端和后一级栅极驱动电路的第二信号端连接。
根据本公开另外的方面，提供了一种显示面板，包括上述栅极驱动器。
根据本公开再另外的方面，提供了一种显示装置，包括上述显示 面板。
附图说明
图1为根据本公开实施例的一种栅极驱动电路的结构示意图；
图2为根据本公开实施例的图1所示栅极驱动电路的具体结构示意图；
图3为根据本公开实施例的栅极驱动器的结构示意图；
图4为根据本公开实施例的如图2所示的栅极驱动电路的工作时序图；以及
图5为根据本公开实施例的栅极驱动电路的驱动方法的流程图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的栅极驱动电路及其驱动方法、显示面板和显示装置进行详细描述。
图1为本公开实施例提供的一种栅极驱动电路的结构示意图。如图1所示，该栅极驱动电路包括第一信号端CN、第二信号端STV、第三信号端CK、第四信号端CKB、第五信号端PU[N+1]、复位端RESET、第一电压端VGL、第二电压端CNB、输出端OUT、上拉子电路101、复位子电路102、下拉子电路103以及输出子电路104。上拉子电路101分别与第一信号端CN、第二信号端STV、第三信号端CK、第四信号端CKB、第五信号端PU[N+1]、第一电压端VGL、下拉节点PD以及上拉节点PU连接，并且配置成根据从第一信号端CN、第二信号端STV、第三信号端CK、第四信号端CKB和第五信号端PU[N+1]输入的信号以及下拉节点PD的电位控制上拉节点PU的电位。复位子电路102分别与复位端RESET、第二电压端CNB以及上拉节点PU连接，并且配置成根据从复位端RESET输入的信号对上拉节点PU的电位进行复位。下拉子电路103分别与第四信号端CKB、第一电压端VGL、输出端OUT、上拉节点PU以及下拉节点PD连接，并且配置成根据从第四信号端CKB输入的信号、从输出端OUT输出的信号以及上拉节点PU的电位控制下拉节点PD的电位。输出子电路104分别与第三信号端CK、第一电压端VGL、输出端OUT、上拉节点PU以及下拉节点PD连接， 并且配置成根据从第三信号端CK输入的信号、下拉节点PD的电位和上拉节点PU的电位控制从输出端OUT输出的信号。
在上述栅极驱动电路之中，上拉节点PU的电位可以通过上拉子电路、复位子电路、下拉子电路和输出子电路之间的配合而被正常拉低，从而避免栅线信号受到其他信号的干扰，因而提高显示画面的均一性和显示品质。
图2为根据本公开的实施例的图1所示栅极驱动电路的电路示意图。如图2所示，上拉子电路101可以包括第一晶体管M1、第五晶体管M5、第九晶体管M9、第十晶体管M10以及第十一晶体管Mll。第一晶体管M1的控制极与第二信号端STV连接，第一晶体管M1的第一极与第一信号端CN连接，并且第一晶体管M1的第二极与上拉节点PU连接。第五晶体管M5的控制极与下拉节点PD连接，第五晶体管M5的第一极与第一电压端VGL连接，并且第五晶体管M5的第二极与上拉节点PU连接。第九晶体管M9的控制极与第五信号端PU[N+1]连接，第九晶体管M9的第一极与第十晶体管M10的第二极连接，并且第九晶体管M9的第二极与第一电压端VGL连接。第十晶体管M10的控制极与第四信号端CKB连接，并且第十晶体管M10的第一极与第十一晶体管Mll的第二极连接。第十一晶体管Mll的控制极与第三信号端CK连接，并且第十一晶体管Mll的第一极与上拉节点PU连接。
可选地，在一些示例实施例中，如图2所示，复位子电路102可以包括第二晶体管M2。第二晶体管M2的控制极与复位端RESET连接，第二晶体管M2的第一极与上拉节点PU连接，并且第二晶体管M2的第二极与第二电压端CNB连接。
可选地，在一些示例实施例中，如图2所示，下拉子电路103可以包括第六晶体管M6、第七晶体管M7、第八晶体管M8以及电容器C。第六晶体管M6的控制极与上拉节点PU连接，第六晶体管M6的第一极与第一电压端VGL连接，并且第六晶体管M6的第二极与下拉节点PD连接。第七晶体管M7的控制极与输出端OUT连接，第七晶体管M7的第一极与下拉节点PD连接，并且第七晶体管M7的第二极与第一电压端VGL连接。第八晶体管M8的控制极和第一极均与第四信号端CKB连接，并且第八晶体管M8的第二极与下拉节点PD连接。电容器C的第一极与上拉节点PU连接，并且电容器C的第二极与输出 端OUT连接。
可选地，在一些示例实施例中，如图2所示，输出子电路104可以包括第三晶体管M3和第四晶体管M4。第三晶体管M3的控制极与上拉节点PU连接，第三晶体管M3的第一极与第三信号端CK连接，并且第三晶体管M3的第二极与输出端OUT连接。第四晶体管M4的控制极与下拉节点PD连接，第四晶体管M4的第一极与输出端OUT连接，并且第四晶体管M4的第二极与第一电压端VGL连接。
在示例实施例中，如图2所示，第十晶体管M10和第十一晶体管M11可以为P型晶体管，并且第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8以及第九晶体管M9可以为N型晶体管。可替换地，在其它示例实施例中，第十晶体管M10和第十一晶体管M11可以为N型晶体管，并且第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8以及第九晶体管M9为P型晶体管。
需要指出的是，本公开实施例中的所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同器件。由于晶体管的源极和漏极在一定条件下是可以互换的，所以其源极、漏极从连接关系的描述上并无本质区别。在本公开实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，并且将栅极称为控制极。晶体管按照特性区分可以分为N型和P型。当采用P型晶体管时，第一极为P型晶体管的源极，第二极为P型晶体管的漏极，并且当栅极输入低电平时，P型晶体管导通。N型晶体管的情况相反。
相应地，本公开的实施例提供了一种栅极驱动器。如图3所示，栅极驱动器包括多个级联的上述任一种栅极驱动电路G[N-1]、G[N]、G[N+1]、G[N+2]......。每一个栅极驱动电路(以第N级栅极驱动电路G[N]为例)的第一电压端VGL与第一电压线Vgl连接，第二电压端CNB与第二电压线Cnb连接，第一信号端CN与第一信号线Cn连接，第二信号端STV与前一级栅极驱动电路G[N-1]的输出端OUT连接，第三信号端CK与第三信号线Ck连接，第四信号端CKB与第四信号线Ckb连接，第五信号端PU[N+1]与后一级栅极驱动电路G[N+1]的上拉节点PU连接，复位端RESET与后一级栅极驱动电路G[N+1]的输出 端OUT连接，并且输出端OUT与前一级栅极驱动电路G[N-1]的复位端RESET和后一级栅极驱动电路G[N+1]的第二信号端STV连接。以下结合图4所示的时序图来具体地描述如图2所示的栅极驱动电路的工作过程。
如图4所示，在复位阶段t1中，从复位端RESET输入有效电平，从第二电压端VGL输入无效电平，使得第二晶体管M2导通，从而将从第二电压端VGL输入的无效电平传输至上拉节点PU，即，将上拉节点PU的电位复位到无效电平。此时，第三晶体管M3断开，从而隔绝其它信号对栅极驱动电路G[N]的输出信号的干扰。
在充电阶段t2中，从第二信号端STV输入有效电平，从第一信号端CN输入有效电平，使得第一晶体管M1导通，从而将从第一信号端CN输入的有效电平传输至上拉节点PU，即，将上拉节点PU的电位上拉至有效电平。传输至上拉节点PU的有效电平存储在电容器C中。
在显示阶段t3中，从第三信号端CK输入第一有效电平，由于电容器C保持上拉节点PU的电位为有效电平，因此第三晶体管M3导通，从而将从第三信号端CK输入的有效电平传输至输入端OUT，即，栅极驱动电路输出有效电平。
在放电阶段t4中，从第二电压端VGL输入无效电平，从第三信号端CK输入第二有效电平，从第四信号端CKB输入有效电平，从第五信号端PU[N+1]输入有效电平，使得第十一晶体管M11、第十晶体管M10和第九晶体管M9导通，从而将从第二电压端VGL输入的无效电平传输至上拉节点PU，即，将上拉节点PU的电位下拉到无效电平。
如本文所使用的，输入信号的“有效电平”是指使得由该信号控制的元件采取相应动作的电平。例如，在如图2所示的电路中，以第十晶体管M10和第十一晶体管M11为P型晶体管，并且第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8以及第九晶体管M9为N型晶体管为例。在复位阶段，从复位端RESET输入的有效电平为使得第二晶体管M2导通的高电平，从第二电压端VGL输入的无效电平为低电平。在充电阶段，从第二信号端STV输入的有效电平为使得第一晶体管M1导通的高电平，从第一信号端CN输入有效电平为高电平。在显示阶段，从第二电压端VGL输入的无效电平为低电平， 从第三信号端CK输入的第一有效电平为使得栅极驱动电路产生有效输出的高电平。在放电阶段，从第三信号端CK输入的第二有效电平为使得第十一晶体管M11导通的低电平，从第四信号端CKB输入的有效电平为使得第十晶体管M10导通的低电平，从第五信号端PU[N+1]输入的有效电平为使得第九晶体管M9导通的高电平。
以此方式，在如图3所示的栅极驱动器中，通过在放电阶段中将下一级栅极驱动电路G[N+1]的上拉节点PU的电位通过当前级栅极驱动电路G[N]的第五信号端PU[N+1]反馈到当前级栅极驱动电路G[N]，可以使得当前级栅极驱动电路G[N]的第九晶体管M9、第十晶体管M10和第十一晶体管M11在下一级栅极驱动电路G[N+1]的充电阶段和显示阶段中(其中所述下一级栅极驱动电路G[N+1]的上拉节点PU的电位为有效电平)导通，从而将当前级栅极驱动电路G[N]的上拉节点PU的电位下拉至无效电平，因此有效地确保当前级栅极驱动电路G[N]的上拉节点PU在所述下一级栅极驱动电路G[N+1]的充电阶段和显示阶段中保持无效电平。同时，上拉节点PU的无效电平使得第三晶体管M3断开，从而避免输出端OUT的输出信号受到其它信号的干扰，从而保证显示画面的均一性，最终提高显示画面的品质。
在当前级栅极驱动电路为显示扫描时段中的最后一级栅极驱动电路时，当前级栅极驱动电路输出触控信号，并且当前级栅极驱动电路G[N]的上拉节点PU在下一级栅极驱动电路G[N+1]的充电阶段和显示阶段中仍旧保持无效电平。
相应地，本公开的实施例提供了一种栅极驱动电路的驱动方法。如图5所示，在复位阶段501中，从复位端输入有效电平，从第二电压端输入无效电平，将从第二电压端VGL输入的无效电平传输至上拉节点。
在充电阶段502中，从第二信号端输入有效电平，从第一信号端输入有效电平，将从第一信号端输入的有效电平传输至上拉节点。
在显示阶段503中，从第三信号端输入有效电平，将从第三信号端输入的有效电平传输至输入端。
在放电阶段504中，从第二电压端输入无效电平，从第三信号端输入有效电平，从第四信号端输入有效电平，从第五信号端输入有效电平，将从第二电压端输入的无效电平传输至上拉节点。
本公开另外的方面提供一种显示面板，包括上述栅极驱动器。
在这样的显示面板中，在这样的显示装置中，通过在下一级栅极驱动电路G[N+1]的充电阶段和显示阶段中，将当前级栅极驱动电路G[N]的上拉节点PU的电位下拉至无效电平，可以有效地确保当前级栅极驱动电路G[N]的上拉节点PU在所述下一级栅极驱动电路G[N+1]的充电阶段和显示阶段中保持无效电平。同时，上拉节点PU的无效电平使得第三晶体管M3断开，从而避免输出端OUT的输出信号受到其它信号的干扰，从而保证显示画面的均一性，最终提高显示画面的品质。
本公开另外的方面还提供一种显示装置，包括上述显示面板。
在这样的显示装置中，通过在下一级栅极驱动电路G[N+1]的充电阶段和显示阶段中，将当前级栅极驱动电路G[N]的上拉节点PU的电位下拉至无效电平，可以有效地确保当前级栅极驱动电路G[N]的上拉节点PU在所述下一级栅极驱动电路G[N+1]的充电阶段和显示阶段中保持无效电平。同时，上拉节点PU的无效电平使得第三晶体管M3断开，从而避免输出端OUT的输出信号受到其它信号的干扰，从而保证显示画面的均一性，最终提高显示画面的品质。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (11)

  1. 一种栅极驱动电路，包括：
    第一信号端、第二信号端、第三信号端、第四信号端、第五信号端、复位端、第一电压端、第二电压端、输出端、上拉子电路、复位子电路、下拉子电路以及输出子电路，
    其中，
    所述上拉子电路分别与第一信号端、第二信号端、第三信号端、第四信号端、第五信号端、第一电压端、下拉节点以及上拉节点PU连接，并且配置成根据从第一信号端、第二信号端、第三信号端、第四信号端和第五信号端输入的信号以及下拉节点的电位控制上拉节点的电位，
    所述复位子电路分别与复位端、第二电压端以及上拉节点连接，并且配置成根据从复位端输入的信号对上拉节点的电位进行复位，
    所述下拉子电路分别与第四信号端、第一电压端、输出端、上拉节点以及下拉节点连接，并且配置成根据从第四信号端输入的信号、从输出端输出的信号以及上拉节点的电位控制下拉节点的电位，
    所述输出子电路分别与第三信号端、第一电压端、输出端、上拉节点以及下拉节点连接，并且配置成根据从第三信号端输入的信号、下拉节点的电位和上拉节点的电位控制从输出端输出的信号。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述上拉子电路包括第一晶体管、第五晶体管、第九晶体管、第十晶体管以及第十一晶体管，
    其中，
    所述第一晶体管的控制极与所述第二信号端连接，所述第一晶体管的第一极与所述第一信号端连接，并且所述第一晶体管的第二极与所述上拉节点连接；
    所述第五晶体管的控制极与所述下拉节点连接，所述第五晶体管的第一极与所述第一电压端连接，并且所述第五晶体管的第二极与所述上拉节点连接；
    所述第九晶体管的控制极与所述第五信号端连接，所述第九晶体管的第一极与所述第十晶体管的第二极连接，并且所述第九晶体管的 第二极与所述第一电压端连接；
    所述第十晶体管的控制极与所述第四信号端连接，并且所述第十晶体管的第一极与所述第十一晶体管的第二极连接；
    所述第十一晶体管的控制极与所述第三信号端连接，并且所述第十一晶体管的第一极与所述上拉节点连接。
  3. 根据权利要求2所述的栅极驱动电路，其中，所述复位子电路包括第二晶体管，所述第二晶体管的控制极与所述复位端连接，所述第二晶体管的第一极与所述上拉节点连接，并且所述第二晶体管的第二极与所述第二电压端连接。
  4. 根据权利要求3所述的栅极驱动电路，其中，
    所述下拉子电路包括第六晶体管、第七晶体管、第八晶体管以及电容器；
    所述第六晶体管的控制极与所述上拉节点连接，所述第六晶体管的第一极与所述第一电压端连接，并且所述第六晶体管的第二极与所述下拉节点连接；
    所述第七晶体管的控制极与所述输出端连接，所述第七晶体管的第一极与所述下拉节点连接，并且所述第七晶体管的第二极与所述第一电压端连接；
    所述第八晶体管的控制极与所述第四信号端连接，所述第八晶体管的第一极与所述第四信号端连接，并且所述第八晶体管的第二极与所述下拉节点连接；
    所述电容器的第一极与所述上拉节点连接，并且所述电容器的第二极与所述输出端连接。
  5. 根据权利要求4所述的栅极驱动电路，其中，
    所述输出子电路包括第三晶体管和第四晶体管；
    所述第三晶体管的控制极与所述上拉节点连接，所述第三晶体管的第一极与所述第三信号端连接，并且所述第三晶体管的第二极与所述输出端连接；
    所述第四晶体管的控制极与所述下拉节点连接，所述第四晶体管的第一极与所述输出端连接，并且所述第四晶体管的第二极与所述第一电压端连接。
  6. 根据权利要求5所述的栅极驱动电路，其中，所述第十晶体管 和所述第十一晶体管为P型晶体管，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管以及所述第九晶体管为N型晶体管。
  7. 根据权利要求5所述的栅极驱动电路，其中，所述第十晶体管和所述第十一晶体管为N型晶体管，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管、所述第七晶体管、所述第八晶体管以及所述第九晶体管为P型晶体管。
  8. 一种根据权利要求1-7中任一项所述的栅极驱动电路的驱动方法，包括：复位阶段、充电阶段、显示阶段和放电阶段，
    其中，
    在复位阶段中，从复位端输入有效电平，从第二电压端输入无效电平，将从第二电压端VGL输入的无效电平传输至上拉节点；
    在充电阶段中，从第二信号端输入有效电平，从第一信号端输入有效电平，将从第一信号端输入的有效电平传输至上拉节点；
    在显示阶段中，从第三信号端输入有效电平，将从第三信号端输入的有效电平传输至输入端；并且
    在放电阶段中，从第二电压端输入无效电平，从第三信号端输入有效电平，从第四信号端输入有效电平，从第五信号端输入有效电平，将从第二电压端输入的无效电平传输至上拉节点。
  9. 一种栅极驱动器，包括多个级联的根据权利要求1-7中任一项所述的栅极驱动电路，其中，对于每一级栅极驱动电路，第一电压端与第一电压线连接，第二电压端与第二电压线连接，第一信号端与第一信号线连接，第二信号端与前一级栅极驱动电路的输出端连接，第三信号端与第三信号线连接，第四信号端与第四信号线连接，第五信号端与后一级栅极驱动电路的上拉节点连接，复位端与后一级栅极驱动电路的输出端连接，并且输出端与前一级栅极驱动电路的复位端和后一级栅极驱动电路的第二信号端连接。
  10. 一种显示面板，包括根据权利要求9所述的栅极驱动器。
  11. 一种显示装置，包括根据权利要求10所述的显示面板。
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