Classifications

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  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
  • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
  • C23C14/24—Vacuum evaporation
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
  • H10K77/10—Substrates, e.g. flexible substrates
  • H10K77/111—Flexible substrates
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
  • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
  • C23C14/14—Metallic material, boron or silicon
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  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
  • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
  • C23C14/14—Metallic material, boron or silicon
  • C23C14/20—Metallic material, boron or silicon on organic substrates
  • C23C14/205—Metallic material, boron or silicon on organic substrates by cathodic sputtering
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
  • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
  • C23C14/34—Sputtering
  • C23C14/3407—Cathode assembly for sputtering apparatus, e.g. Target
  • C23C14/3414—Metallurgical or chemical aspects of target preparation, e.g. casting, powder metallurgy
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C24/00—Coating starting from inorganic powder
  • C23C24/02—Coating starting from inorganic powder by application of pressure only
  • C23C24/04—Impact or kinetic deposition of particles
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
  • C23C28/30—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
  • C23C28/32—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one pure metallic layer
  • C23C28/322—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one pure metallic layer only coatings of metal elements only
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
  • C23C28/30—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
  • C23C28/34—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates
  • C23C28/345—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates with at least one oxide layer
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
  • C23C28/30—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
  • C23C28/34—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates
  • C23C28/345—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates with at least one oxide layer
  • C23C28/3455—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates with at least one oxide layer with a refractory ceramic layer, e.g. refractory metal oxide, ZrO2, rare earth oxides or a thermal barrier system comprising at least one refractory oxide layer
• • H—ELECTRICITY
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
  • H10D30/6739—Conductor-insulator-semiconductor electrodes
• • H—ELECTRICITY
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
  • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
  • H10D30/6743—Silicon
• • H—ELECTRICITY
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/62—Electrodes ohmically coupled to a semiconductor
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
  • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
  • H10D86/441—Interconnections, e.g. scanning lines
  • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
• • H—ELECTRICITY
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
  • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K50/00—Organic light-emitting devices
  • H10K50/80—Constructional details
  • H10K50/805—Electrodes
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
  • H10K59/10—OLED displays
  • H10K59/12—Active-matrix OLED [AMOLED] displays
  • H10K59/131—Interconnections, e.g. wiring lines or terminals
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
  • H10K59/10—OLED displays
  • H10K59/17—Passive-matrix OLED displays
  • H10K59/179—Interconnections, e.g. wiring lines or terminals
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
  • H10K59/80—Constructional details
  • H10K59/805—Electrodes
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
  • H10K71/60—Forming conductive regions or layers, e.g. electrodes
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B22—CASTING; POWDER METALLURGY
  • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
  • B22F3/00—Manufacture of workpieces or articles from metallic powder characterised by the manner of compacting or sintering; Apparatus specially adapted therefor ; Presses and furnaces
  • B22F3/10—Sintering only
  • B22F3/105—Sintering only by using electric current other than for infrared radiant energy, laser radiation or plasma ; by ultrasonic bonding
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B22—CASTING; POWDER METALLURGY
  • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
  • B22F3/00—Manufacture of workpieces or articles from metallic powder characterised by the manner of compacting or sintering; Apparatus specially adapted therefor ; Presses and furnaces
  • B22F3/12—Both compacting and sintering
  • B22F3/14—Both compacting and sintering simultaneously
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B22—CASTING; POWDER METALLURGY
  • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
  • B22F3/00—Manufacture of workpieces or articles from metallic powder characterised by the manner of compacting or sintering; Apparatus specially adapted therefor ; Presses and furnaces
  • B22F3/12—Both compacting and sintering
  • B22F3/14—Both compacting and sintering simultaneously
  • B22F3/15—Hot isostatic pressing
• • G—PHYSICS
  • G02—OPTICS
  • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
  • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
  • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
  • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
  • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
  • G02F1/1333—Constructional arrangements; Manufacturing methods
  • G02F1/133305—Flexible substrates, e.g. plastics, organic film
• • G—PHYSICS
  • G02—OPTICS
  • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
  • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
  • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
  • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
  • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
  • G02F1/1333—Constructional arrangements; Manufacturing methods
  • G02F1/1345—Conductors connecting electrodes to cell terminals
  • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
  • H10K2102/301—Details of OLEDs
  • H10K2102/311—Flexible OLED
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
  • Y02E10/00—Energy generation through renewable energy sources
  • Y02E10/50—Photovoltaic [PV] energy
  • Y02E10/549—Organic PV cells

Definitions

• the invention relates to a use of an additive for the preservation of a
• TFT thin-film transistors
• Display eg liquid crystal displays (TFT-LCDs), AM-OLEDs (active matrix organic light emitting diodes, organic light-emitting diodes with active matrix control), or micro-LED (light emitting diodes) displays
• Structure can also be used in other applications, for example, sensor arrays for X-ray radiation
• electrical tracks are matrix-like, as lines (“gate lines”) and
• the conductor tracks provide an electrically conductive path for transmitting electrical signals, electrical current, or electrical voltage from one point to another.
• Each active matrix row or column consists of a long, narrow trace (for example, with a length of a few centimeters to almost 2 meters, a width of a few micrometers to a few tens of micrometers and a
• source / drain electrodes of the TFT with the edge region of the substrate, where either contact pads for external contacting, or the gate and Data driver structures (row and column drivers) are arranged to control the display.
• the brightness of each individual pixel can be individually controlled via one (e.g., TFT-LCD) or multiple (e.g., AM-OLED display) TFTs; it is crucial that the
• Substrates are arranged, in particular, the long row and column tracks are subjected to a high deformation or bending or torsional stress, which strain in the gate and source / drain electrodes in the TFT structure due to the much smaller spatial extent
• the TFTs arranged along the track are no longer supplied uniformly with a defined voltage and can be length-dependent
• Brightness differences in a display application come. In extreme cases, the conductor completely loses its electrical conductivity and it comes to the total failure of pixels.
• SOP system on display panel
• SOG system-on-glass
• LTPS low-temperature poly-silicon
• Parts of the peripheral circuits arranged on the substrate are connected via electrical tracks, the gate lines and signal lines to the TFTs of the individual pixels, wherein the length can be from a few mm up to 200 cm, depending on the display size.
• the resistance change of the tracks under deformation, bending or torsional load should be as minimal as possible to prevent failure of individual pixels, or entire rows or columns of the display or unwanted differences in the brightness or color ("Mura") of the display to prevent.
• non-linear e.g. B. Sinunsförmige, wavy, rectangular wave, meandering, or sawtooth waveguide interconnect structures proposed.
• the object of the invention is the preservation of the electrical conductivity of a metallic layer which is applied to a flexible substrate which is subjected to a single or repeated bending, tensile and / or torsional loading.
• the invention ensures that it is a one-off or
• the electrical conductivity of the Mo-based (molybdenum-based) layer or the metallic layer is maintained within the layer plane. This is done by increasing the ductility.
• each metallic layer has the restriction that on both sides directly adjacent to a semiconductive or electrically insulating layer and the metallic layer itself according to Claim 2 is designed as a single layer, two-layer system or three-layer system.
• a Mo-based layer or the MoX layer contains at least 50% by weight of Mo, in particular at least 60% by weight of Mo.
• the MoX layer may be composed of multiple MoX with different X containing MoX sublayers.
• Mo-based layer apart from the additive X, does not have to be pure Mo, but it can
• Contaminants may be present, especially those arising from the
• PVD physical vapor deposition
• Vapor phase deposition in particular a sputtering process (sputtering) (eg Ar, O, N, C).
• sputtering eg Ar, O, N, C.
• Impurities should be ⁇ 0.5 at%.
• the layer structure has a metallic layer with a semiconducting or electrically insulating layer immediately adjacent to the metallic layer and with a semiconducting or electrically insulating layer immediately adjacent to the metallic layer, these properties being at least within a certain range one
• electrically insulating is meant that the electrical resistance is greater than 1 megohm.
• Flexibility and "flexibility” mean the property, a
• significantly improved toughness means that the component or, of course, the layer contained, or
• Layers have increased resistance to cracking and crack growth, so that cracks do not form up to a certain elongation or form only at higher elongation or have a modified crack course.
• critical elongation is used in the context of the present invention.
• a flexible substrate based on or a plurality of polymeric materials for example polyimide, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, polyethersulfone, polyarylate or polycyclic olefin.
• Most flexible substrates based on one or more polymeric materials have an E-modulus of less than or equal to 8 GPa.
• thin glass glass with a thickness of less than 1 mm
• metal foils for example steel sheet with a thickness of less than 1 mm, aluminum, copper or titanium foils with a thickness of less than 1 mm, or mineral materials, such as mica, are suitable flexible substrates for a flexible component according to the invention.
• a flexible substrate suitable for the invention may again consist of one or more layers or one or more materials or materials. Likewise, such a substrate may be pre-coated completely or only partially with one or more layers of other materials.
• this component is a coated flexible electronic component.
• a coated flexible component such as
• Packaging films with metallic vapor barrier layers or optical layers, a coated flexible electronic component on at least one electric current conducting layer This is flexible, for example
• the metallic layer of a coated flexible component according to the invention preferably has a thickness of less than 1 ⁇ .
• the metallic layer preferably has a minimum thickness of 5 nm, more preferably a thickness of at least 10 nm. Also preferred is a thickness of 5 to 300 nm, more preferably of 5 to 100 nm. Such layer thicknesses are particularly advantageous when the metallic Layer is used as a primer layer or diffusion barrier layer. Alternatively, a thickness range of 150 to 400 nm is preferred. A layer thickness of 150 to 400 nm is particularly good for use with a coated flexible component according to the invention in a display, for example as a gate electrode layer, suitable.
• One or more metallic layer (s), as specified in claim 2 and optionally in one of the further developments, can form part of a
• TFT Thin-film transistor
• the element in at least one MoX layer X the element is Cu and this MoCu layer contains more than 0.5 at% and less than 50 at% Cu, preferably more than 1 at% and contains less than 20 at% Cu. It is particularly preferred
• the element Ag in at least one MoX layer X the element Ag is and this MoAg layer contains more than 10 at% and less than 50 at% Ag, preferably more than 20 at% and less than Contains 50 at% Ag. It is particularly preferred
• the element Au to be present in at least one MoX layer X, and for this metallic MoAu layer to contain more than 5 at% and less than 20 at% Au. It is particularly preferred that all MoX layers of
• the individual MoX layer has a sheet resistance p of less than 200 pOhmcm, preferably less than 100 ohmcm, more preferably less than 50 ⁇ .
• At least one of the semiconducting or electrically insulating layers immediately adjacent to the metallic layer is formed as layers. It can be provided that both immediately adjacent semiconducting or electrically insulating layers are formed as layers.
• the metallic layer as a whole has a sheet resistance p of less than 50 ⁇ m, preferably less than 10 ⁇ m, particularly preferably less
• At least one MoX layer is deposited which contains more than 0.5 at% and less than 50 at% X, where X is one or more elements from the group of Cu, Ag, Au.
• the MoX layer can thereby form a metallic layer, as defined in claim 2, or be part of the same.
• a deposition of the at least one MoX layer or the metallic layer can be realized by various deposition methods.
• such a coating can be realized by physical or chemical vapor deposition.
• the deposition of the at least one MoX layer or the metallic layer is realized by means of a PVD method, in particular a sputtering method.
• PVD Physical Vapor Deposition
• PVD processes are known thin film deposition technologies in which particles of the coating material are vaporized and then deposited on the substrate.
• PVD Physical Vapor Deposition
• a Mo-based target containing between 0.5 at% and less than 50 at% X occurs before depositing at least one MoX layer or at least one metallic layer.
• the MoX layer or the metallic layer is therefore deposited by the provided target.
• Under Target is a coating source for a coating system to understand.
• the target used is a sputtering target for a sputtering process.
• the chemical composition of the coating is over the chemical
• the Cu content in the deposited coating may be slightly increased.
• a corresponding target may also contain less than 10 at% Cu.
• the metallic layer can also be deposited via co-deposition, preferably co-sputtering, of individual targets become.
• the chemical composition of the coating can additionally be controlled by the choice of the different targets.
• Metallic layers are, for example, can be done by powder metallurgy.
• Possible powder metallurgical routes for producing sputtering targets are based on hot pressing technologies such as hot pressing (HP) or spark plasma sintering (SPS).
• HP hot pressing
• SPS spark plasma sintering
• a powder mixture is filled into a mold of a press, heated in the mold and sintered / compacted at a high press pressure and high temperature into a dense component. This results in a homogeneous microstructure with uniform grains, which has no preferential orientation (texture).
• a similar powder metallurgical route for producing sputtering targets is hot isostatic pressing (HIP).
• the material to be compacted is filled into a deformable, sealed container (usually a steel can). These may be powders, powder mixtures or green bodies (in the form of pressed powder).
• the material in this container is sintered / compacted in the container in a pressurized vessel at high temperatures and pressures under inert gas (eg Ar). The gas pressure acts from all sides, therefore this process is called isostatic pressing.
• Typical process parameters are z. B. 1100 ° C and 100 MPa with a holding time of 3 h. This results in a homogeneous microstructure with uniform grains, the no
• Preferred orientation has.
• powder metallurgical route is sintering and subsequent forming.
• a powder compact is sintered at high temperature under hydrogen or vacuum.
• a forming step such as rolling or
• powder metallurgical route is the application of a powder or a
• Powder mixture on a corresponding support structure such as a plate or a tube, by means of a thermal spraying process, for example
• Figure 1 shows a schematic structure of the uniaxial used
• FIG. 3 Electron micrographs of the crack pattern of a Mo layer and various MoCu layers after a maximum elongation of 15%
• FIG. 5 Electron micrographs of the crack pattern of a Mo layer and various MoAg layers after a maximum elongation of 15%
• FIG. 6 Layer structure of a bottom-gate thin-film transistor in cross section
• FIG. 7 Schematic block diagram of a system-on-panel display (from above)
• Shows trace structures between driver circuits and TFT display area from above 9 shows a section of the TFT display structure (from above, top view), which shows how the gate and source / drain electrodes of the TFT are connected to the gate and data lines.
• FIG. 10 Layer structure of a top gate LTPS TFT in cross section
• FIG. 11 X-ray diffractograms of sputtered 500 nm thick MoCu
• FIG. 12 X-ray diffractograms of sputtered 500 nm thick MoAg
• compositions of the Mo-based metallic layers are summarized in Table 1.
• molybdenum-based alloys As a reference material for the molybdenum-based alloys, pure Mo in the form of a molybdenum layer of 50nm in thickness was used. All layers were deposited on a 50 ⁇ m film of polyimide (PI, eg "Kapton®”) at room temperature, the process parameters being kept constant in order to determine the influence of different process conditions on the PI, eg "Kapton®"
• the layer thickness was kept constant at 50 nm in order to avoid any influence of geometric effects on the results.
• the substrate surface was completely coated, no smaller ones
• the measurement setup is shown schematically in FIG. Uonst designates the fixed clamping length within which no strain takes place.
• FIG. 2 shows the increase of the electrical resistance in comparison to FIG.
• the tested layers were examined by light microscopy and scanning electron microscopy. The shape of the cracks and the average distance between the cracks that occurred in the layers were assessed.
• a crack pattern which is typical for a brittle material behavior. This is characterized by a network of straight, parallel cracks that form approximately at right angles to the loading direction. Such a crack pattern can be seen for example in Figures 3 (Mo, left). These straight cracks usually run the entire width of the sample from one side to the other and through the entire thickness of the layer. Such cracks are also called Through Thickness Cracks (TTC). TTCs reduce the electrical conductivity of the layer considerably, since in the worst case, no continuous conductive connection is left in the layer.
• TTC Through Thickness Cracks
• FIG. 2 shows the resistance curve R / Ro of the samples MoCu 7at.%.
• the appearance of the cracks still corresponds to the TTCs, but is the critical
• the critical strain Ek is thus significantly increased and the occurrence of cracks is reduced. If the Cu content is further increased, the cracking behavior will be brittle towards tough changed. Consequently, Cu as an additive to Mo is characterized in particular by the fact that even low additions lead to a considerable increase in the toughness of the Mo-based layer and that Cu as a material is comparatively favorable.
• FIG. 11 shows X-ray diffractograms of two MoCu layers with one
• Sheet resistance less than 150 pOhmcm.
• the sheet resistance along a long conductor track is determined primarily by the respectively more conductive material Cu or Al.
• a two-day layer of 50 nm oCu34-at.% And 300 nm Cu over (deposited on a nonconductive glass substrate) has a sheet resistance of 2.0 pOhmcm.
• a two-layered layer of 50 nm MoCu34-at.% And 300 nm Al above has one
• the mechanical properties of the investigated layers can be further optimized.
• the microstructure and residual stress state of the deposited Mo-based layers can be further optimized.
• a targeted adjustment of the deposition conditions can also influence the growth of the layers in a targeted manner, and a further increase in toughness is very likely to be achieved.
• compositions of the Mo-based metallic layers are summarized in Table 3.
• the layer thickness was kept constant at 50 nm in order to avoid any influence of geometric effects on the results.
• the substrate surface was completely coated, no smaller ones
• Table 4 Critical strain ⁇ ⁇ of the investigated Mo and MoAg layers, as well as the difference to the reference sample of pure Mo. Furthermore, the sheet resistance of a 500 nm thick layer on a non-conductive boro-silicate glass (Corning Eagle XG) is given. Material critical strain ⁇ ⁇ sheet resistance p
• the tested layers were examined by light microscopy and scanning electron microscopy. The shape of the cracks and the average distance between the cracks that occurred in the layers were assessed.
• a crack pattern that is typical for a brittle material behavior. This is characterized by a network of straight, parallel cracks that form approximately at right angles to the loading direction. Such a crack pattern can be seen for example in Figures 5 (Mo, left). These straight cracks usually run the entire width of the sample from one side to the other and through the entire thickness of the layer. Such cracks are also called Through Thickness Cracks (TTC). TTCs reduce the electrical conductivity of the layer considerably, since in the worst case, there is no longer continuous conductive connection in the layer. As can be seen in the curves measured on the reference materials, the electrical resistance increases very strongly with increasing strain.
• TTC Through Thickness Cracks
• FIG. 4 shows the increase of the electrical resistance in comparison to the output resistance (R / Ro) in relation to the applied strain ⁇ .
• FIG. 4 shows the resistance curves R / Ro of the various MoAg samples.
• the appearance of the cracks still corresponds to the TTCs, as can be seen from FIG. 5 (top right), but the critical strain ⁇ has already been significantly increased.
• FIG. 12 shows the X-ray diffractograms of the deposited MoAg layers.
• the layer deposition and analysis of the crystal structure was carried out analogously to the MoCu system (FIG. 11).
• the diffractograms of a pure Mo or Ag layer are also included.
• the positions of the X-ray reflections of cubic-body-centered (krz) molybdenum (space group lm-3m) and the vertical dashed line are the reflection positions of cubic face-centered (fcc) silver (space group Fm-3m) as a reference
• the MoAg systems have no separate Ag phase up to a silver content of 44% by volume, since the corresponding reflections in the diffractogram are missing. It is therefore to be assumed that the Ag is present in the molybdenum in a positively dissolved state, in the form of a mixed crystal, ie. h., that the silver atoms occupy molybdenum lattice sites. The silver atoms in this way lead to a distortion of the Mo lattice. The distorted Mo lattice is also suggested by the two Mo (110) and Mo (200) reflections, which are compared to the
• the copper or silver (element X) is present in the krz-molybdenum lattice with forced release.
• the crystal structure of pure gold (Au) is the same as that of Cu and Ag (space group Fm-3m). All three elements are in the same subgroup (11) of the Periodic Table of the Chemical Elements and in many ways show a similar chemical and chemical structure
• the sheet resistance p (pOhmcm) of the various Mo or MoAg thin films is indicated (500 nm layer thickness on an insulating glass substrate).
• the specific surface resistance R s (ohms / sheet) was measured by means of a four-point method and multiplied by the layer thickness.
• the layer resistance of the MoAg layers increases up to an Ag content of 31at.%, And then decreases again with increasing Ag content. All MoAg layers have a layer resistance of less than 150 pOhmcm.
• Sheet resistance determined along a long conductor especially by the respective better conductive material Cu or AI is determined along a long conductor especially by the respective better conductive material Cu or AI.
• a two-ply layer of 50 nm MoAg 31at.% And 300 nm Cu over (deposited on a nonconductive glass substrate) has a sheet resistance of 2.0 pOhmcm.
• a two-layered layer of 50 nm MoAg 31at.% And 300 nm Al above has one
• One or more metallic layer (s), as specified in claim 2 and optionally in one of the further developments, can form part of a
• TFT Thin-film transistor
• the layer structure of such an electrical thin-film component is shown in cross-section in FIG.
• the TFT consists of a semiconductor layer 150, a gate electrode 120, a source electrode 170a, and a drain electrode 170b, wherein at least one of these three metallically conductive electrode layers consists of the metallic layer according to the invention.
• the gate electrode 120 is separated from the semiconductor layer 150 by an electrically insulating layer (gate insulator, gate dielectric) 140.
• the source electrode 170a is separated from the drain electrode 170b by an electrically insulating passivation layer 180. Furthermore, this separates
• Passivation layer 180 the source / drain electrodes 170a / 170b also from the pixel electrode layer 190 (apart from that described below
• the TFT layer structure is disposed on a flexible substrate 100.
• a buffer layer 110 can be arranged on the flexible substrate 100, which covers the entire substrate 100 in order to compensate for any unevenness on the upper side of the flexible substrate 100 or the penetration of undesired ones
• the buffer layer may e.g. consist of a single-layer or multi-layer containing silicon oxide or silicon nitride.
• the gate electrode 120 is disposed over the buffer layer 110. By applying an electrical voltage, an electrically conductive channel can form in the semiconductor layer 150 due to an electric field effect, which electrically conductively connects the source electrode 170a to the drain electrode 170b.
• the gate electrode 120 can consist of the metallic layer according to the invention, or of a prior art metallization of a single- or multi-layer, at least aluminum (AI), copper (Cu), silver (Ag), gold (Au ), Platinum (Pt), molybdenum (Mo), tungsten (W), titanium (Ti), chromium, (Cr), niobium (Nb), tantalum (Ta).
• an electrically insulating layer (gate dielectric) 140 is arranged over the gate electrode 120.
• This electrically insulating layer 140 may be, for example, a layer of silicon oxide, silicon nitride, aluminum oxide, or an electrically insulating organic material such as silicon dioxide.
• Benzocyclobutene (BCB) or an acrylic-containing material include.
• the semiconductor layer 150 adjoins the electrically insulating layer (gate dielectric) 140 and may, for. Amorphous silicon (a-Si), poly-silicon, a metal oxide semiconductor such as indium gallium zinc oxide (IGZO), or an organic semiconductor.
• a-Si Amorphous silicon
• IGZO indium gallium zinc oxide
• an organic semiconductor In the case of a semiconductor layer 150a which includes a-Si, an n + -doped semiconductor layer 150b may still be arranged above this layer, for example containing phosphorus-doped a-Si.
• the doped semiconductor layer 150b is usually omitted.
• the source and drain electrode layers 170a and 170b are arranged.
• These layers can consist of the metallic layer according to the invention, or of a prior art metallization of a single- or multi-layer, at least aluminum (AI), copper (Cu), silver (Ag), gold (Au), platinum (Pt), molybdenum (Mo), tungsten (W), titanium (Ti), chromium, (Cr), niobium (Nb), tantalum (Ta).
• AI aluminum
• Cu copper
• Ag gold
• Mo molybdenum
• W tungsten
• Ti titanium
• Cr chromium
• Nb niobium
• Ta tantalum
• the passivation layer 180 is arranged.
• This electrically insulating passivation layer 180 may be, for example, a layer of silicon oxide,
• Material such as e.g. Benzocyclobutene (BCB) or an acrylic-containing material include.
• BCB Benzocyclobutene
• acrylic-containing material include.
• the passivation layer 180 is interrupted by a contact hole that electrically connects the adjacent pixel electrode layer 190 to the drain electrode 170b.
• the pixel electrode layer 190 is electrically conductive and can be embodied as an optically transparent layer or as an optically reflective layer and can be embodied as one or multilayer. When the pixel electrode layer 190 is formed as an optically transparent layer, it may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or aluminum zinc oxide (AZO).
• the pixel electrode layer 190 When the pixel electrode layer 190 is formed as an optically reflective layer, it may include a reflective layer of Al, Ag, Mg, Pt, Pd, Au, Nd, Ni, Ir, and a layer including indium tin oxide (ITO). , Indium Zinc Oxide (IZO), Zinc Oxide (ZnO), or Aluminum Zinc Oxide (AZO).
• a reflective layer of Al Ag, Mg, Pt, Pd, Au, Nd, Ni, Ir
• ITO indium tin oxide
• ITO indium tin oxide
• IZO Indium Zinc Oxide
• ZnO Zinc Oxide
• AZO Aluminum Zinc Oxide
• the TFT described here can be part of a flexible TFT-LCD display or OLED display.
• One or more metallic layers as specified in claim 2 and optionally in one of the further developments can be part of a system-on-panel (SOP) system in which a TFT active matrix display with peripheral
• the display unit 1 may for example consist of a Liquid crystal display (LCD), an organic light emitting diode (OLED), an inorganic light emitting diode (LED), or an electrophoretic display ("E-Ink®", "e-paper”).
• the display unit 1 represents the actual visible part of the display, on which the image content is displayed.
• a plurality of drive and drive circuits on the substrate Arranged around this area are a plurality of drive and drive circuits on the substrate, which are typically hidden behind an opaque part of the housing, not visible to the user.
• one or more of the electronic circuits described below can be arranged on the SOP, although this enumeration is not exhaustive and, depending on the display unit used, further circuits for the control may be necessary.
• a horizontal data driver circuit (column driver) 2a / b may be arranged on the substrate, which is connected via the data lines (not shown) to the source / drain electrodes 170a / b of the TFT (not shown) ,
• a gate driver structure (row driver) 3 may be located on the substrate, which is connected via the gate lines (not shown) to the gate electrodes 120 of the TFTs (not shown).
• a DC-DC converter circuit 4 may be arranged, which has a lower input voltage to a higher
• Converts output voltage; for driving a TFT-LCD display could e.g. at the input a voltage of +3.3 to +5.0 V, which is converted into a higher output voltage in the range -40 to + 40V ("charge pump"), which is needed to drive the liquid crystal.
• an electrical circuit 5 may be disposed on the SOP providing a reference voltage (Vcom, e.g., + 5V for an LCD display) to the display unit 1.
• Vcom a reference voltage
• a timing controller circuit (TCon) 6 a digital-to-analog converter circuit 7, a discharge stage 8, and a Vcom buffer circuit 9 could be arranged on the substrate.
• the SOP is connected via a contacting region 10 with the other components of the Displayan Kunststoffelektronik or a graphics card.
• peripheral circuits 2 to 9 are interconnected with the display unit 1 and the contacting area ("pad contacts") 10 with the metallic layer according to the invention (not shown).
• the contacting of the display unit 1 is exemplified.
• the row driver 3 is connected to the display unit 1 via electrical conductors 20
• the column driver 2b is connected to the display unit 1 via electrical conductors 21.
• One or both conductor tracks 20 or 21 may consist of the metallic layer according to the invention, as claimed in claim 2 and
• FIG. 9 shows the contacting of a thin-film transistor (TFT) with the gate and data lines.
• the gate conductor 20 has a in the region of the TFT
• the data trace 21 has an extension in the region of the TFT which forms the source electrode 170a of the TFT and a region interrupted by the source electrode which forms the drain electrode 170b of the TFT and that with the pixel electrode 190 is connected.
• One or both conductor tracks 20 or 21 or the TFT electrodes 120, 170a / b may consist of the metallic layer according to the invention, as specified in claim 2 and optionally in one of the further developments.
• one or more metallic layer (s), as specified in claim 2 and optionally in one of the further developments may be part of a low-temperature poly-silicon (LTPS) thin-film transistor (TFT) whose
• Layer structure in cross section in Figure 10 is shown by way of example.
• a top-gate TFT ie, the gate electrode 240 is disposed over the semiconductor layer 220, and not below.
• LTPS TFTs are preferably designed as top-gate TFTs.
• the LTPS semiconductor has a significantly higher charge carrier mobility (50-200 cm 2 / Vs).
• such a TFT can also be used to control current-driven displays such as OLEDs or micro-LEDs.
• the layer structure for a top-gate LTPS TFT will be described below by way of example.
• the LTPS TFT is disposed on a flexible substrate 200.
• a buffer layer 210 may be arranged on the flexible substrate 200 covering the entire substrate 200 in order to compensate for any unevenness on the upper side of the flexible substrate 200 or the penetration of unwanted impurities into the semiconductor layer 220 or into doped ones
• the buffer layer 210 may be e.g. consist of a single-layer or multi-layer comprising silicon oxide, silicon nitride, or silicon oxynitride. Depending on the nature of the substrate, it is also possible to dispense with the buffer layer.
• the semiconductor layer 220 which may be made of undoped polycrystalline silicon, is disposed on the buffer layer 210. Adjacent to this layer 220 (also referred to as "channel area") is a source electrode 221 on one side and a drain electrode 222 on the other side, each of which may consist of doped polysilicon
• Ion implantation For example, by using boron (B) or B2H6, p-type doping can be achieved. Depending on the design of the TFT, however, the type of doping (p or n) or the type of dopant may vary.
• a gate insulator layer 230 is disposed over the semiconductor layers 220, 221, and 222.
• This gate insulator layer 230 may be e.g. made of silicon nitride or
• the gate electrode 240 is arranged to have at least a certain range of overlap (in the vertical direction) to the channel area (semiconductor layer 220).
• the gate electrode 240 may consist of the metallic layer according to the invention, or of a prior art metallization of a single- or multi-layer comprising at least aluminum (AI), copper (Cu), silver (Ag), gold (Au ), Platinum (Pt), molybdenum (Mo), tungsten (W), titanium (Ti), chromium, (Cr), niobium (Nb), tantalum (Ta) includes.
• the gate electrode 240 is connected via gate lines (not shown) to the drive electronics (not shown), including the row drivers.
• an insulating layer 250 is applied, which may consist of a similar material as the gate insulator layer 230, for.
• a similar material for example, silicon nitride or silicon oxide.
• the insulating layer 250 and the gate insulator layer 230 are provided with through holes, which make the source and drain electrodes 221/222 of the semiconductor layer (electrically) accessible.
• a driving source electrode layer 260 and a driving drain electrode layer 270 are above the
• the drive or. Contacting source / drain electrode layers 260/270 may consist of the metallic layer according to the invention or of a prior art metallization of a single- or multi-layer, at least aluminum (AI), copper (Cu), silver (Ag ), Gold (Au), platinum (Pt), molybdenum (Mo), tungsten (W), titanium (Ti), chromium, (Cr), niobium (Nb), tantalum (Ta).
• the drive or contact source electrode layer 260 is connected to the drive electronics via the data lines (signal lines, not shown) and the like. a. connected to the column drivers (not shown).
• the thin-film transistor is made of the semiconductor layer 220, the gate electrode 240, and the drive or. Contacting source / drain electrode layers 260/270 are formed. However, the configuration of the TFT is not on the above
• a planarization layer 280 can also be arranged above the TFT structure, in particular if further light-emitting layers, eg OLED layers, are arranged above the TFT (not shown).
• the planarization layer 280 may include, for example, a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin Polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB).
• Planarization layer 280 is provided with a via hole that exposes a portion of the drive-on drain electrode layer 270.
• FIG. 10 also shows a pixel electrode layer 290 which is applied over the planarization layer 280 and which is electrically conductively connected to the drive or contact drain electrode layer 270 via the through-hole.
• the pixel electrode layer 290 forms the first electrode (usually the anode in an upwardly emitting structure) of a light-emitting structure.
• the pixel electrode layer 290 is formed as an optically transparent layer, it may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or aluminum zinc oxide (AZO).
• the pixel electrode layer 290 may include a reflective layer of Al, Ag, Mg, Pt, Pd, Au, Nd, Ni, Ir, and a layer including indium tin oxide (ITO), Indium zinc oxide (IZO), zinc oxide (ZnO), or aluminum-zinc oxide (AZO).
• ITO indium tin oxide
• IZO Indium zinc oxide
• ZnO zinc oxide
• AZO aluminum-zinc oxide
• gate 140 insulating layer (gate insulator, gate dielectric)

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