WO2018198575A1 - Dispositif semiconducteur - Google Patents

Dispositif semiconducteur Download PDF

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Publication number
WO2018198575A1
WO2018198575A1 PCT/JP2018/010274 JP2018010274W WO2018198575A1 WO 2018198575 A1 WO2018198575 A1 WO 2018198575A1 JP 2018010274 W JP2018010274 W JP 2018010274W WO 2018198575 A1 WO2018198575 A1 WO 2018198575A1
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layer
region
gate
electrode
gate electrode
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PCT/JP2018/010274
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English (en)
Japanese (ja)
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正清 住友
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株式会社デンソー
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present disclosure relates to a semiconductor device in which a trench gate type insulated gate bipolar transistor (hereinafter simply referred to as IGBT) is formed.
  • IGBT trench gate type insulated gate bipolar transistor
  • CMOS devices in which IGBTs are formed have been proposed as semiconductor devices used as power switching elements (see, for example, Patent Document 1).
  • a P-type base layer is formed in a surface layer portion of a semiconductor substrate having an N ⁇ -type drift layer, and an N + -type carrier storage layer ( Hereinafter, it is simply referred to as a CS layer).
  • a plurality of trenches are formed in the semiconductor substrate so as to penetrate the base layer and the CS layer, and each trench is embedded by a gate insulating film formed on the wall surface and a gate electrode formed on the gate insulating film. It is.
  • the plurality of gate electrodes include a first gate electrode connected to the gate control circuit and applied with a predetermined voltage, and a second gate electrode connected to the emitter electrode and set to the same potential as the emitter electrode. is doing.
  • An N + -type emitter region is formed in the surface layer portion of the base layer so as to be in contact with the trench.
  • a P + -type collector layer is formed on the back side of the semiconductor substrate.
  • An emitter electrode electrically connected to the base layer and the emitter region is formed on the front surface side of the semiconductor substrate, and a collector electrode electrically connected to the collector layer is formed on the back surface side of the semiconductor substrate. ing.
  • the semiconductor device when a voltage lower than that of the collector electrode is applied to the emitter electrode and a voltage equal to or higher than the threshold voltage Vth of the insulated gate structure is applied to the first gate electrode, the semiconductor device changes from the off state to the on state. That is, in such a semiconductor device, when a voltage lower than the collector electrode is applied to the emitter electrode and a voltage equal to or higher than the threshold voltage Vth is applied to the first gate electrode, the base layer is in contact with the trench. An N-type inversion layer (ie, channel) is formed. In the semiconductor device, electrons are supplied from the emitter region to the drift layer through the inversion layer, and holes are supplied from the collector layer to the drift layer. It becomes. At this time, the holes supplied to the drift layer are suppressed from exiting from the emitter electrode via the base layer by the CS layer. Therefore, the on-voltage can be reduced.
  • N-type inversion layer ie, channel
  • the off state is a state in which no current flows between the collector electrode and the emitter electrode
  • the on state is a state in which a current flows between the collector electrode and the emitter electrode. It is.
  • the mirror period can be increased and the change rate of the collector potential (that is, dVce / dt) can be reduced as compared with the case where the first gate electrodes are not all disposed adjacent to each other. it can.
  • the gate potential of the adjacent first gate electrode is likely to fluctuate in an unstable manner when switching from the off-state to the on-state, and thus between the collector electrode and the emitter electrode. It has been confirmed that the current tends to fluctuate unstablely. That is, it has been confirmed that the switching controllability is lowered.
  • This disclosure is intended to provide a semiconductor device capable of suppressing a decrease in switching controllability.
  • a semiconductor device includes a drift layer of a first conductivity type, a CS layer of a first conductivity type that is disposed on the drift layer and has a higher impurity concentration than the drift layer, a drift layer, A semiconductor substrate having a second conductivity type base layer disposed on the layer and a second conductivity type collector layer formed on the opposite side of the base layer with the drift layer interposed therebetween, and penetrating the base layer A plurality of trench gate structures each including a gate insulating film formed on a wall surface of a trench extending in a predetermined direction in a plane direction of the semiconductor substrate, and a gate electrode formed on the gate insulating film; An emitter region of a first conductivity type that is selectively formed in the surface layer portion and forms part of one surface of the semiconductor substrate, is in contact with the trench; and a first electrode that is electrically connected to the base layer and the emitter region; Collect And it includes a second electrode connected to the layer and electrically, a.
  • the plurality of gate electrodes include a plurality of first gate electrodes to which a predetermined gate voltage is applied, and a second gate electrode that is electrically connected to the first electrode to have the same potential as the first electrode.
  • the plurality of first gate electrodes are arranged in a direction crossing a predetermined direction and at least partially adjacent to each other in a direction along the surface direction of the semiconductor substrate. At least a region between the adjacent first gate electrode and the second gate electrode is formed, and a predetermined gate voltage is applied to the first gate electrode in the region between the adjacent first gate electrodes.
  • the first gate electrode and the first gate electrode adjacent to each other in the region between The impurity concentration of the first conductivity type is made lower than the CS layer formed between the adjacent first gate electrode and the second gate electrode so that the region between the gate electrode and the first electrode can be easily removed. Has an area.
  • the region between the adjacent first gate electrodes is compared with the region where the first conductive type impurity concentration is made equal to the region between the adjacent first gate electrode and the second gate electrode.
  • the second carriers supplied to the drift layer from the region between the adjacent first gate electrodes easily escape to the first electrode. For this reason, even when the first gate electrodes are arranged adjacent to each other, it is possible to suppress the fluctuation of the gate potential of the first gate electrode, and it is possible to suppress the switching controllability from being lowered.
  • FIG. 2 is a cross-sectional view taken along line II-II in FIG. It is a schematic diagram which shows the state of the hole in the semiconductor device with which the impurity concentration of CS layer is made constant. It is a schematic diagram which shows the state of the hole in the semiconductor device shown in FIG. It is a figure which shows the relationship between the voltage between 1st gate electrode-emitter electrodes, and time. It is a figure which shows the relationship between the collector electrode-emitter electrode current, and time. It is sectional drawing of the semiconductor device in 2nd Embodiment. It is sectional drawing of the semiconductor device in 3rd Embodiment. It is sectional drawing of the semiconductor device in 4th Embodiment.
  • a first embodiment will be described. Note that the semiconductor device of this embodiment is preferably used as a power switching element used in a power supply circuit such as an inverter or a DC / DC converter.
  • the semiconductor device has an N ⁇ type semiconductor substrate 10 that functions as a drift layer 11.
  • a P-type base layer 12 and an N-type CS layer 13 having a higher impurity concentration than the drift layer 11 are formed on the drift layer 11 (that is, on the one surface 10a side of the semiconductor substrate 10).
  • the CS layer 13 is formed in the entire region between the drift layer 11 and the base layer 12. That is, the CS layer 13 and the base layer 12 are formed in order from the drift layer 11 side on the drift layer 11.
  • the semiconductor substrate 10 is formed with a plurality of trenches 14 a and 14 b that penetrate the base layer 12 and the CS layer 13 and reach the drift layer 11. Thereby, the base layer 12 and the CS layer 13 are divided by the plurality of trenches 14a and 14b.
  • the plurality of trenches 14 a and 14 b are formed in stripes at regular intervals along a predetermined direction of the surface direction of the one surface 10 a of the semiconductor substrate 10. In FIG. 1, the plurality of trenches 14 a and 14 b are respectively formed along the depth direction of the paper surface in FIG. 1.
  • the trenches 14a and 14b are buried with a gate insulating film 15 formed so as to cover the wall surfaces of the trenches 14a and 14b and gate electrodes 16a and 16b formed on the gate insulating film 15.
  • a trench gate structure is configured.
  • the gate insulating film 15 is made of an oxide film or the like
  • the gate electrodes 16a and 16b are made of polysilicon or the like.
  • the surface layer portion of the base layer 12 has an N ++ -type emitter region 17 having a higher impurity concentration than the drift layer 11 and a higher impurity concentration than the base layer 12.
  • a P + -type contact region 18 is formed.
  • the emitter regions 17 and the contact regions 18 are alternately formed along the extending direction of the trenches 14a and 14b, and are formed so as to be in contact with the side surfaces of the adjacent trenches 14a and 14b.
  • the one surface 10 a of the semiconductor substrate 10 is configured to include the emitter region 17 and the contact region 18.
  • an interlayer insulating film 19 made of BPSG (abbreviation of BoronBoPhosphorus Silicon Glass) or the like is formed on one surface 10a of the semiconductor substrate 10.
  • the interlayer insulating film 19 is formed with a first contact hole 19a that exposes the emitter region 17 and the contact region 18, and a second contact hole 19b that exposes the gate electrode 16b.
  • an emitter electrode 20 is electrically connected to the emitter region 17 and the contact region 18 through the first contact hole 19a, and is connected to the gate electrode 16b through the second contact hole 19b. Is formed. That is, the gate electrode 16b of this embodiment is set to the same potential as the emitter electrode 20, and exhibits a function as a so-called dummy gate electrode.
  • the gate electrode 16a is connected to a gate control circuit (not shown) so that a predetermined gate voltage is applied.
  • the emitter electrode 20 corresponds to the first electrode.
  • the gate electrode 16a connected to the gate control circuit of the gate electrodes 16a and 16b and applied with a predetermined gate voltage is referred to as a first gate electrode 16a.
  • the gate electrode 16b connected to the emitter electrode 20 is defined as a second gate electrode 16b.
  • a trench in which the first gate electrode 16a is disposed is referred to as a first trench 14a
  • a trench in which the second gate electrode 16b is disposed is referred to as a second trench 14b.
  • the 1st gate electrode 16a is arrange
  • the term “arranged so as to be adjacent to each other” means a direction orthogonal to the extending direction of the first and second trenches 14 a and 14 b, and is adjacent in the direction along the surface direction of the semiconductor substrate 10. It is meant to be arranged as follows. That is, in FIG. 1, it means that it arrange
  • An N-type field stop layer (hereinafter simply referred to as an FS layer) 21 is formed on the side of the drift layer 11 opposite to the base layer 12 side (that is, the other surface 10b side of the semiconductor substrate 10).
  • this FS layer 21 is not necessarily required, it is possible to improve the breakdown voltage and steady loss performance by preventing the depletion layer from spreading, and to increase the injection amount of holes injected from the other surface 10b side of the semiconductor substrate 10. Be prepared to control.
  • a P + -type collector layer 22 is formed on the opposite side of the drift layer 11 across the FS layer 21.
  • a collector electrode 23 electrically connected to the collector layer 22 is formed on the opposite side of the FS layer 21 with the collector layer 22 interposed therebetween. That is, the collector electrode 23 that is electrically connected to the collector layer 22 is formed on the other surface 10 b of the semiconductor substrate 10.
  • the collector electrode 23 corresponds to the second electrode.
  • the semiconductor substrate 10 of the present embodiment is configured to include the collector layer 22, the FS layer 21, the drift layer 11, the base layer 12, the CS layer 13, the emitter region 17, and the contact region 18. Yes.
  • the CS layer 13 is divided by a plurality of first and second trenches 14a and 14b, and is sandwiched between the first CS layer 31 sandwiched between the adjacent first gate electrodes 16a and the adjacent first gate electrode 16a.
  • a second CS layer 32 that is not connected.
  • the first CS layer 31 is N-type, and the impurity concentration is lower than that of the second CS layer 32 that is N + -type. That is, the region sandwiched between the adjacent first gate electrodes 16a has a lower impurity concentration than the second CS layer 32 in a region having a depth equal to the depth at which the second CS layer 32 is formed from the one surface 10a of the semiconductor substrate 10. It can be said that it has an area.
  • the impurity concentration of the second CS layer 32 is set so that the holes supplied to the drift layer 11 are difficult to escape directly to the base layer 12 via the second CS layer 32.
  • the impurity concentration of the first CS layer 31 is set so that the holes supplied to the drift layer 11 can be easily removed from the second CS layer 32 through the first CS layer 31.
  • the second CS layer 32 not sandwiched between the adjacent first gate electrodes 16a is a region of the CS layer 13 sandwiched between the adjacent first gate electrode 16a and the second gate electrode 16b, or the CS layer 13 This is a region sandwiched between the adjacent second gate electrodes 16b.
  • N ++ type, N + type, N type, and N ⁇ type correspond to the first conductivity type
  • P type and P + type correspond to the second conductivity type
  • the CS layer 13 having the first CS layer 31 and the second CS layer 32 of the present embodiment is formed by the following process. For example, after preparing the semiconductor substrate 10 constituting the drift layer 11, N-type impurities such as phosphorus are ion-implanted from the one surface 10 a side of the semiconductor substrate 10 so that the first CS layer 31 has a desired impurity concentration. Next, a mask patterned so that impurities are not implanted into a region to be the first CS layer 31 is disposed on the one surface 10 a of the semiconductor substrate 10. Then, N-type impurities are ion-implanted again into the region constituting the second CS layer 32 so that the second CS layer 32 has a desired impurity concentration.
  • a CS layer 13 having regions with different impurity concentrations is formed by diffusing impurities by performing heat treatment.
  • a well-known semiconductor manufacturing process is performed to form the base layer 12, the emitter region 17, the contact region 18 and the like.
  • the first and second trenches 14a and 14b and the first and second gate electrodes 16a and 16b are formed so that the region of the CS layer 13 where the impurity concentration is low is sandwiched between the adjacent first gate electrodes 16a.
  • a semiconductor device in which the impurity concentration of the first CS layer 31 is lower than the impurity concentration of the second CS layer 32 is manufactured.
  • the CS layer 13 having regions having different impurity concentrations may be formed by the following process. That is, after preparing the semiconductor substrate 10 that constitutes the drift layer 11, a mask patterned so as to prevent impurities from being implanted into the region to be the second CS layer 32 is disposed on one surface 10 a of the semiconductor substrate 10. Then, N-type impurities are ion-implanted into the region constituting the first CS layer 31 so that the first CS layer 31 has a desired impurity concentration. Next, a mask is arranged on one surface 10 a of the semiconductor substrate 10 so that impurities are not implanted into a region to be the first CS layer 31.
  • an N-type impurity is ion-implanted into a region constituting the second CS layer 32 so that the second CS layer 32 has a desired impurity concentration.
  • the CS layer 13 having regions with different impurity concentrations may be formed by performing heat treatment to diffuse the impurities.
  • the operation when the semiconductor device is turned from the off state to the on state will be described.
  • the operation of the semiconductor device of the present embodiment will be described in comparison with a semiconductor device in which the impurity concentration of the entire region of the CS layer 13 is equal to that of the second CS layer 32 of the present embodiment.
  • the fact that the impurity concentration of the entire region of the CS layer 13 is equal to that of the second CS layer 32 of the present embodiment is simply referred to as the impurity concentration of the CS layer 13 being made constant.
  • the emitter electrode 20 is grounded and a positive voltage is applied to the collector electrode 23.
  • a predetermined voltage is applied to the first gate electrode 16a from a gate control circuit (not shown) so that the gate potential is equal to or higher than the threshold voltage Vth of the insulated gate structure.
  • an N-type inversion layer that is, a channel
  • electrons are supplied from the emitter electrode 20 to the drift layer 11 through the emitter region 17 and the inversion layer.
  • holes are supplied from the collector electrode 23 to the drift layer 11 through the collector layer 22.
  • the resistance value of the drift layer 11 decreases due to conductivity modulation, and is turned on.
  • electrons correspond to first carriers and holes correspond to second carriers.
  • the CS layer 13 has a lower impurity concentration in the first CS layer 31 than in the second CS layer 32. That is, in the present embodiment, the potential barrier constituted by the first CS layer 31 is made smaller than the potential barrier constituted by the second CS layer 32. For this reason, as shown in FIG. 4, in the first CS layer 31, holes are easier to escape through the region than the second CS layer 32. Therefore, compared with the case where the impurity concentration of the CS layer 13 is constant, holes supplied to the drift layer 11 are less likely to be accumulated in the region between the adjacent first gate electrodes 16a.
  • the gate potential of the first gate electrode 16a is after the collector electrode-emitter electrode current Ice starts flowing, as shown by the dotted line in FIG. Even after the time T1, it rises sharply. That is, the voltage Vge between the first gate electrode and the emitter electrode rises sharply. For this reason, the collector electrode-emitter electrode current Ice is unstablely fluctuated before being stabilized at the time point T2, as indicated by a dotted line in FIG. Therefore, the semiconductor device and peripheral devices connected to the semiconductor device may be damaged or malfunction.
  • the gate potential of the first gate electrode 16a gradually increases after time T1. In other words, the gate potential of the first gate electrode 16a does not rise sharply. That is, the first gate electrode-emitter electrode voltage Vge does not rise sharply. Therefore, as indicated by the solid line in FIG. 6, the collector-emitter electrode current Ice is restrained from unstable fluctuation before stabilizing at the time T2. Therefore, it is possible to prevent the semiconductor device and peripheral devices connected to the semiconductor device from being destroyed or malfunctioning.
  • FIGS. 3 and 4 correspond to enlarged views of a portion where the adjacent first gate electrodes 16a in FIG. 1 are arranged.
  • the hole is indicated as h.
  • the gate potential of the first gate electrode 16a becomes sufficiently high, a stable current flows between the collector electrode 23 and the emitter electrode 20. For this reason, there is no problem even if the gate potential of the first gate electrode 16a rises due to holes.
  • the first CS layer 31 has a lower impurity concentration than the second CS layer 32. That is, the holes supplied to the drift layer 11 are more easily removed from the first CS layer 31 than from the second CS layer 32. For this reason, it is difficult for a large amount of holes to be accumulated in a region located between adjacent first gate electrodes 16a in the drift layer 11 and in the vicinity thereof. Therefore, when the semiconductor device is switched from the off state to the on state, the gate potential of the first gate electrode 16a is prevented from fluctuating due to holes even when the first gate electrodes 16a are arranged adjacent to each other. It is possible to suppress a decrease in switching controllability.
  • the first CS layer 31 has a first region 31 a located below the emitter region 17 and a second region 31 b located below the contact region 18. Yes. More specifically, the second region 31b is formed so as to pass through at least the center of the contact region 18 and intersect with a virtual line along the normal direction to the one surface 10a of the semiconductor substrate 10.
  • the first region 31 a has the same impurity concentration as the second CS layer 32, and the second region 31 b has a lower impurity concentration than the second CS layer 32.
  • the first CS layer 31 has a region in which the impurity concentration is lower than that of the second CS layer 32. 7 corresponds to a cross-sectional view taken along the line II-II in FIG.
  • the first region 31 a of the first CS layer 31 has the same impurity concentration as that of the second CS layer 32. For this reason, the holes supplied to the drift layer 11 are difficult to escape directly from the first region 31a. Therefore, the ON voltage can be further reduced.
  • the second region 31 b of the first CS layer 31 has a lower impurity concentration than the second CS layer 32. For this reason, the holes supplied to the drift layer 11 are easily removed directly from the second region 31b. Therefore, it can suppress that switching controllability falls.
  • holes that escape from the second region 31 b escape from the emitter electrode 20 through the P-type base layer 12 and the P-type contact region 18. For this reason, since the second region 31b is formed below the contact region 18, for example, compared with the case where the second region 31b is formed below the emitter region 17, until the emitter electrode 20 is reached. Can be shortened. Therefore, holes can be easily removed and switching controllability can be improved.
  • the second gate electrode 16b is arranged so that at least a part thereof is adjacent.
  • the interlayer insulating film 19 is not formed with the first contact hole 19a that exposes the portion of the emitter region 17 and the contact region 18 sandwiched between the adjacent second gate electrodes 16b. That is, the portion of the emitter region 17 and the contact region 18 sandwiched between the adjacent second gate electrodes 16 b is not electrically connected to the emitter electrode 20.
  • the emitter electrode 20 is electrically connected only to the emitter region 17 in contact with the first trench 14a and the contact region 18 (that is, the base layer 12) formed on the base layer 12 in contact with the first trench 14a. ing.
  • the hole supplied to the drift layer 11 has no path to the emitter electrode 20 from the region sandwiched between the adjacent second gate electrodes 16b. Therefore, a large amount of holes can be accumulated between the adjacent second gate electrodes 16b, and the on-voltage can be further reduced. Since the gate potential of the second gate electrode 16b does not contribute to the collector-emitter current Ice, there is no particular problem even if the gate potential of the second gate electrode 16b fluctuates.
  • the CS layer 13 is formed only in a region different from the region sandwiched between the adjacent first gate electrodes 16a. That is, the CS layer 13 is formed only in a region between the adjacent first gate electrode 16a and the second gate electrode 16b and a region between the adjacent second gate electrodes 16b. In other words, the CS layer 13 of the present embodiment is composed of only the second CS layer 32.
  • the base layer 12 is formed directly on the drift layer 11 in a region sandwiched between the adjacent first gate electrodes 16a.
  • the drift layer 11 is arranged in a region having a depth equal to the depth at which the CS layer 13 is formed from the one surface 10a of the semiconductor substrate 10 in a region sandwiched between the adjacent first gate electrodes 16a.
  • the impurity concentration in the region sandwiched between the adjacent first gate electrodes 16a is lowered. That is, the region sandwiched between the adjacent first gate electrodes 16a is a region having a depth equal to the depth at which the CS layer 13 is formed from one surface 10a of the semiconductor substrate 10, and the adjacent first gate electrode 16a and the second gate.
  • the N-type impurity concentration is lower than the region sandwiched between the electrodes 16b. For this reason, the holes supplied to the drift layer 11 easily escape from the drift layer 11 located between the adjacent first gate electrodes 16 a directly to the base layer 12. Therefore, it can suppress that switching controllability falls.
  • the first conductivity type is N type and the second conductivity type is P type.
  • the first conductivity type is P type
  • the second conductivity type is N type. You can also.
  • the CS layer 13 is formed so as to divide the base layer 12 into an upper region and a lower region within the base layer 12, not between the drift layer 11 and the base layer 12. May be. That is, the lower region of the base layer 12, the CS layer 13, and the upper region of the base layer 12 may be arranged on the drift layer 11 in order.
  • the emitter region 17 has the first and second trenches in contact with the side surfaces of the first and second trenches 14a and 14b in the region between the first and second trenches 14a and 14b. You may be extended in the rod shape along the extending direction of 14a, 14b.
  • the contact region 18 extends in a rod shape in the extending direction of the first and second trenches 14a and 14b in a state sandwiched between the two emitter regions 17 in the region between the first and second trenches 14a and 14b. It may be provided.
  • the emitter electrode 20 is electrically connected only to the emitter region 17 in contact with the first trench 14 a and the contact region 18 adjacent to the emitter region 17.
  • the contact region 18 does not need to be formed. That is, the one surface 10 a of the semiconductor substrate 10 may be configured by the base layer 12 and the emitter region 17.
  • the second CS layer 32 adjacent to the first CS layer 31 may have the same impurity concentration as that of the first CS layer 31 in the region on the first CS layer 31 side. That is, the CS layer 13 having regions with different impurity concentrations is formed as described above, but the first CS layer of the second CS layer 32 is taken into consideration in consideration of the positional deviation of the first and second trenches 14a and 14b. The impurity concentration on the 31st side may be lowered. Similarly, in the second embodiment, the second CS layer 32 adjacent to the second region 31b may have the same impurity concentration as that of the second CS layer 32 on the second region 31b side.
  • the first CS layer 31 and the second CS layer 32 may have different depths from the one surface 10a of the semiconductor substrate 10. That is, the first CS layer 31 may be deeper than the second CS layer 32, or the second CS layer 32 may be deeper than the first CS layer 31.
  • Such a configuration is configured by changing an acceleration voltage at the time of ion implantation of an N-type impurity.
  • the CS layer 13 has the entire region below the contact region 18 as the second region 31b.
  • the arrangement location of the second region 31b is not limited to this, and for example, the lower part of the contact region 18 may be the first region 31a.
  • the second region 31 b may be formed so as to include the lower part of the emitter region 17, or may be formed only under the emitter region 17. Even in such a semiconductor device, it is possible to suppress a decrease in switching controllability compared to a semiconductor device that does not have the second region 31b.

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Abstract

L'invention concerne une pluralité de structures de grille en tranchée ayant des électrodes grilles (16a, 16b) formées dans un substrat semiconducteur (10) ayant une couche de dérive (11), une couche de base (12), une couche CS (13) et une couche de collecteur (22), et les électrodes grilles (16a, 16b) ayant des premières électrodes grilles (16a), auxquelles une tension de grille prédéterminée est appliquée, et des secondes électrodes grilles (16b) étant électriquement connectées à une première électrode (20). En outre, les premières électrodes grilles (16a) sont disposées de telle sorte qu'au moins des parties des premières électrodes grilles respectives sont adjacentes l'une à l'autre, et la couche CS (13) est disposée au moins entre les première et seconde électrodes grilles adjacentes (16a, 16b). Une région entre les premières électrodes grilles adjacentes (16a) a une région dans laquelle une concentration d'impuretés de premier type de conductivité est réglée de façon à être inférieure à celle de la couche CS (13) formée entre les première et seconde électrodes grilles adjacentes (16a, 16b) de telle sorte qu'un second support fourni à partir d'une seconde électrode (23) puisse facilement passer lorsqu'un courant circule.
PCT/JP2018/010274 2017-04-27 2018-03-15 Dispositif semiconducteur WO2018198575A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111326510A (zh) * 2018-12-17 2020-06-23 三菱电机株式会社 半导体装置
CN111341772A (zh) * 2018-12-19 2020-06-26 富士电机株式会社 半导体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016184712A (ja) * 2015-03-27 2016-10-20 株式会社日立製作所 半導体装置及びそれを用いた電力変換装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005184712A (ja) * 2003-12-24 2005-07-07 Alps Electric Co Ltd Ｓａｗディバイス、及びその製造方法
JP4575713B2 (ja) * 2004-05-31 2010-11-04 三菱電機株式会社 絶縁ゲート型半導体装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016184712A (ja) * 2015-03-27 2016-10-20 株式会社日立製作所 半導体装置及びそれを用いた電力変換装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111326510A (zh) * 2018-12-17 2020-06-23 三菱电机株式会社 半导体装置
CN111326510B (zh) * 2018-12-17 2023-08-25 三菱电机株式会社 半导体装置
CN111341772A (zh) * 2018-12-19 2020-06-26 富士电机株式会社 半导体装置

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