WO2018192322A1 - 微型发光二极管器件及其制作方法 - Google Patents

微型发光二极管器件及其制作方法 Download PDF

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Publication number
WO2018192322A1
WO2018192322A1 PCT/CN2018/078704 CN2018078704W WO2018192322A1 WO 2018192322 A1 WO2018192322 A1 WO 2018192322A1 CN 2018078704 W CN2018078704 W CN 2018078704W WO 2018192322 A1 WO2018192322 A1 WO 2018192322A1
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Prior art keywords
layer
micro
emitting diode
light emitting
micro device
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PCT/CN2018/078704
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English (en)
French (fr)
Inventor
盛翠翠
王笃祥
钟秉宪
吴俊毅
吴超瑜
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厦门三安光电有限公司
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Application filed by 厦门三安光电有限公司 filed Critical 厦门三安光电有限公司
Priority to KR1020197022579A priority Critical patent/KR102239715B1/ko
Publication of WO2018192322A1 publication Critical patent/WO2018192322A1/zh
Priority to US16/579,736 priority patent/US11791446B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present invention relates to a miniature light emitting diode device and a method of fabricating the same.
  • Micro-element technology refers to an array of minute-sized components that are integrated at a high density on a substrate.
  • Some examples of micro devices include microelectromechanical systems (MEMS) micro-switches, LED display systems, and MEMS- or quartz-based oscillators.
  • MEMS microelectromechanical systems
  • High-quality micro-pitch LED products can have a profound impact on traditional display products such as LCD/OLED that are already on the market.
  • Cipheral Patent Document CN105359283 discloses a miniature light emitting diode device having a pillar which is provided with a stabilizing column under the micro device as a support of the micro light emitting diode device, but the adhesion of the stabilizing column to the conductive contact of the device. Not very good, any mechanical movement or other external factors may cause loss of adhesion to the stabilizing column in the micro device before the chip is fabricated.
  • the present invention discloses a junction and method for forming an array of micro devices ready for picking.
  • the technical solution of the present invention is: a miniature light emitting diode device, comprising: a micro device unit array having gaps between adjacent micro device units; a connection layer, a gap between the micro device units, at least one A micro device unit is connected; a pinned layer, located below the array of micro device cells, in contact only with a lower surface of the connection layer and forming a cavity below the micro device unit.
  • connection layer is connected to the lower surface of the at least one micro device unit and extends to the gap to form a connection region, and the fixed layer is only in contact with the connection region.
  • connection layer is formed by extending a material layer constituting the micro device unit toward the gap, and forms a connection region in the gap, and the fixed layer is only in contact with the connection region.
  • the length of the connection layer extending to the gap is 1/ of the distance between adjacent micro device units.
  • the connecting layer is composed of a series of series of discrete patterns, each of which is in the form of a strip or a block.
  • connection layer connects at least two micro device units.
  • the micro device unit is a light emitting diode unit
  • the connection layer is an AlGalnP-based material layer or a GaN-based material layer.
  • the micro device unit is an AlGalnP-based light emitting diode, which comprises a window layer, wherein the connecting layer is formed by extending the window layer to the gap and thinning to a certain thickness.
  • connection layer has a thickness of 10 to 500 nm.
  • a contact area of the fixing layer and the connecting layer is smaller than a projected area of the connecting layer in the gap.
  • the size of the cavity below the micro device unit is larger than the size of the micro device.
  • the micro device unit is facing a cavity below it and has a size larger than the size of the cavity.
  • a portion of the mesa region retains a thickness of the epitaxial layer in contact with the fixed layer portion, and the supporting micro device is in a state to be picked up.
  • the area of the mesa region of the remaining epitaxial layer is larger than the contact area of the lower layer and the fixed layer.
  • the remaining epitaxial layer may be, for example, a GaP layer or a GaN layer, which has good adhesion to the fixed layer.
  • connection layer is formed on the bottom surface of the micro device unit of the device, the connection layer extending toward the gap between the micro device units to form a connection region and contacting the fixed layer in the connection region.
  • the foregoing micro light emitting diode device array can be obtained by the following method, comprising the steps of: (1) providing a semiconductor epitaxial structure having opposite upper and lower surfaces; (2) defining a surface on the surface of the semiconductor epitaxial structure a series of micro device unit regions, a dicing channel region and a connection region, wherein the connection region is located in the scribe line region; (3) forming a series of sacrificial layer units in the micro device unit region on the lower surface of the epitaxial structure; Forming a fixed layer on the sacrificial layer and extending toward the scribe line region to contact the scribe line region of the lower surface of the semiconductor epitaxial structure; (5) removing the epitaxial structure of the scribe line region to form a gap in the scribe line region And retaining a certain thickness as a connection layer in the connection region; (6) removing the sacrificial layer, the germanium epitaxial structure forming a cavity under each micro device unit region, and only the connection layer is in contact with
  • the sacrificial layer unit completely covers the micro device unit region and partially covers the scribe line region.
  • step (5) two mesa etching is performed, the first mesa is etched to the sacrificial layer and the surface of the sacrificial layer is exposed to form a dicing street, and the second mesa is etched to the bottom layer of the epitaxial structure, and Maintain a certain thickness as a connecting layer.
  • the present invention is directed to a small-sized micro-semiconductor unit in which a connection layer is formed in a gap therebetween for contact with a fixed layer, which can greatly increase the contact area of the bonding point, and ensure that the micro device is not externally affected before being picked up. The impact leads to loss of yield.
  • 1 to 20 are schematic views of processes for fabricating a miniature light emitting diode device in accordance with an embodiment of the present invention.
  • 21 is a schematic cross-sectional view of a miniature light emitting diode in accordance with an embodiment of the present invention.
  • FIG. 22 is a top plan view of the micro light emitting diode shown in FIG. 21.
  • FIG. 23 is a cross-sectional view of another miniature light emitting diode in accordance with an embodiment of the present invention.
  • 24 to 26 are several top views of the micro light emitting diode shown in FIG. 23.
  • FIG. 27 is a cross-sectional view showing still another micro light emitting diode according to an embodiment of the present invention.
  • micro device arrays such as miniature light emitting diode (LED) devices on a carrier substrate, such that they are to be picked up and transferred to a receiving substrate.
  • the pinned layer Formed of an adhesive material that maintains the array of micro devices in place on the carrier substrate, while also providing a structure from which the array of micro devices can be easily picked up.
  • the adhesive material includes a thermoset material such as, but not limited to, benzo. Cyclobutene (BCB) or epoxy resin.
  • micro light emitting diode device of the present invention will be described in detail below in conjunction with a fabrication method and a schematic diagram.
  • an epitaxial structure 100 which may generally include a growth substrate 101 and an epitaxial stack thereon, including an N-type semiconductor layer 111, a light-emitting layer 112, and a P-type semiconductor. Layer 113 and window layer 114.
  • red light emitting LED devices examples include green (eg, 495 nm to 570 nm wavelength) LED devices or blue light (eg, 450nm-495nm wavelength) formation of an LED device composed of materials such as indium gallium nitride (InGaN), gallium nitride (GaN), gallium phosphide (GaP), aluminum gallium indium phosphide (AlGa InP) Formed with aluminum gallium phosphide (AlGaP) formed of materials such as gallium nitride (GaN), indium gallium nitride (InGaN), and zinc selenide (ZnSe).
  • an etch stop layer may be formed between the growth substrate and the N-type semiconductor layer 111 to facilitate subsequent removal of the growth substrate 101.
  • the growth substrate 101 may be formed of GaAs
  • the etch stop layer may be formed of InGaP
  • the material of the N-type semiconductor layer 111 may be aluminum gallium arsenide Al x Ga ⁇ x As, x>0.4 or Aluminum gallium indium phosphide (Al x Ga lx ) y In ly P, x>0.4
  • the material of the light-emitting layer 112 may be aluminum gallium indium phosphide ((Al x Ga ⁇ J y In ⁇ y P, x ⁇ 0.5)
  • the material of the P-type semiconductor layer 113 may be aluminum gallium arsenide (Al x G ai — x As, x>0.4) or aluminum gallium indium phosphide (Al x G ai —J y I ni — y P, x>0.4
  • the material of the window layer 114 may be, for example, gallium phosphide
  • the micro device unit region A and the dicing street region B are defined on the surface 100a of the epitaxial structure, and the epitaxial structure 100 is divided into a series of micro cell arrays A by the dicing street region B.
  • the first electrode array 115 can be formed over the micro device cell region on the surface of the epitaxial structure 100, as shown in FIG.
  • the material of the first electrode array IJ 115 may be, for example, A U /AuZn/A U .
  • the first electrode array can be fused to form an ohmic contact with the epitaxial structure.
  • a sacrificial layer 120 is formed on the surface of the first electrode array 115.
  • the thickness of the sacrificial layer 120 is between 0.1 and 5 micrometers, and the material may be oxide, nitride or selectively opposite. Other materials that are removed from other layers, such as a Ti layer having a thickness of 2 to 4 microns, may be used as the sacrificial layer 120.
  • the sacrificial layer 120 is distributed in stripes, as shown in FIG. 5, each strip sacrificial layer unit covers the same column of micro device unit regions (eg, column A i), in adjacent columns A space 121 is reserved in the middle of the micro device unit for subsequent filling of the adhesive material as a fixed layer.
  • each strip sacrificial layer unit completely covers the micro device unit region A and extends a certain distance to the dicing street region B such that the area of the reserved space 121 is smaller than the area of the corresponding scribe line B.
  • the sacrificial layer 120 may overlap adjacent two columns of micro device units (eg, A i +1 column and A i+ ij) and extend to the scribe line regions B on both sides. At a distance, a space 121 is reserved in the middle of the adjacent two columns of micro device units for subsequent filling of the adhesive material as a fixed layer, as shown in Figures 6 and 7; in some embodiments, the sacrificial layer 120 It can also be connected in a single piece, leaving space 121 only in the middle of two or four adjacent micro device units for subsequent filling of the fixed layer, as shown in Figures 8 and 9.
  • a fixed layer 130 is formed on the surface of the sacrificial layer 120, which fills the reserved space 121 to form a support portion 131 and covers the upper surface of the sacrificial layer 120 for the epitaxial structure.
  • 100 is bonded to the carrier substrate 140 (eg, a glass substrate, sapphire or other substrate having a flat surface).
  • the material of the pinned layer 130 may be a thermosetting adhesive material such as, but not limited to, benzocyclobutene (BCB) or epoxy resin, which is cured by heating to form a support in a reserved space.
  • the pinned layer 130 can be cured by heat or by application of UV energy.
  • the pinned layer 130 is formed on the surface of the epitaxial structure.
  • the pinned layer 130 may also be formed on the surface of the carrier substrate 140 first.
  • BCB may be applied as a fixed layer on the surface of the epitaxial structure and the surface of the carrier substrate 140, soft baked, hard baked, and then bonded.
  • AP3000 may be formed as an adhesion promoter on the surface of the epitaxial structure and/or on the surface of the carrier substrate 140, and then BCB may be applied.
  • the growth substrate 101 is removed to expose the surface of the N-type semiconductor layer 111 of the epitaxial structure. Passable There are a number of ways to achieve the removal, including laser lift-off (LLO), grinding or etching, depending on the material selection of the growth substrate 101, in the particular embodiment shown, the growth substrate 101 is formed of GaAs. In this case, the removal can be achieved by a combination of etching or grinding and selective etching along with selective etch stop on the etch stop layer.
  • LLO laser lift-off
  • etching depending on the material selection of the growth substrate 101, in the particular embodiment shown, the growth substrate 101 is formed of GaAs.
  • the removal can be achieved by a combination of etching or grinding and selective etching along with selective etch stop on the etch stop layer.
  • a second electrode array 150 is formed on the surface of the N-type semiconductor 111, which corresponds to the first electrode array 115.
  • Two mesas are formed in this step, both located in the scribe line B shown in FIG. 2, wherein the first mesa serves as the walkway region C between the micro device units; and the second mesa serves as the connection region between the micro device units.
  • D corresponding to the position corresponding to the support portion 131, may be set with reference to the pattern of the reserved space 121 shown in FIGS. 7-9, but the area of the connection area D is larger than the area of the reserved space 121, that is, larger than the area of the support portion 131.
  • the first mesa is etched, as shown in FIGS. 14-18, etched to the sacrificial layer 120, and the surface 120a of the sacrificial layer is exposed to form the scribe line 200.
  • 14 is a plan view after etching the first mesa, which corresponds to the pattern shown in FIG. 5
  • FIG. 15 is a cross-sectional view taken along line CC of FIG. 14, and
  • FIG. 16 corresponds to the pattern shown in FIG. 17 corresponds to the diagram shown in FIG. 8, and
  • FIG. 18 corresponds to the pattern shown in FIG.
  • the second mesa is etched, as shown in FIGS. 19 and 20, which is etched to the bottom layer of the epitaxial structure 100 and held to a certain thickness as the connection layer 114a.
  • 19 is a plan view after etching the second mesa, which corresponds to the pattern shown in FIG. 5, and
  • FIG. 15 is a cross-sectional view taken along line d-d in FIG.
  • the second mesa is etched to the window layer 114, and the thickness of the window layer 114 is 50 to 500 nm as the connection layer 114a.
  • the epitaxial structure 100 forms a laterally bifurcated micro device unit and remains connected in the connection region D.
  • the sacrificial layer 120 is removed to form a cavity 170 under the micro device cells.
  • 21 to FIG. 25 illustrate formation of a connection layer 114a and a lower fixed layer portion region formed between the aisles (ie, a gap between adjacent micro device units) after removal of the sacrificial layer, in accordance with an embodiment of the present invention.
  • the micro device cell array is shown in Figures 21-26.
  • the micro device unit passes through a portion of the epitaxial material layer 114a (eg, gallium phosphide, gallium nitride, etc.) and a fixed layer 130 (eg, benzocyclobutene) remaining in a partial mesa region. Partial contact The micro device is in a state to be picked up.
  • the epitaxial material layer 114a eg, gallium phosphide, gallium nitride, etc.
  • a fixed layer 130 eg, benzocyclobutene
  • the area W1 of the micro device unit is larger than the area W2 of the cavity below it.
  • the mesa area W3 of the residual epitaxial material layer 114a is larger than the area of the support portion 131 in direct contact with it.
  • the micro light-emitting diode devices are all of a vertical type, which form an electrode structure on the upper and lower surfaces of the epitaxial structure, and the present invention is not limited to this structure.
  • the invention is also applicable to horizontally structured micro-semiconductor devices (i.e., the p and n electrodes are on the same side) as shown in FIG.
  • connection region is formed by using the gap between the micro devices, and the contact portion is in contact with the support portion of the fixed layer, and the micro-light-emitting diode device can reach the contact between the large-area fixed layer and the connection layer.
  • a fixed layer such as benzocyclobutene
  • epitaxial material layer such as GaP layer, GaN
  • the arrangement of the aisle area C and the connection area D is not limited to those shown in Figs. 14 to 18. In other embodiments, the arrangement of the aisle area C and the connection area D may be set as a reverse adjustment, or other design.

Abstract

本发明公开了一种微型发光二极管器件及其制作方法，该微型发光二极管器件包括：微器件单元阵列，相邻的微器件单元之间具有间隙；连接层，位于所述微器件单元之间的间隙，至少与一个微器件单元连接；固定层，位于所述微器件单元阵列的下方，仅与所述连接层的下表面接触，并在所述微器件单元的下方形成空腔。本发明针对小尺寸的微半导体单元，在其间的间隙形成连接层，用于与固定层接触，可大大增加粘接点的接触面积，保证微型器件在拾取之前不会因外界因素的影响导致良率损失。

Description

说明书 发明名称:微型发光二极管器件及其制作方法 技术领域
[0001] 本发明涉及一种微型发光二极管器件及其制作方法。
背景技术
[0002] 微元件技术是指在衬底上以高密度集成的微小尺寸的元件阵列。 微型器件的一 些实例包括微机电系统 (MEMS)微动幵关、 发光二极管显示系统和基于 MEMS或 者石英的振荡器。 目前， 微间距发光二极管 （Micro LED) 技术逐渐成为研究热 门， 工业界期待有高品质的微元件产品进入市场。 高品质微间距发光二极管产 品会对市场上已有的诸如 LCD/OLED的传统显示产品产生深刻影响。
[0003] 中国专利文献 CN105359283公幵了一种具有柱的微型发光二极管器件， 其以在 微器件的下方设置稳定柱作为微型发光二极管器件的支撑， 但稳定柱与器件导 电触点的粘附性并不是很好， 芯片制作后到被拾取前， 任意的机械运动或其他 外界因素或可能导致在微型器件失去对稳定柱的粘附。
技术问题
问题的解决方案
技术解决方案
[0004] 本发明公幵了一种形成准备好进行拾取的微型器件阵列的结和方法。
[0005] 本发明的技术方案为： 微型发光二极管器件， 包括： 微器件单元阵列， 相邻的 微器件单元之间具有间隙； 连接层， 位于所述微器件单元之间的间隙， 至少与 一个微器件单元连接； 固定层， 位于所述微器件单元阵列的下方， 仅与所述连 接层的下表面接触， 并在所述微器件单元的下方形成空腔。
[0006] 优选地， 所述连接层与至少一个微器件单元的下表面连接， 并向间隙延伸形成 连接区， 所述固定层仅与连接区接触。
[0007] 优选地， 所述连接层由构成所述微器件单元的材料层向所述间隙延伸而成， 并 在间隙内形成连接区， 所述固定层仅与所述连接区接触。 [0008] 优选地， 所述连接层向所述间隙延伸的长度为相邻的微器件单元之间距离的 1/
2以上。
[0009] 优选地， 所述连接层为一系列系列离散的图案构成， 每个图案呈条状或块状。
[0010] 优选地， 所述连接层至少同吋连接两个微器件单元。
[0011] 优选地， 所述微器件单元为发光二极管单元， 所述连接层为 AlGalnP系材料层 或 GaN基材料层。
[0012] 优选地， 所述微器件单元为 AlGalnP系发光二极管， 其包括窗口层， 所述连接 层为窗口层向间隙延伸并减薄至一定厚度而成。
[0013] 优选地， 所述连接层的厚度为 10~500nm。
[0014] 优选地， 所述固定层与所述连接层的接触面积小于所述连接层位于所述间隙内 的投影面积。
[0015] 优选地， 所述微器件单元下方的空腔尺寸大于该微器件的尺寸。
[0016] 优选地， 所述微器件单元正对其下方的空腔， 且尺寸大于所述空腔的尺寸。
[0017] 在一些实施例中， 该器件在由外延片制成芯片的过程中， 部分台面区域保留一 定厚度的外延层与固定层部分接触， 支撑微型器件处于待拾取状态。 较佳的， 保留的外延层的台面区域面积较下方与固定层的接触面积大。 保留的外延层可 为诸如 GaP层或 GaN层之类， 其与固定层的接触粘附性较好。
[0018] 在一些实施例中， 该器件的微器件单元的底面上形成一连接层， 该连接层向微 器件单元之间的间隙延伸， 形成连接区， 并在连接区与固定层接触。
[0019] 前述微型发光二极管器件阵列可通过下面方法制备获得， 包括步骤： （1) 提 供半导体外延结构， 具有相对的上表面和下表面； （2) 在所述半导体外延结构 的表面上定义一系列微器件单元区、 切割道区和连接区， 其中连接区位于切割 道区内； （3) 在所述外延结构下表面的微器件单元区对应形成一系列牺牲层单 元； （4) 在所述牺牲层上形成固定层， 并向切割道区延伸， 与所述半导体外延 结构下表面的切割道区接触； （5) 去除所述切割道区的外延结构从而在所述切 割道区形成间隙， 并在连接区保留一定厚度作为连接层； （6) 去除所述牺牲层 ， 此吋外延结构在各个微器件单元区的下方形成空腔， 仅连接层与所述固定层 接触。 [0020] 优选地， 所述步骤 （3) 中， 所述牺牲层单元的面积大于所述微器件单元区的 面积。
[0021] 优选地， 所述步骤 （3) 中， 所述牺牲层单元完全覆盖所述微器件单元区， 并 部分覆盖所述切割道区。
[0022] 优选地， 所述步骤 （5) 中进行两次台面蚀刻， 第一次台面蚀刻至牺牲层并裸 露出牺牲层的表面形成切割道， 第二次台面蚀刻至外延结构的底层， 并保持一 定的厚度作为连接层。
发明的有益效果
有益效果
[0023] 本发明针对小尺寸的微半导体单元， 在其间的间隙形成连接层， 用于与固定层 接触， 可大大增加粘接点的接触面积， 保证微型器件在拾取之前不会因外界因 素的影响导致良率损失。
[0024] 本发明的其它特征和优点将在随后的说明书中阐述， 并且， 部分地从说明书中 变得显而易见， 或者通过实施本发明而了解。 本发明的目的和其他优点可通过 在说明书、 权利要求书以及附图中所特别指出的结构来实现和获得。
对附图的简要说明
附图说明
[0025] 附图用来提供对本发明的进一步理解， 并且构成说明书的一部分， 与本发明的 实施例一起用于解释本发明， 并不构成对本发明的限制。 此外， 附图数据是描 述概要， 不是按比例绘制。
[0026] 图 1~ 20为根据本发明实施的制作微型发光二极管器件的过程示意图。
[0027] 图 21为根据本发明实施的一种微型发光二极管的剖面示意图。
[0028] 图 22为图 21所示微型发光二极管的顶面图示。
[0029] 图 23为根据本发明实施的另一种微型发光二极管的剖面示意图。
[0030] 图 24~26为图 23所示微型发光二极管的几种顶面图示。
[0031] 图 27为根据本发明实施的再一种微型发光二极管的剖面示意图。 本发明的实施方式
[0032] 下面各个实施例公幵了用于固定微型器件阵列 （诸如承载基板上的微型发光二 极管 (LED)器件以使其待拾取和转移到接收基板的结构。 在一个实施例中， 固定 层由粘合性材料形成， 可使微型器件阵列保持在承载基板上的适当位置， 同吋 也提供易于从中拾取微型器件阵列的结构。 所述粘合性材料包括热固性材料， 诸如但不限于苯并环丁烯 (BCB)或环氧树脂。
[0033] 下面结合制作方法和示意图对本发明的微型发光二极管器件进行详细的描述。
[0034] (一） 提供外延结构 100如图 1所示， 提供外延结构 100， 其一般可包括生长衬 底 101和其上外延叠层， 包括 N型半导体层 111、 发光层 112、 P型半导体层 113和 窗口层 114。 在下面描述中所示和所述的具体实施例参考了红光发射 LED器件的 形成， 但以下序列和描述也适用于其他 LED器件诸如绿光 (例如 495nm-570nm波 长） LED器件或蓝光 (例如 450nm-495nm波长） LED器件的形成， 所述绿光 LED器 件由材料诸如氮化铟镓 (InGaN)、 氮化镓 (GaN)、 磷化镓 (GaP)、 磷化铝镓铟 (AlGa InP)和磷化铝镓 (AlGaP)形成， 所述蓝光 LED器件由材料诸如氮化镓 (GaN)、 氮化 铟镓 (InGaN)和硒化锌 (ZnSe)形成。 可选的， 蚀刻停止层可形成于生长衬底与 N型 半导体层 111之间以有助于生长衬底 101的后续移除。
[0035] 在一个较佳实施例中， 生长衬底 101可由 GaAs形成， 蚀刻停止层可由 InGaP形 成， N型半导体层 111的材料可为砷化铝镓 Al xGa ^ xAs， x>0.4或磷化铝镓铟（Al x Ga l x) yIn l yP, x>0.4; 发光层 112的材料例可为磷化铝镓铟 （(Al xGa ^ J yIn ^ y P， x<0.5) ； P型半导体层 113的材料可为砷化铝镓 (Al xGa i— xAs， x>0.4)或磷化 铝镓铟（Al xGa i—J yIn i—yP， x>0.4, 窗口层 114的材料例如可为磷化镓、 磷化镓砷 、 砷化铝镓或磷化铝镓铟， 其厚度为 1~10微米。
[0036] (二） 定义微器件单元
[0037] 如图 2所示， 在外延结构的表面 100a上定义微器件单元区 A和切割道区 B， 通过 切割道区 B将外延结构 100划分为一系列微单元阵列 A。
[0038] 在一个较佳实施例中， 可在外延结构 100表面的微器件单元区内上形成第一电 极阵列 115， 如图 3所示。 该第一电极阵歹 IJ 115的材料可以例如 AU/AuZn/AU。 在本 步骤中可对第一电极阵列进行熔合， 使其与外延结构形成欧姆接触。 [0039] (三） 制作牺牲层 120
[0040] 如图 4所示， 在第一电极阵列 115的表面上形成牺牲层 120， 牺牲层 120的厚度为 0.1~5微米之间， 材料可为氧化物、 氮化物或者可选择性地相对于其他层被移除 的其他材料， 例如可选用厚度为 2~4微米的 Ti层作为牺牲层 120。 在一些实施例中 ， 该牺牲层 120呈条状分布， 如图 5所示， 每个条状牺牲层单元覆盖同一列的微 器件单元区 （例如第 A i列） ， 在相邻的两列微器件单元的中间预留一空间 121， 用于后续填充粘合性材料作为固定层。 较佳的， 每个条状牺牲层单元完全覆盖 微器件单元区 A并向切割道区 B延伸一定距离， 使得该预留空间 121的面积小于对 应的切割道 B的面积。
[0041] 在一些实施例中， 该牺牲层 120可同吋覆盖相邻的两列微器件单元 （例如第 A i+1列和第 A i+ ij) ， 并向两侧的切割道区 B延伸一定距离， 在相邻的两列微器件 单元的中间预留一空间 121， 用于后续填充粘合性材料作为固定层， 如图 6和 7所 示； 在一些实施例中， 该牺牲层 120也可连成一片， 仅在相邻的两个或四个微器 件单元的中间预留空间 121， 用于后续填充固定层， 如图 8和 9所示。
[0042] (四） 制作固定层 130
[0043] 如图 10和图 11所示， 在牺牲层 120的表面上形成固定层 130， 其填充了预留空间 121形成支撑部 131， 并覆盖牺牲层 120的上表面， 用于将外延结构 100键合到承 载衬底 140上 （例如玻璃基板、 蓝宝石或其他具有平面的基板） 。 固定层 130的 材料可为热固型粘合性材料， 例如但不限于苯并环丁烯 (BCB)或环氧树脂， 通过 加热固化， 从而在预留空间形成支撑部。 根据所选择的具体材料， 固定层 130可 被热固化或者利用施加 UV能量来固化。
[0044] 在图 10所示的实施例中， 固定层 130形成于外延结构的表面上。 作为另一种实 施例， 固定层 130也可先形成在承载衬底 140的表面上。 作为再一种实施例， 可 同吋在外延结构的表面上和承载衬底 140的表面上涂布 BCB作为固定层， 进行软 烤、 硬烤， 然后键合。 作为再一种实施例， 可先于外延结构的表面上和 /或承载 衬底 140的表面上形成 AP3000作为粘合增进剂， 再涂布 BCB。
[0045] (五） 去除生长衬底 101
[0046] 如图 12所示， 去除生长衬底 101， 露出外延结构的 N型半导体层 111表面。 可通 过多种方法来实现移除， 包括激光剥离 (LLO)、 磨削或者蚀刻， 具体取决于生长 衬底 101的材料选择， 在所示的具体实施例中， 在生长衬底 101由 GaAs形成的情 况下， 可通过蚀刻或磨削及选择性蚀刻的组合连同蚀刻停止层上的选择性蚀刻 停止来实现移除。
[0047] 较佳的， 如图 13所示， 在 N型半导体 111的表面上制作第二电极阵列 150， 其与 第一电极阵列 115对应。
[0048] (六） 台面蚀刻
[0049] 本步骤中形成两个台面， 均位于图 2所示的切割道 B内， 其中第一台面作为微器 件单元之间的走道区域 C; 第二台面作为微器件单元之间的连接区 D， 对应于支 撑部 131对应的位置， 可参考图 7-9所示的预留空间 121的图案进行设置， 但连接 区 D面积大于预留空间 121的面积， 即大于支撑部 131的面积。
[0050] 蚀刻第一台面， 如图 14-18所示， 蚀刻至牺牲层 120， 裸露出牺牲层的表面 120a 形成切割道 200。 其中图 14为蚀刻完第一个台面后的俯视图， 其对应于图 5所示 的图案， 图 15为沿图 14中的线 C-C剖幵的截面图， 图 16对应于图 7所示的图案， 图 17对应于图 8所示的图， 图 18对应于图 9所示的图案。
[0051] 蚀刻第二台面， 如图 19和 20所示， 其蚀刻至外延结构 100的底层， 并保持一定 的厚度作为连接层 114a。 其中图 19为蚀刻完第二个台面后的俯视图， 其对应于图 5所示的图案， 图 15为沿图 19中的线 d-d剖幵的截面图。 在一个较佳实施例中， 第 二台面蚀刻至窗口层 114， 保留窗口层 114的厚度 50~500nm作为连接层 114a。
[0052] 通过台面蚀刻， 外延结构 100形成了侧向分幵的微器件单元， 并在连接区 D保持 连接。
[0053] (六） 去除牺牲层
[0054] 在形成侧向分幵的微器件单元之后， 移除牺牲层 120从而在微器件单元的下方 形成空腔 170。 图 21-图 25示出了根据本发明的实施例在移除牺牲层之后形成通 过走道间 （即为相邻微器件单元之间的间隙） 的连接层 114a与下方的固定层部分 区域支撑的微器件单元阵列， 如图 21~26所示。
[0055] 在图 21所示的具体实施例中， 微器件单元通过部分台面区域残留的外延材料层 114a (例如磷化镓、 氮化镓等） 与固定层 130 (例如苯并环丁烯） 部分接触， 支 撑微型器件处于待拾取状态。
[0056] 较佳的， 微器件单元的面积 W1大于其下方的空腔的面积 W2。 进一步的， 残留 的外延材料层 114a的台面区域面积 W3大于与其直接接触的支撑部 131的面积 W4
[0057] 在上述各图示所示的实施例中， 微型发光二极管器件均为垂直型， 其在外延结 构的上、 下表面形成电极结构， 本发明并不局限于此结构。 在一些实施例， 本 发明也可应用于水平结构的微半导体器件 （即 p、 n电极位于同侧） ， 如图 27所 示。
[0058] 在上述实施例， 一方面利用微器件之间的间隙形成连接区， 在与连接区与固定 层的支撑部接触， 对于微型发光二极管器件能够达到大面积固定层与连接层接 触， 可增加附着性， 避免良率损失； 另一方面利用固定层 （例如苯并环丁烯） 与外延材料层 （例如 GaP层、 GaN) 区域性接触粘附性较好的优点， 保证微型器 件在拾取之前不会因外界因素的影响导致良率损失， 可大大提升 Micro LED芯片 良率。
[0059] 在本发明中， 其中走道区域 C用于裸露牺牲层， 其面积越大， 越容易移除牺牲 层， 连接区 D用于与固定芯粒， 连接区面积越大芯粒越稳定， 因此走道区域 C和 连接区 D的布置并不限于图 14~18所示的那些， 在其他实施例中， 走道区域 C和连 接区 D的布置也可作对调设置， 或者其他设计。

Claims

权利要求书
[权利要求 1] 微型发光二极管器件， 包括：
微器件单元阵列， 相邻的微器件单元之间具有间隙；
连接层， 位于所述微器件单元之间的间隙， 至少与一个微器件单元连 接；
固定层， 位于所述微器件单元阵列的下方， 仅与所述连接层的下表面 接触， 并在所述微器件单元的下方形成空腔。
[权利要求 2] 根据权利要求 1所述的微型发光二极管器件， 其特征在于： 所述连接 层与至少一个微器件单元的下表面连接， 并向间隙延伸形成连接区， 所述固定层仅与连接区接触。
[权利要求 3] 根据权利要求 1所述的微型发光二极管器件， 其特征在于： 所述连接 层由构成所述微器件单元的材料层向所述间隙延伸而成， 并在间隙内 形成连接区， 所述固定层仅与所述连接区接触。
[权利要求 4] 根据权利要求 3所述的微型发光二极管器件， 其特征在于： 所述连接 层向所述间隙延伸的长度为相邻的微器件单元之间距离的 1/2以上。
[权利要求 5] 根据权利要求 1所述的微型发光二极管器件， 其特征在于： 所述连接 层为一系列系列离散的图案构成， 每个图案呈条状或块状。
[权利要求 6] 根据权利要求 5所述的微型发光二极管器件， 其特征在于： 所述连接 层至少同吋连接两个微器件单元。
[权利要求 7] 根据权利要求 1所述的微型发光二极管器件， 其特征在于： 所述微器 件单元为发光二极管单元， 所述连接层为 AlGalnP系材料层或 GaN基 材料层。
[权利要求 8] 根据权利要求 1所述的微型发光二极管器件， 其特征在于： 所述微器 件单元为 AlGalnP系发光二极管， 其包括窗口层， 所述连接层为窗口 层向间隙延伸并减薄至一定厚度而成。
[权利要求 9] 根据权利要求 1所述的微型发光二极管器件， 其特征在于： 所述连接 层的厚度为 10~500nm。
[权利要求 10] 根据权利要求 1所述的微型发光二极管器件， 其特征在于： 所述固定 层与所述连接层的接触面积小于所述连接层位于所述间隙内的投影面 积。
[权利要求 11] 根据权利要求 1所述的微型发光二极管器件， 其特征在于： 所述微器 件单元下方的空腔尺寸大于该微器件的尺寸。
[权利要求 12] 根据权利要求 1所述的微型发光二极管器件， 其特征在于： 所述微器 件单元正对其下方的空腔， 且尺寸大于所述空腔的尺寸。
[权利要求 13] 微型发光二极管器件阵列的制作方法， 包括步骤：
(1) 提供半导体外延结构， 具有相对的上表面和下表面；
(2) 在所述半导体外延结构的表面上定义一系列微器件单元区、 切 割道区和连接区， 其中连接区位于切割道区内；
(3) 在所述外延结构下表面的微器件单元区对应形成一系列牺牲层 单元；
(4) 在所述牺牲层上形成固定层， 并向切割道区延伸， 与所述半导 体外延结构下表面的切割道区接触；
(5) 去除所述切割道区的外延结构从而在所述切割道区形成间隙， 并在连接区保留一定厚度作为连接层；
(6) 去除所述牺牲层， 此吋外延结构在各个微器件单元区的下方形 成空腔， 仅连接层与所述固定层接触。
[权利要求 14] 根据权利要求 13所述的微型发光二极管器件的制作方法， 其特征在于 ： 所述步骤 （3) 中， 所述牺牲层单元的面积大于所述微器件单元区 的面积。
[权利要求 15] 根据权利要求 13所述的微型发光二极管器件的制作方法， 其特征在于 ： 所述步骤 （3) 中， 所述牺牲层单元完全覆盖所述微器件单元区， 并部分覆盖所述切割道区。
[权利要求 16] 根据权利要求 13所述的微型发光二极管器件的制作方法， 其特征在于 ： 所述步骤 （5) 中进行两次台面蚀刻， 第一次台面蚀刻至牺牲层并 裸露出牺牲层的表面形成切割道， 第二次台面蚀刻至外延结构的底层 ， 并保持一定的厚度作为连接层。 [权利要求 17] 根据权利要求 16所述的微型发光二极管器件的制作方法， 其特征在于 ： 通过台面蚀刻， 外延结构形成了侧向分幵的微器件单元， 并在连接 区保持连接。
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