TWI750488B - 半導體結構與微型半導體顯示裝置 - Google Patents

半導體結構與微型半導體顯示裝置 Download PDF

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TWI750488B
TWI750488B TW108125211A TW108125211A TWI750488B TW I750488 B TWI750488 B TW I750488B TW 108125211 A TW108125211 A TW 108125211A TW 108125211 A TW108125211 A TW 108125211A TW I750488 B TWI750488 B TW I750488B
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micro
semiconductor
substrate
layers
conductive
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TW108125211A
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TW202105708A (zh
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楊翔甯
吳志凌
蘇義閔
吳柏威
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錼創顯示科技股份有限公司
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Priority to TW108125211A priority Critical patent/TWI750488B/zh
Priority to US16/585,794 priority patent/US11362245B2/en
Publication of TW202105708A publication Critical patent/TW202105708A/zh
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Publication of TWI750488B publication Critical patent/TWI750488B/zh
Priority to US17/742,705 priority patent/US11843086B2/en

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Abstract

一種半導體結構包括一基板、複數個微型半導體元件以及一固定結構。微型半導體元件設置於基板上。固定結構設置於基板與微型半導體元件之間。固定結構包括複數個導電層及複數個支撐層。導電層設置於微型半導體元件的下表面上。支撐層連接於導電層與基板。導電層的材料與支撐層的材料不同。

Description

半導體結構與微型半導體顯示裝置
本揭露實施例係有關於一種半導體結構，且特別有關於一種微型半導體結構（micro semiconductor structure）與微型半導體顯示裝置。
近年，由於發光二極體（Light Emitting Diode, LED）在製作尺寸上的突破，將發光二極體以陣列排列製作的微型發光二極體（Micro LED）顯示器在市場上逐漸受到重視。微型發光二極體顯示器屬於主動式微型半導體元件顯示器，其相較於有機發光二極體（Organic Micro semiconductor Diode, OLED）顯示器更為省電，也具備更佳優異的對比度表現，在陽光下可具有更佳的可視性。此外，由於微型發光二極體顯示器採用無機材料，其相較於有機發光二極體顯示器具備更佳優良的可靠性以及更長的使用壽命。
微型發光二極體仍然具有一些缺點。舉例來說，發光二極體常透過固定結構（tether）來固持而使微型發光二極體較容易自載體基板（carrier substrate）上拾取並轉移至接收基板上，且藉由固定結構來鞏固微型發光二極體，使微型發光二極體於轉移時不會受到其他外因而影響品質。然而，在微型發光二極體轉移至接收基板後，固定結構可能會殘留導致微型發光二極體的電極接觸不良，造成微型發光二極體之效能降低。
因此，雖然現有的微型發光二極體已大致符合需求，但仍然存在許多問題，因此如何改善現有的微型發光二極體已成為目前業界相當重視的課題之一。
本揭露實施例包括一種半導體結構。半導體結構包括一基板、複數個微型半導體元件以及一固定結構。微型半導體元件設置於基板上。固定結構設置於基板與微型半導體元件之間。固定結構包括複數個導電層及複數個支撐層。導電層設置於微型半導體元件的下表面上。支撐層連接於導電層與基板。導電層的材料與支撐層的材料不同。
本揭露實施例包括一種微型半導體顯示裝置。微型半導體顯示裝置包括一接收基板、複數個微型半導體元件以及複數個導電層。微型半導體元件設置於接收基板上。導電層設置於接收基板與微型半導體元件之間。微型半導體元件於接收基板上之正投影的面積小於導電層於接收基板上之正投影的面積。
本揭露實施例包括一種半導體結構。半導體結構包括一基板、一磊晶結構以及一固定結構。磊晶結構設置於基板上。固定結構設置於基板與磊晶結構之間。固定結構包括複數個導電層及複數個支撐層。導電層設置於磊晶結構的下表面上。支撐層連接於導電層與基板。導電層的材料與支撐層的材料不同。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下的揭露內容敘述各個構件及其排列方式的特定範例，以簡化說明。當然，這些特定的範例並非用以限定。例如，若是本揭露實施例敘述了一第一特徵部件形成於一第二特徵部件之上或上方，即表示其可能包含上述第一特徵部件與上述第二特徵部件是直接接觸的實施例，亦可能包含了有附加特徵部件形成於上述第一特徵部件與上述第二特徵部件之間，而使上述第一特徵部件與第二特徵部件可能未直接接觸的實施例。
應理解的是，額外的操作步驟可實施於所述方法之前、之間或之後，且在所述方法的其他實施例中，部分的操作步驟可被取代或省略。
此外，其中可能用到與空間相關用詞，例如「在… 下方」、「下方」、「較低的」、「在… 上方」、「上方」、「較高的」及類似的用詞，這些空間相關用詞係為了便於描述圖示中一個（些）元件或特徵部件與另一個（些）元件或特徵部件之間的關係，這些空間相關用詞包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時（旋轉90度或其他方位），則其中所使用的空間相關形容詞也將依轉向後的方位來解釋。
在說明書中，「約」、「大約」、「大抵」之用語通常表示在一給定值或範圍的20%之內，或10%之內，或5%之內，或3%之內，或2%之內，或1%之內，或0.5%之內。在此給定的數量為大約的數量，亦即在沒有特定說明「約」、「大約」、「大抵」的情況下，仍可隱含「約」、「大約」、「大抵」之含義。
除非另外定義，在此使用的全部用語（包括技術及科學用語）具有與此篇揭露所屬之一般技藝者所通常理解的相同涵義。能理解的是，這些用語，例如在通常使用的字典中定義的用語，應被解讀成具有與相關技術及本揭露的背景或上下文一致的意思，而不應以一理想化或過度正式的方式解讀，除非在本揭露實施例有特別定義。
以下所揭露之不同實施例可能重複使用相同的參考符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定所討論的不同實施例及/或結構之間有特定的關係。
要注意的是，為了更清楚地說明本揭露各實施例的特徵，本揭露各圖式中可能省略部分元件。
第1圖顯示根據本揭露一實施例之半導體結構100的部分剖面示意圖。如第1圖所示，半導體結構100包括一基板10。在一些實施例中，基板10例如為一承載基板（carrier substrate），其可包括塑膠基板、玻璃基板、藍寶石基板或其他無線路的基板，但本揭露實施例並非以此為限。
如第1圖所示，半導體結構100包括複數個微型半導體元件20，微型半導體元件20設置於基板10上。在一些實施例中，微型半導體元件20例如是微型發光二極體（Micro LED）或微晶片，且後續可將微型半導體元件20轉移整合及組裝到一接收基板（receiving substrate）上，形成異質整合系統，例如包括穿戴式顯示器至大面積顯示器等任何尺寸的微型半導體顯示器。
在此所述之「微型」意指半導體元件20可具有介於1 μm至100 μm的尺寸。舉例來說，微型半導體元件20可具有20 μm、10 μm或5 μm之最大寬度，而微型半導體元件20可具有小於10 μm或5 μm之最大高度，但本揭露實施例並非以此為限。在其他實施例中，半導體元件20可具有更大或更小的尺寸。
在一些實施例中，微型半導體元件20包含p-n二極體，但本揭露實施例並非以此為限。在一些實施例中，微型半導體元件20例如包括可控制執行預定電子功能的微型半導體元件20（例如二極體、電晶體、積體電路）或具光子功能的微型半導體元件20（例如發光二極體、雷射二極體、光電二極體）。在一些實施例中，微型半導體元件20亦可應用於包括電路的微晶片，例如以矽或絕緣體上的半導體（semiconductor-on-insulator, SOI）晶圓為材料且用於邏輯或記憶應用微晶片，或以砷化鎵（GaAs）晶圓為材料且用於RF通信應用的微晶片，但本揭露實施例並非以此為限。
在一些實施例中，微型半導體元件20可為一磊晶結構（第1圖中未詳細繪示），磊晶結構可包括一第一型半導體層、一第二型半導體層及發光層，但本揭露實施例並非以此為限。舉例來說，第一型半導體層可為N型半導體層，而第二型半導體層可為P型半導體層。在一些實施例中，N型半導體層的厚度可大於P型半導體層的厚度。舉例來說，N型半導體層的厚度可介於1 μm至5 μm之間，發光層的厚度可介於0.1 μm至1 μm之間，而P型半導體層的厚度可介於0.1 μm至0.5 μm之間，但本揭露實施例並非以此為限。
在一些實施例中，磊晶結構之N型半導體層的長度與寬度可大於P型半導體層的長度與寬度。亦即，微型半導體元件20（磊晶結構）形成為如第1圖所示之一梯型結構。在此，N型半導體層的最大寬度與P型半導體層的最大寬度差值可介於0至5 μm之間，但本揭露實施例並非以此為限。
如第1圖所示，半導體結構100包括一固定結構30，固定結構30設置於基板10與微型半導體元件20之間。具體而言，固定結構30可包括複數個導電層31及複數個支撐層33，導電層31設置於微型半導體元件20的下表面20B上，而支撐層33連接於導電層31與基板10。在本實施例中，支撐層33直接接觸所連接之導電層31的側表面31S，且支撐層33於基板10上之正投影與導電層31於基板10上之正投影不重疊（彼此切齊），但本揭露實施例並非以此為限。此處，微型半導體元件20的下表面20B、支撐層33的上表面33U與導電層31的上表面31U共平面。亦即，固定結構30只配置於微型半導體元件20的下表面20B上而不會接觸於微型半導體元件20的其他面，可避免固定結構30殘留於微型半導體元件20的其他面上。
在本揭露實施例中，導電層31的材料與支撐層33的材料不同。舉例來說，導電層31的材料可包括金屬（例如，錫、金、銅）、導電高分子（例如，異方性導電膠膜）、金屬氧化物（例如，氧化銦錫（indium tin oxide, ITO））、其他適當的導電材料或前述材料之組合；支撐層33的材料可為非導電材料，例如包括有機材料（例如，光阻材料）、無機材料（例如，氧化矽、氮化矽、氮氧化矽）或前述材料之組合，但本揭露實施例並非以此為限。在一些實施例中，導電層31的楊氏模量可大於支撐層33的楊氏模量，使連接基板10與導電層31的支撐層33可在後續的轉移中提供較佳的緩衝支撐。
由於本揭露實施例之固定結構30包括導電層31及支撐層33，且導電層31及支撐層33為異質材料，於後續將微型半導體元件20轉移到一接收基板（例如，顯示背板）時，較容易從異質介面（即導電層31與支撐層33的交界處）斷裂，使支撐層33不易殘留於微型半導體元件20上，可避免微型半導體元件20的電路接觸不良，有效提升後續形成之異質整合系統（例如，微型發光二極體顯示裝置）的效能。此外，固定結構30之導電層31可直接作為微型半導體元件20的電極，不需要額外的製程，能進一步降低半導體結構100的製程時間與製造成本。
第2圖顯示根據本揭露另一實施例之半導體結構102的部分剖面示意圖。類似地，半導體結構102包括一基板10、複數個微型半導體元件20以及一固定結構30。需注意的是，為了簡便起見，第2圖僅繪示單一半導體元件20。如第2圖所示，微型半導體元件20設置於基板10上，固定結構30設置於基板10與微型半導體元件20之間。
此外，固定結構30包括複數個導電層31及複數個支撐層33，且導電層31的材料與支撐層33的材料不同，在此不多加贅述。類似地，為了簡便起見，第2圖僅繪示單一導電層31。如第2圖所示，導電層31設置於微型半導體元件20的下表面20B上，而支撐層33連接於導電層31與基板10。
與第1圖所示之半導體結構100的不同之處在於，第2圖所示之半導體結構102的支撐層33同時直接接觸所連接之導電層31的側表面31S與下表面31B。亦即，支撐層33於基板10上之正投影與導電層31於基板10上之正投影部分重疊，使支撐層33與導電層31接觸面積較大，提供更好的緩衝功能，但本揭露實施例並非以此為限。此處支撐層33於基板10上之正投影與微型半導體元件20於基板10上之正投影不重疊，避免影響後續轉移的效率。
第3圖顯示根據本揭露又一實施例之半導體結構104的部分剖面示意圖。與第2圖所示之半導體結構102的不同之處在於，第3圖所示之半導體結構104的支撐層33直接接觸所連接之導電層31的下表面31B，且支撐層33於基板10上之正投影位於導電層31於基板10上之正投影內，但本揭露實施例並非以此為限。此處支撐層33與導電層31切齊，但於未繪示出的實施例中，支撐層33亦可以內縮至微型半導體元件20於基板10上之正投影內以靠近微型半導體元件20的重心，提供更好的支撐。在一些實施例中，支撐層33於基板10上之正投影與導電層31於基板10上之正投影的比值可小於0.5，若大於或等於0.5可能使支撐層33與導電層31較難分離。
在第1圖之半導體結構100、在第2圖之半導體結構102及在第3圖之半導體結構104中，每個微型半導體元件20於基板上10之正投影的面積皆小於對應的導電層31於基板10上之正投影的面積。舉例來說，每個微型半導體元件20於基板上10之正投影的面積與對應的導電層31於基板10上之正投影的面積的比值可大於或等於0.5且小於1。其中，此比值若小於0.5會使固定結構30佔據過大空間，減少微型半導體元件20的利用率佔比。
第4圖顯示根據本揭露一實施例之半導體結構106的部分剖面示意圖。與第1圖所示之半導體結構100的不同之處在於，第4圖所示之半導體結構106的每個微型半導體元件22於基板上10之正投影的面積等於對應的導電層31於基板10上之正投影的面積。亦即，微型半導體元件22的下表面22B與對應之導電層31的上表面31U的面積相同且同形配置，後續轉移時可以有更好的接合良率，但本揭露實施例並非以此為限。
第5圖顯示根據本揭露另一實施例之半導體結構108的部分剖面示意圖。與第2圖所示之半導體結構102的不同之處在於，第5圖所示之半導體結構108的每個微型半導體元件22於基板上10之正投影的面積等於對應的導電層31於基板10上之正投影的面積，但本揭露實施例並非以此為限。
第6圖顯示根據本揭露又一實施例之半導體結構110的部分剖面示意圖。與第3圖所示之半導體結構104的不同之處在於，第6圖所示之半導體結構110的每個微型半導體元件22於基板上10之正投影的面積等於對應的導電層31於基板10上之正投影的面積，但本揭露實施例並非以此為限。
第7圖顯示根據本揭露一實施例之半導體結構112的部分剖面示意圖。第7圖所示之半導體結構112類似於第1圖所示之半導體結構100，其支撐層33直接接觸所連接之導電層31的側表面31S，且支撐層33於基板10上之正投影與導電層31於基板10上之正投影不重疊（彼此切齊），其他相同之處在此不多加贅述。
與第1圖所示之半導體結構100的不同之處在於，第7圖所示之半導體結構112的每個微型半導體元件24於基板上10之正投影的面積大於對應的導電層31於基板10上之正投影的面積，且微型半導體元件24的下表面24B可直接接觸支撐層33（例如微型半導體元件24的P型半導體層可直接接觸支撐層33的頂表面），使微型半導體元件24較容易從異質介面（即導電層31與支撐層33的交界處、微型半導體元件24與支撐層33的交界處）斷裂，但本揭露實施例並非以此為限。在一些實施例中，微型半導體元件24與支撐層33的接觸面積與微型半導體元件24的下表面24B之面積的比值小於或等於0.2，此比值若大於0.2可能影響後續的轉移良率。
第8圖顯示根據本揭露另一實施例之半導體結構114的部分剖面示意圖。與第7圖所示之半導體結構112的不同之處在於，第8圖所示之半導體結構114的支撐層33同時直接接觸所連接之導電層31的側表面31S與下表面31B。亦即，支撐層33於基板10上之正投影與導電層31於基板10上之正投影部分重疊，但本揭露實施例並非以此為限。
第9圖顯示根據本揭露又一實施例之半導體結構116的部分剖面示意圖。與第7圖所示之半導體結構112的不同之處在於，第9圖所示之半導體結構116的支撐層33直接接觸所連接之導電層31的下表面31B，且支撐層33於基板10上之正投影位於導電層31於基板10上之正投影內，但本揭露實施例並非以此為限。
第10圖顯示根據本揭露一實施例之半導體結構118的部分剖面示意圖。與第1圖所示之半導體結構100的不同之處在於，第10圖所示之半導體結構118的每個導電層31包括一第一導電部31-1與一第二導電部31-2，第一導電部31-1與第二導電部31-2彼此分離，但本揭露實施例並非以此為限。特別說明的是，第一導電部31-1與第二導電部31-2可具有相反的電性。後續轉移後可將微型半導體元件20直接接合於接收基板上，不需再於另一面製作導電電極。換句話說，微型半導體元件20可以為一覆晶式（Flip Chip）微型半導體元件。
此外，如第10圖所示，支撐層33直接接觸所連接之導電層31的側表面。具體而言，支撐層33可直接接觸第一導電部31-1的側表面31-1S與第二導電部31-2的側表面31-2S，且支撐層33於基板10上之正投影與第一導電部31-1及第二導電部31-2於基板10上之正投影不重疊（彼此切齊），但本揭露實施例並非以此為限。
在其他實施例中，支撐層33可同時直接接觸所連接之第一導電部31-1（或第二導電部31-2）的側表面31-1S（或31-2S）與下表面。亦即，支撐層33於基板10上之正投影與第一導電部31-1（或第二導電部31-2）於基板10上之正投影部分重疊；或者，支撐層33可直接接觸所連接之第一導電部31-1（或第二導電部31-2）的下表面，且支撐層33於基板10上之正投影位於第一導電部31-1（或第二導電部31-2）於基板10上之正投影內。
第11圖顯示根據本揭露另一實施例之半導體結構120的部分剖面示意圖。第11圖所示之半導體結構120類似於第1圖所示之半導體結構100，與第1圖所示之半導體結構100的不同之處在於，第11圖所示之半導體結構120的每個微型半導體元件26具有至少一導角或圓角26A。當微型半導體元件26應用於光電元件時，導角或圓角26A可使微型半導體元件26之側向與正向交界處的出光效率提升，但本揭露實施例並非以此為限。
第12圖顯示根據本揭露又一實施例之半導體結構122的部分剖面示意圖。第12圖所示之半導體結構122類似於第10圖所示之半導體結構118，與第10圖所示之半導體結構118的不同之處在於，第12圖所示之半導體結構122可進一步包括複數出光結構20e，出光結構20e可設置於微型半導體元件20上。舉例來說，出光結構20e可連接於微型半導體元件20的頂表面並向外部延伸，但本揭露實施例並非以此為限。當微型半導體元件20應用於光電元件時，出光結構20e可進一步提升其發光效率。
第13圖顯示根據本揭露一實施例之固定結構30的部分俯視圖，第14圖顯示根據本揭露另一實施例之固定結構30的部分俯視圖。在此，是自微型半導體元件20（或22、24、26）處往基板10處俯視並省略基板10與微型半導體元件20（或22、24、26）。第1圖、第4圖及第7圖所示之固定結構30可例如沿著第13圖的線A-A’所切，而第2圖、第5圖及第8圖所示之固定結構30可例如沿著第14圖的線B-B’所切，但本揭露實施例並非以此為限。
如第13圖與第14圖所示，在一些實施例中，固定結構30之複數個支撐層33可彼此分離。舉例來說，支撐層33可呈一陣列排列，並且分別位於各導電層31的四個角落，即可形成島狀支撐層33，但本揭露實施例並非以此為限。
第15圖顯示根據本揭露又一實施例之固定結構30的部分俯視圖。如第15圖所示，固定結構30之複數個支撐層33可呈一規則排列，並位於各導電層31的兩個角落，並非位於各導電層31的四個角落。亦即，本揭露並未限定支撐層33的排列方式。
第16圖顯示根據本揭露一實施例之固定結構30’的部分俯視圖，第17圖顯示根據本揭露另一實施例之固定結構30’的部分俯視圖。在一些實施例中，固定結構30’之複數個支撐層33’可彼此分離，此外，複數個支撐層33’彼此平行，即此些支撐層33’於 基板10上之正投影彼此平行，以形成平行支撐層33’，但本揭露實施例並非以此為限。
舉例來說，如第16圖所示，每個支撐層33’於基板10上之正投影可沿Y方向延伸；如第17圖所示，每個支撐層33’於 基板10上之正投影可沿X方向延伸。在其他實施例中，支撐層33’的延伸方向可與第16圖或第17圖所繪示之方向不同。
第18圖顯示根據本揭露一實施例之固定結構30’’的部分俯視圖。在本實施例中，支撐層33’’可形成一網狀結構，網狀結構包括複數第一子支撐件33-1及複數第二子支撐件33-2。
舉例來說，如第18圖所示，每個第一子支撐件33-1於基板10上之正投影沿第一方向（X方向）延伸，而每個第二子支撐件33-2於基板10上之正投影沿第二方向（Y方向）延伸，第二方向與第一方向不同。在本實施例中，第二方向與第一方向垂直，但本揭露實施例並非以此為限。形成為網狀結構的支撐層33’’可進一步提升支撐力，以更穩固地支撐微型半導體元件20。
第19圖顯示根據本發明一實施例之微型半導體顯示裝置200的部分剖面示意圖。舉例來說，微型半導體顯示裝置200可為將微型半導體元件20轉移到異質整合系統的接收基板後的裝置，但本揭露實施例並非以此為限。
如第19圖所示，微型半導體顯示裝置200包括一接收基板40、複數個微型半導體元件20以及複數導電層31。微型半導體元件20設置於接收基板40上，導電層31設置於接收基板40與微型半導體元件20之間。在本實施例中，微型半導體元件20於接收基板40上之正投影的面積小於導電層31於接收基板40上之正投影的面積，但本揭露實施例並非以此為限。
在一些實施例中，接收基板40可例如為顯示基板、發光基板、具有薄膜電晶體（Thin-film transistor, TFT）或積體電路（integrated circuit, IC）等功能元件的基板或其他類型的電路基板，但本揭露實施例並非以此為限。
如第19圖所示，在一些實施例中，微型半導體顯示裝置200可進一步包括複數接合層50，接合層50可設置於接收基板40與導電層31之間。接合層50可用於接合導電層31以電性連接微型半導體元件20，其可進一步提升微型半導體元件20接合於接收基板40上的良率。在一些實施例中，接合層50的材料可包括金屬、導電高分子或是金屬氧化物，但本揭露實施例並非以此為限。
在第19圖所示之實施例中，接合層50於接收基板40上之正投影的面積小於對應的導電層31於接收基板40上之正投影的面積，使導電層31可以完整地接觸接合層50並增加接合容許度，但本揭露實施例並非以此為限。在其他實施例中，接合層50於接收基板40上之正投影的面積也可等於或大於對應的導電層31於接收基板40上之正投影的面積。
雖然前述實施例中皆以複數個微型半導體元件設置於基板10上為例進行說明，但本揭露實施例並非以此為限。第20圖顯示根據本揭露一實施例之半導體結構100’的部分剖面示意圖。如第20圖所示，半導體結構100’包括一基板10’、一磊晶結構20’以及一固定結構30。磊晶結構20’設置於基板10’上，固定結構30設置於基板10’與磊晶結構20’之間。固定結構30包括複數個導電層31及複數個支撐層33，且導電層31的材料與支撐層33的材料不同。導電層31設置於磊晶結構20’的下表面20B’上，而支撐層33連接於導電層31與基板10’。
更具體而言，磊晶結構20’可例如為第1圖所示之複數個微型半導體元件20尚未進行元件分離製程前，自生長基板(未繪示)完整磊晶生長的一磊晶結構。
承上述說明，本揭露實施例之半導體結構的固定結構包括導電層及支撐層，且導電層及支撐層為異質材料，使支撐層於微型半導體元件轉移後不易殘留於微型半導體元件上，可避免微型半導體元件的電路接觸不良，有效提升後續形成之異質整合系統（例如，微型發光二極體顯示裝置）的效能。此外，固定結構之導電層可直接作為微型半導體元件的電極，不需要額外的製程，能進一步降低半導體結構的製程時間與製造成本。
以上概述數個實施例的部件，以便在本揭露所屬技術領域中具有通常知識者可以更理解本揭露實施例的觀點。在本揭露所屬技術領域中具有通常知識者應該理解，他們能以本揭露實施例為基礎，設計或修改其他製程和結構以達到與在此介紹的實施例相同之目的及/或優勢。在本揭露所屬技術領域中具有通常知識者也應該理解到，此類等效的結構並無悖離本揭露的精神與範圍，且他們能在不違背本揭露之精神和範圍之下，做各式各樣的改變、取代和替換。因此，本揭露之保護範圍當視後附之申請專利範圍所界定者為準。另外，雖然本揭露已以數個較佳實施例揭露如上，然其並非用以限定本揭露。
整份本說明書對特徵、優點或類似語言的引用並非意味可以利用本揭露實現的所有特徵和優點應該是或者在本揭露的任何單個實施例中。相對地，涉及特徵和優點的語言被理解為其意味著結合實施例描述的特定特徵、優點或特性包括在本揭露的至少一個實施例中。因而，在整份說明書中對特徵和優點以及類似語言的討論可以但不一定代表相同的實施例。
再者，在一個或多個實施例中，可以任何合適的方式組合本揭露的所描述的特徵、優點和特性。根據本文的描述，相關領域的技術人員將意識到，可在沒有特定實施例的一個或多個特定特徵或優點的情況下實現本揭露。在其他情況下，在某些實施例中可辨識附加的特徵和優點，這些特徵和優點可能不存在於本揭露的所有實施例中。
100、100’、102、104、106、108、110、112、114、116、118、120、122:半導體結構 10、10’:基板 20、22、24、26:微型半導體元件 20B、22B、24B:下表面 20e:出光結構 20’:磊晶結構 26A:導角或圓角 30、30’、30’’:固定結構 31:導電層 31B:下表面 31S:側表面 31U:上表面 31-1:第一導電部 31-1S:側表面 31-2:第二導電部 31-2S:側表面 33、33’、33’’:支撐層 33-1:第一子支撐件 33-2:第二子支撐件 33U:上表面 200:微型半導體顯示裝置 40:接收基板 50:接合層 A-A’、B-B’:剖面線 X、Y:座標軸
以下將配合所附圖式詳述本揭露實施例。應注意的是，各種特徵部件並未按照比例繪製且僅用以說明例示。事實上，元件的尺寸可能經放大或縮小，以清楚地表現出本揭露實施例的技術特徵。 第1圖顯示根據本揭露一實施例之半導體結構的部分剖面示意圖。 第2圖顯示根據本揭露另一實施例之半導體結構的部分剖面示意圖。 第3圖顯示根據本揭露又一實施例之半導體結構的部分剖面示意圖。 第4圖顯示根據本揭露一實施例之半導體結構的部分剖面示意圖。 第5圖顯示根據本揭露另一實施例之半導體結構的部分剖面示意圖。 第6圖顯示根據本揭露又一實施例之半導體結構的部分剖面示意圖。 第7圖顯示根據本揭露一實施例之半導體結構的部分剖面示意圖。 第8圖顯示根據本揭露另一實施例之半導體結構的部分剖面示意圖。 第9圖顯示根據本揭露又一實施例之半導體結構的部分剖面示意圖。 第10圖顯示根據本揭露一實施例之半導體結構的部分剖面示意圖。 第11圖顯示根據本揭露另一實施例之半導體結構的部分剖面示意圖。 第12圖顯示根據本揭露又一實施例之半導體結構的部分剖面示意圖。 第13圖顯示根據本揭露一實施例之固定結構的部分俯視圖。 第14圖顯示根據本揭露另一實施例之固定結構的部分俯視圖。 第15圖顯示根據本揭露又一實施例之固定結構的部分俯視圖。 第16圖顯示根據本揭露一實施例之固定結構的部分俯視圖。 第17圖顯示根據本揭露另一實施例之固定結構的部分俯視圖。 第18圖顯示根據本揭露一實施例之固定結構的部分俯視圖。 第19圖顯示根據本發明一實施例之微型半導體顯示裝置的部分剖面示意圖。 第20圖顯示根據本揭露一實施例之半導體結構的部分剖面示意圖。
100:半導體結構
10:基板
20:微型半導體元件
20B:下表面
30:固定結構
31:導電層
31S:側表面
31U:上表面
33:支撐層
33U:上表面

Claims (12)

  1. 一種半導體結構，包括：一無線路基板；複數個微型半導體元件，設置於該無線路基板上，且每該微型半導體元件與該無線路基板之間具有一間隙；以及一固定結構，設置於該無線路基板與該些微型半導體元件之間，且該固定結構包括：複數個導電層，設置於該些微型半導體元件的下表面上；及複數個支撐層，連接於該些導電層與該無線路基板；其中該些導電層的材料與該些支撐層的材料不同，且每該微型半導體元件於該無線路基板上之正投影的面積小於或等於對應的該導電層於該無線路基板上之正投影的面積。
  2. 如申請專利範圍第1項所述之半導體結構，其中每該支撐層直接接觸所連接之導電層的一側表面與一下表面的至少其中之一。
  3. 如申請專利範圍第2項所述之半導體結構，其中每該微型半導體元件於該無線路基板上之正投影的面積與對應的該導電層於該無線路基板上之正投影的面積的比值大於或等於0.5且小於1。
  4. 如申請專利範圍第1項所述之半導體結構，其中每該導電層包括一第一導電部與一第二導電部，該第一導電部與該第二導電部彼此分離。
  5. 如申請專利範圍第4項所述之半導體結構，其中該第一導電部的一部分自對應的微型半導體元件的下表面向外凸出，且該第二導電部的一部分自對應的微型半導體元件的下表面向外凸出。
  6. 如申請專利範圍第1項所述之半導體結構，其中該些導電層的楊氏模量大於該些支撐層的楊氏模量。
  7. 如申請專利範圍第1項所述之半導體結構，其中該些微型半導體元件的下表面、該些支撐層的上表面與該些導電層的上表面共平面。
  8. 如申請專利範圍第1項所述之半導體結構，其中該些支撐層彼此分離。
  9. 如申請專利範圍第1項所述之半導體結構，其中該些支撐層形成一網狀結構，該網狀結構包括：複數第一子支撐件，每該第一子支撐件於該無線路基板上之正投影沿一第一方向延伸；及複數第二子支撐件，每該第二子支撐件於該無線路基板上之正投影沿一第二方向延伸，該第二方向與該第一方向不同。
  10. 一種微型半導體顯示裝置，包括：一接收基板；複數個微型半導體元件，設置於該接收基板上；以及複數個導電層，設置於該接收基板與該些微型半導體元件之間且與該接收基板彼此分離； 其中該些微型半導體元件於該接收基板上之正投影的面積小於該些導電層於該接收基板上之正投影的面積。
  11. 如申請專利範圍第10項所述之微型半導體顯示裝置，更包括：複數接合層，設置於該接收基板與該些導電層之間，其中每該接合層於該接收基板上之正投影的面積小於對應的該導電層於該接收基板上之正投影的面積。
  12. 如申請專利範圍第11項所述之微型半導體顯示裝置，其中該些微型半導體元件於該接收基板上之正投影的面積小於該些接合層於該接收基板上之正投影的面積。
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