WO2018188018A1 - 低压差线性稳压器 - Google Patents

低压差线性稳压器 Download PDF

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Publication number
WO2018188018A1
WO2018188018A1 PCT/CN2017/080422 CN2017080422W WO2018188018A1 WO 2018188018 A1 WO2018188018 A1 WO 2018188018A1 CN 2017080422 W CN2017080422 W CN 2017080422W WO 2018188018 A1 WO2018188018 A1 WO 2018188018A1
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source
tube
amplifier
voltage
dropout linear
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PCT/CN2017/080422
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English (en)
French (fr)
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李经珊
陈科
詹昶
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2017/080422 priority Critical patent/WO2018188018A1/zh
Priority to CN201780000309.2A priority patent/CN109416552B/zh
Publication of WO2018188018A1 publication Critical patent/WO2018188018A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

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  • the present application relates to the field of circuit design technologies, and in particular, to a low dropout linear regulator.
  • Low dropout regulator can provide output voltage independent of power supply and ambient temperature. It has a certain load capacity and has been widely used in various power chips. Compared to traditional linear regulators, the LDO allows a small voltage difference between the input and output; for example, the input voltage of the LDO can be only 1.7V higher or lower than the output voltage.
  • a conventional low-power voltage-flip flip follower (FVF) structure LDO circuit whose output voltage is greatly affected by process and temperature
  • LDO When the load capacitance at the output of the circuit changes over a wide range, the loop stability of the LDO circuit is reduced.
  • a conventional low-power LDO circuit is used, although the stability problem caused by a large change in load capacitance can be solved, the LDO circuit cannot output a voltage close to the power supply voltage, and the output voltage of the LDO circuit is limited.
  • the output impedance of the device is such that the pole corresponding to the output node is at a higher frequency.
  • One embodiment of the present invention provides a low dropout linear regulator including: an operational amplifier, a source follower, a power adjustment transistor, a common gate amplifier, a pull-up transistor, and a tail current source; a source of the source follower Connected to the drain of the power regulator and the inverting input of the operational amplifier, the drain of the source follower is grounded through the tail current source, the gate of the source follower is connected to the output of the operational amplifier; the drain of the common-gate amplifier The pole is connected to the drain of the pull-up tube and the gate of the power adjustment tube, and the source of the common-gate amplifier is grounded through the tail current source; the source of the power adjustment tube and the source of the pull-up tube are connected to the voltage source; The non-inverting input of the op amp is used to input the reference voltage, and the source of the source follower is used to output the regulated voltage.
  • the operational amplifier and the source follower form a unity gain negative feedback circuit, and the output voltage of the low dropout linear regulator is equal to the reference voltage, which is not affected by the threshold voltage of the source follower, and is not only improved.
  • the accuracy of the output voltage, and the ability to obtain different output voltages by adjusting the reference voltage ie, the output voltage is not limited), so that the output voltage has a higher degree of freedom; at the same time, after the introduction of the operational amplifier, low-dropout linear regulator
  • the output impedance of the device is further reduced, so that the pole corresponding to the output node is at a higher frequency, which can avoid the influence of the external load capacitance on the loop stability when it changes within a large range.
  • the low dropout linear regulator also includes an external capacitor; one end of the external capacitor is connected to the source of the source follower, and the other end is grounded; the capacitance of the external capacitor ranges from 0 to 1 uF.
  • an external capacitor is provided in the low-dropout linear regulator to improve transient response performance, meet the high current requirement of the load, and not affect the stability of the low-dropout linear regulator.
  • the low dropout linear regulator further includes a first cascode amplifier and a second cascode amplifier; the first cascode amplifier is connected between the drain and the tail current source of the source follower, A cascode amplifier is coupled between the drain of the common-gate amplifier and the drain of the pull-up tube.
  • This embodiment can improve the loop gain to improve the linearity adjustment and load regulation performance of the low dropout linear regulator.
  • the first cascode amplifier is an NMOS transistor
  • the second cascode amplifier is a PMOS transistor. This embodiment provides a specific implementation of the first cascode amplifier and the second cascode amplifier.
  • the tail current source is an NMOS transistor. This embodiment provides a specific implementation of the tail current source.
  • the source follower, the power adjustment tube and the pull-up tube are all PMOS tubes
  • the common-gate amplifier is an NMOS tube. This embodiment provides a specific implementation of the source follower, the power adjustment tube, the pull-up tube, and the common-gate amplifier, which can improve the loop loop gain, thereby improving the linear adjustment and load adjustment performance of the low-dropout linear regulator.
  • FIG. 1 is a circuit diagram of a low dropout linear regulator according to a first embodiment of the present application
  • FIG. 2 is a circuit diagram of a low dropout linear regulator according to a second embodiment of the present application.
  • FIG. 3 is a circuit diagram of a low dropout linear regulator according to a third embodiment of the present application.
  • the first embodiment of the present application relates to a low dropout linear regulator, which is applied to provide an output voltage independent of power supply and ambient temperature, has a certain load capacity, and can be externally connected to a capacitor.
  • the low dropout linear regulator includes an operational amplifier A1, a source follower M2, a power adjustment tube M4, a common gate amplifier M3, a pull-up tube M5, and a tail current source M1; wherein, VBP For the bias voltage of the pull-up tube M5, VBN1 is the bias voltage of the common-gate amplifier M3, and VBN2 is the bias voltage of the tail current source M1; wherein the bias voltages VBP, VBN1, and VBN2 respectively make the pull-up tube M5,
  • the gate amplifier M3 and the tail current source M1 operate in a saturation region.
  • the source of the source follower M2 is connected to the drain of the power adjustment transistor M4 and the inverting input of the operational amplifier A1, and the drain of the source follower M2 is grounded through the tail current source, the source follower
  • the gate of M2 is connected to the output terminal of the operational amplifier A1;
  • the drain of the common-gate amplifier M3 is connected to the drain of the pull-up transistor M5 and the gate of the power adjustment transistor M4, and the source of the common-gate amplifier M3 passes through the tail current source M1.
  • Grounding; the source of the power regulating tube M4 and the source of the pull-up tube M5 are both connected to a voltage source.
  • the positive phase input of the operational amplifier A1 is used to input the reference voltage, and the source of the source follower M2 is used to output the regulated voltage.
  • the tail current source M1 may be an NMOS transistor.
  • the present invention is not limited thereto, and may be a semiconductor transistor.
  • the source follower M2, the power adjustment tube M4, and the pull-up tube M5 are all PMOS transistors, and the common-gate amplifier M3 is an NMOS transistor.
  • the source follower M2, the common gate amplifier M3 and the power adjustment tube M4 form a negative feedback loop, and the operational amplifier A1 and the source follower M2 form a unity gain negative feedback loop; the pull-up tube M5 is for guarantee
  • the common-gate amplifier M3 has a certain gain.
  • V out is the output voltage and V ref is the reference voltage.
  • V out is only related to the reference voltage V ref , and as long as V ref has a zero temperature coefficient, V out is also a zero temperature coefficient.
  • the negative feedback loop formed by the source follower M2, the common gate amplifier M3 and the power adjustment tube M4 is disconnected, and the zero-pole distribution of the LDO circuit is as follows:
  • the pole corresponding to the output of the LDO circuit is:
  • r out is the output impedance of the LDO circuit
  • a v is the voltage gain of the operational amplifier A1
  • g M2 is the transconductance of the source follower M2
  • C L is the load capacitance.
  • the pole corresponding to the X node is:
  • C x is the parasitic capacitance of the X node
  • g M3 is the transconductance of the common gate amplifier M3.
  • the pole corresponding to the Y node is:
  • r Y is the output impedance of the pull-up tube M5
  • C Y is mainly composed of the parasitic capacitance of the gate terminal of the power adjustment tube M4.
  • the pole frequency corresponding to the output node of the operational amplifier A1 is:
  • r oA1 is the output impedance of op amp A1 and C A1 is the parasitic capacitance at the output node of the op amp.
  • the operational amplifier A1 is not included, so that the output voltage of the LDO circuit becomes:
  • V out V ref +V th
  • V out is the output voltage
  • V ref is the reference voltage
  • V th is the threshold voltage of the M2 tube.
  • the LDO circuit output voltage V out is not only related to the reference voltage V ref , but also related to the threshold voltage V th of the M 2 tube. Since the V th is greatly affected by the process and has a certain temperature coefficient, the LDO circuit output voltage is V out is also affected by process and temperature. To achieve V ref and V th temperature compensation, V ref must have a positive temperature coefficient. At this time, the LDO circuit output voltage V out can only achieve a zero temperature coefficient at a certain voltage value, so the output voltage of the LDO circuit is limited.
  • the main pole is still p Y , when the output load capacitance of the LDO circuit changes within a large range, the secondary main pole will change between p X and P out , or the positions of the two are similar, thereby reducing The loop stability of the LDO circuit.
  • the operational amplifier and the source follower form a unity gain negative feedback circuit, and the output voltage of the low dropout linear regulator is equal to the reference voltage and is not affected by the threshold voltage of the source follower, not only The accuracy of the output voltage is improved, and since the output voltage can be obtained by adjusting the reference voltage (ie, the output voltage is not limited), the output voltage has a higher degree of freedom.
  • the operational amplifier is introduced, the low dropout linearly stabilizes. The output impedance of the voltage device is further reduced, so that the pole corresponding to the output node is at a higher frequency, which can avoid the influence of the external load capacitance on the loop stability when it changes within a large range.
  • the second embodiment of the present application relates to a low dropout linear regulator, and this embodiment is in the first implementation.
  • the improvement based on the example, the main improvement is:
  • the low dropout linear regulator further includes an external capacitor C1.
  • One end of the external capacitor C1 is connected to the source of the source follower M2, and the other end is grounded.
  • the external capacitor C1 is generally a large capacitor, that is, the capacitance value of the external capacitor C1 ranges from 0 to 1 uF; since the output impedance of the LDO circuit is reduced a lot, the LDO circuit The pole Pout corresponding to the output terminal is also at a higher frequency, which does not affect the loop stability of the LDO circuit; therefore, when the external capacitor C1 of the LDO circuit is a large capacitor, the LDO circuit can also be guaranteed to have a good stability.
  • the present embodiment sets an external capacitor in the low-dropout linear regulator to improve the transient response performance, meet the high current requirement of the load, and does not affect the stability of the low-dropout linear regulator. .
  • the third embodiment of the present application relates to a low-dropout linear voltage regulator.
  • This embodiment is an improvement on the basis of the first embodiment.
  • the main improvement is that, in this embodiment, please refer to FIG.
  • the voltage device further includes a first cascode amplifier M6 and a second cascode amplifier M7; wherein VBN3 is a bias voltage of the first cascode amplifier M6, and VBP1 is a second cascode amplifier M7
  • the bias voltage, VBP2 is the bias voltage of the pull-up tube M5; wherein the bias voltages VBN3, VBP1, and VBP2 cause the first cascode amplifier M6, the second cascode amplifier M7, and the pull-up tube M5 to operate, respectively. In the saturation zone.
  • the first cascode amplifier M5 is connected between the drain of the source follower M2 and the tail current source M1 and the second cascode amplifier M6 is connected to the drain and the top of the common-gate amplifier M3. Pull the tube between the drains of M5.
  • the first cascode amplifier M6 is an NMOS transistor
  • the second cascode amplifier M7 is a PMOS tube.
  • the working principle of the low dropout linear regulator of this embodiment is substantially the same as that of the first embodiment, and the main difference is:
  • the negative feedback loop gain formed by the source follower M2, the common gate amplifier M3, and the power adjustment transistor M4 is:
  • g M4 is the transconductance of the power adjustment tube M4. As can be seen from the above formula (6), the loop gain of the LDO circuit is small.
  • the negative feedback loop gain formed by the source follower M2, the common gate amplifier M3, and the power adjustment tube M4 is:
  • this embodiment can improve the loop gain to improve the linearity adjustment and load regulation performance of the low dropout linear regulator. It should be noted that the present embodiment can also be used as an improvement on the basis of the second embodiment, and the same technical effects can be achieved.

Abstract

一种低压差线性稳压器，包括：运算放大器(A1)、源极跟随器(M2)、功率调整管(M4)、共栅放大器(M3)、上拉管(M5)以及尾电流源(M1)；源极跟随器(M2)的源极连接于功率调整管(M4)的漏极与运算放大器(A1)的反相输入端，源极跟随器(M2)的漏极通过尾电流源(M1)接地，源极跟随器(M2)的栅极连接于运算放大器(A1)的输出端；共栅放大器(M3)的漏极连接于上拉管(M5)的漏极与功率调整管(M4)的栅极，共栅放大器(M3)的源极通过尾电流源(M1)接地；功率调整管(M4)的源极与上拉管(M5)的源极均连接至电压源；其中，运算放大器(A1)的正相输入端用于输入参考电压，源极跟随器(M2)的源极用于输出稳压电压。采用所述低压差线性稳压器，能够得到高精度的输出电压，且输出电压具有较高的自由度。

Description

低压差线性稳压器 技术领域
本申请涉及电路设计技术领域，特别涉及一种低压差线性稳压器。
背景技术
低压差线性稳压器(low dropout regulator，缩写为LDO)可以提供与电源及环境温度无关的输出电压，具有一定的负载能力，已经广泛地应用于各种功率芯片中。相对于传统的线性稳压器，LDO允许输入端和输出端之间的电压差较小；例如，LDO的输入端电压可以仅比输出端电压高1.7V，或者更小。
发明人发现现有技术中至少存在以下问题：现有的一种常规低功耗电压跟随翻转(flipped voltage follower，缩写为FVF)结构LDO电路，其输出电压受工艺和温度影响较大，且LDO电路输出端的负载电容在较大范围内变化时，会降低LDO电路的环路稳定性。另外，若采用一种常规低功耗LDO电路，虽然能够解决负载电容变化较大时带来的稳定性问题，但是LDO电路无法输出与电源电压比较接近的电压，LDO电路的输出电压受到限制。
发明内容
本发明部分实施例的目的在于提供一种低压差线性稳压器，可以通过调整参考电压获得不同的高精度的输出电压，同时输出电压具有较高的自由度；减小了低压差线性稳压器的输出阻抗，使得输出节点对应的极点处于较高的频率。
本发明的一个实施例提供了一种低压差线性稳压器，包括：运算放大器、源极跟随器、功率调整管、共栅放大器、上拉管以及尾电流源；源极跟随器的源极连接于功率调整管的漏极与运算放大器的反相输入端，源极跟随器的漏极通过尾电流源接地，源极跟随器的栅极连接于运算放大器的输出端；共栅放大器的漏极连接于上拉管的漏极与功率调整管的栅极，共栅放大器的源极通过尾电流源接地；功率调整管的源极与上拉管的源极均连接至电压源；其中，运算放大器的正相输入端用于输入参考电压，源极跟随器的源极用于输出稳压电压。
本申请相对于现有技术而言，运算放大器和源极跟随器构成单位增益负反馈电路，低压差线性稳压器的输出电压等于参考电压，不受源极跟随器的阈值电压影响，不仅提高了输出电压的精度，而且，由于能够通过调整参考电压获得不同的输出电压(即输出电压不受限)，使得输出电压具有较高的自由度；同时，引入运算放大器后，低压差线性稳压器的输出阻抗进一步减小了，使得输出节点对应的极点处于较高的频率，能够避免外接负载电容在较大范围内变化时对环路稳定性造成影响。
另外，低压差线性稳压器还包括外接电容；外接电容的一端连接于源极跟随器的源极，另一端接地；外接电容的电容值范围为0到1uF。本实施例中，于低压差线性稳压器中设置外接电容，以提高瞬态响应性能，满足负载的大电流要求，同时不影响低压差线性稳压器的稳定性。
另外，低压差线性稳压器还包括第一共源共栅放大器与第二共源共栅放大器；第一共源共栅放大器连接于源极跟随器的漏极与尾电流源之间，第二共源共栅放大器连接于共栅放大器的漏极与上拉管的漏极之间。本实施例能够提高环路增益，以提高低压差线性稳压器线性调整和负载调整性能。
另外，第一共源共栅放大器为NMOS管，第二共源共栅放大器为PMOS管。本实施例提供了第一共源共栅放大器与第二共源共栅放大器的具体实现方式。
另外，尾电流源为NMOS管。本实施例提供了尾电流源的具体实现方式。
另外，源极跟随器、功率调整管及上拉管均为PMOS管，共栅放大器为NMOS管。本实施例提供了源极跟随器、功率调整管、上拉管以及共栅放大器的具体实现方式，可以提高环路环路增益，从而提高低压差线性稳压器线性调整和负载调整性能。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是根据本申请第一实施例的低压差线性稳压器的电路图；
图2是根据本申请第二实施例的低压差线性稳压器的电路图；
图3是根据本申请第三实施例的低压差线性稳压器的电路图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明部分实施例进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本申请第一实施例涉及一种低压差线性稳压器，应用于提供与电源及环境温度无关的输出电压，具有一定的负载能力，可以外接电容。本实施例中，请参考图1，低压差线性稳压器包括运算放大器A1、源极跟随器M2、功率调整管M4、共栅放大器M3、上拉管M5以及尾电流源M1；其中，VBP为上拉管M5的偏置电压，VBN1为共栅放大器M3的偏置电压，VBN2为尾电流源M1的偏置电压；其中，偏置电压VBP、VBN1以及VBN2分别使得上拉管M5、共栅放大器M3以及尾电流源M1工作在饱和区。
本实施例中，源极跟随器M2的源极连接于功率调整管M4的漏极与运算放大器A1的反相输入端，源极跟随器M2的漏极通过尾电流源接地，源极跟随器M2的栅极连接于运算放大器A1的输出端；共栅放大器M3的漏极连接于上拉管M5的漏极与功率调整管M4的栅极，共栅放大器M3的源极通过尾电流源M1接地；功率调整管M4的源极与上拉管M5的源极均连接至电压源。
其中，运算放大器A1的正相输入端用于输入参考电压，源极跟随器M2的源极用于输出稳压电压。
本实施例中，尾电流源M1可以为NMOS管，然不限于此，也可以为半导体三极管。
本实施例中，源极跟随器M2、功率调整管M4及上拉管M5均为PMOS管，共栅放大器M3为NMOS管。
本实施例中，源极跟随器M2、共栅放大器M3和功率调整管M4构成负反馈环路，运算放大器A1与源极跟随器M2构成单位增益负反馈环路；上拉管M5是为了保证共栅放大器M3具有一定的增益。
本实施例的低压差线性稳压器的工作原理如下：
LDO电路的输出电压表达式：Vout＝Vref  (1)
其中，Vout为输出电压，Vref为参考电压。
由上式(1)可知，输出电压Vout只与参考电压Vref有关，只要Vref具有零温度系数，则Vout同样也是零温度系数。
断开源极跟随器M2、共栅放大器M3和功率调整管M4构成的负反馈环路，LDO电路的零极点分布情况如下：
LDO电路输出端所对应的极点为：
Figure PCTCN2017080422-appb-000001
其中，
Figure PCTCN2017080422-appb-000002
rout为LDO电路的输出阻抗，Av为运算放大器A1的电压增益，gM2为源极跟随器M2的跨导，CL为负载电容。
X节点所对应的极点为：
Figure PCTCN2017080422-appb-000003
其中，
Figure PCTCN2017080422-appb-000004
Cx为X节点的寄生电容，gM3为共栅放大器M3的跨导。
Y节点所对应的极点为：
Figure PCTCN2017080422-appb-000005
其中，rY≈ro5，ro5为上拉管M5的输出阻抗，CY主要由功率调整管M4的栅端寄生电容构成。
运算放大器A1输出节点对应的极点频率为：
Figure PCTCN2017080422-appb-000006
其中，roA1为运算放大器A1的输出阻抗，CA1为运算放大器输出节点处的寄生电容。
由上式(2)至(5)可知，主极点为pY，次主极点为p1，而非主极点 pX和pout离pY和pX较远，由于LDO电路的输出阻抗减小了很多，pout也会处于较高频率处，因此，LDO电路能够保证很好的稳定性。
现有的FVF结构LDO电路中，不包括运算放大器A1，使得LDO电路的输出电压变为：
Vout＝Vref+Vth
其中，Vout为输出电压，Vref为参考电压，Vth为M2管的阈值电压。
此时，LDO电路输出电压Vout不仅跟参考电压Vref有关，还与M2管的阈值电压Vth有关，由于Vth受工艺的影响较大，且具有一定的温度系数，所以LDO电路输出电压Vout受工艺和温度的影响也比较大。若要实现Vref和Vth温度补偿，Vref必须具有正温度系数，此时LDO电路输出电压Vout只能实现在某个电压值具有零温度系数，因此LDO电路的输出电压受到限制。
另外，由于没有运算放大器A1，主极点仍为pY，当LDO电路输出负载电容在较大范围内变化，次主极点会在pX和Pout之间变化，或者两者位置相近，从而降低了LDO电路的环路稳定性。
本实施例相对于现有技术而言，运算放大器和源极跟随器构成单位增益负反馈电路，低压差线性稳压器的输出电压等于参考电压，不受源极跟随器的阈值电压影响，不仅提高了输出电压的精度，而且，由于能够通过调整参考电压获得不同的输出电压(即输出电压不受限)，使得输出电压具有较高的自由度；同时，引入运算放大器后，低压差线性稳压器的输出阻抗进一步减小了，使得输出节点对应的极点处于较高的频率，能够避免外接负载电容在较大范围内变化时对环路稳定性造成影响。
本申请第二实施例涉及一种低压差线性稳压器，本实施例是在第一实施 例基础上的改进，主要改进之处在于：本实施例中，请参考图2，低压差线性稳压器还包括外接电容C1。
外接电容C1的一端连接于源极跟随器M2的源极，另一端接地。
本实施例中，为了提高LDO电路的瞬态响应性能，外接电容C1一般为大电容，即外接电容C1的电容值的范围为0到1uF；由于LDO电路的输出阻抗减小了很多，LDO电路输出端所对应的极点Pout也处于较高频率，此时不会对LDO电路的环路稳定性造成影响；因此，LDO电路外接电容C1为大电容时，同样可以保证LDO电路具有很好的稳定性。
本实施例相对于第一实施例而言，于低压差线性稳压器中设置外接电容，以提高瞬态响应性能，满足负载的大电流要求，同时不影响低压差线性稳压器的稳定性。
本申请第三实施例涉及一种低压差线性稳压器，本实施例是在第一实施例基础上的改进，主要改进之处在于：本实施例中，请参考图3，低压差线性稳压器还包括第一共源共栅放大器M6与第二共源共栅放大器M7；其中，VBN3为第一共源共栅放大器M6的偏置电压，VBP1为第二共源共栅放大器M7的偏置电压，VBP2为上拉管M5的偏置电压；其中，偏置电压VBN3、VBP1以及VBP2分别使得第一共源共栅放大器M6、第二共源共栅放大器M7以及上拉管M5工作在饱和区。
本实施例中，第一共源共栅放大器M5连接于源极跟随器M2的漏极与尾电流源M1之间，第二共源共栅放大器M6连接于共栅放大器M3的漏极与上拉管M5的漏极之间。
其中，第一共源共栅放大器M6为NMOS管，所述第二共源共栅放大器 M7为PMOS管。
本实施例的低压差线性稳压器的工作原理与第一实施例大致相同，主要不同之处在于：
在第一实施例中，源极跟随器M2、共栅放大器M3和功率调整管M4构成的负反馈环路增益为：
Figure PCTCN2017080422-appb-000007
其中，gM4为功率调整管M4的跨导，由上式(6)可知，LDO电路的环路增益较小。
本实施例中，源极跟随器M2、共栅放大器M3和功率调整管M4构成的负反馈环路增益为：
Figure PCTCN2017080422-appb-000008
其中，rx＝ro，rY＝(gM2ro)2，可以假设ro5＝ro7＝ro；由于rx和ry都增大为原来的gMro倍，根据式(6)和(7)可知，本实施例中环路增益便增大为第一实施例中环路增益的(gMro)2倍。
本实施例相对于第一实施例而言，能够提高环路增益，以提高低压差线性稳压器线性调整和负载调整性能。需要说明的是，本实施例也可以作为在第二实施例基础上的改进，能够达到同样的技术效果。
本领域的普通技术人员可以理解，上述各实施例是实现本发明的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本发明的精神和范围。

Claims (3)

  1. 一种低压差线性稳压器，包括：运算放大器、源极跟随器、功率调整管、共栅放大器、上拉管以及尾电流源；
    所述源极跟随器的源极连接于所述功率调整管的漏极与所述运算放大器的反相输入端，所述源极跟随器的漏极通过所述尾电流源接地，所述源极跟随器的栅极连接于所述运算放大器的输出端；
    所述共栅放大器的漏极连接于所述上拉管的漏极与所述功率调整管的栅极，所述共栅放大器的源极通过所述尾电流源接地；
    所述功率调整管的源极与所述上拉管的源极均连接至电压源；
    其中，所述运算放大器的正相输入端用于输入参考电压，所述源极跟随器的源极用于输出稳压电压。
  2. 如权利要求1所述的低压差线性稳压器，其中，所述低压差线性稳压器还包括外接电容；
    所述外接电容的一端连接于所述源极跟随器的源极，另一端接地；
    所述外接电容的电容值的范围为0到1uF。
  3. 如权利要求1或2所述的低压差线性稳压器，其中，所述低压差线性稳压器还包括第一共源共栅放大器与第二共源共栅放大器；
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